1 /*****************************************************************************/ 2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */ 3 /* */ 4 /* Written By: Keith Mitchell, IBM Corporation */ 5 /* Jack Hammer, Adaptec, Inc. */ 6 /* David Jeffery, Adaptec, Inc. */ 7 /* */ 8 /* Copyright (C) 1999 IBM Corporation */ 9 /* Copyright (C) 2003 Adaptec, Inc. */ 10 /* */ 11 /* This program is free software; you can redistribute it and/or modify */ 12 /* it under the terms of the GNU General Public License as published by */ 13 /* the Free Software Foundation; either version 2 of the License, or */ 14 /* (at your option) any later version. */ 15 /* */ 16 /* This program is distributed in the hope that it will be useful, */ 17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19 /* GNU General Public License for more details. */ 20 /* */ 21 /* NO WARRANTY */ 22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26 /* solely responsible for determining the appropriateness of using and */ 27 /* distributing the Program and assumes all risks associated with its */ 28 /* exercise of rights under this Agreement, including but not limited to */ 29 /* the risks and costs of program errors, damage to or loss of data, */ 30 /* programs or equipment, and unavailability or interruption of operations. */ 31 /* */ 32 /* DISCLAIMER OF LIABILITY */ 33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40 /* */ 41 /* You should have received a copy of the GNU General Public License */ 42 /* along with this program; if not, write to the Free Software */ 43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44 /* */ 45 /* Bugs/Comments/Suggestions should be mailed to: */ 46 /* ipslinux@adaptec.com */ 47 /* */ 48 /*****************************************************************************/ 49 50 #ifndef _IPS_H_ 51 #define _IPS_H_ 52 53 #include <asm/uaccess.h> 54 #include <asm/io.h> 55 56 /* 57 * Some handy macros 58 */ 59 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO 60 #define IPS_HIGHIO 61 #endif 62 63 #define IPS_HA(x) ((ips_ha_t *) x->hostdata) 64 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs) 65 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \ 66 (ha->revision_id >= IPS_REVID_TROMBONE32) && \ 67 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0) 68 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \ 69 (ha->revision_id >= IPS_REVID_CLARINETP1) && \ 70 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0) 71 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS) 72 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO) 73 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \ 74 (IPS_IS_TROMBONE(ha) && \ 75 (ips_force_i2o))) ? 1 : 0) 76 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \ 77 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \ 78 (ips_force_memio))) ? 1 : 0) 79 80 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) 81 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG) 82 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \ 83 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST)) 84 85 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4) 86 #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 ) 87 #define scsi_set_pci_device(sh,dev) (0) 88 #endif 89 90 #ifndef IRQ_NONE 91 typedef void irqreturn_t; 92 #define IRQ_NONE 93 #define IRQ_HANDLED 94 #define IRQ_RETVAL(x) 95 #endif 96 97 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 98 #define IPS_REGISTER_HOSTS(SHT) scsi_register_module(MODULE_SCSI_HA,SHT) 99 #define IPS_UNREGISTER_HOSTS(SHT) scsi_unregister_module(MODULE_SCSI_HA,SHT) 100 #define IPS_ADD_HOST(shost,device) 101 #define IPS_REMOVE_HOST(shost) 102 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_pci_device(sh, (ha)->pcidev) 103 #define IPS_PRINTK(level, pcidev, format, arg...) \ 104 printk(level "%s %s:" format , "ips" , \ 105 (pcidev)->slot_name , ## arg) 106 #define scsi_host_alloc(sh,size) scsi_register(sh,size) 107 #define scsi_host_put(sh) scsi_unregister(sh) 108 #else 109 #define IPS_REGISTER_HOSTS(SHT) (!ips_detect(SHT)) 110 #define IPS_UNREGISTER_HOSTS(SHT) 111 #define IPS_ADD_HOST(shost,device) do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0) 112 #define IPS_REMOVE_HOST(shost) scsi_remove_host(shost) 113 #define IPS_SCSI_SET_DEVICE(sh,ha) do { } while (0) 114 #define IPS_PRINTK(level, pcidev, format, arg...) \ 115 dev_printk(level , &((pcidev)->dev) , format , ## arg) 116 #endif 117 118 #ifndef MDELAY 119 #define MDELAY mdelay 120 #endif 121 122 #ifndef min 123 #define min(x,y) ((x) < (y) ? x : y) 124 #endif 125 126 #ifndef __iomem /* For clean compiles in earlier kernels without __iomem annotations */ 127 #define __iomem 128 #endif 129 130 #define pci_dma_hi32(a) ((a >> 16) >> 16) 131 #define pci_dma_lo32(a) (a & 0xffffffff) 132 133 #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO) 134 #define IPS_ENABLE_DMA64 (1) 135 #else 136 #define IPS_ENABLE_DMA64 (0) 137 #endif 138 139 /* 140 * Adapter address map equates 141 */ 142 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */ 143 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */ 144 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */ 145 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */ 146 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */ 147 #define IPS_REG_SQER 0x28 /* Status Q End Reg */ 148 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */ 149 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */ 150 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */ 151 #define IPS_REG_CBSP 0x07 /* CBSP register */ 152 #define IPS_REG_FLAP 0x18 /* Flash address port */ 153 #define IPS_REG_FLDP 0x1C /* Flash data port */ 154 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */ 155 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */ 156 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */ 157 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */ 158 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */ 159 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */ 160 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */ 161 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */ 162 163 /* 164 * Adapter register bit equates 165 */ 166 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */ 167 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */ 168 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */ 169 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */ 170 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */ 171 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */ 172 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */ 173 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */ 174 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */ 175 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */ 176 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */ 177 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */ 178 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/ 179 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/ 180 181 /* 182 * Adapter Command ID Equates 183 */ 184 #define IPS_CMD_GET_LD_INFO 0x19 185 #define IPS_CMD_GET_SUBSYS 0x40 186 #define IPS_CMD_READ_CONF 0x38 187 #define IPS_CMD_RW_NVRAM_PAGE 0xBC 188 #define IPS_CMD_READ 0x02 189 #define IPS_CMD_WRITE 0x03 190 #define IPS_CMD_FFDC 0xD7 191 #define IPS_CMD_ENQUIRY 0x05 192 #define IPS_CMD_FLUSH 0x0A 193 #define IPS_CMD_READ_SG 0x82 194 #define IPS_CMD_WRITE_SG 0x83 195 #define IPS_CMD_DCDB 0x04 196 #define IPS_CMD_DCDB_SG 0x84 197 #define IPS_CMD_EXTENDED_DCDB 0x95 198 #define IPS_CMD_EXTENDED_DCDB_SG 0x96 199 #define IPS_CMD_CONFIG_SYNC 0x58 200 #define IPS_CMD_ERROR_TABLE 0x17 201 #define IPS_CMD_DOWNLOAD 0x20 202 #define IPS_CMD_RW_BIOSFW 0x22 203 #define IPS_CMD_GET_VERSION_INFO 0xC6 204 #define IPS_CMD_RESET_CHANNEL 0x1A 205 206 /* 207 * Adapter Equates 208 */ 209 #define IPS_CSL 0xFF 210 #define IPS_POCL 0x30 211 #define IPS_NORM_STATE 0x00 212 #define IPS_MAX_ADAPTER_TYPES 3 213 #define IPS_MAX_ADAPTERS 16 214 #define IPS_MAX_IOCTL 1 215 #define IPS_MAX_IOCTL_QUEUE 8 216 #define IPS_MAX_QUEUE 128 217 #define IPS_BLKSIZE 512 218 #define IPS_MAX_SG 17 219 #define IPS_MAX_LD 8 220 #define IPS_MAX_CHANNELS 4 221 #define IPS_MAX_TARGETS 15 222 #define IPS_MAX_CHUNKS 16 223 #define IPS_MAX_CMDS 128 224 #define IPS_MAX_XFER 0x10000 225 #define IPS_NVRAM_P5_SIG 0xFFDDBB99 226 #define IPS_MAX_POST_BYTES 0x02 227 #define IPS_MAX_CONFIG_BYTES 0x02 228 #define IPS_GOOD_POST_STATUS 0x80 229 #define IPS_SEM_TIMEOUT 2000 230 #define IPS_IOCTL_COMMAND 0x0D 231 #define IPS_INTR_ON 0 232 #define IPS_INTR_IORL 1 233 #define IPS_FFDC 99 234 #define IPS_ADAPTER_ID 0xF 235 #define IPS_VENDORID_IBM 0x1014 236 #define IPS_VENDORID_ADAPTEC 0x9005 237 #define IPS_DEVICEID_COPPERHEAD 0x002E 238 #define IPS_DEVICEID_MORPHEUS 0x01BD 239 #define IPS_DEVICEID_MARCO 0x0250 240 #define IPS_SUBDEVICEID_4M 0x01BE 241 #define IPS_SUBDEVICEID_4L 0x01BF 242 #define IPS_SUBDEVICEID_4MX 0x0208 243 #define IPS_SUBDEVICEID_4LX 0x020E 244 #define IPS_SUBDEVICEID_5I2 0x0259 245 #define IPS_SUBDEVICEID_5I1 0x0258 246 #define IPS_SUBDEVICEID_6M 0x0279 247 #define IPS_SUBDEVICEID_6I 0x028C 248 #define IPS_SUBDEVICEID_7k 0x028E 249 #define IPS_SUBDEVICEID_7M 0x028F 250 #define IPS_IOCTL_SIZE 8192 251 #define IPS_STATUS_SIZE 4 252 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE 253 #define IPS_IMAGE_SIZE 500 * 1024 254 #define IPS_MEMMAP_SIZE 128 255 #define IPS_ONE_MSEC 1 256 #define IPS_ONE_SEC 1000 257 258 /* 259 * Geometry Settings 260 */ 261 #define IPS_COMP_HEADS 128 262 #define IPS_COMP_SECTORS 32 263 #define IPS_NORM_HEADS 254 264 #define IPS_NORM_SECTORS 63 265 266 /* 267 * Adapter Basic Status Codes 268 */ 269 #define IPS_BASIC_STATUS_MASK 0xFF 270 #define IPS_GSC_STATUS_MASK 0x0F 271 #define IPS_CMD_SUCCESS 0x00 272 #define IPS_CMD_RECOVERED_ERROR 0x01 273 #define IPS_INVAL_OPCO 0x03 274 #define IPS_INVAL_CMD_BLK 0x04 275 #define IPS_INVAL_PARM_BLK 0x05 276 #define IPS_BUSY 0x08 277 #define IPS_CMD_CMPLT_WERROR 0x0C 278 #define IPS_LD_ERROR 0x0D 279 #define IPS_CMD_TIMEOUT 0x0E 280 #define IPS_PHYS_DRV_ERROR 0x0F 281 282 /* 283 * Adapter Extended Status Equates 284 */ 285 #define IPS_ERR_SEL_TO 0xF0 286 #define IPS_ERR_OU_RUN 0xF2 287 #define IPS_ERR_HOST_RESET 0xF7 288 #define IPS_ERR_DEV_RESET 0xF8 289 #define IPS_ERR_RECOVERY 0xFC 290 #define IPS_ERR_CKCOND 0xFF 291 292 /* 293 * Operating System Defines 294 */ 295 #define IPS_OS_WINDOWS_NT 0x01 296 #define IPS_OS_NETWARE 0x02 297 #define IPS_OS_OPENSERVER 0x03 298 #define IPS_OS_UNIXWARE 0x04 299 #define IPS_OS_SOLARIS 0x05 300 #define IPS_OS_OS2 0x06 301 #define IPS_OS_LINUX 0x07 302 #define IPS_OS_FREEBSD 0x08 303 304 /* 305 * Adapter Revision ID's 306 */ 307 #define IPS_REVID_SERVERAID 0x02 308 #define IPS_REVID_NAVAJO 0x03 309 #define IPS_REVID_SERVERAID2 0x04 310 #define IPS_REVID_CLARINETP1 0x05 311 #define IPS_REVID_CLARINETP2 0x07 312 #define IPS_REVID_CLARINETP3 0x0D 313 #define IPS_REVID_TROMBONE32 0x0F 314 #define IPS_REVID_TROMBONE64 0x10 315 316 /* 317 * NVRAM Page 5 Adapter Defines 318 */ 319 #define IPS_ADTYPE_SERVERAID 0x01 320 #define IPS_ADTYPE_SERVERAID2 0x02 321 #define IPS_ADTYPE_NAVAJO 0x03 322 #define IPS_ADTYPE_KIOWA 0x04 323 #define IPS_ADTYPE_SERVERAID3 0x05 324 #define IPS_ADTYPE_SERVERAID3L 0x06 325 #define IPS_ADTYPE_SERVERAID4H 0x07 326 #define IPS_ADTYPE_SERVERAID4M 0x08 327 #define IPS_ADTYPE_SERVERAID4L 0x09 328 #define IPS_ADTYPE_SERVERAID4MX 0x0A 329 #define IPS_ADTYPE_SERVERAID4LX 0x0B 330 #define IPS_ADTYPE_SERVERAID5I2 0x0C 331 #define IPS_ADTYPE_SERVERAID5I1 0x0D 332 #define IPS_ADTYPE_SERVERAID6M 0x0E 333 #define IPS_ADTYPE_SERVERAID6I 0x0F 334 #define IPS_ADTYPE_SERVERAID7t 0x10 335 #define IPS_ADTYPE_SERVERAID7k 0x11 336 #define IPS_ADTYPE_SERVERAID7M 0x12 337 338 /* 339 * Adapter Command/Status Packet Definitions 340 */ 341 #define IPS_SUCCESS 0x01 /* Successfully completed */ 342 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */ 343 #define IPS_FAILURE 0x04 /* Completed with Error */ 344 345 /* 346 * Logical Drive Equates 347 */ 348 #define IPS_LD_OFFLINE 0x02 349 #define IPS_LD_OKAY 0x03 350 #define IPS_LD_FREE 0x00 351 #define IPS_LD_SYS 0x06 352 #define IPS_LD_CRS 0x24 353 354 /* 355 * DCDB Table Equates 356 */ 357 #define IPS_NO_DISCONNECT 0x00 358 #define IPS_DISCONNECT_ALLOWED 0x80 359 #define IPS_NO_AUTO_REQSEN 0x40 360 #define IPS_DATA_NONE 0x00 361 #define IPS_DATA_UNK 0x00 362 #define IPS_DATA_IN 0x01 363 #define IPS_DATA_OUT 0x02 364 #define IPS_TRANSFER64K 0x08 365 #define IPS_NOTIMEOUT 0x00 366 #define IPS_TIMEOUT10 0x10 367 #define IPS_TIMEOUT60 0x20 368 #define IPS_TIMEOUT20M 0x30 369 370 /* 371 * SCSI Inquiry Data Flags 372 */ 373 #define IPS_SCSI_INQ_TYPE_DASD 0x00 374 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03 375 #define IPS_SCSI_INQ_LU_CONNECTED 0x00 376 #define IPS_SCSI_INQ_RD_REV2 0x02 377 #define IPS_SCSI_INQ_REV2 0x02 378 #define IPS_SCSI_INQ_REV3 0x03 379 #define IPS_SCSI_INQ_Address16 0x01 380 #define IPS_SCSI_INQ_Address32 0x02 381 #define IPS_SCSI_INQ_MedChanger 0x08 382 #define IPS_SCSI_INQ_MultiPort 0x10 383 #define IPS_SCSI_INQ_EncServ 0x40 384 #define IPS_SCSI_INQ_SoftReset 0x01 385 #define IPS_SCSI_INQ_CmdQue 0x02 386 #define IPS_SCSI_INQ_Linked 0x08 387 #define IPS_SCSI_INQ_Sync 0x10 388 #define IPS_SCSI_INQ_WBus16 0x20 389 #define IPS_SCSI_INQ_WBus32 0x40 390 #define IPS_SCSI_INQ_RelAdr 0x80 391 392 /* 393 * SCSI Request Sense Data Flags 394 */ 395 #define IPS_SCSI_REQSEN_VALID 0x80 396 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70 397 #define IPS_SCSI_REQSEN_NO_SENSE 0x00 398 399 /* 400 * SCSI Mode Page Equates 401 */ 402 #define IPS_SCSI_MP3_SoftSector 0x01 403 #define IPS_SCSI_MP3_HardSector 0x02 404 #define IPS_SCSI_MP3_Removeable 0x04 405 #define IPS_SCSI_MP3_AllocateSurface 0x08 406 407 /* 408 * HA Flags 409 */ 410 411 #define IPS_HA_ENH_SG 0x1 412 413 /* 414 * SCB Flags 415 */ 416 #define IPS_SCB_MAP_SG 0x00008 417 #define IPS_SCB_MAP_SINGLE 0X00010 418 419 /* 420 * Passthru stuff 421 */ 422 #define IPS_COPPUSRCMD (('C'<<8) | 65) 423 #define IPS_COPPIOCCMD (('C'<<8) | 66) 424 #define IPS_NUMCTRLS (('C'<<8) | 68) 425 #define IPS_CTRLINFO (('C'<<8) | 69) 426 427 /* flashing defines */ 428 #define IPS_FW_IMAGE 0x00 429 #define IPS_BIOS_IMAGE 0x01 430 #define IPS_WRITE_FW 0x01 431 #define IPS_WRITE_BIOS 0x02 432 #define IPS_ERASE_BIOS 0x03 433 #define IPS_BIOS_HEADER 0xC0 434 435 /* time oriented stuff */ 436 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0) 437 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400) 438 439 #define IPS_SECS_MIN 60 440 #define IPS_SECS_HOUR 3600 441 #define IPS_SECS_8HOURS 28800 442 #define IPS_SECS_DAY 86400 443 #define IPS_DAYS_NORMAL_YEAR 365 444 #define IPS_DAYS_LEAP_YEAR 366 445 #define IPS_EPOCH_YEAR 1970 446 447 /* 448 * Scsi_Host Template 449 */ 450 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0) 451 static int ips_proc24_info(char *, char **, off_t, int, int, int); 452 static void ips_select_queue_depth(struct Scsi_Host *, Scsi_Device *); 453 static int ips_biosparam(Disk *disk, kdev_t dev, int geom[]); 454 #else 455 static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int); 456 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 457 sector_t capacity, int geom[]); 458 static int ips_slave_configure(Scsi_Device *SDptr); 459 #endif 460 461 /* 462 * Raid Command Formats 463 */ 464 typedef struct { 465 uint8_t op_code; 466 uint8_t command_id; 467 uint8_t log_drv; 468 uint8_t sg_count; 469 uint32_t lba; 470 uint32_t sg_addr; 471 uint16_t sector_count; 472 uint8_t segment_4G; 473 uint8_t enhanced_sg; 474 uint32_t ccsar; 475 uint32_t cccr; 476 } IPS_IO_CMD, *PIPS_IO_CMD; 477 478 typedef struct { 479 uint8_t op_code; 480 uint8_t command_id; 481 uint16_t reserved; 482 uint32_t reserved2; 483 uint32_t buffer_addr; 484 uint32_t reserved3; 485 uint32_t ccsar; 486 uint32_t cccr; 487 } IPS_LD_CMD, *PIPS_LD_CMD; 488 489 typedef struct { 490 uint8_t op_code; 491 uint8_t command_id; 492 uint8_t reserved; 493 uint8_t reserved2; 494 uint32_t reserved3; 495 uint32_t buffer_addr; 496 uint32_t reserved4; 497 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD; 498 499 typedef struct { 500 uint8_t op_code; 501 uint8_t command_id; 502 uint8_t channel; 503 uint8_t reserved3; 504 uint8_t reserved4; 505 uint8_t reserved5; 506 uint8_t reserved6; 507 uint8_t reserved7; 508 uint8_t reserved8; 509 uint8_t reserved9; 510 uint8_t reserved10; 511 uint8_t reserved11; 512 uint8_t reserved12; 513 uint8_t reserved13; 514 uint8_t reserved14; 515 uint8_t adapter_flag; 516 } IPS_RESET_CMD, *PIPS_RESET_CMD; 517 518 typedef struct { 519 uint8_t op_code; 520 uint8_t command_id; 521 uint16_t reserved; 522 uint32_t reserved2; 523 uint32_t dcdb_address; 524 uint16_t reserved3; 525 uint8_t segment_4G; 526 uint8_t enhanced_sg; 527 uint32_t ccsar; 528 uint32_t cccr; 529 } IPS_DCDB_CMD, *PIPS_DCDB_CMD; 530 531 typedef struct { 532 uint8_t op_code; 533 uint8_t command_id; 534 uint8_t channel; 535 uint8_t source_target; 536 uint32_t reserved; 537 uint32_t reserved2; 538 uint32_t reserved3; 539 uint32_t ccsar; 540 uint32_t cccr; 541 } IPS_CS_CMD, *PIPS_CS_CMD; 542 543 typedef struct { 544 uint8_t op_code; 545 uint8_t command_id; 546 uint8_t log_drv; 547 uint8_t control; 548 uint32_t reserved; 549 uint32_t reserved2; 550 uint32_t reserved3; 551 uint32_t ccsar; 552 uint32_t cccr; 553 } IPS_US_CMD, *PIPS_US_CMD; 554 555 typedef struct { 556 uint8_t op_code; 557 uint8_t command_id; 558 uint8_t reserved; 559 uint8_t state; 560 uint32_t reserved2; 561 uint32_t reserved3; 562 uint32_t reserved4; 563 uint32_t ccsar; 564 uint32_t cccr; 565 } IPS_FC_CMD, *PIPS_FC_CMD; 566 567 typedef struct { 568 uint8_t op_code; 569 uint8_t command_id; 570 uint8_t reserved; 571 uint8_t desc; 572 uint32_t reserved2; 573 uint32_t buffer_addr; 574 uint32_t reserved3; 575 uint32_t ccsar; 576 uint32_t cccr; 577 } IPS_STATUS_CMD, *PIPS_STATUS_CMD; 578 579 typedef struct { 580 uint8_t op_code; 581 uint8_t command_id; 582 uint8_t page; 583 uint8_t write; 584 uint32_t reserved; 585 uint32_t buffer_addr; 586 uint32_t reserved2; 587 uint32_t ccsar; 588 uint32_t cccr; 589 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD; 590 591 typedef struct 592 { 593 uint8_t op_code; 594 uint8_t command_id; 595 uint16_t reserved; 596 uint32_t count; 597 uint32_t buffer_addr; 598 uint32_t reserved2; 599 } IPS_VERSION_INFO, *PIPS_VERSION_INFO; 600 601 typedef struct { 602 uint8_t op_code; 603 uint8_t command_id; 604 uint8_t reset_count; 605 uint8_t reset_type; 606 uint8_t second; 607 uint8_t minute; 608 uint8_t hour; 609 uint8_t day; 610 uint8_t reserved1[4]; 611 uint8_t month; 612 uint8_t yearH; 613 uint8_t yearL; 614 uint8_t reserved2; 615 } IPS_FFDC_CMD, *PIPS_FFDC_CMD; 616 617 typedef struct { 618 uint8_t op_code; 619 uint8_t command_id; 620 uint8_t type; 621 uint8_t direction; 622 uint32_t count; 623 uint32_t buffer_addr; 624 uint8_t total_packets; 625 uint8_t packet_num; 626 uint16_t reserved; 627 } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD; 628 629 typedef struct { 630 uint8_t op_code; 631 uint8_t command_id; 632 uint8_t type; 633 uint8_t direction; 634 uint32_t count; 635 uint32_t buffer_addr; 636 uint32_t offset; 637 } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD; 638 639 typedef union { 640 IPS_IO_CMD basic_io; 641 IPS_LD_CMD logical_info; 642 IPS_IOCTL_CMD ioctl_info; 643 IPS_DCDB_CMD dcdb; 644 IPS_CS_CMD config_sync; 645 IPS_US_CMD unlock_stripe; 646 IPS_FC_CMD flush_cache; 647 IPS_STATUS_CMD status; 648 IPS_NVRAM_CMD nvram; 649 IPS_FFDC_CMD ffdc; 650 IPS_FLASHFW_CMD flashfw; 651 IPS_FLASHBIOS_CMD flashbios; 652 IPS_VERSION_INFO version_info; 653 IPS_RESET_CMD reset; 654 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND; 655 656 typedef struct { 657 uint8_t logical_id; 658 uint8_t reserved; 659 uint8_t raid_level; 660 uint8_t state; 661 uint32_t sector_count; 662 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO; 663 664 typedef struct { 665 uint8_t no_of_log_drive; 666 uint8_t reserved[3]; 667 IPS_DRIVE_INFO drive_info[IPS_MAX_LD]; 668 } IPS_LD_INFO, *PIPS_LD_INFO; 669 670 typedef struct { 671 uint8_t device_address; 672 uint8_t cmd_attribute; 673 uint16_t transfer_length; 674 uint32_t buffer_pointer; 675 uint8_t cdb_length; 676 uint8_t sense_length; 677 uint8_t sg_count; 678 uint8_t reserved; 679 uint8_t scsi_cdb[12]; 680 uint8_t sense_info[64]; 681 uint8_t scsi_status; 682 uint8_t reserved2[3]; 683 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE; 684 685 typedef struct { 686 uint8_t device_address; 687 uint8_t cmd_attribute; 688 uint8_t cdb_length; 689 uint8_t reserved_for_LUN; 690 uint32_t transfer_length; 691 uint32_t buffer_pointer; 692 uint16_t sg_count; 693 uint8_t sense_length; 694 uint8_t scsi_status; 695 uint32_t reserved; 696 uint8_t scsi_cdb[16]; 697 uint8_t sense_info[56]; 698 } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE; 699 700 typedef union { 701 struct { 702 volatile uint8_t reserved; 703 volatile uint8_t command_id; 704 volatile uint8_t basic_status; 705 volatile uint8_t extended_status; 706 } fields; 707 708 volatile uint32_t value; 709 } IPS_STATUS, *PIPS_STATUS; 710 711 typedef struct { 712 IPS_STATUS status[IPS_MAX_CMDS + 1]; 713 volatile PIPS_STATUS p_status_start; 714 volatile PIPS_STATUS p_status_end; 715 volatile PIPS_STATUS p_status_tail; 716 volatile uint32_t hw_status_start; 717 volatile uint32_t hw_status_tail; 718 } IPS_ADAPTER, *PIPS_ADAPTER; 719 720 typedef struct { 721 uint8_t ucLogDriveCount; 722 uint8_t ucMiscFlag; 723 uint8_t ucSLTFlag; 724 uint8_t ucBSTFlag; 725 uint8_t ucPwrChgCnt; 726 uint8_t ucWrongAdrCnt; 727 uint8_t ucUnidentCnt; 728 uint8_t ucNVramDevChgCnt; 729 uint8_t CodeBlkVersion[8]; 730 uint8_t BootBlkVersion[8]; 731 uint32_t ulDriveSize[IPS_MAX_LD]; 732 uint8_t ucConcurrentCmdCount; 733 uint8_t ucMaxPhysicalDevices; 734 uint16_t usFlashRepgmCount; 735 uint8_t ucDefunctDiskCount; 736 uint8_t ucRebuildFlag; 737 uint8_t ucOfflineLogDrvCount; 738 uint8_t ucCriticalDrvCount; 739 uint16_t usConfigUpdateCount; 740 uint8_t ucBlkFlag; 741 uint8_t reserved; 742 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)]; 743 } IPS_ENQ, *PIPS_ENQ; 744 745 typedef struct { 746 uint8_t ucInitiator; 747 uint8_t ucParameters; 748 uint8_t ucMiscFlag; 749 uint8_t ucState; 750 uint32_t ulBlockCount; 751 uint8_t ucDeviceId[28]; 752 } IPS_DEVSTATE, *PIPS_DEVSTATE; 753 754 typedef struct { 755 uint8_t ucChn; 756 uint8_t ucTgt; 757 uint16_t ucReserved; 758 uint32_t ulStartSect; 759 uint32_t ulNoOfSects; 760 } IPS_CHUNK, *PIPS_CHUNK; 761 762 typedef struct { 763 uint16_t ucUserField; 764 uint8_t ucState; 765 uint8_t ucRaidCacheParam; 766 uint8_t ucNoOfChunkUnits; 767 uint8_t ucStripeSize; 768 uint8_t ucParams; 769 uint8_t ucReserved; 770 uint32_t ulLogDrvSize; 771 IPS_CHUNK chunk[IPS_MAX_CHUNKS]; 772 } IPS_LD, *PIPS_LD; 773 774 typedef struct { 775 uint8_t board_disc[8]; 776 uint8_t processor[8]; 777 uint8_t ucNoChanType; 778 uint8_t ucNoHostIntType; 779 uint8_t ucCompression; 780 uint8_t ucNvramType; 781 uint32_t ulNvramSize; 782 } IPS_HARDWARE, *PIPS_HARDWARE; 783 784 typedef struct { 785 uint8_t ucLogDriveCount; 786 uint8_t ucDateD; 787 uint8_t ucDateM; 788 uint8_t ucDateY; 789 uint8_t init_id[4]; 790 uint8_t host_id[12]; 791 uint8_t time_sign[8]; 792 uint32_t UserOpt; 793 uint16_t user_field; 794 uint8_t ucRebuildRate; 795 uint8_t ucReserve; 796 IPS_HARDWARE hardware_disc; 797 IPS_LD logical_drive[IPS_MAX_LD]; 798 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1]; 799 uint8_t reserved[512]; 800 } IPS_CONF, *PIPS_CONF; 801 802 typedef struct { 803 uint32_t signature; 804 uint8_t reserved1; 805 uint8_t adapter_slot; 806 uint16_t adapter_type; 807 uint8_t ctrl_bios[8]; 808 uint8_t versioning; /* 1 = Versioning Supported, else 0 */ 809 uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */ 810 uint8_t reserved2; 811 uint8_t operating_system; 812 uint8_t driver_high[4]; 813 uint8_t driver_low[4]; 814 uint8_t BiosCompatibilityID[8]; 815 uint8_t ReservedForOS2[8]; 816 uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */ 817 uint8_t bios_low[4]; 818 uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */ 819 uint8_t Filler[60]; 820 } IPS_NVRAM_P5, *PIPS_NVRAM_P5; 821 822 /*--------------------------------------------------------------------------*/ 823 /* Data returned from a GetVersion Command */ 824 /*--------------------------------------------------------------------------*/ 825 826 /* SubSystem Parameter[4] */ 827 #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */ 828 829 typedef struct 830 { 831 uint32_t revision; 832 uint8_t bootBlkVersion[32]; 833 uint8_t bootBlkAttributes[4]; 834 uint8_t codeBlkVersion[32]; 835 uint8_t biosVersion[32]; 836 uint8_t biosAttributes[4]; 837 uint8_t compatibilityId[32]; 838 uint8_t reserved[4]; 839 } IPS_VERSION_DATA; 840 841 842 typedef struct _IPS_SUBSYS { 843 uint32_t param[128]; 844 } IPS_SUBSYS, *PIPS_SUBSYS; 845 846 /** 847 ** SCSI Structures 848 **/ 849 850 /* 851 * Inquiry Data Format 852 */ 853 typedef struct { 854 uint8_t DeviceType; 855 uint8_t DeviceTypeQualifier; 856 uint8_t Version; 857 uint8_t ResponseDataFormat; 858 uint8_t AdditionalLength; 859 uint8_t Reserved; 860 uint8_t Flags[2]; 861 uint8_t VendorId[8]; 862 uint8_t ProductId[16]; 863 uint8_t ProductRevisionLevel[4]; 864 uint8_t Reserved2; /* Provides NULL terminator to name */ 865 } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA; 866 867 /* 868 * Read Capacity Data Format 869 */ 870 typedef struct { 871 uint32_t lba; 872 uint32_t len; 873 } IPS_SCSI_CAPACITY; 874 875 /* 876 * Request Sense Data Format 877 */ 878 typedef struct { 879 uint8_t ResponseCode; 880 uint8_t SegmentNumber; 881 uint8_t Flags; 882 uint8_t Information[4]; 883 uint8_t AdditionalLength; 884 uint8_t CommandSpecific[4]; 885 uint8_t AdditionalSenseCode; 886 uint8_t AdditionalSenseCodeQual; 887 uint8_t FRUCode; 888 uint8_t SenseKeySpecific[3]; 889 } IPS_SCSI_REQSEN; 890 891 /* 892 * Sense Data Format - Page 3 893 */ 894 typedef struct { 895 uint8_t PageCode; 896 uint8_t PageLength; 897 uint16_t TracksPerZone; 898 uint16_t AltSectorsPerZone; 899 uint16_t AltTracksPerZone; 900 uint16_t AltTracksPerVolume; 901 uint16_t SectorsPerTrack; 902 uint16_t BytesPerSector; 903 uint16_t Interleave; 904 uint16_t TrackSkew; 905 uint16_t CylinderSkew; 906 uint8_t flags; 907 uint8_t reserved[3]; 908 } IPS_SCSI_MODE_PAGE3; 909 910 /* 911 * Sense Data Format - Page 4 912 */ 913 typedef struct { 914 uint8_t PageCode; 915 uint8_t PageLength; 916 uint16_t CylindersHigh; 917 uint8_t CylindersLow; 918 uint8_t Heads; 919 uint16_t WritePrecompHigh; 920 uint8_t WritePrecompLow; 921 uint16_t ReducedWriteCurrentHigh; 922 uint8_t ReducedWriteCurrentLow; 923 uint16_t StepRate; 924 uint16_t LandingZoneHigh; 925 uint8_t LandingZoneLow; 926 uint8_t flags; 927 uint8_t RotationalOffset; 928 uint8_t Reserved; 929 uint16_t MediumRotationRate; 930 uint8_t Reserved2[2]; 931 } IPS_SCSI_MODE_PAGE4; 932 933 /* 934 * Sense Data Format - Page 8 935 */ 936 typedef struct { 937 uint8_t PageCode; 938 uint8_t PageLength; 939 uint8_t flags; 940 uint8_t RetentPrio; 941 uint16_t DisPrefetchLen; 942 uint16_t MinPrefetchLen; 943 uint16_t MaxPrefetchLen; 944 uint16_t MaxPrefetchCeiling; 945 } IPS_SCSI_MODE_PAGE8; 946 947 /* 948 * Sense Data Format - Block Descriptor (DASD) 949 */ 950 typedef struct { 951 uint32_t NumberOfBlocks; 952 uint8_t DensityCode; 953 uint16_t BlockLengthHigh; 954 uint8_t BlockLengthLow; 955 } IPS_SCSI_MODE_PAGE_BLKDESC; 956 957 /* 958 * Sense Data Format - Mode Page Header 959 */ 960 typedef struct { 961 uint8_t DataLength; 962 uint8_t MediumType; 963 uint8_t Reserved; 964 uint8_t BlockDescLength; 965 } IPS_SCSI_MODE_PAGE_HEADER; 966 967 typedef struct { 968 IPS_SCSI_MODE_PAGE_HEADER hdr; 969 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc; 970 971 union { 972 IPS_SCSI_MODE_PAGE3 pg3; 973 IPS_SCSI_MODE_PAGE4 pg4; 974 IPS_SCSI_MODE_PAGE8 pg8; 975 } pdata; 976 } IPS_SCSI_MODE_PAGE_DATA; 977 978 /* 979 * Scatter Gather list format 980 */ 981 typedef struct ips_sglist { 982 uint32_t address; 983 uint32_t length; 984 } IPS_STD_SG_LIST; 985 986 typedef struct ips_enh_sglist { 987 uint32_t address_lo; 988 uint32_t address_hi; 989 uint32_t length; 990 uint32_t reserved; 991 } IPS_ENH_SG_LIST; 992 993 typedef union { 994 void *list; 995 IPS_STD_SG_LIST *std_list; 996 IPS_ENH_SG_LIST *enh_list; 997 } IPS_SG_LIST; 998 999 typedef struct _IPS_INFOSTR { 1000 char *buffer; 1001 int length; 1002 int offset; 1003 int pos; 1004 int localpos; 1005 } IPS_INFOSTR; 1006 1007 typedef struct { 1008 char *option_name; 1009 int *option_flag; 1010 int option_value; 1011 } IPS_OPTION; 1012 1013 /* 1014 * Status Info 1015 */ 1016 typedef struct ips_stat { 1017 uint32_t residue_len; 1018 void *scb_addr; 1019 uint8_t padding[12 - sizeof(void *)]; 1020 } ips_stat_t; 1021 1022 /* 1023 * SCB Queue Format 1024 */ 1025 typedef struct ips_scb_queue { 1026 struct ips_scb *head; 1027 struct ips_scb *tail; 1028 int count; 1029 } ips_scb_queue_t; 1030 1031 /* 1032 * Wait queue_format 1033 */ 1034 typedef struct ips_wait_queue { 1035 Scsi_Cmnd *head; 1036 Scsi_Cmnd *tail; 1037 int count; 1038 } ips_wait_queue_t; 1039 1040 typedef struct ips_copp_wait_item { 1041 Scsi_Cmnd *scsi_cmd; 1042 struct ips_copp_wait_item *next; 1043 } ips_copp_wait_item_t; 1044 1045 typedef struct ips_copp_queue { 1046 struct ips_copp_wait_item *head; 1047 struct ips_copp_wait_item *tail; 1048 int count; 1049 } ips_copp_queue_t; 1050 1051 /* forward decl for host structure */ 1052 struct ips_ha; 1053 1054 typedef struct { 1055 int (*reset)(struct ips_ha *); 1056 int (*issue)(struct ips_ha *, struct ips_scb *); 1057 int (*isinit)(struct ips_ha *); 1058 int (*isintr)(struct ips_ha *); 1059 int (*init)(struct ips_ha *); 1060 int (*erasebios)(struct ips_ha *); 1061 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t); 1062 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t); 1063 void (*statinit)(struct ips_ha *); 1064 int (*intr)(struct ips_ha *); 1065 void (*enableint)(struct ips_ha *); 1066 uint32_t (*statupd)(struct ips_ha *); 1067 } ips_hw_func_t; 1068 1069 typedef struct ips_ha { 1070 uint8_t ha_id[IPS_MAX_CHANNELS+1]; 1071 uint32_t dcdb_active[IPS_MAX_CHANNELS]; 1072 uint32_t io_addr; /* Base I/O address */ 1073 uint8_t irq; /* IRQ for adapter */ 1074 uint8_t ntargets; /* Number of targets */ 1075 uint8_t nbus; /* Number of buses */ 1076 uint8_t nlun; /* Number of Luns */ 1077 uint16_t ad_type; /* Adapter type */ 1078 uint16_t host_num; /* Adapter number */ 1079 uint32_t max_xfer; /* Maximum Xfer size */ 1080 uint32_t max_cmds; /* Max concurrent commands */ 1081 uint32_t num_ioctl; /* Number of Ioctls */ 1082 ips_stat_t sp; /* Status packer pointer */ 1083 struct ips_scb *scbs; /* Array of all CCBS */ 1084 struct ips_scb *scb_freelist; /* SCB free list */ 1085 ips_wait_queue_t scb_waitlist; /* Pending SCB list */ 1086 ips_copp_queue_t copp_waitlist; /* Pending PT list */ 1087 ips_scb_queue_t scb_activelist; /* Active SCB list */ 1088 IPS_IO_CMD *dummy; /* dummy command */ 1089 IPS_ADAPTER *adapt; /* Adapter status area */ 1090 IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */ 1091 dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */ 1092 IPS_ENQ *enq; /* Adapter Enquiry data */ 1093 IPS_CONF *conf; /* Adapter config data */ 1094 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */ 1095 IPS_SUBSYS *subsys; /* Subsystem parameters */ 1096 char *ioctl_data; /* IOCTL data area */ 1097 uint32_t ioctl_datasize; /* IOCTL data size */ 1098 uint32_t cmd_in_progress; /* Current command in progress*/ 1099 int flags; /* */ 1100 uint8_t waitflag; /* are we waiting for cmd */ 1101 uint8_t active; 1102 int ioctl_reset; /* IOCTL Requested Reset Flag */ 1103 uint16_t reset_count; /* number of resets */ 1104 time_t last_ffdc; /* last time we sent ffdc info*/ 1105 uint8_t revision_id; /* Revision level */ 1106 uint16_t device_id; /* PCI device ID */ 1107 uint8_t slot_num; /* PCI Slot Number */ 1108 uint16_t subdevice_id; /* Subsystem device ID */ 1109 int ioctl_len; /* size of ioctl buffer */ 1110 dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/ 1111 uint8_t bios_version[8]; /* BIOS Revision */ 1112 uint32_t mem_addr; /* Memory mapped address */ 1113 uint32_t io_len; /* Size of IO Address */ 1114 uint32_t mem_len; /* Size of memory address */ 1115 char __iomem *mem_ptr; /* Memory mapped Ptr */ 1116 char __iomem *ioremap_ptr;/* ioremapped memory pointer */ 1117 ips_hw_func_t func; /* hw function pointers */ 1118 struct pci_dev *pcidev; /* PCI device handle */ 1119 char *flash_data; /* Save Area for flash data */ 1120 int flash_len; /* length of flash buffer */ 1121 u32 flash_datasize; /* Save Area for flash data size */ 1122 dma_addr_t flash_busaddr; /* dma address of flash buffer*/ 1123 dma_addr_t enq_busaddr; /* dma address of enq struct */ 1124 uint8_t requires_esl; /* Requires an EraseStripeLock */ 1125 } ips_ha_t; 1126 1127 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *); 1128 1129 /* 1130 * SCB Format 1131 */ 1132 typedef struct ips_scb { 1133 IPS_HOST_COMMAND cmd; 1134 IPS_DCDB_TABLE dcdb; 1135 uint8_t target_id; 1136 uint8_t bus; 1137 uint8_t lun; 1138 uint8_t cdb[12]; 1139 uint32_t scb_busaddr; 1140 uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility 1141 uint32_t timeout; 1142 uint8_t basic_status; 1143 uint8_t extended_status; 1144 uint8_t breakup; 1145 uint8_t sg_break; 1146 uint32_t data_len; 1147 uint32_t sg_len; 1148 uint32_t flags; 1149 uint32_t op_code; 1150 IPS_SG_LIST sg_list; 1151 Scsi_Cmnd *scsi_cmd; 1152 struct ips_scb *q_next; 1153 ips_scb_callback callback; 1154 uint32_t sg_busaddr; 1155 int sg_count; 1156 dma_addr_t data_busaddr; 1157 } ips_scb_t; 1158 1159 typedef struct ips_scb_pt { 1160 IPS_HOST_COMMAND cmd; 1161 IPS_DCDB_TABLE dcdb; 1162 uint8_t target_id; 1163 uint8_t bus; 1164 uint8_t lun; 1165 uint8_t cdb[12]; 1166 uint32_t scb_busaddr; 1167 uint32_t data_busaddr; 1168 uint32_t timeout; 1169 uint8_t basic_status; 1170 uint8_t extended_status; 1171 uint16_t breakup; 1172 uint32_t data_len; 1173 uint32_t sg_len; 1174 uint32_t flags; 1175 uint32_t op_code; 1176 IPS_SG_LIST *sg_list; 1177 Scsi_Cmnd *scsi_cmd; 1178 struct ips_scb *q_next; 1179 ips_scb_callback callback; 1180 } ips_scb_pt_t; 1181 1182 /* 1183 * Passthru Command Format 1184 */ 1185 typedef struct { 1186 uint8_t CoppID[4]; 1187 uint32_t CoppCmd; 1188 uint32_t PtBuffer; 1189 uint8_t *CmdBuffer; 1190 uint32_t CmdBSize; 1191 ips_scb_pt_t CoppCP; 1192 uint32_t TimeOut; 1193 uint8_t BasicStatus; 1194 uint8_t ExtendedStatus; 1195 uint8_t AdapterType; 1196 uint8_t reserved; 1197 } ips_passthru_t; 1198 1199 #endif 1200 1201 /* The Version Information below gets created by SED during the build process. */ 1202 /* Do not modify the next line; it's what SED is looking for to do the insert. */ 1203 /* Version Info */ 1204 /************************************************************************* 1205 * 1206 * VERSION.H -- version numbers and copyright notices in various formats 1207 * 1208 *************************************************************************/ 1209 1210 #define IPS_VER_MAJOR 7 1211 #define IPS_VER_MAJOR_STRING "7" 1212 #define IPS_VER_MINOR 12 1213 #define IPS_VER_MINOR_STRING "12" 1214 #define IPS_VER_BUILD 02 1215 #define IPS_VER_BUILD_STRING "02" 1216 #define IPS_VER_STRING "7.12.02" 1217 #define IPS_RELEASE_ID 0x00020000 1218 #define IPS_BUILD_IDENT 761 1219 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved." 1220 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved." 1221 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved." 1222 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002." 1223 1224 /* Version numbers for various adapters */ 1225 #define IPS_VER_SERVERAID1 "2.25.01" 1226 #define IPS_VER_SERVERAID2 "2.88.13" 1227 #define IPS_VER_NAVAJO "2.88.13" 1228 #define IPS_VER_SERVERAID3 "6.10.24" 1229 #define IPS_VER_SERVERAID4H "7.12.02" 1230 #define IPS_VER_SERVERAID4MLx "7.12.02" 1231 #define IPS_VER_SARASOTA "7.12.02" 1232 #define IPS_VER_MARCO "7.12.02" 1233 #define IPS_VER_SEBRING "7.12.02" 1234 #define IPS_VER_KEYWEST "7.12.02" 1235 1236 /* Compatability IDs for various adapters */ 1237 #define IPS_COMPAT_UNKNOWN "" 1238 #define IPS_COMPAT_CURRENT "KW710" 1239 #define IPS_COMPAT_SERVERAID1 "2.25.01" 1240 #define IPS_COMPAT_SERVERAID2 "2.88.13" 1241 #define IPS_COMPAT_NAVAJO "2.88.13" 1242 #define IPS_COMPAT_KIOWA "2.88.13" 1243 #define IPS_COMPAT_SERVERAID3H "SB610" 1244 #define IPS_COMPAT_SERVERAID3L "SB610" 1245 #define IPS_COMPAT_SERVERAID4H "KW710" 1246 #define IPS_COMPAT_SERVERAID4M "KW710" 1247 #define IPS_COMPAT_SERVERAID4L "KW710" 1248 #define IPS_COMPAT_SERVERAID4Mx "KW710" 1249 #define IPS_COMPAT_SERVERAID4Lx "KW710" 1250 #define IPS_COMPAT_SARASOTA "KW710" 1251 #define IPS_COMPAT_MARCO "KW710" 1252 #define IPS_COMPAT_SEBRING "KW710" 1253 #define IPS_COMPAT_TAMPA "KW710" 1254 #define IPS_COMPAT_KEYWEST "KW710" 1255 #define IPS_COMPAT_BIOS "KW710" 1256 1257 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18 1258 #define IPS_COMPAT_ID_LENGTH 8 1259 1260 #define IPS_DEFINE_COMPAT_TABLE(tablename) \ 1261 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \ 1262 IPS_COMPAT_UNKNOWN, \ 1263 IPS_COMPAT_SERVERAID1, \ 1264 IPS_COMPAT_SERVERAID2, \ 1265 IPS_COMPAT_NAVAJO, \ 1266 IPS_COMPAT_KIOWA, \ 1267 IPS_COMPAT_SERVERAID3H, \ 1268 IPS_COMPAT_SERVERAID3L, \ 1269 IPS_COMPAT_SERVERAID4H, \ 1270 IPS_COMPAT_SERVERAID4M, \ 1271 IPS_COMPAT_SERVERAID4L, \ 1272 IPS_COMPAT_SERVERAID4Mx, \ 1273 IPS_COMPAT_SERVERAID4Lx, \ 1274 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \ 1275 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \ 1276 IPS_COMPAT_MARCO, \ 1277 IPS_COMPAT_SEBRING, \ 1278 IPS_COMPAT_TAMPA, \ 1279 IPS_COMPAT_KEYWEST \ 1280 } 1281 1282 1283 /* 1284 * Overrides for Emacs so that we almost follow Linus's tabbing style. 1285 * Emacs will notice this stuff at the end of the file and automatically 1286 * adjust the settings for this buffer only. This must remain at the end 1287 * of the file. 1288 * --------------------------------------------------------------------------- 1289 * Local variables: 1290 * c-indent-level: 2 1291 * c-brace-imaginary-offset: 0 1292 * c-brace-offset: -2 1293 * c-argdecl-indent: 2 1294 * c-label-offset: -2 1295 * c-continued-statement-offset: 2 1296 * c-continued-brace-offset: 0 1297 * indent-tabs-mode: nil 1298 * tab-width: 8 1299 * End: 1300 */ 1301