1 /* 2 * ipr.h -- driver for IBM Power Linux RAID adapters 3 * 4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation 5 * 6 * Copyright (C) 2003, 2004 IBM Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors 23 * that broke 64bit platforms. 24 */ 25 26 #ifndef _IPR_H 27 #define _IPR_H 28 29 #include <linux/types.h> 30 #include <linux/completion.h> 31 #include <linux/libata.h> 32 #include <linux/list.h> 33 #include <linux/kref.h> 34 #include <scsi/scsi.h> 35 #include <scsi/scsi_cmnd.h> 36 37 /* 38 * Literals 39 */ 40 #define IPR_DRIVER_VERSION "2.4.3" 41 #define IPR_DRIVER_DATE "(June 10, 2009)" 42 43 /* 44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 45 * ops per device for devices not running tagged command queuing. 46 * This can be adjusted at runtime through sysfs device attributes. 47 */ 48 #define IPR_MAX_CMD_PER_LUN 6 49 #define IPR_MAX_CMD_PER_ATA_LUN 1 50 51 /* 52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of 53 * ops the mid-layer can send to the adapter. 54 */ 55 #define IPR_NUM_BASE_CMD_BLKS 100 56 57 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 58 #define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A 59 60 #define IPR_SUBS_DEV_ID_2780 0x0264 61 #define IPR_SUBS_DEV_ID_5702 0x0266 62 #define IPR_SUBS_DEV_ID_5703 0x0278 63 #define IPR_SUBS_DEV_ID_572E 0x028D 64 #define IPR_SUBS_DEV_ID_573E 0x02D3 65 #define IPR_SUBS_DEV_ID_573D 0x02D4 66 #define IPR_SUBS_DEV_ID_571A 0x02C0 67 #define IPR_SUBS_DEV_ID_571B 0x02BE 68 #define IPR_SUBS_DEV_ID_571E 0x02BF 69 #define IPR_SUBS_DEV_ID_571F 0x02D5 70 #define IPR_SUBS_DEV_ID_572A 0x02C1 71 #define IPR_SUBS_DEV_ID_572B 0x02C2 72 #define IPR_SUBS_DEV_ID_572F 0x02C3 73 #define IPR_SUBS_DEV_ID_574D 0x030B 74 #define IPR_SUBS_DEV_ID_574E 0x030A 75 #define IPR_SUBS_DEV_ID_575B 0x030D 76 #define IPR_SUBS_DEV_ID_575C 0x0338 77 #define IPR_SUBS_DEV_ID_575D 0x033E 78 #define IPR_SUBS_DEV_ID_57B3 0x033A 79 #define IPR_SUBS_DEV_ID_57B7 0x0360 80 #define IPR_SUBS_DEV_ID_57B8 0x02C2 81 82 #define IPR_NAME "ipr" 83 84 /* 85 * Return codes 86 */ 87 #define IPR_RC_JOB_CONTINUE 1 88 #define IPR_RC_JOB_RETURN 2 89 90 /* 91 * IOASCs 92 */ 93 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 94 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 95 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 96 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 97 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 98 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 99 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 100 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF 101 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 102 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 103 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 104 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 105 #define IPR_IOASC_BUS_WAS_RESET 0x06290000 106 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 107 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 108 109 #define IPR_FIRST_DRIVER_IOASC 0x10000000 110 #define IPR_IOASC_IOA_WAS_RESET 0x10000001 111 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 112 113 /* Driver data flags */ 114 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 115 #define IPR_USE_PCI_WARM_RESET 0x00000002 116 117 #define IPR_DEFAULT_MAX_ERROR_DUMP 984 118 #define IPR_NUM_LOG_HCAMS 2 119 #define IPR_NUM_CFG_CHG_HCAMS 2 120 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 121 #define IPR_MAX_NUM_TARGETS_PER_BUS 256 122 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 123 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 124 #define IPR_VSET_BUS 0xff 125 #define IPR_IOA_BUS 0xff 126 #define IPR_IOA_TARGET 0xff 127 #define IPR_IOA_LUN 0xff 128 #define IPR_MAX_NUM_BUSES 16 129 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES 130 131 #define IPR_NUM_RESET_RELOAD_RETRIES 3 132 133 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 134 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 135 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3) 136 137 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS 138 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 139 IPR_NUM_INTERNAL_CMD_BLKS) 140 141 #define IPR_MAX_PHYSICAL_DEVS 192 142 143 #define IPR_MAX_SGLIST 64 144 #define IPR_IOA_MAX_SECTORS 32767 145 #define IPR_VSET_MAX_SECTORS 512 146 #define IPR_MAX_CDB_LEN 16 147 #define IPR_MAX_HRRQ_RETRIES 3 148 149 #define IPR_DEFAULT_BUS_WIDTH 16 150 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 151 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 152 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 153 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) 154 155 #define IPR_IOA_RES_HANDLE 0xffffffff 156 #define IPR_INVALID_RES_HANDLE 0 157 #define IPR_IOA_RES_ADDR 0x00ffffff 158 159 /* 160 * Adapter Commands 161 */ 162 #define IPR_QUERY_RSRC_STATE 0xC2 163 #define IPR_RESET_DEVICE 0xC3 164 #define IPR_RESET_TYPE_SELECT 0x80 165 #define IPR_LUN_RESET 0x40 166 #define IPR_TARGET_RESET 0x20 167 #define IPR_BUS_RESET 0x10 168 #define IPR_ATA_PHY_RESET 0x80 169 #define IPR_ID_HOST_RR_Q 0xC4 170 #define IPR_QUERY_IOA_CONFIG 0xC5 171 #define IPR_CANCEL_ALL_REQUESTS 0xCE 172 #define IPR_HOST_CONTROLLED_ASYNC 0xCF 173 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 174 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 175 #define IPR_SET_SUPPORTED_DEVICES 0xFB 176 #define IPR_IOA_SHUTDOWN 0xF7 177 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 178 179 /* 180 * Timeouts 181 */ 182 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) 183 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) 184 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) 185 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) 186 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 187 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 188 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 189 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 190 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ) 191 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) 192 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) 193 #define IPR_OPERATIONAL_TIMEOUT (5 * 60) 194 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) 195 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) 196 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) 197 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) 198 #define IPR_PCI_RESET_TIMEOUT (HZ / 2) 199 #define IPR_DUMP_TIMEOUT (15 * HZ) 200 201 /* 202 * SCSI Literals 203 */ 204 #define IPR_VENDOR_ID_LEN 8 205 #define IPR_PROD_ID_LEN 16 206 #define IPR_SERIAL_NUM_LEN 8 207 208 /* 209 * Hardware literals 210 */ 211 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff 212 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 213 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 214 #define IPR_GET_FMT2_BAR_SEL(mbx) \ 215 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) 216 #define IPR_SDT_FMT2_BAR0_SEL 0x0 217 #define IPR_SDT_FMT2_BAR1_SEL 0x1 218 #define IPR_SDT_FMT2_BAR2_SEL 0x2 219 #define IPR_SDT_FMT2_BAR3_SEL 0x3 220 #define IPR_SDT_FMT2_BAR4_SEL 0x4 221 #define IPR_SDT_FMT2_BAR5_SEL 0x5 222 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 223 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 224 #define IPR_DOORBELL 0x82800000 225 #define IPR_RUNTIME_RESET 0x40000000 226 227 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 228 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 229 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 230 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) 231 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) 232 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) 233 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) 234 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) 235 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) 236 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) 237 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) 238 239 #define IPR_PCII_ERROR_INTERRUPTS \ 240 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ 241 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) 242 243 #define IPR_PCII_OPER_INTERRUPTS \ 244 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) 245 246 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) 247 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) 248 249 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 250 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 251 252 /* 253 * Dump literals 254 */ 255 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) 256 #define IPR_NUM_SDT_ENTRIES 511 257 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 258 259 /* 260 * Misc literals 261 */ 262 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST 263 264 /* 265 * Adapter interface types 266 */ 267 268 struct ipr_res_addr { 269 u8 reserved; 270 u8 bus; 271 u8 target; 272 u8 lun; 273 #define IPR_GET_PHYS_LOC(res_addr) \ 274 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) 275 }__attribute__((packed, aligned (4))); 276 277 struct ipr_std_inq_vpids { 278 u8 vendor_id[IPR_VENDOR_ID_LEN]; 279 u8 product_id[IPR_PROD_ID_LEN]; 280 }__attribute__((packed)); 281 282 struct ipr_vpd { 283 struct ipr_std_inq_vpids vpids; 284 u8 sn[IPR_SERIAL_NUM_LEN]; 285 }__attribute__((packed)); 286 287 struct ipr_ext_vpd { 288 struct ipr_vpd vpd; 289 __be32 wwid[2]; 290 }__attribute__((packed)); 291 292 struct ipr_std_inq_data { 293 u8 peri_qual_dev_type; 294 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) 295 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) 296 297 u8 removeable_medium_rsvd; 298 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 299 300 #define IPR_IS_DASD_DEVICE(std_inq) \ 301 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ 302 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) 303 304 #define IPR_IS_SES_DEVICE(std_inq) \ 305 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) 306 307 u8 version; 308 u8 aen_naca_fmt; 309 u8 additional_len; 310 u8 sccs_rsvd; 311 u8 bq_enc_multi; 312 u8 sync_cmdq_flags; 313 314 struct ipr_std_inq_vpids vpids; 315 316 u8 ros_rsvd_ram_rsvd[4]; 317 318 u8 serial_num[IPR_SERIAL_NUM_LEN]; 319 }__attribute__ ((packed)); 320 321 struct ipr_config_table_entry { 322 u8 proto; 323 #define IPR_PROTO_SATA 0x02 324 #define IPR_PROTO_SATA_ATAPI 0x03 325 #define IPR_PROTO_SAS_STP 0x06 326 #define IPR_PROTO_SAS_STP_ATAPI 0x07 327 u8 array_id; 328 u8 flags; 329 #define IPR_IS_IOA_RESOURCE 0x80 330 #define IPR_IS_ARRAY_MEMBER 0x20 331 #define IPR_IS_HOT_SPARE 0x10 332 333 u8 rsvd_subtype; 334 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f) 335 #define IPR_SUBTYPE_AF_DASD 0 336 #define IPR_SUBTYPE_GENERIC_SCSI 1 337 #define IPR_SUBTYPE_VOLUME_SET 2 338 #define IPR_SUBTYPE_GENERIC_ATA 4 339 340 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4) 341 #define IPR_QUEUE_FROZEN_MODEL 0 342 #define IPR_QUEUE_NACA_MODEL 1 343 344 struct ipr_res_addr res_addr; 345 __be32 res_handle; 346 __be32 reserved4[2]; 347 struct ipr_std_inq_data std_inq_data; 348 }__attribute__ ((packed, aligned (4))); 349 350 struct ipr_config_table_hdr { 351 u8 num_entries; 352 u8 flags; 353 #define IPR_UCODE_DOWNLOAD_REQ 0x10 354 __be16 reserved; 355 }__attribute__((packed, aligned (4))); 356 357 struct ipr_config_table { 358 struct ipr_config_table_hdr hdr; 359 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS]; 360 }__attribute__((packed, aligned (4))); 361 362 struct ipr_hostrcb_cfg_ch_not { 363 struct ipr_config_table_entry cfgte; 364 u8 reserved[936]; 365 }__attribute__((packed, aligned (4))); 366 367 struct ipr_supported_device { 368 __be16 data_length; 369 u8 reserved; 370 u8 num_records; 371 struct ipr_std_inq_vpids vpids; 372 u8 reserved2[16]; 373 }__attribute__((packed, aligned (4))); 374 375 /* Command packet structure */ 376 struct ipr_cmd_pkt { 377 __be16 reserved; /* Reserved by IOA */ 378 u8 request_type; 379 #define IPR_RQTYPE_SCSICDB 0x00 380 #define IPR_RQTYPE_IOACMD 0x01 381 #define IPR_RQTYPE_HCAM 0x02 382 #define IPR_RQTYPE_ATA_PASSTHRU 0x04 383 384 u8 luntar_luntrn; 385 386 u8 flags_hi; 387 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 388 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 389 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 390 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 391 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 392 393 u8 flags_lo; 394 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 395 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 396 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 397 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 398 #define IPR_FLAGS_LO_ORDERED_TASK 0x04 399 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 400 #define IPR_FLAGS_LO_ACA_TASK 0x08 401 402 u8 cdb[16]; 403 __be16 timeout; 404 }__attribute__ ((packed, aligned(4))); 405 406 struct ipr_ioarcb_ata_regs { 407 u8 flags; 408 #define IPR_ATA_FLAG_PACKET_CMD 0x80 409 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 410 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 411 u8 reserved[3]; 412 413 __be16 data; 414 u8 feature; 415 u8 nsect; 416 u8 lbal; 417 u8 lbam; 418 u8 lbah; 419 u8 device; 420 u8 command; 421 u8 reserved2[3]; 422 u8 hob_feature; 423 u8 hob_nsect; 424 u8 hob_lbal; 425 u8 hob_lbam; 426 u8 hob_lbah; 427 u8 ctl; 428 }__attribute__ ((packed, aligned(4))); 429 430 struct ipr_ioadl_desc { 431 __be32 flags_and_data_len; 432 #define IPR_IOADL_FLAGS_MASK 0xff000000 433 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) 434 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff 435 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) 436 #define IPR_IOADL_FLAGS_READ 0x48000000 437 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 438 #define IPR_IOADL_FLAGS_WRITE 0x68000000 439 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 440 #define IPR_IOADL_FLAGS_LAST 0x01000000 441 442 __be32 address; 443 }__attribute__((packed, aligned (8))); 444 445 struct ipr_ioarcb_add_data { 446 union { 447 struct ipr_ioarcb_ata_regs regs; 448 struct ipr_ioadl_desc ioadl[5]; 449 __be32 add_cmd_parms[10]; 450 }u; 451 }__attribute__ ((packed, aligned(4))); 452 453 /* IOA Request Control Block 128 bytes */ 454 struct ipr_ioarcb { 455 __be32 ioarcb_host_pci_addr; 456 __be32 reserved; 457 __be32 res_handle; 458 __be32 host_response_handle; 459 __be32 reserved1; 460 __be32 reserved2; 461 __be32 reserved3; 462 463 __be32 write_data_transfer_length; 464 __be32 read_data_transfer_length; 465 __be32 write_ioadl_addr; 466 __be32 write_ioadl_len; 467 __be32 read_ioadl_addr; 468 __be32 read_ioadl_len; 469 470 __be32 ioasa_host_pci_addr; 471 __be16 ioasa_len; 472 __be16 reserved4; 473 474 struct ipr_cmd_pkt cmd_pkt; 475 476 __be32 add_cmd_parms_len; 477 struct ipr_ioarcb_add_data add_data; 478 }__attribute__((packed, aligned (4))); 479 480 struct ipr_ioasa_vset { 481 __be32 failing_lba_hi; 482 __be32 failing_lba_lo; 483 __be32 reserved; 484 }__attribute__((packed, aligned (4))); 485 486 struct ipr_ioasa_af_dasd { 487 __be32 failing_lba; 488 __be32 reserved[2]; 489 }__attribute__((packed, aligned (4))); 490 491 struct ipr_ioasa_gpdd { 492 u8 end_state; 493 u8 bus_phase; 494 __be16 reserved; 495 __be32 ioa_data[2]; 496 }__attribute__((packed, aligned (4))); 497 498 struct ipr_ioasa_gata { 499 u8 error; 500 u8 nsect; /* Interrupt reason */ 501 u8 lbal; 502 u8 lbam; 503 u8 lbah; 504 u8 device; 505 u8 status; 506 u8 alt_status; /* ATA CTL */ 507 u8 hob_nsect; 508 u8 hob_lbal; 509 u8 hob_lbam; 510 u8 hob_lbah; 511 }__attribute__((packed, aligned (4))); 512 513 struct ipr_auto_sense { 514 __be16 auto_sense_len; 515 __be16 ioa_data_len; 516 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; 517 }; 518 519 struct ipr_ioasa { 520 __be32 ioasc; 521 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 522 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 523 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 524 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 525 526 __be16 ret_stat_len; /* Length of the returned IOASA */ 527 528 __be16 avail_stat_len; /* Total Length of status available. */ 529 530 __be32 residual_data_len; /* number of bytes in the host data */ 531 /* buffers that were not used by the IOARCB command. */ 532 533 __be32 ilid; 534 #define IPR_NO_ILID 0 535 #define IPR_DRIVER_ILID 0xffffffff 536 537 __be32 fd_ioasc; 538 539 __be32 fd_phys_locator; 540 541 __be32 fd_res_handle; 542 543 __be32 ioasc_specific; /* status code specific field */ 544 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 545 #define IPR_AUTOSENSE_VALID 0x40000000 546 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 547 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff 548 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) 549 #define IPR_FIELD_POINTER_MASK 0x0000ffff 550 551 union { 552 struct ipr_ioasa_vset vset; 553 struct ipr_ioasa_af_dasd dasd; 554 struct ipr_ioasa_gpdd gpdd; 555 struct ipr_ioasa_gata gata; 556 } u; 557 558 struct ipr_auto_sense auto_sense; 559 }__attribute__((packed, aligned (4))); 560 561 struct ipr_mode_parm_hdr { 562 u8 length; 563 u8 medium_type; 564 u8 device_spec_parms; 565 u8 block_desc_len; 566 }__attribute__((packed)); 567 568 struct ipr_mode_pages { 569 struct ipr_mode_parm_hdr hdr; 570 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; 571 }__attribute__((packed)); 572 573 struct ipr_mode_page_hdr { 574 u8 ps_page_code; 575 #define IPR_MODE_PAGE_PS 0x80 576 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) 577 u8 page_length; 578 }__attribute__ ((packed)); 579 580 struct ipr_dev_bus_entry { 581 struct ipr_res_addr res_addr; 582 u8 flags; 583 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 584 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 585 #define IPR_SCSI_ATTR_QAS_MASK 0xC0 586 #define IPR_SCSI_ATTR_ENABLE_TM 0x20 587 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 588 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 589 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 590 591 u8 scsi_id; 592 u8 bus_width; 593 u8 extended_reset_delay; 594 #define IPR_EXTENDED_RESET_DELAY 7 595 596 __be32 max_xfer_rate; 597 598 u8 spinup_delay; 599 u8 reserved3; 600 __be16 reserved4; 601 }__attribute__((packed, aligned (4))); 602 603 struct ipr_mode_page28 { 604 struct ipr_mode_page_hdr hdr; 605 u8 num_entries; 606 u8 entry_length; 607 struct ipr_dev_bus_entry bus[0]; 608 }__attribute__((packed)); 609 610 struct ipr_mode_page24 { 611 struct ipr_mode_page_hdr hdr; 612 u8 flags; 613 #define IPR_ENABLE_DUAL_IOA_AF 0x80 614 }__attribute__((packed)); 615 616 struct ipr_ioa_vpd { 617 struct ipr_std_inq_data std_inq_data; 618 u8 ascii_part_num[12]; 619 u8 reserved[40]; 620 u8 ascii_plant_code[4]; 621 }__attribute__((packed)); 622 623 struct ipr_inquiry_page3 { 624 u8 peri_qual_dev_type; 625 u8 page_code; 626 u8 reserved1; 627 u8 page_length; 628 u8 ascii_len; 629 u8 reserved2[3]; 630 u8 load_id[4]; 631 u8 major_release; 632 u8 card_type; 633 u8 minor_release[2]; 634 u8 ptf_number[4]; 635 u8 patch_number[4]; 636 }__attribute__((packed)); 637 638 struct ipr_inquiry_cap { 639 u8 peri_qual_dev_type; 640 u8 page_code; 641 u8 reserved1; 642 u8 page_length; 643 u8 ascii_len; 644 u8 reserved2; 645 u8 sis_version[2]; 646 u8 cap; 647 #define IPR_CAP_DUAL_IOA_RAID 0x80 648 u8 reserved3[15]; 649 }__attribute__((packed)); 650 651 #define IPR_INQUIRY_PAGE0_ENTRIES 20 652 struct ipr_inquiry_page0 { 653 u8 peri_qual_dev_type; 654 u8 page_code; 655 u8 reserved1; 656 u8 len; 657 u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; 658 }__attribute__((packed)); 659 660 struct ipr_hostrcb_device_data_entry { 661 struct ipr_vpd vpd; 662 struct ipr_res_addr dev_res_addr; 663 struct ipr_vpd new_vpd; 664 struct ipr_vpd ioa_last_with_dev_vpd; 665 struct ipr_vpd cfc_last_with_dev_vpd; 666 __be32 ioa_data[5]; 667 }__attribute__((packed, aligned (4))); 668 669 struct ipr_hostrcb_device_data_entry_enhanced { 670 struct ipr_ext_vpd vpd; 671 u8 ccin[4]; 672 struct ipr_res_addr dev_res_addr; 673 struct ipr_ext_vpd new_vpd; 674 u8 new_ccin[4]; 675 struct ipr_ext_vpd ioa_last_with_dev_vpd; 676 struct ipr_ext_vpd cfc_last_with_dev_vpd; 677 }__attribute__((packed, aligned (4))); 678 679 struct ipr_hostrcb_array_data_entry { 680 struct ipr_vpd vpd; 681 struct ipr_res_addr expected_dev_res_addr; 682 struct ipr_res_addr dev_res_addr; 683 }__attribute__((packed, aligned (4))); 684 685 struct ipr_hostrcb_array_data_entry_enhanced { 686 struct ipr_ext_vpd vpd; 687 u8 ccin[4]; 688 struct ipr_res_addr expected_dev_res_addr; 689 struct ipr_res_addr dev_res_addr; 690 }__attribute__((packed, aligned (4))); 691 692 struct ipr_hostrcb_type_ff_error { 693 __be32 ioa_data[502]; 694 }__attribute__((packed, aligned (4))); 695 696 struct ipr_hostrcb_type_01_error { 697 __be32 seek_counter; 698 __be32 read_counter; 699 u8 sense_data[32]; 700 __be32 ioa_data[236]; 701 }__attribute__((packed, aligned (4))); 702 703 struct ipr_hostrcb_type_02_error { 704 struct ipr_vpd ioa_vpd; 705 struct ipr_vpd cfc_vpd; 706 struct ipr_vpd ioa_last_attached_to_cfc_vpd; 707 struct ipr_vpd cfc_last_attached_to_ioa_vpd; 708 __be32 ioa_data[3]; 709 }__attribute__((packed, aligned (4))); 710 711 struct ipr_hostrcb_type_12_error { 712 struct ipr_ext_vpd ioa_vpd; 713 struct ipr_ext_vpd cfc_vpd; 714 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; 715 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; 716 __be32 ioa_data[3]; 717 }__attribute__((packed, aligned (4))); 718 719 struct ipr_hostrcb_type_03_error { 720 struct ipr_vpd ioa_vpd; 721 struct ipr_vpd cfc_vpd; 722 __be32 errors_detected; 723 __be32 errors_logged; 724 u8 ioa_data[12]; 725 struct ipr_hostrcb_device_data_entry dev[3]; 726 }__attribute__((packed, aligned (4))); 727 728 struct ipr_hostrcb_type_13_error { 729 struct ipr_ext_vpd ioa_vpd; 730 struct ipr_ext_vpd cfc_vpd; 731 __be32 errors_detected; 732 __be32 errors_logged; 733 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 734 }__attribute__((packed, aligned (4))); 735 736 struct ipr_hostrcb_type_04_error { 737 struct ipr_vpd ioa_vpd; 738 struct ipr_vpd cfc_vpd; 739 u8 ioa_data[12]; 740 struct ipr_hostrcb_array_data_entry array_member[10]; 741 __be32 exposed_mode_adn; 742 __be32 array_id; 743 struct ipr_vpd incomp_dev_vpd; 744 __be32 ioa_data2; 745 struct ipr_hostrcb_array_data_entry array_member2[8]; 746 struct ipr_res_addr last_func_vset_res_addr; 747 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 748 u8 protection_level[8]; 749 }__attribute__((packed, aligned (4))); 750 751 struct ipr_hostrcb_type_14_error { 752 struct ipr_ext_vpd ioa_vpd; 753 struct ipr_ext_vpd cfc_vpd; 754 __be32 exposed_mode_adn; 755 __be32 array_id; 756 struct ipr_res_addr last_func_vset_res_addr; 757 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 758 u8 protection_level[8]; 759 __be32 num_entries; 760 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 761 }__attribute__((packed, aligned (4))); 762 763 struct ipr_hostrcb_type_07_error { 764 u8 failure_reason[64]; 765 struct ipr_vpd vpd; 766 u32 data[222]; 767 }__attribute__((packed, aligned (4))); 768 769 struct ipr_hostrcb_type_17_error { 770 u8 failure_reason[64]; 771 struct ipr_ext_vpd vpd; 772 u32 data[476]; 773 }__attribute__((packed, aligned (4))); 774 775 struct ipr_hostrcb_config_element { 776 u8 type_status; 777 #define IPR_PATH_CFG_TYPE_MASK 0xF0 778 #define IPR_PATH_CFG_NOT_EXIST 0x00 779 #define IPR_PATH_CFG_IOA_PORT 0x10 780 #define IPR_PATH_CFG_EXP_PORT 0x20 781 #define IPR_PATH_CFG_DEVICE_PORT 0x30 782 #define IPR_PATH_CFG_DEVICE_LUN 0x40 783 784 #define IPR_PATH_CFG_STATUS_MASK 0x0F 785 #define IPR_PATH_CFG_NO_PROB 0x00 786 #define IPR_PATH_CFG_DEGRADED 0x01 787 #define IPR_PATH_CFG_FAILED 0x02 788 #define IPR_PATH_CFG_SUSPECT 0x03 789 #define IPR_PATH_NOT_DETECTED 0x04 790 #define IPR_PATH_INCORRECT_CONN 0x05 791 792 u8 cascaded_expander; 793 u8 phy; 794 u8 link_rate; 795 #define IPR_PHY_LINK_RATE_MASK 0x0F 796 797 __be32 wwid[2]; 798 }__attribute__((packed, aligned (4))); 799 800 struct ipr_hostrcb_fabric_desc { 801 __be16 length; 802 u8 ioa_port; 803 u8 cascaded_expander; 804 u8 phy; 805 u8 path_state; 806 #define IPR_PATH_ACTIVE_MASK 0xC0 807 #define IPR_PATH_NO_INFO 0x00 808 #define IPR_PATH_ACTIVE 0x40 809 #define IPR_PATH_NOT_ACTIVE 0x80 810 811 #define IPR_PATH_STATE_MASK 0x0F 812 #define IPR_PATH_STATE_NO_INFO 0x00 813 #define IPR_PATH_HEALTHY 0x01 814 #define IPR_PATH_DEGRADED 0x02 815 #define IPR_PATH_FAILED 0x03 816 817 __be16 num_entries; 818 struct ipr_hostrcb_config_element elem[1]; 819 }__attribute__((packed, aligned (4))); 820 821 #define for_each_fabric_cfg(fabric, cfg) \ 822 for (cfg = (fabric)->elem; \ 823 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ 824 cfg++) 825 826 struct ipr_hostrcb_type_20_error { 827 u8 failure_reason[64]; 828 u8 reserved[3]; 829 u8 num_entries; 830 struct ipr_hostrcb_fabric_desc desc[1]; 831 }__attribute__((packed, aligned (4))); 832 833 struct ipr_hostrcb_error { 834 __be32 failing_dev_ioasc; 835 struct ipr_res_addr failing_dev_res_addr; 836 __be32 failing_dev_res_handle; 837 __be32 prc; 838 union { 839 struct ipr_hostrcb_type_ff_error type_ff_error; 840 struct ipr_hostrcb_type_01_error type_01_error; 841 struct ipr_hostrcb_type_02_error type_02_error; 842 struct ipr_hostrcb_type_03_error type_03_error; 843 struct ipr_hostrcb_type_04_error type_04_error; 844 struct ipr_hostrcb_type_07_error type_07_error; 845 struct ipr_hostrcb_type_12_error type_12_error; 846 struct ipr_hostrcb_type_13_error type_13_error; 847 struct ipr_hostrcb_type_14_error type_14_error; 848 struct ipr_hostrcb_type_17_error type_17_error; 849 struct ipr_hostrcb_type_20_error type_20_error; 850 } u; 851 }__attribute__((packed, aligned (4))); 852 853 struct ipr_hostrcb_raw { 854 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 855 }__attribute__((packed, aligned (4))); 856 857 struct ipr_hcam { 858 u8 op_code; 859 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 860 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 861 862 u8 notify_type; 863 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 864 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 865 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 866 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 867 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 868 869 u8 notifications_lost; 870 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 871 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 872 873 u8 flags; 874 #define IPR_HOSTRCB_INTERNAL_OPER 0x80 875 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 876 877 u8 overlay_id; 878 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 879 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 880 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 881 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 882 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 883 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 884 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 885 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 886 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 887 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 888 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 889 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 890 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 891 892 u8 reserved1[3]; 893 __be32 ilid; 894 __be32 time_since_last_ioa_reset; 895 __be32 reserved2; 896 __be32 length; 897 898 union { 899 struct ipr_hostrcb_error error; 900 struct ipr_hostrcb_cfg_ch_not ccn; 901 struct ipr_hostrcb_raw raw; 902 } u; 903 }__attribute__((packed, aligned (4))); 904 905 struct ipr_hostrcb { 906 struct ipr_hcam hcam; 907 dma_addr_t hostrcb_dma; 908 struct list_head queue; 909 struct ipr_ioa_cfg *ioa_cfg; 910 }; 911 912 /* IPR smart dump table structures */ 913 struct ipr_sdt_entry { 914 __be32 bar_str_offset; 915 __be32 end_offset; 916 u8 entry_byte; 917 u8 reserved[3]; 918 919 u8 flags; 920 #define IPR_SDT_ENDIAN 0x80 921 #define IPR_SDT_VALID_ENTRY 0x20 922 923 u8 resv; 924 __be16 priority; 925 }__attribute__((packed, aligned (4))); 926 927 struct ipr_sdt_header { 928 __be32 state; 929 __be32 num_entries; 930 __be32 num_entries_used; 931 __be32 dump_size; 932 }__attribute__((packed, aligned (4))); 933 934 struct ipr_sdt { 935 struct ipr_sdt_header hdr; 936 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES]; 937 }__attribute__((packed, aligned (4))); 938 939 struct ipr_uc_sdt { 940 struct ipr_sdt_header hdr; 941 struct ipr_sdt_entry entry[1]; 942 }__attribute__((packed, aligned (4))); 943 944 /* 945 * Driver types 946 */ 947 struct ipr_bus_attributes { 948 u8 bus; 949 u8 qas_enabled; 950 u8 bus_width; 951 u8 reserved; 952 u32 max_xfer_rate; 953 }; 954 955 struct ipr_sata_port { 956 struct ipr_ioa_cfg *ioa_cfg; 957 struct ata_port *ap; 958 struct ipr_resource_entry *res; 959 struct ipr_ioasa_gata ioasa; 960 }; 961 962 struct ipr_resource_entry { 963 struct ipr_config_table_entry cfgte; 964 u8 needs_sync_complete:1; 965 u8 in_erp:1; 966 u8 add_to_ml:1; 967 u8 del_from_ml:1; 968 u8 resetting_device:1; 969 970 struct scsi_device *sdev; 971 struct ipr_sata_port *sata_port; 972 struct list_head queue; 973 }; 974 975 struct ipr_resource_hdr { 976 u16 num_entries; 977 u16 reserved; 978 }; 979 980 struct ipr_resource_table { 981 struct ipr_resource_hdr hdr; 982 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS]; 983 }; 984 985 struct ipr_misc_cbs { 986 struct ipr_ioa_vpd ioa_vpd; 987 struct ipr_inquiry_page0 page0_data; 988 struct ipr_inquiry_page3 page3_data; 989 struct ipr_inquiry_cap cap; 990 struct ipr_mode_pages mode_pages; 991 struct ipr_supported_device supp_dev; 992 }; 993 994 struct ipr_interrupt_offsets { 995 unsigned long set_interrupt_mask_reg; 996 unsigned long clr_interrupt_mask_reg; 997 unsigned long sense_interrupt_mask_reg; 998 unsigned long clr_interrupt_reg; 999 1000 unsigned long sense_interrupt_reg; 1001 unsigned long ioarrin_reg; 1002 unsigned long sense_uproc_interrupt_reg; 1003 unsigned long set_uproc_interrupt_reg; 1004 unsigned long clr_uproc_interrupt_reg; 1005 }; 1006 1007 struct ipr_interrupts { 1008 void __iomem *set_interrupt_mask_reg; 1009 void __iomem *clr_interrupt_mask_reg; 1010 void __iomem *sense_interrupt_mask_reg; 1011 void __iomem *clr_interrupt_reg; 1012 1013 void __iomem *sense_interrupt_reg; 1014 void __iomem *ioarrin_reg; 1015 void __iomem *sense_uproc_interrupt_reg; 1016 void __iomem *set_uproc_interrupt_reg; 1017 void __iomem *clr_uproc_interrupt_reg; 1018 }; 1019 1020 struct ipr_chip_cfg_t { 1021 u32 mailbox; 1022 u8 cache_line_size; 1023 struct ipr_interrupt_offsets regs; 1024 }; 1025 1026 struct ipr_chip_t { 1027 u16 vendor; 1028 u16 device; 1029 u16 intr_type; 1030 #define IPR_USE_LSI 0x00 1031 #define IPR_USE_MSI 0x01 1032 const struct ipr_chip_cfg_t *cfg; 1033 }; 1034 1035 enum ipr_shutdown_type { 1036 IPR_SHUTDOWN_NORMAL = 0x00, 1037 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, 1038 IPR_SHUTDOWN_ABBREV = 0x80, 1039 IPR_SHUTDOWN_NONE = 0x100 1040 }; 1041 1042 struct ipr_trace_entry { 1043 u32 time; 1044 1045 u8 op_code; 1046 u8 ata_op_code; 1047 u8 type; 1048 #define IPR_TRACE_START 0x00 1049 #define IPR_TRACE_FINISH 0xff 1050 u8 cmd_index; 1051 1052 __be32 res_handle; 1053 union { 1054 u32 ioasc; 1055 u32 add_data; 1056 u32 res_addr; 1057 } u; 1058 }; 1059 1060 struct ipr_sglist { 1061 u32 order; 1062 u32 num_sg; 1063 u32 num_dma_sg; 1064 u32 buffer_len; 1065 struct scatterlist scatterlist[1]; 1066 }; 1067 1068 enum ipr_sdt_state { 1069 INACTIVE, 1070 WAIT_FOR_DUMP, 1071 GET_DUMP, 1072 ABORT_DUMP, 1073 DUMP_OBTAINED 1074 }; 1075 1076 enum ipr_cache_state { 1077 CACHE_NONE, 1078 CACHE_DISABLED, 1079 CACHE_ENABLED, 1080 CACHE_INVALID 1081 }; 1082 1083 /* Per-controller data */ 1084 struct ipr_ioa_cfg { 1085 char eye_catcher[8]; 1086 #define IPR_EYECATCHER "iprcfg" 1087 1088 struct list_head queue; 1089 1090 u8 allow_interrupts:1; 1091 u8 in_reset_reload:1; 1092 u8 in_ioa_bringdown:1; 1093 u8 ioa_unit_checked:1; 1094 u8 ioa_is_dead:1; 1095 u8 dump_taken:1; 1096 u8 allow_cmds:1; 1097 u8 allow_ml_add_del:1; 1098 u8 needs_hard_reset:1; 1099 u8 dual_raid:1; 1100 u8 needs_warm_reset:1; 1101 u8 msi_received:1; 1102 1103 u8 revid; 1104 1105 enum ipr_cache_state cache_state; 1106 u16 type; /* CCIN of the card */ 1107 1108 u8 log_level; 1109 #define IPR_MAX_LOG_LEVEL 4 1110 #define IPR_DEFAULT_LOG_LEVEL 2 1111 1112 #define IPR_NUM_TRACE_INDEX_BITS 8 1113 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) 1114 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) 1115 char trace_start[8]; 1116 #define IPR_TRACE_START_LABEL "trace" 1117 struct ipr_trace_entry *trace; 1118 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS; 1119 1120 /* 1121 * Queue for free command blocks 1122 */ 1123 char ipr_free_label[8]; 1124 #define IPR_FREEQ_LABEL "free-q" 1125 struct list_head free_q; 1126 1127 /* 1128 * Queue for command blocks outstanding to the adapter 1129 */ 1130 char ipr_pending_label[8]; 1131 #define IPR_PENDQ_LABEL "pend-q" 1132 struct list_head pending_q; 1133 1134 char cfg_table_start[8]; 1135 #define IPR_CFG_TBL_START "cfg" 1136 struct ipr_config_table *cfg_table; 1137 dma_addr_t cfg_table_dma; 1138 1139 char resource_table_label[8]; 1140 #define IPR_RES_TABLE_LABEL "res_tbl" 1141 struct ipr_resource_entry *res_entries; 1142 struct list_head free_res_q; 1143 struct list_head used_res_q; 1144 1145 char ipr_hcam_label[8]; 1146 #define IPR_HCAM_LABEL "hcams" 1147 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; 1148 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; 1149 struct list_head hostrcb_free_q; 1150 struct list_head hostrcb_pending_q; 1151 1152 __be32 *host_rrq; 1153 dma_addr_t host_rrq_dma; 1154 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc 1155 #define IPR_HRRQ_RESP_BIT_SET 0x00000002 1156 #define IPR_HRRQ_TOGGLE_BIT 0x00000001 1157 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 1158 volatile __be32 *hrrq_start; 1159 volatile __be32 *hrrq_end; 1160 volatile __be32 *hrrq_curr; 1161 volatile u32 toggle_bit; 1162 1163 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; 1164 1165 unsigned int transop_timeout; 1166 const struct ipr_chip_cfg_t *chip_cfg; 1167 const struct ipr_chip_t *ipr_chip; 1168 1169 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ 1170 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ 1171 void __iomem *ioa_mailbox; 1172 struct ipr_interrupts regs; 1173 1174 u16 saved_pcix_cmd_reg; 1175 u16 reset_retries; 1176 1177 u32 errors_logged; 1178 u32 doorbell; 1179 1180 struct Scsi_Host *host; 1181 struct pci_dev *pdev; 1182 struct ipr_sglist *ucode_sglist; 1183 u8 saved_mode_page_len; 1184 1185 struct work_struct work_q; 1186 1187 wait_queue_head_t reset_wait_q; 1188 wait_queue_head_t msi_wait_q; 1189 1190 struct ipr_dump *dump; 1191 enum ipr_sdt_state sdt_state; 1192 1193 struct ipr_misc_cbs *vpd_cbs; 1194 dma_addr_t vpd_cbs_dma; 1195 1196 struct pci_pool *ipr_cmd_pool; 1197 1198 struct ipr_cmnd *reset_cmd; 1199 int (*reset) (struct ipr_cmnd *); 1200 1201 struct ata_host ata_host; 1202 char ipr_cmd_label[8]; 1203 #define IPR_CMD_LABEL "ipr_cmd" 1204 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; 1205 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; 1206 }; 1207 1208 struct ipr_cmnd { 1209 struct ipr_ioarcb ioarcb; 1210 struct ipr_ioasa ioasa; 1211 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; 1212 struct list_head queue; 1213 struct scsi_cmnd *scsi_cmd; 1214 struct ata_queued_cmd *qc; 1215 struct completion completion; 1216 struct timer_list timer; 1217 void (*done) (struct ipr_cmnd *); 1218 int (*job_step) (struct ipr_cmnd *); 1219 int (*job_step_failed) (struct ipr_cmnd *); 1220 u16 cmd_index; 1221 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1222 dma_addr_t sense_buffer_dma; 1223 unsigned short dma_use_sg; 1224 dma_addr_t dma_handle; 1225 struct ipr_cmnd *sibling; 1226 union { 1227 enum ipr_shutdown_type shutdown_type; 1228 struct ipr_hostrcb *hostrcb; 1229 unsigned long time_left; 1230 unsigned long scratch; 1231 struct ipr_resource_entry *res; 1232 struct scsi_device *sdev; 1233 } u; 1234 1235 struct ipr_ioa_cfg *ioa_cfg; 1236 }; 1237 1238 struct ipr_ses_table_entry { 1239 char product_id[17]; 1240 char compare_product_id_byte[17]; 1241 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ 1242 }; 1243 1244 struct ipr_dump_header { 1245 u32 eye_catcher; 1246 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1247 u32 len; 1248 u32 num_entries; 1249 u32 first_entry_offset; 1250 u32 status; 1251 #define IPR_DUMP_STATUS_SUCCESS 0 1252 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 1253 #define IPR_DUMP_STATUS_FAILED 0xffffffff 1254 u32 os; 1255 #define IPR_DUMP_OS_LINUX 0x4C4E5558 1256 u32 driver_name; 1257 #define IPR_DUMP_DRIVER_NAME 0x49505232 1258 }__attribute__((packed, aligned (4))); 1259 1260 struct ipr_dump_entry_header { 1261 u32 eye_catcher; 1262 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1263 u32 len; 1264 u32 num_elems; 1265 u32 offset; 1266 u32 data_type; 1267 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 1268 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 1269 u32 id; 1270 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 1271 #define IPR_DUMP_LOCATION_ID 0x4C4F4341 1272 #define IPR_DUMP_TRACE_ID 0x54524143 1273 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 1274 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 1275 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 1276 #define IPR_DUMP_PEND_OPS 0x414F5053 1277 u32 status; 1278 }__attribute__((packed, aligned (4))); 1279 1280 struct ipr_dump_location_entry { 1281 struct ipr_dump_entry_header hdr; 1282 u8 location[20]; 1283 }__attribute__((packed)); 1284 1285 struct ipr_dump_trace_entry { 1286 struct ipr_dump_entry_header hdr; 1287 u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; 1288 }__attribute__((packed, aligned (4))); 1289 1290 struct ipr_dump_version_entry { 1291 struct ipr_dump_entry_header hdr; 1292 u8 version[sizeof(IPR_DRIVER_VERSION)]; 1293 }; 1294 1295 struct ipr_dump_ioa_type_entry { 1296 struct ipr_dump_entry_header hdr; 1297 u32 type; 1298 u32 fw_version; 1299 }; 1300 1301 struct ipr_driver_dump { 1302 struct ipr_dump_header hdr; 1303 struct ipr_dump_version_entry version_entry; 1304 struct ipr_dump_location_entry location_entry; 1305 struct ipr_dump_ioa_type_entry ioa_type_entry; 1306 struct ipr_dump_trace_entry trace_entry; 1307 }__attribute__((packed)); 1308 1309 struct ipr_ioa_dump { 1310 struct ipr_dump_entry_header hdr; 1311 struct ipr_sdt sdt; 1312 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES]; 1313 u32 reserved; 1314 u32 next_page_index; 1315 u32 page_offset; 1316 u32 format; 1317 #define IPR_SDT_FMT2 2 1318 #define IPR_SDT_UNKNOWN 3 1319 }__attribute__((packed, aligned (4))); 1320 1321 struct ipr_dump { 1322 struct kref kref; 1323 struct ipr_ioa_cfg *ioa_cfg; 1324 struct ipr_driver_dump driver_dump; 1325 struct ipr_ioa_dump ioa_dump; 1326 }; 1327 1328 struct ipr_error_table_t { 1329 u32 ioasc; 1330 int log_ioasa; 1331 int log_hcam; 1332 char *error; 1333 }; 1334 1335 struct ipr_software_inq_lid_info { 1336 __be32 load_id; 1337 __be32 timestamp[3]; 1338 }__attribute__((packed, aligned (4))); 1339 1340 struct ipr_ucode_image_header { 1341 __be32 header_length; 1342 __be32 lid_table_offset; 1343 u8 major_release; 1344 u8 card_type; 1345 u8 minor_release[2]; 1346 u8 reserved[20]; 1347 char eyecatcher[16]; 1348 __be32 num_lids; 1349 struct ipr_software_inq_lid_info lid[1]; 1350 }__attribute__((packed, aligned (4))); 1351 1352 /* 1353 * Macros 1354 */ 1355 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } 1356 1357 #ifdef CONFIG_SCSI_IPR_TRACE 1358 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1359 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1360 #else 1361 #define ipr_create_trace_file(kobj, attr) 0 1362 #define ipr_remove_trace_file(kobj, attr) do { } while(0) 1363 #endif 1364 1365 #ifdef CONFIG_SCSI_IPR_DUMP 1366 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1367 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1368 #else 1369 #define ipr_create_dump_file(kobj, attr) 0 1370 #define ipr_remove_dump_file(kobj, attr) do { } while(0) 1371 #endif 1372 1373 /* 1374 * Error logging macros 1375 */ 1376 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) 1377 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1378 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1379 1380 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ 1381 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1382 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) 1383 1384 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ 1385 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) 1386 1387 #define ipr_res_err(ioa_cfg, res, fmt, ...) \ 1388 ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__) 1389 1390 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1391 { \ 1392 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1393 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ 1394 } else { \ 1395 ipr_err(fmt": %d:%d:%d:%d\n", \ 1396 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ 1397 (res).bus, (res).target, (res).lun); \ 1398 } \ 1399 } 1400 1401 #define ipr_hcam_err(hostrcb, fmt, ...) \ 1402 { \ 1403 if (ipr_is_device(&(hostrcb)->hcam.u.error.failing_dev_res_addr)) { \ 1404 ipr_ra_err((hostrcb)->ioa_cfg, \ 1405 (hostrcb)->hcam.u.error.failing_dev_res_addr, \ 1406 fmt, ##__VA_ARGS__); \ 1407 } else { \ 1408 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, ##__VA_ARGS__); \ 1409 } \ 1410 } 1411 1412 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1413 __FILE__, __func__, __LINE__) 1414 1415 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) 1416 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) 1417 1418 #define ipr_err_separator \ 1419 ipr_err("----------------------------------------------------------\n") 1420 1421 1422 /* 1423 * Inlines 1424 */ 1425 1426 /** 1427 * ipr_is_ioa_resource - Determine if a resource is the IOA 1428 * @res: resource entry struct 1429 * 1430 * Return value: 1431 * 1 if IOA / 0 if not IOA 1432 **/ 1433 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1434 { 1435 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0; 1436 } 1437 1438 /** 1439 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD 1440 * @res: resource entry struct 1441 * 1442 * Return value: 1443 * 1 if AF DASD / 0 if not AF DASD 1444 **/ 1445 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1446 { 1447 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1448 !ipr_is_ioa_resource(res) && 1449 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD) 1450 return 1; 1451 else 1452 return 0; 1453 } 1454 1455 /** 1456 * ipr_is_vset_device - Determine if a resource is a VSET 1457 * @res: resource entry struct 1458 * 1459 * Return value: 1460 * 1 if VSET / 0 if not VSET 1461 **/ 1462 static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1463 { 1464 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) && 1465 !ipr_is_ioa_resource(res) && 1466 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET) 1467 return 1; 1468 else 1469 return 0; 1470 } 1471 1472 /** 1473 * ipr_is_gscsi - Determine if a resource is a generic scsi resource 1474 * @res: resource entry struct 1475 * 1476 * Return value: 1477 * 1 if GSCSI / 0 if not GSCSI 1478 **/ 1479 static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1480 { 1481 if (!ipr_is_ioa_resource(res) && 1482 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI) 1483 return 1; 1484 else 1485 return 0; 1486 } 1487 1488 /** 1489 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk 1490 * @res: resource entry struct 1491 * 1492 * Return value: 1493 * 1 if SCSI disk / 0 if not SCSI disk 1494 **/ 1495 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) 1496 { 1497 if (ipr_is_af_dasd_device(res) || 1498 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data))) 1499 return 1; 1500 else 1501 return 0; 1502 } 1503 1504 /** 1505 * ipr_is_gata - Determine if a resource is a generic ATA resource 1506 * @res: resource entry struct 1507 * 1508 * Return value: 1509 * 1 if GATA / 0 if not GATA 1510 **/ 1511 static inline int ipr_is_gata(struct ipr_resource_entry *res) 1512 { 1513 if (!ipr_is_ioa_resource(res) && 1514 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_ATA) 1515 return 1; 1516 else 1517 return 0; 1518 } 1519 1520 /** 1521 * ipr_is_naca_model - Determine if a resource is using NACA queueing model 1522 * @res: resource entry struct 1523 * 1524 * Return value: 1525 * 1 if NACA queueing model / 0 if not NACA queueing model 1526 **/ 1527 static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1528 { 1529 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL) 1530 return 1; 1531 return 0; 1532 } 1533 1534 /** 1535 * ipr_is_device - Determine if resource address is that of a device 1536 * @res_addr: resource address struct 1537 * 1538 * Return value: 1539 * 1 if AF / 0 if not AF 1540 **/ 1541 static inline int ipr_is_device(struct ipr_res_addr *res_addr) 1542 { 1543 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1544 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1545 return 1; 1546 1547 return 0; 1548 } 1549 1550 /** 1551 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 1552 * @sdt_word: SDT address 1553 * 1554 * Return value: 1555 * 1 if format 2 / 0 if not 1556 **/ 1557 static inline int ipr_sdt_is_fmt2(u32 sdt_word) 1558 { 1559 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); 1560 1561 switch (bar_sel) { 1562 case IPR_SDT_FMT2_BAR0_SEL: 1563 case IPR_SDT_FMT2_BAR1_SEL: 1564 case IPR_SDT_FMT2_BAR2_SEL: 1565 case IPR_SDT_FMT2_BAR3_SEL: 1566 case IPR_SDT_FMT2_BAR4_SEL: 1567 case IPR_SDT_FMT2_BAR5_SEL: 1568 case IPR_SDT_FMT2_EXP_ROM_SEL: 1569 return 1; 1570 }; 1571 1572 return 0; 1573 } 1574 1575 #endif 1576