1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_CMD_H 22 #define HPSA_CMD_H 23 24 /* general boundary defintions */ 25 #define SENSEINFOBYTES 32 /* may vary between hbas */ 26 #define MAXSGENTRIES 32 27 #define HPSA_SG_CHAIN 0x80000000 28 #define MAXREPLYQS 256 29 30 /* Command Status value */ 31 #define CMD_SUCCESS 0x0000 32 #define CMD_TARGET_STATUS 0x0001 33 #define CMD_DATA_UNDERRUN 0x0002 34 #define CMD_DATA_OVERRUN 0x0003 35 #define CMD_INVALID 0x0004 36 #define CMD_PROTOCOL_ERR 0x0005 37 #define CMD_HARDWARE_ERR 0x0006 38 #define CMD_CONNECTION_LOST 0x0007 39 #define CMD_ABORTED 0x0008 40 #define CMD_ABORT_FAILED 0x0009 41 #define CMD_UNSOLICITED_ABORT 0x000A 42 #define CMD_TIMEOUT 0x000B 43 #define CMD_UNABORTABLE 0x000C 44 45 /* Unit Attentions ASC's as defined for the MSA2012sa */ 46 #define POWER_OR_RESET 0x29 47 #define STATE_CHANGED 0x2a 48 #define UNIT_ATTENTION_CLEARED 0x2f 49 #define LUN_FAILED 0x3e 50 #define REPORT_LUNS_CHANGED 0x3f 51 52 /* Unit Attentions ASCQ's as defined for the MSA2012sa */ 53 54 /* These ASCQ's defined for ASC = POWER_OR_RESET */ 55 #define POWER_ON_RESET 0x00 56 #define POWER_ON_REBOOT 0x01 57 #define SCSI_BUS_RESET 0x02 58 #define MSA_TARGET_RESET 0x03 59 #define CONTROLLER_FAILOVER 0x04 60 #define TRANSCEIVER_SE 0x05 61 #define TRANSCEIVER_LVD 0x06 62 63 /* These ASCQ's defined for ASC = STATE_CHANGED */ 64 #define RESERVATION_PREEMPTED 0x03 65 #define ASYM_ACCESS_CHANGED 0x06 66 #define LUN_CAPACITY_CHANGED 0x09 67 68 /* transfer direction */ 69 #define XFER_NONE 0x00 70 #define XFER_WRITE 0x01 71 #define XFER_READ 0x02 72 #define XFER_RSVD 0x03 73 74 /* task attribute */ 75 #define ATTR_UNTAGGED 0x00 76 #define ATTR_SIMPLE 0x04 77 #define ATTR_HEADOFQUEUE 0x05 78 #define ATTR_ORDERED 0x06 79 #define ATTR_ACA 0x07 80 81 /* cdb type */ 82 #define TYPE_CMD 0x00 83 #define TYPE_MSG 0x01 84 85 /* config space register offsets */ 86 #define CFG_VENDORID 0x00 87 #define CFG_DEVICEID 0x02 88 #define CFG_I2OBAR 0x10 89 #define CFG_MEM1BAR 0x14 90 91 /* i2o space register offsets */ 92 #define I2O_IBDB_SET 0x20 93 #define I2O_IBDB_CLEAR 0x70 94 #define I2O_INT_STATUS 0x30 95 #define I2O_INT_MASK 0x34 96 #define I2O_IBPOST_Q 0x40 97 #define I2O_OBPOST_Q 0x44 98 #define I2O_DMA1_CFG 0x214 99 100 /* Configuration Table */ 101 #define CFGTBL_ChangeReq 0x00000001l 102 #define CFGTBL_AccCmds 0x00000001l 103 #define DOORBELL_CTLR_RESET 0x00000004l 104 105 #define CFGTBL_Trans_Simple 0x00000002l 106 #define CFGTBL_Trans_Performant 0x00000004l 107 #define CFGTBL_Trans_use_short_tags 0x20000000l 108 109 #define CFGTBL_BusType_Ultra2 0x00000001l 110 #define CFGTBL_BusType_Ultra3 0x00000002l 111 #define CFGTBL_BusType_Fibre1G 0x00000100l 112 #define CFGTBL_BusType_Fibre2G 0x00000200l 113 struct vals32 { 114 u32 lower; 115 u32 upper; 116 }; 117 118 union u64bit { 119 struct vals32 val32; 120 u64 val; 121 }; 122 123 /* FIXME this is a per controller value (barf!) */ 124 #define HPSA_MAX_TARGETS_PER_CTLR 16 125 #define HPSA_MAX_LUN 256 126 #define HPSA_MAX_PHYS_LUN 1024 127 128 /* SCSI-3 Commands */ 129 #pragma pack(1) 130 131 #define HPSA_INQUIRY 0x12 132 struct InquiryData { 133 u8 data_byte[36]; 134 }; 135 136 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 137 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 138 struct ReportLUNdata { 139 u8 LUNListLength[4]; 140 u32 reserved; 141 u8 LUN[HPSA_MAX_LUN][8]; 142 }; 143 144 struct ReportExtendedLUNdata { 145 u8 LUNListLength[4]; 146 u8 extended_response_flag; 147 u8 reserved[3]; 148 u8 LUN[HPSA_MAX_LUN][24]; 149 }; 150 151 struct SenseSubsystem_info { 152 u8 reserved[36]; 153 u8 portname[8]; 154 u8 reserved1[1108]; 155 }; 156 157 /* BMIC commands */ 158 #define BMIC_READ 0x26 159 #define BMIC_WRITE 0x27 160 #define BMIC_CACHE_FLUSH 0xc2 161 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 162 163 /* Command List Structure */ 164 union SCSI3Addr { 165 struct { 166 u8 Dev; 167 u8 Bus:6; 168 u8 Mode:2; /* b00 */ 169 } PeripDev; 170 struct { 171 u8 DevLSB; 172 u8 DevMSB:6; 173 u8 Mode:2; /* b01 */ 174 } LogDev; 175 struct { 176 u8 Dev:5; 177 u8 Bus:3; 178 u8 Targ:6; 179 u8 Mode:2; /* b10 */ 180 } LogUnit; 181 }; 182 183 struct PhysDevAddr { 184 u32 TargetId:24; 185 u32 Bus:6; 186 u32 Mode:2; 187 /* 2 level target device addr */ 188 union SCSI3Addr Target[2]; 189 }; 190 191 struct LogDevAddr { 192 u32 VolId:30; 193 u32 Mode:2; 194 u8 reserved[4]; 195 }; 196 197 union LUNAddr { 198 u8 LunAddrBytes[8]; 199 union SCSI3Addr SCSI3Lun[4]; 200 struct PhysDevAddr PhysDev; 201 struct LogDevAddr LogDev; 202 }; 203 204 struct CommandListHeader { 205 u8 ReplyQueue; 206 u8 SGList; 207 u16 SGTotal; 208 struct vals32 Tag; 209 union LUNAddr LUN; 210 }; 211 212 struct RequestBlock { 213 u8 CDBLen; 214 struct { 215 u8 Type:3; 216 u8 Attribute:3; 217 u8 Direction:2; 218 } Type; 219 u16 Timeout; 220 u8 CDB[16]; 221 }; 222 223 struct ErrDescriptor { 224 struct vals32 Addr; 225 u32 Len; 226 }; 227 228 struct SGDescriptor { 229 struct vals32 Addr; 230 u32 Len; 231 u32 Ext; 232 }; 233 234 union MoreErrInfo { 235 struct { 236 u8 Reserved[3]; 237 u8 Type; 238 u32 ErrorInfo; 239 } Common_Info; 240 struct { 241 u8 Reserved[2]; 242 u8 offense_size; /* size of offending entry */ 243 u8 offense_num; /* byte # of offense 0-base */ 244 u32 offense_value; 245 } Invalid_Cmd; 246 }; 247 struct ErrorInfo { 248 u8 ScsiStatus; 249 u8 SenseLen; 250 u16 CommandStatus; 251 u32 ResidualCnt; 252 union MoreErrInfo MoreErrInfo; 253 u8 SenseInfo[SENSEINFOBYTES]; 254 }; 255 /* Command types */ 256 #define CMD_IOCTL_PEND 0x01 257 #define CMD_SCSI 0x03 258 259 #define DIRECT_LOOKUP_SHIFT 5 260 #define DIRECT_LOOKUP_BIT 0x10 261 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) 262 263 #define HPSA_ERROR_BIT 0x02 264 struct ctlr_info; /* defined in hpsa.h */ 265 /* The size of this structure needs to be divisible by 32 266 * on all architectures because low 5 bits of the addresses 267 * are used as follows: 268 * 269 * bit 0: to device, used to indicate "performant mode" command 270 * from device, indidcates error status. 271 * bit 1-3: to device, indicates block fetch table entry for 272 * reducing DMA in fetching commands from host memory. 273 * bit 4: used to indicate whether tag is "direct lookup" (index), 274 * or a bus address. 275 */ 276 277 struct CommandList { 278 struct CommandListHeader Header; 279 struct RequestBlock Request; 280 struct ErrDescriptor ErrDesc; 281 struct SGDescriptor SG[MAXSGENTRIES]; 282 /* information associated with the command */ 283 u32 busaddr; /* physical addr of this record */ 284 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 285 struct ctlr_info *h; 286 int cmd_type; 287 long cmdindex; 288 struct list_head list; 289 struct request *rq; 290 struct completion *waiting; 291 void *scsi_cmd; 292 293 /* on 64 bit architectures, to get this to be 32-byte-aligned 294 * it so happens we need PAD_64 bytes of padding, on 32 bit systems, 295 * we need PAD_32 bytes of padding (see below). This does that. 296 * If it happens that 64 bit and 32 bit systems need different 297 * padding, PAD_32 and PAD_64 can be set independently, and. 298 * the code below will do the right thing. 299 */ 300 #define IS_32_BIT ((8 - sizeof(long))/4) 301 #define IS_64_BIT (!IS_32_BIT) 302 #define PAD_32 (4) 303 #define PAD_64 (4) 304 #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) 305 u8 pad[COMMANDLIST_PAD]; 306 }; 307 308 /* Configuration Table Structure */ 309 struct HostWrite { 310 u32 TransportRequest; 311 u32 Reserved; 312 u32 CoalIntDelay; 313 u32 CoalIntCount; 314 }; 315 316 #define SIMPLE_MODE 0x02 317 #define PERFORMANT_MODE 0x04 318 #define MEMQ_MODE 0x08 319 320 struct CfgTable { 321 u8 Signature[4]; 322 u32 SpecValence; 323 u32 TransportSupport; 324 u32 TransportActive; 325 struct HostWrite HostWrite; 326 u32 CmdsOutMax; 327 u32 BusTypes; 328 u32 TransMethodOffset; 329 u8 ServerName[16]; 330 u32 HeartBeat; 331 u32 SCSI_Prefetch; 332 u32 MaxScatterGatherElements; 333 u32 MaxLogicalUnits; 334 u32 MaxPhysicalDevices; 335 u32 MaxPhysicalDrivesPerLogicalUnit; 336 u32 MaxPerformantModeCommands; 337 u8 reserved[0x78 - 0x58]; 338 u32 misc_fw_support; /* offset 0x78 */ 339 #define MISC_FW_DOORBELL_RESET (0x02) 340 }; 341 342 #define NUM_BLOCKFETCH_ENTRIES 8 343 struct TransTable_struct { 344 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 345 u32 RepQSize; 346 u32 RepQCount; 347 u32 RepQCtrAddrLow32; 348 u32 RepQCtrAddrHigh32; 349 u32 RepQAddr0Low32; 350 u32 RepQAddr0High32; 351 }; 352 353 struct hpsa_pci_info { 354 unsigned char bus; 355 unsigned char dev_fn; 356 unsigned short domain; 357 u32 board_id; 358 }; 359 360 #pragma pack() 361 #endif /* HPSA_CMD_H */ 362