1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2016 Microsemi Corporation 4 * Copyright 2014-2015 PMC-Sierra, Inc. 5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14 * NON INFRINGEMENT. See the GNU General Public License for more details. 15 * 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/types.h> 23 #include <linux/pci.h> 24 #include <linux/pci-aspm.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/delay.h> 28 #include <linux/fs.h> 29 #include <linux/timer.h> 30 #include <linux/init.h> 31 #include <linux/spinlock.h> 32 #include <linux/compat.h> 33 #include <linux/blktrace_api.h> 34 #include <linux/uaccess.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/completion.h> 38 #include <linux/moduleparam.h> 39 #include <scsi/scsi.h> 40 #include <scsi/scsi_cmnd.h> 41 #include <scsi/scsi_device.h> 42 #include <scsi/scsi_host.h> 43 #include <scsi/scsi_tcq.h> 44 #include <scsi/scsi_eh.h> 45 #include <scsi/scsi_transport_sas.h> 46 #include <scsi/scsi_dbg.h> 47 #include <linux/cciss_ioctl.h> 48 #include <linux/string.h> 49 #include <linux/bitmap.h> 50 #include <linux/atomic.h> 51 #include <linux/jiffies.h> 52 #include <linux/percpu-defs.h> 53 #include <linux/percpu.h> 54 #include <asm/unaligned.h> 55 #include <asm/div64.h> 56 #include "hpsa_cmd.h" 57 #include "hpsa.h" 58 59 /* 60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' 61 * with an optional trailing '-' followed by a byte value (0-255). 62 */ 63 #define HPSA_DRIVER_VERSION "3.4.20-0" 64 #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" 65 #define HPSA "hpsa" 66 67 /* How long to wait for CISS doorbell communication */ 68 #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ 69 #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ 70 #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ 71 #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ 72 #define MAX_IOCTL_CONFIG_WAIT 1000 73 74 /*define how many times we will try a command because of bus resets */ 75 #define MAX_CMD_RETRIES 3 76 77 /* Embedded module documentation macros - see modules.h */ 78 MODULE_AUTHOR("Hewlett-Packard Company"); 79 MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ 80 HPSA_DRIVER_VERSION); 81 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); 82 MODULE_VERSION(HPSA_DRIVER_VERSION); 83 MODULE_LICENSE("GPL"); 84 MODULE_ALIAS("cciss"); 85 86 static int hpsa_simple_mode; 87 module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); 88 MODULE_PARM_DESC(hpsa_simple_mode, 89 "Use 'simple mode' rather than 'performant mode'"); 90 91 /* define the PCI info for the cards we can control */ 92 static const struct pci_device_id hpsa_pci_device_id[] = { 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, 105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, 107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920}, 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925}, 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, 116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, 118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, 129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, 130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, 132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, 133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, 134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, 135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, 138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, 139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, 140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, 141 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, 143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, 144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, 145 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, 146 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 147 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 148 {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 149 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 150 {0,} 151 }; 152 153 MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); 154 155 /* board_id = Subsystem Device ID & Vendor ID 156 * product = Marketing Name for the board 157 * access = Address of the struct of function pointers 158 */ 159 static struct board_type products[] = { 160 {0x40700E11, "Smart Array 5300", &SA5A_access}, 161 {0x40800E11, "Smart Array 5i", &SA5B_access}, 162 {0x40820E11, "Smart Array 532", &SA5B_access}, 163 {0x40830E11, "Smart Array 5312", &SA5B_access}, 164 {0x409A0E11, "Smart Array 641", &SA5A_access}, 165 {0x409B0E11, "Smart Array 642", &SA5A_access}, 166 {0x409C0E11, "Smart Array 6400", &SA5A_access}, 167 {0x409D0E11, "Smart Array 6400 EM", &SA5A_access}, 168 {0x40910E11, "Smart Array 6i", &SA5A_access}, 169 {0x3225103C, "Smart Array P600", &SA5A_access}, 170 {0x3223103C, "Smart Array P800", &SA5A_access}, 171 {0x3234103C, "Smart Array P400", &SA5A_access}, 172 {0x3235103C, "Smart Array P400i", &SA5A_access}, 173 {0x3211103C, "Smart Array E200i", &SA5A_access}, 174 {0x3212103C, "Smart Array E200", &SA5A_access}, 175 {0x3213103C, "Smart Array E200i", &SA5A_access}, 176 {0x3214103C, "Smart Array E200i", &SA5A_access}, 177 {0x3215103C, "Smart Array E200i", &SA5A_access}, 178 {0x3237103C, "Smart Array E500", &SA5A_access}, 179 {0x323D103C, "Smart Array P700m", &SA5A_access}, 180 {0x3241103C, "Smart Array P212", &SA5_access}, 181 {0x3243103C, "Smart Array P410", &SA5_access}, 182 {0x3245103C, "Smart Array P410i", &SA5_access}, 183 {0x3247103C, "Smart Array P411", &SA5_access}, 184 {0x3249103C, "Smart Array P812", &SA5_access}, 185 {0x324A103C, "Smart Array P712m", &SA5_access}, 186 {0x324B103C, "Smart Array P711m", &SA5_access}, 187 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ 188 {0x3350103C, "Smart Array P222", &SA5_access}, 189 {0x3351103C, "Smart Array P420", &SA5_access}, 190 {0x3352103C, "Smart Array P421", &SA5_access}, 191 {0x3353103C, "Smart Array P822", &SA5_access}, 192 {0x3354103C, "Smart Array P420i", &SA5_access}, 193 {0x3355103C, "Smart Array P220i", &SA5_access}, 194 {0x3356103C, "Smart Array P721m", &SA5_access}, 195 {0x1920103C, "Smart Array P430i", &SA5_access}, 196 {0x1921103C, "Smart Array P830i", &SA5_access}, 197 {0x1922103C, "Smart Array P430", &SA5_access}, 198 {0x1923103C, "Smart Array P431", &SA5_access}, 199 {0x1924103C, "Smart Array P830", &SA5_access}, 200 {0x1925103C, "Smart Array P831", &SA5_access}, 201 {0x1926103C, "Smart Array P731m", &SA5_access}, 202 {0x1928103C, "Smart Array P230i", &SA5_access}, 203 {0x1929103C, "Smart Array P530", &SA5_access}, 204 {0x21BD103C, "Smart Array P244br", &SA5_access}, 205 {0x21BE103C, "Smart Array P741m", &SA5_access}, 206 {0x21BF103C, "Smart HBA H240ar", &SA5_access}, 207 {0x21C0103C, "Smart Array P440ar", &SA5_access}, 208 {0x21C1103C, "Smart Array P840ar", &SA5_access}, 209 {0x21C2103C, "Smart Array P440", &SA5_access}, 210 {0x21C3103C, "Smart Array P441", &SA5_access}, 211 {0x21C4103C, "Smart Array", &SA5_access}, 212 {0x21C5103C, "Smart Array P841", &SA5_access}, 213 {0x21C6103C, "Smart HBA H244br", &SA5_access}, 214 {0x21C7103C, "Smart HBA H240", &SA5_access}, 215 {0x21C8103C, "Smart HBA H241", &SA5_access}, 216 {0x21C9103C, "Smart Array", &SA5_access}, 217 {0x21CA103C, "Smart Array P246br", &SA5_access}, 218 {0x21CB103C, "Smart Array P840", &SA5_access}, 219 {0x21CC103C, "Smart Array", &SA5_access}, 220 {0x21CD103C, "Smart Array", &SA5_access}, 221 {0x21CE103C, "Smart HBA", &SA5_access}, 222 {0x05809005, "SmartHBA-SA", &SA5_access}, 223 {0x05819005, "SmartHBA-SA 8i", &SA5_access}, 224 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, 225 {0x05839005, "SmartHBA-SA 8e", &SA5_access}, 226 {0x05849005, "SmartHBA-SA 16i", &SA5_access}, 227 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, 228 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, 229 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, 230 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, 231 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, 232 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, 233 {0xFFFF103C, "Unknown Smart Array", &SA5_access}, 234 }; 235 236 static struct scsi_transport_template *hpsa_sas_transport_template; 237 static int hpsa_add_sas_host(struct ctlr_info *h); 238 static void hpsa_delete_sas_host(struct ctlr_info *h); 239 static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 240 struct hpsa_scsi_dev_t *device); 241 static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); 242 static struct hpsa_scsi_dev_t 243 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 244 struct sas_rphy *rphy); 245 246 #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) 247 static const struct scsi_cmnd hpsa_cmd_busy; 248 #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) 249 static const struct scsi_cmnd hpsa_cmd_idle; 250 static int number_of_controllers; 251 252 static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); 253 static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); 254 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg); 255 256 #ifdef CONFIG_COMPAT 257 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, 258 void __user *arg); 259 #endif 260 261 static void cmd_free(struct ctlr_info *h, struct CommandList *c); 262 static struct CommandList *cmd_alloc(struct ctlr_info *h); 263 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); 264 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 265 struct scsi_cmnd *scmd); 266 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 267 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 268 int cmd_type); 269 static void hpsa_free_cmd_pool(struct ctlr_info *h); 270 #define VPD_PAGE (1 << 8) 271 #define HPSA_SIMPLE_ERROR_BITS 0x03 272 273 static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 274 static void hpsa_scan_start(struct Scsi_Host *); 275 static int hpsa_scan_finished(struct Scsi_Host *sh, 276 unsigned long elapsed_time); 277 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); 278 279 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); 280 static int hpsa_slave_alloc(struct scsi_device *sdev); 281 static int hpsa_slave_configure(struct scsi_device *sdev); 282 static void hpsa_slave_destroy(struct scsi_device *sdev); 283 284 static void hpsa_update_scsi_devices(struct ctlr_info *h); 285 static int check_for_unit_attention(struct ctlr_info *h, 286 struct CommandList *c); 287 static void check_ioctl_unit_attention(struct ctlr_info *h, 288 struct CommandList *c); 289 /* performant mode helper functions */ 290 static void calc_bucket_map(int *bucket, int num_buckets, 291 int nsgs, int min_blocks, u32 *bucket_map); 292 static void hpsa_free_performant_mode(struct ctlr_info *h); 293 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); 294 static inline u32 next_command(struct ctlr_info *h, u8 q); 295 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 296 u32 *cfg_base_addr, u64 *cfg_base_addr_index, 297 u64 *cfg_offset); 298 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 299 unsigned long *memory_bar); 300 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 301 bool *legacy_board); 302 static int wait_for_device_to_become_ready(struct ctlr_info *h, 303 unsigned char lunaddr[], 304 int reply_queue); 305 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 306 int wait_for_ready); 307 static inline void finish_cmd(struct CommandList *c); 308 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); 309 #define BOARD_NOT_READY 0 310 #define BOARD_READY 1 311 static void hpsa_drain_accel_commands(struct ctlr_info *h); 312 static void hpsa_flush_cache(struct ctlr_info *h); 313 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 314 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 315 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); 316 static void hpsa_command_resubmit_worker(struct work_struct *work); 317 static u32 lockup_detected(struct ctlr_info *h); 318 static int detect_controller_lockup(struct ctlr_info *h); 319 static void hpsa_disable_rld_caching(struct ctlr_info *h); 320 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 321 struct ReportExtendedLUNdata *buf, int bufsize); 322 static bool hpsa_vpd_page_supported(struct ctlr_info *h, 323 unsigned char scsi3addr[], u8 page); 324 static int hpsa_luns_changed(struct ctlr_info *h); 325 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 326 struct hpsa_scsi_dev_t *dev, 327 unsigned char *scsi3addr); 328 329 static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) 330 { 331 unsigned long *priv = shost_priv(sdev->host); 332 return (struct ctlr_info *) *priv; 333 } 334 335 static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) 336 { 337 unsigned long *priv = shost_priv(sh); 338 return (struct ctlr_info *) *priv; 339 } 340 341 static inline bool hpsa_is_cmd_idle(struct CommandList *c) 342 { 343 return c->scsi_cmd == SCSI_CMD_IDLE; 344 } 345 346 static inline bool hpsa_is_pending_event(struct CommandList *c) 347 { 348 return c->reset_pending; 349 } 350 351 /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ 352 static void decode_sense_data(const u8 *sense_data, int sense_data_len, 353 u8 *sense_key, u8 *asc, u8 *ascq) 354 { 355 struct scsi_sense_hdr sshdr; 356 bool rc; 357 358 *sense_key = -1; 359 *asc = -1; 360 *ascq = -1; 361 362 if (sense_data_len < 1) 363 return; 364 365 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); 366 if (rc) { 367 *sense_key = sshdr.sense_key; 368 *asc = sshdr.asc; 369 *ascq = sshdr.ascq; 370 } 371 } 372 373 static int check_for_unit_attention(struct ctlr_info *h, 374 struct CommandList *c) 375 { 376 u8 sense_key, asc, ascq; 377 int sense_len; 378 379 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 380 sense_len = sizeof(c->err_info->SenseInfo); 381 else 382 sense_len = c->err_info->SenseLen; 383 384 decode_sense_data(c->err_info->SenseInfo, sense_len, 385 &sense_key, &asc, &ascq); 386 if (sense_key != UNIT_ATTENTION || asc == 0xff) 387 return 0; 388 389 switch (asc) { 390 case STATE_CHANGED: 391 dev_warn(&h->pdev->dev, 392 "%s: a state change detected, command retried\n", 393 h->devname); 394 break; 395 case LUN_FAILED: 396 dev_warn(&h->pdev->dev, 397 "%s: LUN failure detected\n", h->devname); 398 break; 399 case REPORT_LUNS_CHANGED: 400 dev_warn(&h->pdev->dev, 401 "%s: report LUN data changed\n", h->devname); 402 /* 403 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external 404 * target (array) devices. 405 */ 406 break; 407 case POWER_OR_RESET: 408 dev_warn(&h->pdev->dev, 409 "%s: a power on or device reset detected\n", 410 h->devname); 411 break; 412 case UNIT_ATTENTION_CLEARED: 413 dev_warn(&h->pdev->dev, 414 "%s: unit attention cleared by another initiator\n", 415 h->devname); 416 break; 417 default: 418 dev_warn(&h->pdev->dev, 419 "%s: unknown unit attention detected\n", 420 h->devname); 421 break; 422 } 423 return 1; 424 } 425 426 static int check_for_busy(struct ctlr_info *h, struct CommandList *c) 427 { 428 if (c->err_info->CommandStatus != CMD_TARGET_STATUS || 429 (c->err_info->ScsiStatus != SAM_STAT_BUSY && 430 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) 431 return 0; 432 dev_warn(&h->pdev->dev, HPSA "device busy"); 433 return 1; 434 } 435 436 static u32 lockup_detected(struct ctlr_info *h); 437 static ssize_t host_show_lockup_detected(struct device *dev, 438 struct device_attribute *attr, char *buf) 439 { 440 int ld; 441 struct ctlr_info *h; 442 struct Scsi_Host *shost = class_to_shost(dev); 443 444 h = shost_to_hba(shost); 445 ld = lockup_detected(h); 446 447 return sprintf(buf, "ld=%d\n", ld); 448 } 449 450 static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, 451 struct device_attribute *attr, 452 const char *buf, size_t count) 453 { 454 int status, len; 455 struct ctlr_info *h; 456 struct Scsi_Host *shost = class_to_shost(dev); 457 char tmpbuf[10]; 458 459 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 460 return -EACCES; 461 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 462 strncpy(tmpbuf, buf, len); 463 tmpbuf[len] = '\0'; 464 if (sscanf(tmpbuf, "%d", &status) != 1) 465 return -EINVAL; 466 h = shost_to_hba(shost); 467 h->acciopath_status = !!status; 468 dev_warn(&h->pdev->dev, 469 "hpsa: HP SSD Smart Path %s via sysfs update.\n", 470 h->acciopath_status ? "enabled" : "disabled"); 471 return count; 472 } 473 474 static ssize_t host_store_raid_offload_debug(struct device *dev, 475 struct device_attribute *attr, 476 const char *buf, size_t count) 477 { 478 int debug_level, len; 479 struct ctlr_info *h; 480 struct Scsi_Host *shost = class_to_shost(dev); 481 char tmpbuf[10]; 482 483 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 484 return -EACCES; 485 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 486 strncpy(tmpbuf, buf, len); 487 tmpbuf[len] = '\0'; 488 if (sscanf(tmpbuf, "%d", &debug_level) != 1) 489 return -EINVAL; 490 if (debug_level < 0) 491 debug_level = 0; 492 h = shost_to_hba(shost); 493 h->raid_offload_debug = debug_level; 494 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", 495 h->raid_offload_debug); 496 return count; 497 } 498 499 static ssize_t host_store_rescan(struct device *dev, 500 struct device_attribute *attr, 501 const char *buf, size_t count) 502 { 503 struct ctlr_info *h; 504 struct Scsi_Host *shost = class_to_shost(dev); 505 h = shost_to_hba(shost); 506 hpsa_scan_start(h->scsi_host); 507 return count; 508 } 509 510 static ssize_t host_show_firmware_revision(struct device *dev, 511 struct device_attribute *attr, char *buf) 512 { 513 struct ctlr_info *h; 514 struct Scsi_Host *shost = class_to_shost(dev); 515 unsigned char *fwrev; 516 517 h = shost_to_hba(shost); 518 if (!h->hba_inquiry_data) 519 return 0; 520 fwrev = &h->hba_inquiry_data[32]; 521 return snprintf(buf, 20, "%c%c%c%c\n", 522 fwrev[0], fwrev[1], fwrev[2], fwrev[3]); 523 } 524 525 static ssize_t host_show_commands_outstanding(struct device *dev, 526 struct device_attribute *attr, char *buf) 527 { 528 struct Scsi_Host *shost = class_to_shost(dev); 529 struct ctlr_info *h = shost_to_hba(shost); 530 531 return snprintf(buf, 20, "%d\n", 532 atomic_read(&h->commands_outstanding)); 533 } 534 535 static ssize_t host_show_transport_mode(struct device *dev, 536 struct device_attribute *attr, char *buf) 537 { 538 struct ctlr_info *h; 539 struct Scsi_Host *shost = class_to_shost(dev); 540 541 h = shost_to_hba(shost); 542 return snprintf(buf, 20, "%s\n", 543 h->transMethod & CFGTBL_Trans_Performant ? 544 "performant" : "simple"); 545 } 546 547 static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, 548 struct device_attribute *attr, char *buf) 549 { 550 struct ctlr_info *h; 551 struct Scsi_Host *shost = class_to_shost(dev); 552 553 h = shost_to_hba(shost); 554 return snprintf(buf, 30, "HP SSD Smart Path %s\n", 555 (h->acciopath_status == 1) ? "enabled" : "disabled"); 556 } 557 558 /* List of controllers which cannot be hard reset on kexec with reset_devices */ 559 static u32 unresettable_controller[] = { 560 0x324a103C, /* Smart Array P712m */ 561 0x324b103C, /* Smart Array P711m */ 562 0x3223103C, /* Smart Array P800 */ 563 0x3234103C, /* Smart Array P400 */ 564 0x3235103C, /* Smart Array P400i */ 565 0x3211103C, /* Smart Array E200i */ 566 0x3212103C, /* Smart Array E200 */ 567 0x3213103C, /* Smart Array E200i */ 568 0x3214103C, /* Smart Array E200i */ 569 0x3215103C, /* Smart Array E200i */ 570 0x3237103C, /* Smart Array E500 */ 571 0x323D103C, /* Smart Array P700m */ 572 0x40800E11, /* Smart Array 5i */ 573 0x409C0E11, /* Smart Array 6400 */ 574 0x409D0E11, /* Smart Array 6400 EM */ 575 0x40700E11, /* Smart Array 5300 */ 576 0x40820E11, /* Smart Array 532 */ 577 0x40830E11, /* Smart Array 5312 */ 578 0x409A0E11, /* Smart Array 641 */ 579 0x409B0E11, /* Smart Array 642 */ 580 0x40910E11, /* Smart Array 6i */ 581 }; 582 583 /* List of controllers which cannot even be soft reset */ 584 static u32 soft_unresettable_controller[] = { 585 0x40800E11, /* Smart Array 5i */ 586 0x40700E11, /* Smart Array 5300 */ 587 0x40820E11, /* Smart Array 532 */ 588 0x40830E11, /* Smart Array 5312 */ 589 0x409A0E11, /* Smart Array 641 */ 590 0x409B0E11, /* Smart Array 642 */ 591 0x40910E11, /* Smart Array 6i */ 592 /* Exclude 640x boards. These are two pci devices in one slot 593 * which share a battery backed cache module. One controls the 594 * cache, the other accesses the cache through the one that controls 595 * it. If we reset the one controlling the cache, the other will 596 * likely not be happy. Just forbid resetting this conjoined mess. 597 * The 640x isn't really supported by hpsa anyway. 598 */ 599 0x409C0E11, /* Smart Array 6400 */ 600 0x409D0E11, /* Smart Array 6400 EM */ 601 }; 602 603 static int board_id_in_array(u32 a[], int nelems, u32 board_id) 604 { 605 int i; 606 607 for (i = 0; i < nelems; i++) 608 if (a[i] == board_id) 609 return 1; 610 return 0; 611 } 612 613 static int ctlr_is_hard_resettable(u32 board_id) 614 { 615 return !board_id_in_array(unresettable_controller, 616 ARRAY_SIZE(unresettable_controller), board_id); 617 } 618 619 static int ctlr_is_soft_resettable(u32 board_id) 620 { 621 return !board_id_in_array(soft_unresettable_controller, 622 ARRAY_SIZE(soft_unresettable_controller), board_id); 623 } 624 625 static int ctlr_is_resettable(u32 board_id) 626 { 627 return ctlr_is_hard_resettable(board_id) || 628 ctlr_is_soft_resettable(board_id); 629 } 630 631 static ssize_t host_show_resettable(struct device *dev, 632 struct device_attribute *attr, char *buf) 633 { 634 struct ctlr_info *h; 635 struct Scsi_Host *shost = class_to_shost(dev); 636 637 h = shost_to_hba(shost); 638 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); 639 } 640 641 static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) 642 { 643 return (scsi3addr[3] & 0xC0) == 0x40; 644 } 645 646 static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", 647 "1(+0)ADM", "UNKNOWN", "PHYS DRV" 648 }; 649 #define HPSA_RAID_0 0 650 #define HPSA_RAID_4 1 651 #define HPSA_RAID_1 2 /* also used for RAID 10 */ 652 #define HPSA_RAID_5 3 /* also used for RAID 50 */ 653 #define HPSA_RAID_51 4 654 #define HPSA_RAID_6 5 /* also used for RAID 60 */ 655 #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 656 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) 657 #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) 658 659 static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) 660 { 661 return !device->physical_device; 662 } 663 664 static ssize_t raid_level_show(struct device *dev, 665 struct device_attribute *attr, char *buf) 666 { 667 ssize_t l = 0; 668 unsigned char rlevel; 669 struct ctlr_info *h; 670 struct scsi_device *sdev; 671 struct hpsa_scsi_dev_t *hdev; 672 unsigned long flags; 673 674 sdev = to_scsi_device(dev); 675 h = sdev_to_hba(sdev); 676 spin_lock_irqsave(&h->lock, flags); 677 hdev = sdev->hostdata; 678 if (!hdev) { 679 spin_unlock_irqrestore(&h->lock, flags); 680 return -ENODEV; 681 } 682 683 /* Is this even a logical drive? */ 684 if (!is_logical_device(hdev)) { 685 spin_unlock_irqrestore(&h->lock, flags); 686 l = snprintf(buf, PAGE_SIZE, "N/A\n"); 687 return l; 688 } 689 690 rlevel = hdev->raid_level; 691 spin_unlock_irqrestore(&h->lock, flags); 692 if (rlevel > RAID_UNKNOWN) 693 rlevel = RAID_UNKNOWN; 694 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); 695 return l; 696 } 697 698 static ssize_t lunid_show(struct device *dev, 699 struct device_attribute *attr, char *buf) 700 { 701 struct ctlr_info *h; 702 struct scsi_device *sdev; 703 struct hpsa_scsi_dev_t *hdev; 704 unsigned long flags; 705 unsigned char lunid[8]; 706 707 sdev = to_scsi_device(dev); 708 h = sdev_to_hba(sdev); 709 spin_lock_irqsave(&h->lock, flags); 710 hdev = sdev->hostdata; 711 if (!hdev) { 712 spin_unlock_irqrestore(&h->lock, flags); 713 return -ENODEV; 714 } 715 memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); 716 spin_unlock_irqrestore(&h->lock, flags); 717 return snprintf(buf, 20, "0x%8phN\n", lunid); 718 } 719 720 static ssize_t unique_id_show(struct device *dev, 721 struct device_attribute *attr, char *buf) 722 { 723 struct ctlr_info *h; 724 struct scsi_device *sdev; 725 struct hpsa_scsi_dev_t *hdev; 726 unsigned long flags; 727 unsigned char sn[16]; 728 729 sdev = to_scsi_device(dev); 730 h = sdev_to_hba(sdev); 731 spin_lock_irqsave(&h->lock, flags); 732 hdev = sdev->hostdata; 733 if (!hdev) { 734 spin_unlock_irqrestore(&h->lock, flags); 735 return -ENODEV; 736 } 737 memcpy(sn, hdev->device_id, sizeof(sn)); 738 spin_unlock_irqrestore(&h->lock, flags); 739 return snprintf(buf, 16 * 2 + 2, 740 "%02X%02X%02X%02X%02X%02X%02X%02X" 741 "%02X%02X%02X%02X%02X%02X%02X%02X\n", 742 sn[0], sn[1], sn[2], sn[3], 743 sn[4], sn[5], sn[6], sn[7], 744 sn[8], sn[9], sn[10], sn[11], 745 sn[12], sn[13], sn[14], sn[15]); 746 } 747 748 static ssize_t sas_address_show(struct device *dev, 749 struct device_attribute *attr, char *buf) 750 { 751 struct ctlr_info *h; 752 struct scsi_device *sdev; 753 struct hpsa_scsi_dev_t *hdev; 754 unsigned long flags; 755 u64 sas_address; 756 757 sdev = to_scsi_device(dev); 758 h = sdev_to_hba(sdev); 759 spin_lock_irqsave(&h->lock, flags); 760 hdev = sdev->hostdata; 761 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) { 762 spin_unlock_irqrestore(&h->lock, flags); 763 return -ENODEV; 764 } 765 sas_address = hdev->sas_address; 766 spin_unlock_irqrestore(&h->lock, flags); 767 768 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address); 769 } 770 771 static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, 772 struct device_attribute *attr, char *buf) 773 { 774 struct ctlr_info *h; 775 struct scsi_device *sdev; 776 struct hpsa_scsi_dev_t *hdev; 777 unsigned long flags; 778 int offload_enabled; 779 780 sdev = to_scsi_device(dev); 781 h = sdev_to_hba(sdev); 782 spin_lock_irqsave(&h->lock, flags); 783 hdev = sdev->hostdata; 784 if (!hdev) { 785 spin_unlock_irqrestore(&h->lock, flags); 786 return -ENODEV; 787 } 788 offload_enabled = hdev->offload_enabled; 789 spin_unlock_irqrestore(&h->lock, flags); 790 return snprintf(buf, 20, "%d\n", offload_enabled); 791 } 792 793 #define MAX_PATHS 8 794 static ssize_t path_info_show(struct device *dev, 795 struct device_attribute *attr, char *buf) 796 { 797 struct ctlr_info *h; 798 struct scsi_device *sdev; 799 struct hpsa_scsi_dev_t *hdev; 800 unsigned long flags; 801 int i; 802 int output_len = 0; 803 u8 box; 804 u8 bay; 805 u8 path_map_index = 0; 806 char *active; 807 unsigned char phys_connector[2]; 808 809 sdev = to_scsi_device(dev); 810 h = sdev_to_hba(sdev); 811 spin_lock_irqsave(&h->devlock, flags); 812 hdev = sdev->hostdata; 813 if (!hdev) { 814 spin_unlock_irqrestore(&h->devlock, flags); 815 return -ENODEV; 816 } 817 818 bay = hdev->bay; 819 for (i = 0; i < MAX_PATHS; i++) { 820 path_map_index = 1<<i; 821 if (i == hdev->active_path_index) 822 active = "Active"; 823 else if (hdev->path_map & path_map_index) 824 active = "Inactive"; 825 else 826 continue; 827 828 output_len += scnprintf(buf + output_len, 829 PAGE_SIZE - output_len, 830 "[%d:%d:%d:%d] %20.20s ", 831 h->scsi_host->host_no, 832 hdev->bus, hdev->target, hdev->lun, 833 scsi_device_type(hdev->devtype)); 834 835 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) { 836 output_len += scnprintf(buf + output_len, 837 PAGE_SIZE - output_len, 838 "%s\n", active); 839 continue; 840 } 841 842 box = hdev->box[i]; 843 memcpy(&phys_connector, &hdev->phys_connector[i], 844 sizeof(phys_connector)); 845 if (phys_connector[0] < '0') 846 phys_connector[0] = '0'; 847 if (phys_connector[1] < '0') 848 phys_connector[1] = '0'; 849 output_len += scnprintf(buf + output_len, 850 PAGE_SIZE - output_len, 851 "PORT: %.2s ", 852 phys_connector); 853 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) && 854 hdev->expose_device) { 855 if (box == 0 || box == 0xFF) { 856 output_len += scnprintf(buf + output_len, 857 PAGE_SIZE - output_len, 858 "BAY: %hhu %s\n", 859 bay, active); 860 } else { 861 output_len += scnprintf(buf + output_len, 862 PAGE_SIZE - output_len, 863 "BOX: %hhu BAY: %hhu %s\n", 864 box, bay, active); 865 } 866 } else if (box != 0 && box != 0xFF) { 867 output_len += scnprintf(buf + output_len, 868 PAGE_SIZE - output_len, "BOX: %hhu %s\n", 869 box, active); 870 } else 871 output_len += scnprintf(buf + output_len, 872 PAGE_SIZE - output_len, "%s\n", active); 873 } 874 875 spin_unlock_irqrestore(&h->devlock, flags); 876 return output_len; 877 } 878 879 static ssize_t host_show_ctlr_num(struct device *dev, 880 struct device_attribute *attr, char *buf) 881 { 882 struct ctlr_info *h; 883 struct Scsi_Host *shost = class_to_shost(dev); 884 885 h = shost_to_hba(shost); 886 return snprintf(buf, 20, "%d\n", h->ctlr); 887 } 888 889 static ssize_t host_show_legacy_board(struct device *dev, 890 struct device_attribute *attr, char *buf) 891 { 892 struct ctlr_info *h; 893 struct Scsi_Host *shost = class_to_shost(dev); 894 895 h = shost_to_hba(shost); 896 return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0); 897 } 898 899 static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); 900 static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); 901 static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); 902 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); 903 static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL); 904 static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, 905 host_show_hp_ssd_smart_path_enabled, NULL); 906 static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL); 907 static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, 908 host_show_hp_ssd_smart_path_status, 909 host_store_hp_ssd_smart_path_status); 910 static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, 911 host_store_raid_offload_debug); 912 static DEVICE_ATTR(firmware_revision, S_IRUGO, 913 host_show_firmware_revision, NULL); 914 static DEVICE_ATTR(commands_outstanding, S_IRUGO, 915 host_show_commands_outstanding, NULL); 916 static DEVICE_ATTR(transport_mode, S_IRUGO, 917 host_show_transport_mode, NULL); 918 static DEVICE_ATTR(resettable, S_IRUGO, 919 host_show_resettable, NULL); 920 static DEVICE_ATTR(lockup_detected, S_IRUGO, 921 host_show_lockup_detected, NULL); 922 static DEVICE_ATTR(ctlr_num, S_IRUGO, 923 host_show_ctlr_num, NULL); 924 static DEVICE_ATTR(legacy_board, S_IRUGO, 925 host_show_legacy_board, NULL); 926 927 static struct device_attribute *hpsa_sdev_attrs[] = { 928 &dev_attr_raid_level, 929 &dev_attr_lunid, 930 &dev_attr_unique_id, 931 &dev_attr_hp_ssd_smart_path_enabled, 932 &dev_attr_path_info, 933 &dev_attr_sas_address, 934 NULL, 935 }; 936 937 static struct device_attribute *hpsa_shost_attrs[] = { 938 &dev_attr_rescan, 939 &dev_attr_firmware_revision, 940 &dev_attr_commands_outstanding, 941 &dev_attr_transport_mode, 942 &dev_attr_resettable, 943 &dev_attr_hp_ssd_smart_path_status, 944 &dev_attr_raid_offload_debug, 945 &dev_attr_lockup_detected, 946 &dev_attr_ctlr_num, 947 &dev_attr_legacy_board, 948 NULL, 949 }; 950 951 #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\ 952 HPSA_MAX_CONCURRENT_PASSTHRUS) 953 954 static struct scsi_host_template hpsa_driver_template = { 955 .module = THIS_MODULE, 956 .name = HPSA, 957 .proc_name = HPSA, 958 .queuecommand = hpsa_scsi_queue_command, 959 .scan_start = hpsa_scan_start, 960 .scan_finished = hpsa_scan_finished, 961 .change_queue_depth = hpsa_change_queue_depth, 962 .this_id = -1, 963 .use_clustering = ENABLE_CLUSTERING, 964 .eh_device_reset_handler = hpsa_eh_device_reset_handler, 965 .ioctl = hpsa_ioctl, 966 .slave_alloc = hpsa_slave_alloc, 967 .slave_configure = hpsa_slave_configure, 968 .slave_destroy = hpsa_slave_destroy, 969 #ifdef CONFIG_COMPAT 970 .compat_ioctl = hpsa_compat_ioctl, 971 #endif 972 .sdev_attrs = hpsa_sdev_attrs, 973 .shost_attrs = hpsa_shost_attrs, 974 .max_sectors = 1024, 975 .no_write_same = 1, 976 }; 977 978 static inline u32 next_command(struct ctlr_info *h, u8 q) 979 { 980 u32 a; 981 struct reply_queue_buffer *rq = &h->reply_queue[q]; 982 983 if (h->transMethod & CFGTBL_Trans_io_accel1) 984 return h->access.command_completed(h, q); 985 986 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) 987 return h->access.command_completed(h, q); 988 989 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { 990 a = rq->head[rq->current_entry]; 991 rq->current_entry++; 992 atomic_dec(&h->commands_outstanding); 993 } else { 994 a = FIFO_EMPTY; 995 } 996 /* Check for wraparound */ 997 if (rq->current_entry == h->max_commands) { 998 rq->current_entry = 0; 999 rq->wraparound ^= 1; 1000 } 1001 return a; 1002 } 1003 1004 /* 1005 * There are some special bits in the bus address of the 1006 * command that we have to set for the controller to know 1007 * how to process the command: 1008 * 1009 * Normal performant mode: 1010 * bit 0: 1 means performant mode, 0 means simple mode. 1011 * bits 1-3 = block fetch table entry 1012 * bits 4-6 = command type (== 0) 1013 * 1014 * ioaccel1 mode: 1015 * bit 0 = "performant mode" bit. 1016 * bits 1-3 = block fetch table entry 1017 * bits 4-6 = command type (== 110) 1018 * (command type is needed because ioaccel1 mode 1019 * commands are submitted through the same register as normal 1020 * mode commands, so this is how the controller knows whether 1021 * the command is normal mode or ioaccel1 mode.) 1022 * 1023 * ioaccel2 mode: 1024 * bit 0 = "performant mode" bit. 1025 * bits 1-4 = block fetch table entry (note extra bit) 1026 * bits 4-6 = not needed, because ioaccel2 mode has 1027 * a separate special register for submitting commands. 1028 */ 1029 1030 /* 1031 * set_performant_mode: Modify the tag for cciss performant 1032 * set bit 0 for pull model, bits 3-1 for block fetch 1033 * register number 1034 */ 1035 #define DEFAULT_REPLY_QUEUE (-1) 1036 static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, 1037 int reply_queue) 1038 { 1039 if (likely(h->transMethod & CFGTBL_Trans_Performant)) { 1040 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); 1041 if (unlikely(!h->msix_vectors)) 1042 return; 1043 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1044 c->Header.ReplyQueue = 1045 raw_smp_processor_id() % h->nreply_queues; 1046 else 1047 c->Header.ReplyQueue = reply_queue % h->nreply_queues; 1048 } 1049 } 1050 1051 static void set_ioaccel1_performant_mode(struct ctlr_info *h, 1052 struct CommandList *c, 1053 int reply_queue) 1054 { 1055 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 1056 1057 /* 1058 * Tell the controller to post the reply to the queue for this 1059 * processor. This seems to give the best I/O throughput. 1060 */ 1061 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1062 cp->ReplyQueue = smp_processor_id() % h->nreply_queues; 1063 else 1064 cp->ReplyQueue = reply_queue % h->nreply_queues; 1065 /* 1066 * Set the bits in the address sent down to include: 1067 * - performant mode bit (bit 0) 1068 * - pull count (bits 1-3) 1069 * - command type (bits 4-6) 1070 */ 1071 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | 1072 IOACCEL1_BUSADDR_CMDTYPE; 1073 } 1074 1075 static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, 1076 struct CommandList *c, 1077 int reply_queue) 1078 { 1079 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) 1080 &h->ioaccel2_cmd_pool[c->cmdindex]; 1081 1082 /* Tell the controller to post the reply to the queue for this 1083 * processor. This seems to give the best I/O throughput. 1084 */ 1085 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1086 cp->reply_queue = smp_processor_id() % h->nreply_queues; 1087 else 1088 cp->reply_queue = reply_queue % h->nreply_queues; 1089 /* Set the bits in the address sent down to include: 1090 * - performant mode bit not used in ioaccel mode 2 1091 * - pull count (bits 0-3) 1092 * - command type isn't needed for ioaccel2 1093 */ 1094 c->busaddr |= h->ioaccel2_blockFetchTable[0]; 1095 } 1096 1097 static void set_ioaccel2_performant_mode(struct ctlr_info *h, 1098 struct CommandList *c, 1099 int reply_queue) 1100 { 1101 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 1102 1103 /* 1104 * Tell the controller to post the reply to the queue for this 1105 * processor. This seems to give the best I/O throughput. 1106 */ 1107 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1108 cp->reply_queue = smp_processor_id() % h->nreply_queues; 1109 else 1110 cp->reply_queue = reply_queue % h->nreply_queues; 1111 /* 1112 * Set the bits in the address sent down to include: 1113 * - performant mode bit not used in ioaccel mode 2 1114 * - pull count (bits 0-3) 1115 * - command type isn't needed for ioaccel2 1116 */ 1117 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); 1118 } 1119 1120 static int is_firmware_flash_cmd(u8 *cdb) 1121 { 1122 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; 1123 } 1124 1125 /* 1126 * During firmware flash, the heartbeat register may not update as frequently 1127 * as it should. So we dial down lockup detection during firmware flash. and 1128 * dial it back up when firmware flash completes. 1129 */ 1130 #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) 1131 #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) 1132 #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ) 1133 static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, 1134 struct CommandList *c) 1135 { 1136 if (!is_firmware_flash_cmd(c->Request.CDB)) 1137 return; 1138 atomic_inc(&h->firmware_flash_in_progress); 1139 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; 1140 } 1141 1142 static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, 1143 struct CommandList *c) 1144 { 1145 if (is_firmware_flash_cmd(c->Request.CDB) && 1146 atomic_dec_and_test(&h->firmware_flash_in_progress)) 1147 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 1148 } 1149 1150 static void __enqueue_cmd_and_start_io(struct ctlr_info *h, 1151 struct CommandList *c, int reply_queue) 1152 { 1153 dial_down_lockup_detection_during_fw_flash(h, c); 1154 atomic_inc(&h->commands_outstanding); 1155 switch (c->cmd_type) { 1156 case CMD_IOACCEL1: 1157 set_ioaccel1_performant_mode(h, c, reply_queue); 1158 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 1159 break; 1160 case CMD_IOACCEL2: 1161 set_ioaccel2_performant_mode(h, c, reply_queue); 1162 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 1163 break; 1164 case IOACCEL2_TMF: 1165 set_ioaccel2_tmf_performant_mode(h, c, reply_queue); 1166 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 1167 break; 1168 default: 1169 set_performant_mode(h, c, reply_queue); 1170 h->access.submit_command(h, c); 1171 } 1172 } 1173 1174 static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) 1175 { 1176 if (unlikely(hpsa_is_pending_event(c))) 1177 return finish_cmd(c); 1178 1179 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); 1180 } 1181 1182 static inline int is_hba_lunid(unsigned char scsi3addr[]) 1183 { 1184 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; 1185 } 1186 1187 static inline int is_scsi_rev_5(struct ctlr_info *h) 1188 { 1189 if (!h->hba_inquiry_data) 1190 return 0; 1191 if ((h->hba_inquiry_data[2] & 0x07) == 5) 1192 return 1; 1193 return 0; 1194 } 1195 1196 static int hpsa_find_target_lun(struct ctlr_info *h, 1197 unsigned char scsi3addr[], int bus, int *target, int *lun) 1198 { 1199 /* finds an unused bus, target, lun for a new physical device 1200 * assumes h->devlock is held 1201 */ 1202 int i, found = 0; 1203 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); 1204 1205 bitmap_zero(lun_taken, HPSA_MAX_DEVICES); 1206 1207 for (i = 0; i < h->ndevices; i++) { 1208 if (h->dev[i]->bus == bus && h->dev[i]->target != -1) 1209 __set_bit(h->dev[i]->target, lun_taken); 1210 } 1211 1212 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); 1213 if (i < HPSA_MAX_DEVICES) { 1214 /* *bus = 1; */ 1215 *target = i; 1216 *lun = 0; 1217 found = 1; 1218 } 1219 return !found; 1220 } 1221 1222 static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, 1223 struct hpsa_scsi_dev_t *dev, char *description) 1224 { 1225 #define LABEL_SIZE 25 1226 char label[LABEL_SIZE]; 1227 1228 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) 1229 return; 1230 1231 switch (dev->devtype) { 1232 case TYPE_RAID: 1233 snprintf(label, LABEL_SIZE, "controller"); 1234 break; 1235 case TYPE_ENCLOSURE: 1236 snprintf(label, LABEL_SIZE, "enclosure"); 1237 break; 1238 case TYPE_DISK: 1239 case TYPE_ZBC: 1240 if (dev->external) 1241 snprintf(label, LABEL_SIZE, "external"); 1242 else if (!is_logical_dev_addr_mode(dev->scsi3addr)) 1243 snprintf(label, LABEL_SIZE, "%s", 1244 raid_label[PHYSICAL_DRIVE]); 1245 else 1246 snprintf(label, LABEL_SIZE, "RAID-%s", 1247 dev->raid_level > RAID_UNKNOWN ? "?" : 1248 raid_label[dev->raid_level]); 1249 break; 1250 case TYPE_ROM: 1251 snprintf(label, LABEL_SIZE, "rom"); 1252 break; 1253 case TYPE_TAPE: 1254 snprintf(label, LABEL_SIZE, "tape"); 1255 break; 1256 case TYPE_MEDIUM_CHANGER: 1257 snprintf(label, LABEL_SIZE, "changer"); 1258 break; 1259 default: 1260 snprintf(label, LABEL_SIZE, "UNKNOWN"); 1261 break; 1262 } 1263 1264 dev_printk(level, &h->pdev->dev, 1265 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", 1266 h->scsi_host->host_no, dev->bus, dev->target, dev->lun, 1267 description, 1268 scsi_device_type(dev->devtype), 1269 dev->vendor, 1270 dev->model, 1271 label, 1272 dev->offload_config ? '+' : '-', 1273 dev->offload_enabled ? '+' : '-', 1274 dev->expose_device); 1275 } 1276 1277 /* Add an entry into h->dev[] array. */ 1278 static int hpsa_scsi_add_entry(struct ctlr_info *h, 1279 struct hpsa_scsi_dev_t *device, 1280 struct hpsa_scsi_dev_t *added[], int *nadded) 1281 { 1282 /* assumes h->devlock is held */ 1283 int n = h->ndevices; 1284 int i; 1285 unsigned char addr1[8], addr2[8]; 1286 struct hpsa_scsi_dev_t *sd; 1287 1288 if (n >= HPSA_MAX_DEVICES) { 1289 dev_err(&h->pdev->dev, "too many devices, some will be " 1290 "inaccessible.\n"); 1291 return -1; 1292 } 1293 1294 /* physical devices do not have lun or target assigned until now. */ 1295 if (device->lun != -1) 1296 /* Logical device, lun is already assigned. */ 1297 goto lun_assigned; 1298 1299 /* If this device a non-zero lun of a multi-lun device 1300 * byte 4 of the 8-byte LUN addr will contain the logical 1301 * unit no, zero otherwise. 1302 */ 1303 if (device->scsi3addr[4] == 0) { 1304 /* This is not a non-zero lun of a multi-lun device */ 1305 if (hpsa_find_target_lun(h, device->scsi3addr, 1306 device->bus, &device->target, &device->lun) != 0) 1307 return -1; 1308 goto lun_assigned; 1309 } 1310 1311 /* This is a non-zero lun of a multi-lun device. 1312 * Search through our list and find the device which 1313 * has the same 8 byte LUN address, excepting byte 4 and 5. 1314 * Assign the same bus and target for this new LUN. 1315 * Use the logical unit number from the firmware. 1316 */ 1317 memcpy(addr1, device->scsi3addr, 8); 1318 addr1[4] = 0; 1319 addr1[5] = 0; 1320 for (i = 0; i < n; i++) { 1321 sd = h->dev[i]; 1322 memcpy(addr2, sd->scsi3addr, 8); 1323 addr2[4] = 0; 1324 addr2[5] = 0; 1325 /* differ only in byte 4 and 5? */ 1326 if (memcmp(addr1, addr2, 8) == 0) { 1327 device->bus = sd->bus; 1328 device->target = sd->target; 1329 device->lun = device->scsi3addr[4]; 1330 break; 1331 } 1332 } 1333 if (device->lun == -1) { 1334 dev_warn(&h->pdev->dev, "physical device with no LUN=0," 1335 " suspect firmware bug or unsupported hardware " 1336 "configuration.\n"); 1337 return -1; 1338 } 1339 1340 lun_assigned: 1341 1342 h->dev[n] = device; 1343 h->ndevices++; 1344 added[*nadded] = device; 1345 (*nadded)++; 1346 hpsa_show_dev_msg(KERN_INFO, h, device, 1347 device->expose_device ? "added" : "masked"); 1348 device->offload_to_be_enabled = device->offload_enabled; 1349 device->offload_enabled = 0; 1350 return 0; 1351 } 1352 1353 /* Update an entry in h->dev[] array. */ 1354 static void hpsa_scsi_update_entry(struct ctlr_info *h, 1355 int entry, struct hpsa_scsi_dev_t *new_entry) 1356 { 1357 int offload_enabled; 1358 /* assumes h->devlock is held */ 1359 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1360 1361 /* Raid level changed. */ 1362 h->dev[entry]->raid_level = new_entry->raid_level; 1363 1364 /* Raid offload parameters changed. Careful about the ordering. */ 1365 if (new_entry->offload_config && new_entry->offload_enabled) { 1366 /* 1367 * if drive is newly offload_enabled, we want to copy the 1368 * raid map data first. If previously offload_enabled and 1369 * offload_config were set, raid map data had better be 1370 * the same as it was before. if raid map data is changed 1371 * then it had better be the case that 1372 * h->dev[entry]->offload_enabled is currently 0. 1373 */ 1374 h->dev[entry]->raid_map = new_entry->raid_map; 1375 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1376 } 1377 if (new_entry->hba_ioaccel_enabled) { 1378 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1379 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ 1380 } 1381 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; 1382 h->dev[entry]->offload_config = new_entry->offload_config; 1383 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; 1384 h->dev[entry]->queue_depth = new_entry->queue_depth; 1385 1386 /* 1387 * We can turn off ioaccel offload now, but need to delay turning 1388 * it on until we can update h->dev[entry]->phys_disk[], but we 1389 * can't do that until all the devices are updated. 1390 */ 1391 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled; 1392 if (!new_entry->offload_enabled) 1393 h->dev[entry]->offload_enabled = 0; 1394 1395 offload_enabled = h->dev[entry]->offload_enabled; 1396 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled; 1397 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); 1398 h->dev[entry]->offload_enabled = offload_enabled; 1399 } 1400 1401 /* Replace an entry from h->dev[] array. */ 1402 static void hpsa_scsi_replace_entry(struct ctlr_info *h, 1403 int entry, struct hpsa_scsi_dev_t *new_entry, 1404 struct hpsa_scsi_dev_t *added[], int *nadded, 1405 struct hpsa_scsi_dev_t *removed[], int *nremoved) 1406 { 1407 /* assumes h->devlock is held */ 1408 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1409 removed[*nremoved] = h->dev[entry]; 1410 (*nremoved)++; 1411 1412 /* 1413 * New physical devices won't have target/lun assigned yet 1414 * so we need to preserve the values in the slot we are replacing. 1415 */ 1416 if (new_entry->target == -1) { 1417 new_entry->target = h->dev[entry]->target; 1418 new_entry->lun = h->dev[entry]->lun; 1419 } 1420 1421 h->dev[entry] = new_entry; 1422 added[*nadded] = new_entry; 1423 (*nadded)++; 1424 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); 1425 new_entry->offload_to_be_enabled = new_entry->offload_enabled; 1426 new_entry->offload_enabled = 0; 1427 } 1428 1429 /* Remove an entry from h->dev[] array. */ 1430 static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, 1431 struct hpsa_scsi_dev_t *removed[], int *nremoved) 1432 { 1433 /* assumes h->devlock is held */ 1434 int i; 1435 struct hpsa_scsi_dev_t *sd; 1436 1437 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1438 1439 sd = h->dev[entry]; 1440 removed[*nremoved] = h->dev[entry]; 1441 (*nremoved)++; 1442 1443 for (i = entry; i < h->ndevices-1; i++) 1444 h->dev[i] = h->dev[i+1]; 1445 h->ndevices--; 1446 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); 1447 } 1448 1449 #define SCSI3ADDR_EQ(a, b) ( \ 1450 (a)[7] == (b)[7] && \ 1451 (a)[6] == (b)[6] && \ 1452 (a)[5] == (b)[5] && \ 1453 (a)[4] == (b)[4] && \ 1454 (a)[3] == (b)[3] && \ 1455 (a)[2] == (b)[2] && \ 1456 (a)[1] == (b)[1] && \ 1457 (a)[0] == (b)[0]) 1458 1459 static void fixup_botched_add(struct ctlr_info *h, 1460 struct hpsa_scsi_dev_t *added) 1461 { 1462 /* called when scsi_add_device fails in order to re-adjust 1463 * h->dev[] to match the mid layer's view. 1464 */ 1465 unsigned long flags; 1466 int i, j; 1467 1468 spin_lock_irqsave(&h->lock, flags); 1469 for (i = 0; i < h->ndevices; i++) { 1470 if (h->dev[i] == added) { 1471 for (j = i; j < h->ndevices-1; j++) 1472 h->dev[j] = h->dev[j+1]; 1473 h->ndevices--; 1474 break; 1475 } 1476 } 1477 spin_unlock_irqrestore(&h->lock, flags); 1478 kfree(added); 1479 } 1480 1481 static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, 1482 struct hpsa_scsi_dev_t *dev2) 1483 { 1484 /* we compare everything except lun and target as these 1485 * are not yet assigned. Compare parts likely 1486 * to differ first 1487 */ 1488 if (memcmp(dev1->scsi3addr, dev2->scsi3addr, 1489 sizeof(dev1->scsi3addr)) != 0) 1490 return 0; 1491 if (memcmp(dev1->device_id, dev2->device_id, 1492 sizeof(dev1->device_id)) != 0) 1493 return 0; 1494 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) 1495 return 0; 1496 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) 1497 return 0; 1498 if (dev1->devtype != dev2->devtype) 1499 return 0; 1500 if (dev1->bus != dev2->bus) 1501 return 0; 1502 return 1; 1503 } 1504 1505 static inline int device_updated(struct hpsa_scsi_dev_t *dev1, 1506 struct hpsa_scsi_dev_t *dev2) 1507 { 1508 /* Device attributes that can change, but don't mean 1509 * that the device is a different device, nor that the OS 1510 * needs to be told anything about the change. 1511 */ 1512 if (dev1->raid_level != dev2->raid_level) 1513 return 1; 1514 if (dev1->offload_config != dev2->offload_config) 1515 return 1; 1516 if (dev1->offload_enabled != dev2->offload_enabled) 1517 return 1; 1518 if (!is_logical_dev_addr_mode(dev1->scsi3addr)) 1519 if (dev1->queue_depth != dev2->queue_depth) 1520 return 1; 1521 return 0; 1522 } 1523 1524 /* Find needle in haystack. If exact match found, return DEVICE_SAME, 1525 * and return needle location in *index. If scsi3addr matches, but not 1526 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle 1527 * location in *index. 1528 * In the case of a minor device attribute change, such as RAID level, just 1529 * return DEVICE_UPDATED, along with the updated device's location in index. 1530 * If needle not found, return DEVICE_NOT_FOUND. 1531 */ 1532 static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, 1533 struct hpsa_scsi_dev_t *haystack[], int haystack_size, 1534 int *index) 1535 { 1536 int i; 1537 #define DEVICE_NOT_FOUND 0 1538 #define DEVICE_CHANGED 1 1539 #define DEVICE_SAME 2 1540 #define DEVICE_UPDATED 3 1541 if (needle == NULL) 1542 return DEVICE_NOT_FOUND; 1543 1544 for (i = 0; i < haystack_size; i++) { 1545 if (haystack[i] == NULL) /* previously removed. */ 1546 continue; 1547 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { 1548 *index = i; 1549 if (device_is_the_same(needle, haystack[i])) { 1550 if (device_updated(needle, haystack[i])) 1551 return DEVICE_UPDATED; 1552 return DEVICE_SAME; 1553 } else { 1554 /* Keep offline devices offline */ 1555 if (needle->volume_offline) 1556 return DEVICE_NOT_FOUND; 1557 return DEVICE_CHANGED; 1558 } 1559 } 1560 } 1561 *index = -1; 1562 return DEVICE_NOT_FOUND; 1563 } 1564 1565 static void hpsa_monitor_offline_device(struct ctlr_info *h, 1566 unsigned char scsi3addr[]) 1567 { 1568 struct offline_device_entry *device; 1569 unsigned long flags; 1570 1571 /* Check to see if device is already on the list */ 1572 spin_lock_irqsave(&h->offline_device_lock, flags); 1573 list_for_each_entry(device, &h->offline_device_list, offline_list) { 1574 if (memcmp(device->scsi3addr, scsi3addr, 1575 sizeof(device->scsi3addr)) == 0) { 1576 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1577 return; 1578 } 1579 } 1580 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1581 1582 /* Device is not on the list, add it. */ 1583 device = kmalloc(sizeof(*device), GFP_KERNEL); 1584 if (!device) 1585 return; 1586 1587 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); 1588 spin_lock_irqsave(&h->offline_device_lock, flags); 1589 list_add_tail(&device->offline_list, &h->offline_device_list); 1590 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1591 } 1592 1593 /* Print a message explaining various offline volume states */ 1594 static void hpsa_show_volume_status(struct ctlr_info *h, 1595 struct hpsa_scsi_dev_t *sd) 1596 { 1597 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) 1598 dev_info(&h->pdev->dev, 1599 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", 1600 h->scsi_host->host_no, 1601 sd->bus, sd->target, sd->lun); 1602 switch (sd->volume_offline) { 1603 case HPSA_LV_OK: 1604 break; 1605 case HPSA_LV_UNDERGOING_ERASE: 1606 dev_info(&h->pdev->dev, 1607 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", 1608 h->scsi_host->host_no, 1609 sd->bus, sd->target, sd->lun); 1610 break; 1611 case HPSA_LV_NOT_AVAILABLE: 1612 dev_info(&h->pdev->dev, 1613 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", 1614 h->scsi_host->host_no, 1615 sd->bus, sd->target, sd->lun); 1616 break; 1617 case HPSA_LV_UNDERGOING_RPI: 1618 dev_info(&h->pdev->dev, 1619 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", 1620 h->scsi_host->host_no, 1621 sd->bus, sd->target, sd->lun); 1622 break; 1623 case HPSA_LV_PENDING_RPI: 1624 dev_info(&h->pdev->dev, 1625 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", 1626 h->scsi_host->host_no, 1627 sd->bus, sd->target, sd->lun); 1628 break; 1629 case HPSA_LV_ENCRYPTED_NO_KEY: 1630 dev_info(&h->pdev->dev, 1631 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", 1632 h->scsi_host->host_no, 1633 sd->bus, sd->target, sd->lun); 1634 break; 1635 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 1636 dev_info(&h->pdev->dev, 1637 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", 1638 h->scsi_host->host_no, 1639 sd->bus, sd->target, sd->lun); 1640 break; 1641 case HPSA_LV_UNDERGOING_ENCRYPTION: 1642 dev_info(&h->pdev->dev, 1643 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", 1644 h->scsi_host->host_no, 1645 sd->bus, sd->target, sd->lun); 1646 break; 1647 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 1648 dev_info(&h->pdev->dev, 1649 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", 1650 h->scsi_host->host_no, 1651 sd->bus, sd->target, sd->lun); 1652 break; 1653 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 1654 dev_info(&h->pdev->dev, 1655 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", 1656 h->scsi_host->host_no, 1657 sd->bus, sd->target, sd->lun); 1658 break; 1659 case HPSA_LV_PENDING_ENCRYPTION: 1660 dev_info(&h->pdev->dev, 1661 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", 1662 h->scsi_host->host_no, 1663 sd->bus, sd->target, sd->lun); 1664 break; 1665 case HPSA_LV_PENDING_ENCRYPTION_REKEYING: 1666 dev_info(&h->pdev->dev, 1667 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", 1668 h->scsi_host->host_no, 1669 sd->bus, sd->target, sd->lun); 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * Figure the list of physical drive pointers for a logical drive with 1676 * raid offload configured. 1677 */ 1678 static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, 1679 struct hpsa_scsi_dev_t *dev[], int ndevices, 1680 struct hpsa_scsi_dev_t *logical_drive) 1681 { 1682 struct raid_map_data *map = &logical_drive->raid_map; 1683 struct raid_map_disk_data *dd = &map->data[0]; 1684 int i, j; 1685 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 1686 le16_to_cpu(map->metadata_disks_per_row); 1687 int nraid_map_entries = le16_to_cpu(map->row_cnt) * 1688 le16_to_cpu(map->layout_map_count) * 1689 total_disks_per_row; 1690 int nphys_disk = le16_to_cpu(map->layout_map_count) * 1691 total_disks_per_row; 1692 int qdepth; 1693 1694 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) 1695 nraid_map_entries = RAID_MAP_MAX_ENTRIES; 1696 1697 logical_drive->nphysical_disks = nraid_map_entries; 1698 1699 qdepth = 0; 1700 for (i = 0; i < nraid_map_entries; i++) { 1701 logical_drive->phys_disk[i] = NULL; 1702 if (!logical_drive->offload_config) 1703 continue; 1704 for (j = 0; j < ndevices; j++) { 1705 if (dev[j] == NULL) 1706 continue; 1707 if (dev[j]->devtype != TYPE_DISK && 1708 dev[j]->devtype != TYPE_ZBC) 1709 continue; 1710 if (is_logical_device(dev[j])) 1711 continue; 1712 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) 1713 continue; 1714 1715 logical_drive->phys_disk[i] = dev[j]; 1716 if (i < nphys_disk) 1717 qdepth = min(h->nr_cmds, qdepth + 1718 logical_drive->phys_disk[i]->queue_depth); 1719 break; 1720 } 1721 1722 /* 1723 * This can happen if a physical drive is removed and 1724 * the logical drive is degraded. In that case, the RAID 1725 * map data will refer to a physical disk which isn't actually 1726 * present. And in that case offload_enabled should already 1727 * be 0, but we'll turn it off here just in case 1728 */ 1729 if (!logical_drive->phys_disk[i]) { 1730 logical_drive->offload_enabled = 0; 1731 logical_drive->offload_to_be_enabled = 0; 1732 logical_drive->queue_depth = 8; 1733 } 1734 } 1735 if (nraid_map_entries) 1736 /* 1737 * This is correct for reads, too high for full stripe writes, 1738 * way too high for partial stripe writes 1739 */ 1740 logical_drive->queue_depth = qdepth; 1741 else 1742 logical_drive->queue_depth = h->nr_cmds; 1743 } 1744 1745 static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, 1746 struct hpsa_scsi_dev_t *dev[], int ndevices) 1747 { 1748 int i; 1749 1750 for (i = 0; i < ndevices; i++) { 1751 if (dev[i] == NULL) 1752 continue; 1753 if (dev[i]->devtype != TYPE_DISK && 1754 dev[i]->devtype != TYPE_ZBC) 1755 continue; 1756 if (!is_logical_device(dev[i])) 1757 continue; 1758 1759 /* 1760 * If offload is currently enabled, the RAID map and 1761 * phys_disk[] assignment *better* not be changing 1762 * and since it isn't changing, we do not need to 1763 * update it. 1764 */ 1765 if (dev[i]->offload_enabled) 1766 continue; 1767 1768 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); 1769 } 1770 } 1771 1772 static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) 1773 { 1774 int rc = 0; 1775 1776 if (!h->scsi_host) 1777 return 1; 1778 1779 if (is_logical_device(device)) /* RAID */ 1780 rc = scsi_add_device(h->scsi_host, device->bus, 1781 device->target, device->lun); 1782 else /* HBA */ 1783 rc = hpsa_add_sas_device(h->sas_host, device); 1784 1785 return rc; 1786 } 1787 1788 static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h, 1789 struct hpsa_scsi_dev_t *dev) 1790 { 1791 int i; 1792 int count = 0; 1793 1794 for (i = 0; i < h->nr_cmds; i++) { 1795 struct CommandList *c = h->cmd_pool + i; 1796 int refcount = atomic_inc_return(&c->refcount); 1797 1798 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, 1799 dev->scsi3addr)) { 1800 unsigned long flags; 1801 1802 spin_lock_irqsave(&h->lock, flags); /* Implied MB */ 1803 if (!hpsa_is_cmd_idle(c)) 1804 ++count; 1805 spin_unlock_irqrestore(&h->lock, flags); 1806 } 1807 1808 cmd_free(h, c); 1809 } 1810 1811 return count; 1812 } 1813 1814 static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h, 1815 struct hpsa_scsi_dev_t *device) 1816 { 1817 int cmds = 0; 1818 int waits = 0; 1819 1820 while (1) { 1821 cmds = hpsa_find_outstanding_commands_for_dev(h, device); 1822 if (cmds == 0) 1823 break; 1824 if (++waits > 20) 1825 break; 1826 dev_warn(&h->pdev->dev, 1827 "%s: removing device with %d outstanding commands!\n", 1828 __func__, cmds); 1829 msleep(1000); 1830 } 1831 } 1832 1833 static void hpsa_remove_device(struct ctlr_info *h, 1834 struct hpsa_scsi_dev_t *device) 1835 { 1836 struct scsi_device *sdev = NULL; 1837 1838 if (!h->scsi_host) 1839 return; 1840 1841 if (is_logical_device(device)) { /* RAID */ 1842 sdev = scsi_device_lookup(h->scsi_host, device->bus, 1843 device->target, device->lun); 1844 if (sdev) { 1845 scsi_remove_device(sdev); 1846 scsi_device_put(sdev); 1847 } else { 1848 /* 1849 * We don't expect to get here. Future commands 1850 * to this device will get a selection timeout as 1851 * if the device were gone. 1852 */ 1853 hpsa_show_dev_msg(KERN_WARNING, h, device, 1854 "didn't find device for removal."); 1855 } 1856 } else { /* HBA */ 1857 1858 device->removed = 1; 1859 hpsa_wait_for_outstanding_commands_for_dev(h, device); 1860 1861 hpsa_remove_sas_device(device); 1862 } 1863 } 1864 1865 static void adjust_hpsa_scsi_table(struct ctlr_info *h, 1866 struct hpsa_scsi_dev_t *sd[], int nsds) 1867 { 1868 /* sd contains scsi3 addresses and devtypes, and inquiry 1869 * data. This function takes what's in sd to be the current 1870 * reality and updates h->dev[] to reflect that reality. 1871 */ 1872 int i, entry, device_change, changes = 0; 1873 struct hpsa_scsi_dev_t *csd; 1874 unsigned long flags; 1875 struct hpsa_scsi_dev_t **added, **removed; 1876 int nadded, nremoved; 1877 1878 /* 1879 * A reset can cause a device status to change 1880 * re-schedule the scan to see what happened. 1881 */ 1882 spin_lock_irqsave(&h->reset_lock, flags); 1883 if (h->reset_in_progress) { 1884 h->drv_req_rescan = 1; 1885 spin_unlock_irqrestore(&h->reset_lock, flags); 1886 return; 1887 } 1888 spin_unlock_irqrestore(&h->reset_lock, flags); 1889 1890 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); 1891 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); 1892 1893 if (!added || !removed) { 1894 dev_warn(&h->pdev->dev, "out of memory in " 1895 "adjust_hpsa_scsi_table\n"); 1896 goto free_and_out; 1897 } 1898 1899 spin_lock_irqsave(&h->devlock, flags); 1900 1901 /* find any devices in h->dev[] that are not in 1902 * sd[] and remove them from h->dev[], and for any 1903 * devices which have changed, remove the old device 1904 * info and add the new device info. 1905 * If minor device attributes change, just update 1906 * the existing device structure. 1907 */ 1908 i = 0; 1909 nremoved = 0; 1910 nadded = 0; 1911 while (i < h->ndevices) { 1912 csd = h->dev[i]; 1913 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); 1914 if (device_change == DEVICE_NOT_FOUND) { 1915 changes++; 1916 hpsa_scsi_remove_entry(h, i, removed, &nremoved); 1917 continue; /* remove ^^^, hence i not incremented */ 1918 } else if (device_change == DEVICE_CHANGED) { 1919 changes++; 1920 hpsa_scsi_replace_entry(h, i, sd[entry], 1921 added, &nadded, removed, &nremoved); 1922 /* Set it to NULL to prevent it from being freed 1923 * at the bottom of hpsa_update_scsi_devices() 1924 */ 1925 sd[entry] = NULL; 1926 } else if (device_change == DEVICE_UPDATED) { 1927 hpsa_scsi_update_entry(h, i, sd[entry]); 1928 } 1929 i++; 1930 } 1931 1932 /* Now, make sure every device listed in sd[] is also 1933 * listed in h->dev[], adding them if they aren't found 1934 */ 1935 1936 for (i = 0; i < nsds; i++) { 1937 if (!sd[i]) /* if already added above. */ 1938 continue; 1939 1940 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS 1941 * as the SCSI mid-layer does not handle such devices well. 1942 * It relentlessly loops sending TUR at 3Hz, then READ(10) 1943 * at 160Hz, and prevents the system from coming up. 1944 */ 1945 if (sd[i]->volume_offline) { 1946 hpsa_show_volume_status(h, sd[i]); 1947 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); 1948 continue; 1949 } 1950 1951 device_change = hpsa_scsi_find_entry(sd[i], h->dev, 1952 h->ndevices, &entry); 1953 if (device_change == DEVICE_NOT_FOUND) { 1954 changes++; 1955 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) 1956 break; 1957 sd[i] = NULL; /* prevent from being freed later. */ 1958 } else if (device_change == DEVICE_CHANGED) { 1959 /* should never happen... */ 1960 changes++; 1961 dev_warn(&h->pdev->dev, 1962 "device unexpectedly changed.\n"); 1963 /* but if it does happen, we just ignore that device */ 1964 } 1965 } 1966 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); 1967 1968 /* Now that h->dev[]->phys_disk[] is coherent, we can enable 1969 * any logical drives that need it enabled. 1970 */ 1971 for (i = 0; i < h->ndevices; i++) { 1972 if (h->dev[i] == NULL) 1973 continue; 1974 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; 1975 } 1976 1977 spin_unlock_irqrestore(&h->devlock, flags); 1978 1979 /* Monitor devices which are in one of several NOT READY states to be 1980 * brought online later. This must be done without holding h->devlock, 1981 * so don't touch h->dev[] 1982 */ 1983 for (i = 0; i < nsds; i++) { 1984 if (!sd[i]) /* if already added above. */ 1985 continue; 1986 if (sd[i]->volume_offline) 1987 hpsa_monitor_offline_device(h, sd[i]->scsi3addr); 1988 } 1989 1990 /* Don't notify scsi mid layer of any changes the first time through 1991 * (or if there are no changes) scsi_scan_host will do it later the 1992 * first time through. 1993 */ 1994 if (!changes) 1995 goto free_and_out; 1996 1997 /* Notify scsi mid layer of any removed devices */ 1998 for (i = 0; i < nremoved; i++) { 1999 if (removed[i] == NULL) 2000 continue; 2001 if (removed[i]->expose_device) 2002 hpsa_remove_device(h, removed[i]); 2003 kfree(removed[i]); 2004 removed[i] = NULL; 2005 } 2006 2007 /* Notify scsi mid layer of any added devices */ 2008 for (i = 0; i < nadded; i++) { 2009 int rc = 0; 2010 2011 if (added[i] == NULL) 2012 continue; 2013 if (!(added[i]->expose_device)) 2014 continue; 2015 rc = hpsa_add_device(h, added[i]); 2016 if (!rc) 2017 continue; 2018 dev_warn(&h->pdev->dev, 2019 "addition failed %d, device not added.", rc); 2020 /* now we have to remove it from h->dev, 2021 * since it didn't get added to scsi mid layer 2022 */ 2023 fixup_botched_add(h, added[i]); 2024 h->drv_req_rescan = 1; 2025 } 2026 2027 free_and_out: 2028 kfree(added); 2029 kfree(removed); 2030 } 2031 2032 /* 2033 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * 2034 * Assume's h->devlock is held. 2035 */ 2036 static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, 2037 int bus, int target, int lun) 2038 { 2039 int i; 2040 struct hpsa_scsi_dev_t *sd; 2041 2042 for (i = 0; i < h->ndevices; i++) { 2043 sd = h->dev[i]; 2044 if (sd->bus == bus && sd->target == target && sd->lun == lun) 2045 return sd; 2046 } 2047 return NULL; 2048 } 2049 2050 static int hpsa_slave_alloc(struct scsi_device *sdev) 2051 { 2052 struct hpsa_scsi_dev_t *sd = NULL; 2053 unsigned long flags; 2054 struct ctlr_info *h; 2055 2056 h = sdev_to_hba(sdev); 2057 spin_lock_irqsave(&h->devlock, flags); 2058 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { 2059 struct scsi_target *starget; 2060 struct sas_rphy *rphy; 2061 2062 starget = scsi_target(sdev); 2063 rphy = target_to_rphy(starget); 2064 sd = hpsa_find_device_by_sas_rphy(h, rphy); 2065 if (sd) { 2066 sd->target = sdev_id(sdev); 2067 sd->lun = sdev->lun; 2068 } 2069 } 2070 if (!sd) 2071 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), 2072 sdev_id(sdev), sdev->lun); 2073 2074 if (sd && sd->expose_device) { 2075 atomic_set(&sd->ioaccel_cmds_out, 0); 2076 sdev->hostdata = sd; 2077 } else 2078 sdev->hostdata = NULL; 2079 spin_unlock_irqrestore(&h->devlock, flags); 2080 return 0; 2081 } 2082 2083 /* configure scsi device based on internal per-device structure */ 2084 static int hpsa_slave_configure(struct scsi_device *sdev) 2085 { 2086 struct hpsa_scsi_dev_t *sd; 2087 int queue_depth; 2088 2089 sd = sdev->hostdata; 2090 sdev->no_uld_attach = !sd || !sd->expose_device; 2091 2092 if (sd) { 2093 if (sd->external) 2094 queue_depth = EXTERNAL_QD; 2095 else 2096 queue_depth = sd->queue_depth != 0 ? 2097 sd->queue_depth : sdev->host->can_queue; 2098 } else 2099 queue_depth = sdev->host->can_queue; 2100 2101 scsi_change_queue_depth(sdev, queue_depth); 2102 2103 return 0; 2104 } 2105 2106 static void hpsa_slave_destroy(struct scsi_device *sdev) 2107 { 2108 /* nothing to do. */ 2109 } 2110 2111 static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2112 { 2113 int i; 2114 2115 if (!h->ioaccel2_cmd_sg_list) 2116 return; 2117 for (i = 0; i < h->nr_cmds; i++) { 2118 kfree(h->ioaccel2_cmd_sg_list[i]); 2119 h->ioaccel2_cmd_sg_list[i] = NULL; 2120 } 2121 kfree(h->ioaccel2_cmd_sg_list); 2122 h->ioaccel2_cmd_sg_list = NULL; 2123 } 2124 2125 static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2126 { 2127 int i; 2128 2129 if (h->chainsize <= 0) 2130 return 0; 2131 2132 h->ioaccel2_cmd_sg_list = 2133 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds, 2134 GFP_KERNEL); 2135 if (!h->ioaccel2_cmd_sg_list) 2136 return -ENOMEM; 2137 for (i = 0; i < h->nr_cmds; i++) { 2138 h->ioaccel2_cmd_sg_list[i] = 2139 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) * 2140 h->maxsgentries, GFP_KERNEL); 2141 if (!h->ioaccel2_cmd_sg_list[i]) 2142 goto clean; 2143 } 2144 return 0; 2145 2146 clean: 2147 hpsa_free_ioaccel2_sg_chain_blocks(h); 2148 return -ENOMEM; 2149 } 2150 2151 static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) 2152 { 2153 int i; 2154 2155 if (!h->cmd_sg_list) 2156 return; 2157 for (i = 0; i < h->nr_cmds; i++) { 2158 kfree(h->cmd_sg_list[i]); 2159 h->cmd_sg_list[i] = NULL; 2160 } 2161 kfree(h->cmd_sg_list); 2162 h->cmd_sg_list = NULL; 2163 } 2164 2165 static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) 2166 { 2167 int i; 2168 2169 if (h->chainsize <= 0) 2170 return 0; 2171 2172 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, 2173 GFP_KERNEL); 2174 if (!h->cmd_sg_list) 2175 return -ENOMEM; 2176 2177 for (i = 0; i < h->nr_cmds; i++) { 2178 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * 2179 h->chainsize, GFP_KERNEL); 2180 if (!h->cmd_sg_list[i]) 2181 goto clean; 2182 2183 } 2184 return 0; 2185 2186 clean: 2187 hpsa_free_sg_chain_blocks(h); 2188 return -ENOMEM; 2189 } 2190 2191 static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, 2192 struct io_accel2_cmd *cp, struct CommandList *c) 2193 { 2194 struct ioaccel2_sg_element *chain_block; 2195 u64 temp64; 2196 u32 chain_size; 2197 2198 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; 2199 chain_size = le32_to_cpu(cp->sg[0].length); 2200 temp64 = pci_map_single(h->pdev, chain_block, chain_size, 2201 PCI_DMA_TODEVICE); 2202 if (dma_mapping_error(&h->pdev->dev, temp64)) { 2203 /* prevent subsequent unmapping */ 2204 cp->sg->address = 0; 2205 return -1; 2206 } 2207 cp->sg->address = cpu_to_le64(temp64); 2208 return 0; 2209 } 2210 2211 static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, 2212 struct io_accel2_cmd *cp) 2213 { 2214 struct ioaccel2_sg_element *chain_sg; 2215 u64 temp64; 2216 u32 chain_size; 2217 2218 chain_sg = cp->sg; 2219 temp64 = le64_to_cpu(chain_sg->address); 2220 chain_size = le32_to_cpu(cp->sg[0].length); 2221 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE); 2222 } 2223 2224 static int hpsa_map_sg_chain_block(struct ctlr_info *h, 2225 struct CommandList *c) 2226 { 2227 struct SGDescriptor *chain_sg, *chain_block; 2228 u64 temp64; 2229 u32 chain_len; 2230 2231 chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 2232 chain_block = h->cmd_sg_list[c->cmdindex]; 2233 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); 2234 chain_len = sizeof(*chain_sg) * 2235 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); 2236 chain_sg->Len = cpu_to_le32(chain_len); 2237 temp64 = pci_map_single(h->pdev, chain_block, chain_len, 2238 PCI_DMA_TODEVICE); 2239 if (dma_mapping_error(&h->pdev->dev, temp64)) { 2240 /* prevent subsequent unmapping */ 2241 chain_sg->Addr = cpu_to_le64(0); 2242 return -1; 2243 } 2244 chain_sg->Addr = cpu_to_le64(temp64); 2245 return 0; 2246 } 2247 2248 static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, 2249 struct CommandList *c) 2250 { 2251 struct SGDescriptor *chain_sg; 2252 2253 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) 2254 return; 2255 2256 chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 2257 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr), 2258 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE); 2259 } 2260 2261 2262 /* Decode the various types of errors on ioaccel2 path. 2263 * Return 1 for any error that should generate a RAID path retry. 2264 * Return 0 for errors that don't require a RAID path retry. 2265 */ 2266 static int handle_ioaccel_mode2_error(struct ctlr_info *h, 2267 struct CommandList *c, 2268 struct scsi_cmnd *cmd, 2269 struct io_accel2_cmd *c2, 2270 struct hpsa_scsi_dev_t *dev) 2271 { 2272 int data_len; 2273 int retry = 0; 2274 u32 ioaccel2_resid = 0; 2275 2276 switch (c2->error_data.serv_response) { 2277 case IOACCEL2_SERV_RESPONSE_COMPLETE: 2278 switch (c2->error_data.status) { 2279 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: 2280 break; 2281 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: 2282 cmd->result |= SAM_STAT_CHECK_CONDITION; 2283 if (c2->error_data.data_present != 2284 IOACCEL2_SENSE_DATA_PRESENT) { 2285 memset(cmd->sense_buffer, 0, 2286 SCSI_SENSE_BUFFERSIZE); 2287 break; 2288 } 2289 /* copy the sense data */ 2290 data_len = c2->error_data.sense_data_len; 2291 if (data_len > SCSI_SENSE_BUFFERSIZE) 2292 data_len = SCSI_SENSE_BUFFERSIZE; 2293 if (data_len > sizeof(c2->error_data.sense_data_buff)) 2294 data_len = 2295 sizeof(c2->error_data.sense_data_buff); 2296 memcpy(cmd->sense_buffer, 2297 c2->error_data.sense_data_buff, data_len); 2298 retry = 1; 2299 break; 2300 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: 2301 retry = 1; 2302 break; 2303 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: 2304 retry = 1; 2305 break; 2306 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: 2307 retry = 1; 2308 break; 2309 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: 2310 retry = 1; 2311 break; 2312 default: 2313 retry = 1; 2314 break; 2315 } 2316 break; 2317 case IOACCEL2_SERV_RESPONSE_FAILURE: 2318 switch (c2->error_data.status) { 2319 case IOACCEL2_STATUS_SR_IO_ERROR: 2320 case IOACCEL2_STATUS_SR_IO_ABORTED: 2321 case IOACCEL2_STATUS_SR_OVERRUN: 2322 retry = 1; 2323 break; 2324 case IOACCEL2_STATUS_SR_UNDERRUN: 2325 cmd->result = (DID_OK << 16); /* host byte */ 2326 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2327 ioaccel2_resid = get_unaligned_le32( 2328 &c2->error_data.resid_cnt[0]); 2329 scsi_set_resid(cmd, ioaccel2_resid); 2330 break; 2331 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: 2332 case IOACCEL2_STATUS_SR_INVALID_DEVICE: 2333 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: 2334 /* 2335 * Did an HBA disk disappear? We will eventually 2336 * get a state change event from the controller but 2337 * in the meantime, we need to tell the OS that the 2338 * HBA disk is no longer there and stop I/O 2339 * from going down. This allows the potential re-insert 2340 * of the disk to get the same device node. 2341 */ 2342 if (dev->physical_device && dev->expose_device) { 2343 cmd->result = DID_NO_CONNECT << 16; 2344 dev->removed = 1; 2345 h->drv_req_rescan = 1; 2346 dev_warn(&h->pdev->dev, 2347 "%s: device is gone!\n", __func__); 2348 } else 2349 /* 2350 * Retry by sending down the RAID path. 2351 * We will get an event from ctlr to 2352 * trigger rescan regardless. 2353 */ 2354 retry = 1; 2355 break; 2356 default: 2357 retry = 1; 2358 } 2359 break; 2360 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: 2361 break; 2362 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: 2363 break; 2364 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: 2365 retry = 1; 2366 break; 2367 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: 2368 break; 2369 default: 2370 retry = 1; 2371 break; 2372 } 2373 2374 return retry; /* retry on raid path? */ 2375 } 2376 2377 static void hpsa_cmd_resolve_events(struct ctlr_info *h, 2378 struct CommandList *c) 2379 { 2380 bool do_wake = false; 2381 2382 /* 2383 * Reset c->scsi_cmd here so that the reset handler will know 2384 * this command has completed. Then, check to see if the handler is 2385 * waiting for this command, and, if so, wake it. 2386 */ 2387 c->scsi_cmd = SCSI_CMD_IDLE; 2388 mb(); /* Declare command idle before checking for pending events. */ 2389 if (c->reset_pending) { 2390 unsigned long flags; 2391 struct hpsa_scsi_dev_t *dev; 2392 2393 /* 2394 * There appears to be a reset pending; lock the lock and 2395 * reconfirm. If so, then decrement the count of outstanding 2396 * commands and wake the reset command if this is the last one. 2397 */ 2398 spin_lock_irqsave(&h->lock, flags); 2399 dev = c->reset_pending; /* Re-fetch under the lock. */ 2400 if (dev && atomic_dec_and_test(&dev->reset_cmds_out)) 2401 do_wake = true; 2402 c->reset_pending = NULL; 2403 spin_unlock_irqrestore(&h->lock, flags); 2404 } 2405 2406 if (do_wake) 2407 wake_up_all(&h->event_sync_wait_queue); 2408 } 2409 2410 static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, 2411 struct CommandList *c) 2412 { 2413 hpsa_cmd_resolve_events(h, c); 2414 cmd_tagged_free(h, c); 2415 } 2416 2417 static void hpsa_cmd_free_and_done(struct ctlr_info *h, 2418 struct CommandList *c, struct scsi_cmnd *cmd) 2419 { 2420 hpsa_cmd_resolve_and_free(h, c); 2421 if (cmd && cmd->scsi_done) 2422 cmd->scsi_done(cmd); 2423 } 2424 2425 static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) 2426 { 2427 INIT_WORK(&c->work, hpsa_command_resubmit_worker); 2428 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); 2429 } 2430 2431 static void process_ioaccel2_completion(struct ctlr_info *h, 2432 struct CommandList *c, struct scsi_cmnd *cmd, 2433 struct hpsa_scsi_dev_t *dev) 2434 { 2435 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 2436 2437 /* check for good status */ 2438 if (likely(c2->error_data.serv_response == 0 && 2439 c2->error_data.status == 0)) 2440 return hpsa_cmd_free_and_done(h, c, cmd); 2441 2442 /* 2443 * Any RAID offload error results in retry which will use 2444 * the normal I/O path so the controller can handle whatever's 2445 * wrong. 2446 */ 2447 if (is_logical_device(dev) && 2448 c2->error_data.serv_response == 2449 IOACCEL2_SERV_RESPONSE_FAILURE) { 2450 if (c2->error_data.status == 2451 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) { 2452 dev->offload_enabled = 0; 2453 dev->offload_to_be_enabled = 0; 2454 } 2455 2456 return hpsa_retry_cmd(h, c); 2457 } 2458 2459 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev)) 2460 return hpsa_retry_cmd(h, c); 2461 2462 return hpsa_cmd_free_and_done(h, c, cmd); 2463 } 2464 2465 /* Returns 0 on success, < 0 otherwise. */ 2466 static int hpsa_evaluate_tmf_status(struct ctlr_info *h, 2467 struct CommandList *cp) 2468 { 2469 u8 tmf_status = cp->err_info->ScsiStatus; 2470 2471 switch (tmf_status) { 2472 case CISS_TMF_COMPLETE: 2473 /* 2474 * CISS_TMF_COMPLETE never happens, instead, 2475 * ei->CommandStatus == 0 for this case. 2476 */ 2477 case CISS_TMF_SUCCESS: 2478 return 0; 2479 case CISS_TMF_INVALID_FRAME: 2480 case CISS_TMF_NOT_SUPPORTED: 2481 case CISS_TMF_FAILED: 2482 case CISS_TMF_WRONG_LUN: 2483 case CISS_TMF_OVERLAPPED_TAG: 2484 break; 2485 default: 2486 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", 2487 tmf_status); 2488 break; 2489 } 2490 return -tmf_status; 2491 } 2492 2493 static void complete_scsi_command(struct CommandList *cp) 2494 { 2495 struct scsi_cmnd *cmd; 2496 struct ctlr_info *h; 2497 struct ErrorInfo *ei; 2498 struct hpsa_scsi_dev_t *dev; 2499 struct io_accel2_cmd *c2; 2500 2501 u8 sense_key; 2502 u8 asc; /* additional sense code */ 2503 u8 ascq; /* additional sense code qualifier */ 2504 unsigned long sense_data_size; 2505 2506 ei = cp->err_info; 2507 cmd = cp->scsi_cmd; 2508 h = cp->h; 2509 2510 if (!cmd->device) { 2511 cmd->result = DID_NO_CONNECT << 16; 2512 return hpsa_cmd_free_and_done(h, cp, cmd); 2513 } 2514 2515 dev = cmd->device->hostdata; 2516 if (!dev) { 2517 cmd->result = DID_NO_CONNECT << 16; 2518 return hpsa_cmd_free_and_done(h, cp, cmd); 2519 } 2520 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; 2521 2522 scsi_dma_unmap(cmd); /* undo the DMA mappings */ 2523 if ((cp->cmd_type == CMD_SCSI) && 2524 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) 2525 hpsa_unmap_sg_chain_block(h, cp); 2526 2527 if ((cp->cmd_type == CMD_IOACCEL2) && 2528 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) 2529 hpsa_unmap_ioaccel2_sg_chain_block(h, c2); 2530 2531 cmd->result = (DID_OK << 16); /* host byte */ 2532 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2533 2534 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) { 2535 if (dev->physical_device && dev->expose_device && 2536 dev->removed) { 2537 cmd->result = DID_NO_CONNECT << 16; 2538 return hpsa_cmd_free_and_done(h, cp, cmd); 2539 } 2540 if (likely(cp->phys_disk != NULL)) 2541 atomic_dec(&cp->phys_disk->ioaccel_cmds_out); 2542 } 2543 2544 /* 2545 * We check for lockup status here as it may be set for 2546 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by 2547 * fail_all_oustanding_cmds() 2548 */ 2549 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { 2550 /* DID_NO_CONNECT will prevent a retry */ 2551 cmd->result = DID_NO_CONNECT << 16; 2552 return hpsa_cmd_free_and_done(h, cp, cmd); 2553 } 2554 2555 if ((unlikely(hpsa_is_pending_event(cp)))) 2556 if (cp->reset_pending) 2557 return hpsa_cmd_free_and_done(h, cp, cmd); 2558 2559 if (cp->cmd_type == CMD_IOACCEL2) 2560 return process_ioaccel2_completion(h, cp, cmd, dev); 2561 2562 scsi_set_resid(cmd, ei->ResidualCnt); 2563 if (ei->CommandStatus == 0) 2564 return hpsa_cmd_free_and_done(h, cp, cmd); 2565 2566 /* For I/O accelerator commands, copy over some fields to the normal 2567 * CISS header used below for error handling. 2568 */ 2569 if (cp->cmd_type == CMD_IOACCEL1) { 2570 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; 2571 cp->Header.SGList = scsi_sg_count(cmd); 2572 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); 2573 cp->Request.CDBLen = le16_to_cpu(c->io_flags) & 2574 IOACCEL1_IOFLAGS_CDBLEN_MASK; 2575 cp->Header.tag = c->tag; 2576 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); 2577 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); 2578 2579 /* Any RAID offload error results in retry which will use 2580 * the normal I/O path so the controller can handle whatever's 2581 * wrong. 2582 */ 2583 if (is_logical_device(dev)) { 2584 if (ei->CommandStatus == CMD_IOACCEL_DISABLED) 2585 dev->offload_enabled = 0; 2586 return hpsa_retry_cmd(h, cp); 2587 } 2588 } 2589 2590 /* an error has occurred */ 2591 switch (ei->CommandStatus) { 2592 2593 case CMD_TARGET_STATUS: 2594 cmd->result |= ei->ScsiStatus; 2595 /* copy the sense data */ 2596 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) 2597 sense_data_size = SCSI_SENSE_BUFFERSIZE; 2598 else 2599 sense_data_size = sizeof(ei->SenseInfo); 2600 if (ei->SenseLen < sense_data_size) 2601 sense_data_size = ei->SenseLen; 2602 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); 2603 if (ei->ScsiStatus) 2604 decode_sense_data(ei->SenseInfo, sense_data_size, 2605 &sense_key, &asc, &ascq); 2606 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { 2607 if (sense_key == ABORTED_COMMAND) { 2608 cmd->result |= DID_SOFT_ERROR << 16; 2609 break; 2610 } 2611 break; 2612 } 2613 /* Problem was not a check condition 2614 * Pass it up to the upper layers... 2615 */ 2616 if (ei->ScsiStatus) { 2617 dev_warn(&h->pdev->dev, "cp %p has status 0x%x " 2618 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " 2619 "Returning result: 0x%x\n", 2620 cp, ei->ScsiStatus, 2621 sense_key, asc, ascq, 2622 cmd->result); 2623 } else { /* scsi status is zero??? How??? */ 2624 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " 2625 "Returning no connection.\n", cp), 2626 2627 /* Ordinarily, this case should never happen, 2628 * but there is a bug in some released firmware 2629 * revisions that allows it to happen if, for 2630 * example, a 4100 backplane loses power and 2631 * the tape drive is in it. We assume that 2632 * it's a fatal error of some kind because we 2633 * can't show that it wasn't. We will make it 2634 * look like selection timeout since that is 2635 * the most common reason for this to occur, 2636 * and it's severe enough. 2637 */ 2638 2639 cmd->result = DID_NO_CONNECT << 16; 2640 } 2641 break; 2642 2643 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2644 break; 2645 case CMD_DATA_OVERRUN: 2646 dev_warn(&h->pdev->dev, 2647 "CDB %16phN data overrun\n", cp->Request.CDB); 2648 break; 2649 case CMD_INVALID: { 2650 /* print_bytes(cp, sizeof(*cp), 1, 0); 2651 print_cmd(cp); */ 2652 /* We get CMD_INVALID if you address a non-existent device 2653 * instead of a selection timeout (no response). You will 2654 * see this if you yank out a drive, then try to access it. 2655 * This is kind of a shame because it means that any other 2656 * CMD_INVALID (e.g. driver bug) will get interpreted as a 2657 * missing target. */ 2658 cmd->result = DID_NO_CONNECT << 16; 2659 } 2660 break; 2661 case CMD_PROTOCOL_ERR: 2662 cmd->result = DID_ERROR << 16; 2663 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", 2664 cp->Request.CDB); 2665 break; 2666 case CMD_HARDWARE_ERR: 2667 cmd->result = DID_ERROR << 16; 2668 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", 2669 cp->Request.CDB); 2670 break; 2671 case CMD_CONNECTION_LOST: 2672 cmd->result = DID_ERROR << 16; 2673 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", 2674 cp->Request.CDB); 2675 break; 2676 case CMD_ABORTED: 2677 cmd->result = DID_ABORT << 16; 2678 break; 2679 case CMD_ABORT_FAILED: 2680 cmd->result = DID_ERROR << 16; 2681 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", 2682 cp->Request.CDB); 2683 break; 2684 case CMD_UNSOLICITED_ABORT: 2685 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ 2686 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", 2687 cp->Request.CDB); 2688 break; 2689 case CMD_TIMEOUT: 2690 cmd->result = DID_TIME_OUT << 16; 2691 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", 2692 cp->Request.CDB); 2693 break; 2694 case CMD_UNABORTABLE: 2695 cmd->result = DID_ERROR << 16; 2696 dev_warn(&h->pdev->dev, "Command unabortable\n"); 2697 break; 2698 case CMD_TMF_STATUS: 2699 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ 2700 cmd->result = DID_ERROR << 16; 2701 break; 2702 case CMD_IOACCEL_DISABLED: 2703 /* This only handles the direct pass-through case since RAID 2704 * offload is handled above. Just attempt a retry. 2705 */ 2706 cmd->result = DID_SOFT_ERROR << 16; 2707 dev_warn(&h->pdev->dev, 2708 "cp %p had HP SSD Smart Path error\n", cp); 2709 break; 2710 default: 2711 cmd->result = DID_ERROR << 16; 2712 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", 2713 cp, ei->CommandStatus); 2714 } 2715 2716 return hpsa_cmd_free_and_done(h, cp, cmd); 2717 } 2718 2719 static void hpsa_pci_unmap(struct pci_dev *pdev, 2720 struct CommandList *c, int sg_used, int data_direction) 2721 { 2722 int i; 2723 2724 for (i = 0; i < sg_used; i++) 2725 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr), 2726 le32_to_cpu(c->SG[i].Len), 2727 data_direction); 2728 } 2729 2730 static int hpsa_map_one(struct pci_dev *pdev, 2731 struct CommandList *cp, 2732 unsigned char *buf, 2733 size_t buflen, 2734 int data_direction) 2735 { 2736 u64 addr64; 2737 2738 if (buflen == 0 || data_direction == PCI_DMA_NONE) { 2739 cp->Header.SGList = 0; 2740 cp->Header.SGTotal = cpu_to_le16(0); 2741 return 0; 2742 } 2743 2744 addr64 = pci_map_single(pdev, buf, buflen, data_direction); 2745 if (dma_mapping_error(&pdev->dev, addr64)) { 2746 /* Prevent subsequent unmap of something never mapped */ 2747 cp->Header.SGList = 0; 2748 cp->Header.SGTotal = cpu_to_le16(0); 2749 return -1; 2750 } 2751 cp->SG[0].Addr = cpu_to_le64(addr64); 2752 cp->SG[0].Len = cpu_to_le32(buflen); 2753 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ 2754 cp->Header.SGList = 1; /* no. SGs contig in this cmd */ 2755 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ 2756 return 0; 2757 } 2758 2759 #define NO_TIMEOUT ((unsigned long) -1) 2760 #define DEFAULT_TIMEOUT 30000 /* milliseconds */ 2761 static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, 2762 struct CommandList *c, int reply_queue, unsigned long timeout_msecs) 2763 { 2764 DECLARE_COMPLETION_ONSTACK(wait); 2765 2766 c->waiting = &wait; 2767 __enqueue_cmd_and_start_io(h, c, reply_queue); 2768 if (timeout_msecs == NO_TIMEOUT) { 2769 /* TODO: get rid of this no-timeout thing */ 2770 wait_for_completion_io(&wait); 2771 return IO_OK; 2772 } 2773 if (!wait_for_completion_io_timeout(&wait, 2774 msecs_to_jiffies(timeout_msecs))) { 2775 dev_warn(&h->pdev->dev, "Command timed out.\n"); 2776 return -ETIMEDOUT; 2777 } 2778 return IO_OK; 2779 } 2780 2781 static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, 2782 int reply_queue, unsigned long timeout_msecs) 2783 { 2784 if (unlikely(lockup_detected(h))) { 2785 c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 2786 return IO_OK; 2787 } 2788 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); 2789 } 2790 2791 static u32 lockup_detected(struct ctlr_info *h) 2792 { 2793 int cpu; 2794 u32 rc, *lockup_detected; 2795 2796 cpu = get_cpu(); 2797 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 2798 rc = *lockup_detected; 2799 put_cpu(); 2800 return rc; 2801 } 2802 2803 #define MAX_DRIVER_CMD_RETRIES 25 2804 static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, 2805 struct CommandList *c, int data_direction, unsigned long timeout_msecs) 2806 { 2807 int backoff_time = 10, retry_count = 0; 2808 int rc; 2809 2810 do { 2811 memset(c->err_info, 0, sizeof(*c->err_info)); 2812 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 2813 timeout_msecs); 2814 if (rc) 2815 break; 2816 retry_count++; 2817 if (retry_count > 3) { 2818 msleep(backoff_time); 2819 if (backoff_time < 1000) 2820 backoff_time *= 2; 2821 } 2822 } while ((check_for_unit_attention(h, c) || 2823 check_for_busy(h, c)) && 2824 retry_count <= MAX_DRIVER_CMD_RETRIES); 2825 hpsa_pci_unmap(h->pdev, c, 1, data_direction); 2826 if (retry_count > MAX_DRIVER_CMD_RETRIES) 2827 rc = -EIO; 2828 return rc; 2829 } 2830 2831 static void hpsa_print_cmd(struct ctlr_info *h, char *txt, 2832 struct CommandList *c) 2833 { 2834 const u8 *cdb = c->Request.CDB; 2835 const u8 *lun = c->Header.LUN.LunAddrBytes; 2836 2837 dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n", 2838 txt, lun, cdb); 2839 } 2840 2841 static void hpsa_scsi_interpret_error(struct ctlr_info *h, 2842 struct CommandList *cp) 2843 { 2844 const struct ErrorInfo *ei = cp->err_info; 2845 struct device *d = &cp->h->pdev->dev; 2846 u8 sense_key, asc, ascq; 2847 int sense_len; 2848 2849 switch (ei->CommandStatus) { 2850 case CMD_TARGET_STATUS: 2851 if (ei->SenseLen > sizeof(ei->SenseInfo)) 2852 sense_len = sizeof(ei->SenseInfo); 2853 else 2854 sense_len = ei->SenseLen; 2855 decode_sense_data(ei->SenseInfo, sense_len, 2856 &sense_key, &asc, &ascq); 2857 hpsa_print_cmd(h, "SCSI status", cp); 2858 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) 2859 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", 2860 sense_key, asc, ascq); 2861 else 2862 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); 2863 if (ei->ScsiStatus == 0) 2864 dev_warn(d, "SCSI status is abnormally zero. " 2865 "(probably indicates selection timeout " 2866 "reported incorrectly due to a known " 2867 "firmware bug, circa July, 2001.)\n"); 2868 break; 2869 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2870 break; 2871 case CMD_DATA_OVERRUN: 2872 hpsa_print_cmd(h, "overrun condition", cp); 2873 break; 2874 case CMD_INVALID: { 2875 /* controller unfortunately reports SCSI passthru's 2876 * to non-existent targets as invalid commands. 2877 */ 2878 hpsa_print_cmd(h, "invalid command", cp); 2879 dev_warn(d, "probably means device no longer present\n"); 2880 } 2881 break; 2882 case CMD_PROTOCOL_ERR: 2883 hpsa_print_cmd(h, "protocol error", cp); 2884 break; 2885 case CMD_HARDWARE_ERR: 2886 hpsa_print_cmd(h, "hardware error", cp); 2887 break; 2888 case CMD_CONNECTION_LOST: 2889 hpsa_print_cmd(h, "connection lost", cp); 2890 break; 2891 case CMD_ABORTED: 2892 hpsa_print_cmd(h, "aborted", cp); 2893 break; 2894 case CMD_ABORT_FAILED: 2895 hpsa_print_cmd(h, "abort failed", cp); 2896 break; 2897 case CMD_UNSOLICITED_ABORT: 2898 hpsa_print_cmd(h, "unsolicited abort", cp); 2899 break; 2900 case CMD_TIMEOUT: 2901 hpsa_print_cmd(h, "timed out", cp); 2902 break; 2903 case CMD_UNABORTABLE: 2904 hpsa_print_cmd(h, "unabortable", cp); 2905 break; 2906 case CMD_CTLR_LOCKUP: 2907 hpsa_print_cmd(h, "controller lockup detected", cp); 2908 break; 2909 default: 2910 hpsa_print_cmd(h, "unknown status", cp); 2911 dev_warn(d, "Unknown command status %x\n", 2912 ei->CommandStatus); 2913 } 2914 } 2915 2916 static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, 2917 u16 page, unsigned char *buf, 2918 unsigned char bufsize) 2919 { 2920 int rc = IO_OK; 2921 struct CommandList *c; 2922 struct ErrorInfo *ei; 2923 2924 c = cmd_alloc(h); 2925 2926 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, 2927 page, scsi3addr, TYPE_CMD)) { 2928 rc = -1; 2929 goto out; 2930 } 2931 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 2932 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 2933 if (rc) 2934 goto out; 2935 ei = c->err_info; 2936 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 2937 hpsa_scsi_interpret_error(h, c); 2938 rc = -1; 2939 } 2940 out: 2941 cmd_free(h, c); 2942 return rc; 2943 } 2944 2945 static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, 2946 u8 reset_type, int reply_queue) 2947 { 2948 int rc = IO_OK; 2949 struct CommandList *c; 2950 struct ErrorInfo *ei; 2951 2952 c = cmd_alloc(h); 2953 2954 2955 /* fill_cmd can't fail here, no data buffer to map. */ 2956 (void) fill_cmd(c, reset_type, h, NULL, 0, 0, 2957 scsi3addr, TYPE_MSG); 2958 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); 2959 if (rc) { 2960 dev_warn(&h->pdev->dev, "Failed to send reset command\n"); 2961 goto out; 2962 } 2963 /* no unmap needed here because no data xfer. */ 2964 2965 ei = c->err_info; 2966 if (ei->CommandStatus != 0) { 2967 hpsa_scsi_interpret_error(h, c); 2968 rc = -1; 2969 } 2970 out: 2971 cmd_free(h, c); 2972 return rc; 2973 } 2974 2975 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 2976 struct hpsa_scsi_dev_t *dev, 2977 unsigned char *scsi3addr) 2978 { 2979 int i; 2980 bool match = false; 2981 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 2982 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; 2983 2984 if (hpsa_is_cmd_idle(c)) 2985 return false; 2986 2987 switch (c->cmd_type) { 2988 case CMD_SCSI: 2989 case CMD_IOCTL_PEND: 2990 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, 2991 sizeof(c->Header.LUN.LunAddrBytes)); 2992 break; 2993 2994 case CMD_IOACCEL1: 2995 case CMD_IOACCEL2: 2996 if (c->phys_disk == dev) { 2997 /* HBA mode match */ 2998 match = true; 2999 } else { 3000 /* Possible RAID mode -- check each phys dev. */ 3001 /* FIXME: Do we need to take out a lock here? If 3002 * so, we could just call hpsa_get_pdisk_of_ioaccel2() 3003 * instead. */ 3004 for (i = 0; i < dev->nphysical_disks && !match; i++) { 3005 /* FIXME: an alternate test might be 3006 * 3007 * match = dev->phys_disk[i]->ioaccel_handle 3008 * == c2->scsi_nexus; */ 3009 match = dev->phys_disk[i] == c->phys_disk; 3010 } 3011 } 3012 break; 3013 3014 case IOACCEL2_TMF: 3015 for (i = 0; i < dev->nphysical_disks && !match; i++) { 3016 match = dev->phys_disk[i]->ioaccel_handle == 3017 le32_to_cpu(ac->it_nexus); 3018 } 3019 break; 3020 3021 case 0: /* The command is in the middle of being initialized. */ 3022 match = false; 3023 break; 3024 3025 default: 3026 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", 3027 c->cmd_type); 3028 BUG(); 3029 } 3030 3031 return match; 3032 } 3033 3034 static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, 3035 unsigned char *scsi3addr, u8 reset_type, int reply_queue) 3036 { 3037 int i; 3038 int rc = 0; 3039 3040 /* We can really only handle one reset at a time */ 3041 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { 3042 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); 3043 return -EINTR; 3044 } 3045 3046 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0); 3047 3048 for (i = 0; i < h->nr_cmds; i++) { 3049 struct CommandList *c = h->cmd_pool + i; 3050 int refcount = atomic_inc_return(&c->refcount); 3051 3052 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) { 3053 unsigned long flags; 3054 3055 /* 3056 * Mark the target command as having a reset pending, 3057 * then lock a lock so that the command cannot complete 3058 * while we're considering it. If the command is not 3059 * idle then count it; otherwise revoke the event. 3060 */ 3061 c->reset_pending = dev; 3062 spin_lock_irqsave(&h->lock, flags); /* Implied MB */ 3063 if (!hpsa_is_cmd_idle(c)) 3064 atomic_inc(&dev->reset_cmds_out); 3065 else 3066 c->reset_pending = NULL; 3067 spin_unlock_irqrestore(&h->lock, flags); 3068 } 3069 3070 cmd_free(h, c); 3071 } 3072 3073 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue); 3074 if (!rc) 3075 wait_event(h->event_sync_wait_queue, 3076 atomic_read(&dev->reset_cmds_out) == 0 || 3077 lockup_detected(h)); 3078 3079 if (unlikely(lockup_detected(h))) { 3080 dev_warn(&h->pdev->dev, 3081 "Controller lockup detected during reset wait\n"); 3082 rc = -ENODEV; 3083 } 3084 3085 if (unlikely(rc)) 3086 atomic_set(&dev->reset_cmds_out, 0); 3087 else 3088 rc = wait_for_device_to_become_ready(h, scsi3addr, 0); 3089 3090 mutex_unlock(&h->reset_mutex); 3091 return rc; 3092 } 3093 3094 static void hpsa_get_raid_level(struct ctlr_info *h, 3095 unsigned char *scsi3addr, unsigned char *raid_level) 3096 { 3097 int rc; 3098 unsigned char *buf; 3099 3100 *raid_level = RAID_UNKNOWN; 3101 buf = kzalloc(64, GFP_KERNEL); 3102 if (!buf) 3103 return; 3104 3105 if (!hpsa_vpd_page_supported(h, scsi3addr, 3106 HPSA_VPD_LV_DEVICE_GEOMETRY)) 3107 goto exit; 3108 3109 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 3110 HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64); 3111 3112 if (rc == 0) 3113 *raid_level = buf[8]; 3114 if (*raid_level > RAID_UNKNOWN) 3115 *raid_level = RAID_UNKNOWN; 3116 exit: 3117 kfree(buf); 3118 return; 3119 } 3120 3121 #define HPSA_MAP_DEBUG 3122 #ifdef HPSA_MAP_DEBUG 3123 static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, 3124 struct raid_map_data *map_buff) 3125 { 3126 struct raid_map_disk_data *dd = &map_buff->data[0]; 3127 int map, row, col; 3128 u16 map_cnt, row_cnt, disks_per_row; 3129 3130 if (rc != 0) 3131 return; 3132 3133 /* Show details only if debugging has been activated. */ 3134 if (h->raid_offload_debug < 2) 3135 return; 3136 3137 dev_info(&h->pdev->dev, "structure_size = %u\n", 3138 le32_to_cpu(map_buff->structure_size)); 3139 dev_info(&h->pdev->dev, "volume_blk_size = %u\n", 3140 le32_to_cpu(map_buff->volume_blk_size)); 3141 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", 3142 le64_to_cpu(map_buff->volume_blk_cnt)); 3143 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", 3144 map_buff->phys_blk_shift); 3145 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", 3146 map_buff->parity_rotation_shift); 3147 dev_info(&h->pdev->dev, "strip_size = %u\n", 3148 le16_to_cpu(map_buff->strip_size)); 3149 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", 3150 le64_to_cpu(map_buff->disk_starting_blk)); 3151 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", 3152 le64_to_cpu(map_buff->disk_blk_cnt)); 3153 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", 3154 le16_to_cpu(map_buff->data_disks_per_row)); 3155 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", 3156 le16_to_cpu(map_buff->metadata_disks_per_row)); 3157 dev_info(&h->pdev->dev, "row_cnt = %u\n", 3158 le16_to_cpu(map_buff->row_cnt)); 3159 dev_info(&h->pdev->dev, "layout_map_count = %u\n", 3160 le16_to_cpu(map_buff->layout_map_count)); 3161 dev_info(&h->pdev->dev, "flags = 0x%x\n", 3162 le16_to_cpu(map_buff->flags)); 3163 dev_info(&h->pdev->dev, "encryption = %s\n", 3164 le16_to_cpu(map_buff->flags) & 3165 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); 3166 dev_info(&h->pdev->dev, "dekindex = %u\n", 3167 le16_to_cpu(map_buff->dekindex)); 3168 map_cnt = le16_to_cpu(map_buff->layout_map_count); 3169 for (map = 0; map < map_cnt; map++) { 3170 dev_info(&h->pdev->dev, "Map%u:\n", map); 3171 row_cnt = le16_to_cpu(map_buff->row_cnt); 3172 for (row = 0; row < row_cnt; row++) { 3173 dev_info(&h->pdev->dev, " Row%u:\n", row); 3174 disks_per_row = 3175 le16_to_cpu(map_buff->data_disks_per_row); 3176 for (col = 0; col < disks_per_row; col++, dd++) 3177 dev_info(&h->pdev->dev, 3178 " D%02u: h=0x%04x xor=%u,%u\n", 3179 col, dd->ioaccel_handle, 3180 dd->xor_mult[0], dd->xor_mult[1]); 3181 disks_per_row = 3182 le16_to_cpu(map_buff->metadata_disks_per_row); 3183 for (col = 0; col < disks_per_row; col++, dd++) 3184 dev_info(&h->pdev->dev, 3185 " M%02u: h=0x%04x xor=%u,%u\n", 3186 col, dd->ioaccel_handle, 3187 dd->xor_mult[0], dd->xor_mult[1]); 3188 } 3189 } 3190 } 3191 #else 3192 static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, 3193 __attribute__((unused)) int rc, 3194 __attribute__((unused)) struct raid_map_data *map_buff) 3195 { 3196 } 3197 #endif 3198 3199 static int hpsa_get_raid_map(struct ctlr_info *h, 3200 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3201 { 3202 int rc = 0; 3203 struct CommandList *c; 3204 struct ErrorInfo *ei; 3205 3206 c = cmd_alloc(h); 3207 3208 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, 3209 sizeof(this_device->raid_map), 0, 3210 scsi3addr, TYPE_CMD)) { 3211 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); 3212 cmd_free(h, c); 3213 return -1; 3214 } 3215 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3216 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 3217 if (rc) 3218 goto out; 3219 ei = c->err_info; 3220 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3221 hpsa_scsi_interpret_error(h, c); 3222 rc = -1; 3223 goto out; 3224 } 3225 cmd_free(h, c); 3226 3227 /* @todo in the future, dynamically allocate RAID map memory */ 3228 if (le32_to_cpu(this_device->raid_map.structure_size) > 3229 sizeof(this_device->raid_map)) { 3230 dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); 3231 rc = -1; 3232 } 3233 hpsa_debug_map_buff(h, rc, &this_device->raid_map); 3234 return rc; 3235 out: 3236 cmd_free(h, c); 3237 return rc; 3238 } 3239 3240 static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, 3241 unsigned char scsi3addr[], u16 bmic_device_index, 3242 struct bmic_sense_subsystem_info *buf, size_t bufsize) 3243 { 3244 int rc = IO_OK; 3245 struct CommandList *c; 3246 struct ErrorInfo *ei; 3247 3248 c = cmd_alloc(h); 3249 3250 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, 3251 0, RAID_CTLR_LUNID, TYPE_CMD); 3252 if (rc) 3253 goto out; 3254 3255 c->Request.CDB[2] = bmic_device_index & 0xff; 3256 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 3257 3258 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3259 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 3260 if (rc) 3261 goto out; 3262 ei = c->err_info; 3263 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3264 hpsa_scsi_interpret_error(h, c); 3265 rc = -1; 3266 } 3267 out: 3268 cmd_free(h, c); 3269 return rc; 3270 } 3271 3272 static int hpsa_bmic_id_controller(struct ctlr_info *h, 3273 struct bmic_identify_controller *buf, size_t bufsize) 3274 { 3275 int rc = IO_OK; 3276 struct CommandList *c; 3277 struct ErrorInfo *ei; 3278 3279 c = cmd_alloc(h); 3280 3281 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, 3282 0, RAID_CTLR_LUNID, TYPE_CMD); 3283 if (rc) 3284 goto out; 3285 3286 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3287 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 3288 if (rc) 3289 goto out; 3290 ei = c->err_info; 3291 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3292 hpsa_scsi_interpret_error(h, c); 3293 rc = -1; 3294 } 3295 out: 3296 cmd_free(h, c); 3297 return rc; 3298 } 3299 3300 static int hpsa_bmic_id_physical_device(struct ctlr_info *h, 3301 unsigned char scsi3addr[], u16 bmic_device_index, 3302 struct bmic_identify_physical_device *buf, size_t bufsize) 3303 { 3304 int rc = IO_OK; 3305 struct CommandList *c; 3306 struct ErrorInfo *ei; 3307 3308 c = cmd_alloc(h); 3309 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, 3310 0, RAID_CTLR_LUNID, TYPE_CMD); 3311 if (rc) 3312 goto out; 3313 3314 c->Request.CDB[2] = bmic_device_index & 0xff; 3315 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 3316 3317 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, 3318 NO_TIMEOUT); 3319 ei = c->err_info; 3320 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3321 hpsa_scsi_interpret_error(h, c); 3322 rc = -1; 3323 } 3324 out: 3325 cmd_free(h, c); 3326 3327 return rc; 3328 } 3329 3330 /* 3331 * get enclosure information 3332 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number 3333 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure 3334 * Uses id_physical_device to determine the box_index. 3335 */ 3336 static void hpsa_get_enclosure_info(struct ctlr_info *h, 3337 unsigned char *scsi3addr, 3338 struct ReportExtendedLUNdata *rlep, int rle_index, 3339 struct hpsa_scsi_dev_t *encl_dev) 3340 { 3341 int rc = -1; 3342 struct CommandList *c = NULL; 3343 struct ErrorInfo *ei = NULL; 3344 struct bmic_sense_storage_box_params *bssbp = NULL; 3345 struct bmic_identify_physical_device *id_phys = NULL; 3346 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; 3347 u16 bmic_device_index = 0; 3348 3349 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]); 3350 3351 if (encl_dev->target == -1 || encl_dev->lun == -1) { 3352 rc = IO_OK; 3353 goto out; 3354 } 3355 3356 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) { 3357 rc = IO_OK; 3358 goto out; 3359 } 3360 3361 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL); 3362 if (!bssbp) 3363 goto out; 3364 3365 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 3366 if (!id_phys) 3367 goto out; 3368 3369 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index, 3370 id_phys, sizeof(*id_phys)); 3371 if (rc) { 3372 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n", 3373 __func__, encl_dev->external, bmic_device_index); 3374 goto out; 3375 } 3376 3377 c = cmd_alloc(h); 3378 3379 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp, 3380 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD); 3381 3382 if (rc) 3383 goto out; 3384 3385 if (id_phys->phys_connector[1] == 'E') 3386 c->Request.CDB[5] = id_phys->box_index; 3387 else 3388 c->Request.CDB[5] = 0; 3389 3390 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, 3391 NO_TIMEOUT); 3392 if (rc) 3393 goto out; 3394 3395 ei = c->err_info; 3396 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3397 rc = -1; 3398 goto out; 3399 } 3400 3401 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port; 3402 memcpy(&encl_dev->phys_connector[id_phys->active_path_number], 3403 bssbp->phys_connector, sizeof(bssbp->phys_connector)); 3404 3405 rc = IO_OK; 3406 out: 3407 kfree(bssbp); 3408 kfree(id_phys); 3409 3410 if (c) 3411 cmd_free(h, c); 3412 3413 if (rc != IO_OK) 3414 hpsa_show_dev_msg(KERN_INFO, h, encl_dev, 3415 "Error, could not get enclosure information\n"); 3416 } 3417 3418 static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, 3419 unsigned char *scsi3addr) 3420 { 3421 struct ReportExtendedLUNdata *physdev; 3422 u32 nphysicals; 3423 u64 sa = 0; 3424 int i; 3425 3426 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); 3427 if (!physdev) 3428 return 0; 3429 3430 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 3431 dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 3432 kfree(physdev); 3433 return 0; 3434 } 3435 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; 3436 3437 for (i = 0; i < nphysicals; i++) 3438 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { 3439 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); 3440 break; 3441 } 3442 3443 kfree(physdev); 3444 3445 return sa; 3446 } 3447 3448 static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, 3449 struct hpsa_scsi_dev_t *dev) 3450 { 3451 int rc; 3452 u64 sa = 0; 3453 3454 if (is_hba_lunid(scsi3addr)) { 3455 struct bmic_sense_subsystem_info *ssi; 3456 3457 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); 3458 if (!ssi) 3459 return; 3460 3461 rc = hpsa_bmic_sense_subsystem_information(h, 3462 scsi3addr, 0, ssi, sizeof(*ssi)); 3463 if (rc == 0) { 3464 sa = get_unaligned_be64(ssi->primary_world_wide_id); 3465 h->sas_address = sa; 3466 } 3467 3468 kfree(ssi); 3469 } else 3470 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); 3471 3472 dev->sas_address = sa; 3473 } 3474 3475 static void hpsa_ext_ctrl_present(struct ctlr_info *h, 3476 struct ReportExtendedLUNdata *physdev) 3477 { 3478 u32 nphysicals; 3479 int i; 3480 3481 if (h->discovery_polling) 3482 return; 3483 3484 nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1; 3485 3486 for (i = 0; i < nphysicals; i++) { 3487 if (physdev->LUN[i].device_type == 3488 BMIC_DEVICE_TYPE_CONTROLLER 3489 && !is_hba_lunid(physdev->LUN[i].lunid)) { 3490 dev_info(&h->pdev->dev, 3491 "External controller present, activate discovery polling and disable rld caching\n"); 3492 hpsa_disable_rld_caching(h); 3493 h->discovery_polling = 1; 3494 break; 3495 } 3496 } 3497 } 3498 3499 /* Get a device id from inquiry page 0x83 */ 3500 static bool hpsa_vpd_page_supported(struct ctlr_info *h, 3501 unsigned char scsi3addr[], u8 page) 3502 { 3503 int rc; 3504 int i; 3505 int pages; 3506 unsigned char *buf, bufsize; 3507 3508 buf = kzalloc(256, GFP_KERNEL); 3509 if (!buf) 3510 return false; 3511 3512 /* Get the size of the page list first */ 3513 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3514 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 3515 buf, HPSA_VPD_HEADER_SZ); 3516 if (rc != 0) 3517 goto exit_unsupported; 3518 pages = buf[3]; 3519 if ((pages + HPSA_VPD_HEADER_SZ) <= 255) 3520 bufsize = pages + HPSA_VPD_HEADER_SZ; 3521 else 3522 bufsize = 255; 3523 3524 /* Get the whole VPD page list */ 3525 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3526 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 3527 buf, bufsize); 3528 if (rc != 0) 3529 goto exit_unsupported; 3530 3531 pages = buf[3]; 3532 for (i = 1; i <= pages; i++) 3533 if (buf[3 + i] == page) 3534 goto exit_supported; 3535 exit_unsupported: 3536 kfree(buf); 3537 return false; 3538 exit_supported: 3539 kfree(buf); 3540 return true; 3541 } 3542 3543 static void hpsa_get_ioaccel_status(struct ctlr_info *h, 3544 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3545 { 3546 int rc; 3547 unsigned char *buf; 3548 u8 ioaccel_status; 3549 3550 this_device->offload_config = 0; 3551 this_device->offload_enabled = 0; 3552 this_device->offload_to_be_enabled = 0; 3553 3554 buf = kzalloc(64, GFP_KERNEL); 3555 if (!buf) 3556 return; 3557 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) 3558 goto out; 3559 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3560 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); 3561 if (rc != 0) 3562 goto out; 3563 3564 #define IOACCEL_STATUS_BYTE 4 3565 #define OFFLOAD_CONFIGURED_BIT 0x01 3566 #define OFFLOAD_ENABLED_BIT 0x02 3567 ioaccel_status = buf[IOACCEL_STATUS_BYTE]; 3568 this_device->offload_config = 3569 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); 3570 if (this_device->offload_config) { 3571 this_device->offload_enabled = 3572 !!(ioaccel_status & OFFLOAD_ENABLED_BIT); 3573 if (hpsa_get_raid_map(h, scsi3addr, this_device)) 3574 this_device->offload_enabled = 0; 3575 } 3576 this_device->offload_to_be_enabled = this_device->offload_enabled; 3577 out: 3578 kfree(buf); 3579 return; 3580 } 3581 3582 /* Get the device id from inquiry page 0x83 */ 3583 static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, 3584 unsigned char *device_id, int index, int buflen) 3585 { 3586 int rc; 3587 unsigned char *buf; 3588 3589 /* Does controller have VPD for device id? */ 3590 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID)) 3591 return 1; /* not supported */ 3592 3593 buf = kzalloc(64, GFP_KERNEL); 3594 if (!buf) 3595 return -ENOMEM; 3596 3597 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 3598 HPSA_VPD_LV_DEVICE_ID, buf, 64); 3599 if (rc == 0) { 3600 if (buflen > 16) 3601 buflen = 16; 3602 memcpy(device_id, &buf[8], buflen); 3603 } 3604 3605 kfree(buf); 3606 3607 return rc; /*0 - got id, otherwise, didn't */ 3608 } 3609 3610 static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, 3611 void *buf, int bufsize, 3612 int extended_response) 3613 { 3614 int rc = IO_OK; 3615 struct CommandList *c; 3616 unsigned char scsi3addr[8]; 3617 struct ErrorInfo *ei; 3618 3619 c = cmd_alloc(h); 3620 3621 /* address the controller */ 3622 memset(scsi3addr, 0, sizeof(scsi3addr)); 3623 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, 3624 buf, bufsize, 0, scsi3addr, TYPE_CMD)) { 3625 rc = -EAGAIN; 3626 goto out; 3627 } 3628 if (extended_response) 3629 c->Request.CDB[1] = extended_response; 3630 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3631 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 3632 if (rc) 3633 goto out; 3634 ei = c->err_info; 3635 if (ei->CommandStatus != 0 && 3636 ei->CommandStatus != CMD_DATA_UNDERRUN) { 3637 hpsa_scsi_interpret_error(h, c); 3638 rc = -EIO; 3639 } else { 3640 struct ReportLUNdata *rld = buf; 3641 3642 if (rld->extended_response_flag != extended_response) { 3643 if (!h->legacy_board) { 3644 dev_err(&h->pdev->dev, 3645 "report luns requested format %u, got %u\n", 3646 extended_response, 3647 rld->extended_response_flag); 3648 rc = -EINVAL; 3649 } else 3650 rc = -EOPNOTSUPP; 3651 } 3652 } 3653 out: 3654 cmd_free(h, c); 3655 return rc; 3656 } 3657 3658 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 3659 struct ReportExtendedLUNdata *buf, int bufsize) 3660 { 3661 int rc; 3662 struct ReportLUNdata *lbuf; 3663 3664 rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize, 3665 HPSA_REPORT_PHYS_EXTENDED); 3666 if (!rc || rc != -EOPNOTSUPP) 3667 return rc; 3668 3669 /* REPORT PHYS EXTENDED is not supported */ 3670 lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL); 3671 if (!lbuf) 3672 return -ENOMEM; 3673 3674 rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0); 3675 if (!rc) { 3676 int i; 3677 u32 nphys; 3678 3679 /* Copy ReportLUNdata header */ 3680 memcpy(buf, lbuf, 8); 3681 nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8; 3682 for (i = 0; i < nphys; i++) 3683 memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8); 3684 } 3685 kfree(lbuf); 3686 return rc; 3687 } 3688 3689 static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, 3690 struct ReportLUNdata *buf, int bufsize) 3691 { 3692 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); 3693 } 3694 3695 static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, 3696 int bus, int target, int lun) 3697 { 3698 device->bus = bus; 3699 device->target = target; 3700 device->lun = lun; 3701 } 3702 3703 /* Use VPD inquiry to get details of volume status */ 3704 static int hpsa_get_volume_status(struct ctlr_info *h, 3705 unsigned char scsi3addr[]) 3706 { 3707 int rc; 3708 int status; 3709 int size; 3710 unsigned char *buf; 3711 3712 buf = kzalloc(64, GFP_KERNEL); 3713 if (!buf) 3714 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3715 3716 /* Does controller have VPD for logical volume status? */ 3717 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) 3718 goto exit_failed; 3719 3720 /* Get the size of the VPD return buffer */ 3721 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 3722 buf, HPSA_VPD_HEADER_SZ); 3723 if (rc != 0) 3724 goto exit_failed; 3725 size = buf[3]; 3726 3727 /* Now get the whole VPD buffer */ 3728 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 3729 buf, size + HPSA_VPD_HEADER_SZ); 3730 if (rc != 0) 3731 goto exit_failed; 3732 status = buf[4]; /* status byte */ 3733 3734 kfree(buf); 3735 return status; 3736 exit_failed: 3737 kfree(buf); 3738 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3739 } 3740 3741 /* Determine offline status of a volume. 3742 * Return either: 3743 * 0 (not offline) 3744 * 0xff (offline for unknown reasons) 3745 * # (integer code indicating one of several NOT READY states 3746 * describing why a volume is to be kept offline) 3747 */ 3748 static unsigned char hpsa_volume_offline(struct ctlr_info *h, 3749 unsigned char scsi3addr[]) 3750 { 3751 struct CommandList *c; 3752 unsigned char *sense; 3753 u8 sense_key, asc, ascq; 3754 int sense_len; 3755 int rc, ldstat = 0; 3756 u16 cmd_status; 3757 u8 scsi_status; 3758 #define ASC_LUN_NOT_READY 0x04 3759 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 3760 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 3761 3762 c = cmd_alloc(h); 3763 3764 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); 3765 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 3766 NO_TIMEOUT); 3767 if (rc) { 3768 cmd_free(h, c); 3769 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3770 } 3771 sense = c->err_info->SenseInfo; 3772 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 3773 sense_len = sizeof(c->err_info->SenseInfo); 3774 else 3775 sense_len = c->err_info->SenseLen; 3776 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); 3777 cmd_status = c->err_info->CommandStatus; 3778 scsi_status = c->err_info->ScsiStatus; 3779 cmd_free(h, c); 3780 3781 /* Determine the reason for not ready state */ 3782 ldstat = hpsa_get_volume_status(h, scsi3addr); 3783 3784 /* Keep volume offline in certain cases: */ 3785 switch (ldstat) { 3786 case HPSA_LV_FAILED: 3787 case HPSA_LV_UNDERGOING_ERASE: 3788 case HPSA_LV_NOT_AVAILABLE: 3789 case HPSA_LV_UNDERGOING_RPI: 3790 case HPSA_LV_PENDING_RPI: 3791 case HPSA_LV_ENCRYPTED_NO_KEY: 3792 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 3793 case HPSA_LV_UNDERGOING_ENCRYPTION: 3794 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 3795 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 3796 return ldstat; 3797 case HPSA_VPD_LV_STATUS_UNSUPPORTED: 3798 /* If VPD status page isn't available, 3799 * use ASC/ASCQ to determine state 3800 */ 3801 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || 3802 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) 3803 return ldstat; 3804 break; 3805 default: 3806 break; 3807 } 3808 return HPSA_LV_OK; 3809 } 3810 3811 static int hpsa_update_device_info(struct ctlr_info *h, 3812 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, 3813 unsigned char *is_OBDR_device) 3814 { 3815 3816 #define OBDR_SIG_OFFSET 43 3817 #define OBDR_TAPE_SIG "$DR-10" 3818 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 3819 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 3820 3821 unsigned char *inq_buff; 3822 unsigned char *obdr_sig; 3823 int rc = 0; 3824 3825 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); 3826 if (!inq_buff) { 3827 rc = -ENOMEM; 3828 goto bail_out; 3829 } 3830 3831 /* Do an inquiry to the device to see what it is. */ 3832 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, 3833 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { 3834 dev_err(&h->pdev->dev, 3835 "%s: inquiry failed, device will be skipped.\n", 3836 __func__); 3837 rc = HPSA_INQUIRY_FAILED; 3838 goto bail_out; 3839 } 3840 3841 scsi_sanitize_inquiry_string(&inq_buff[8], 8); 3842 scsi_sanitize_inquiry_string(&inq_buff[16], 16); 3843 3844 this_device->devtype = (inq_buff[0] & 0x1f); 3845 memcpy(this_device->scsi3addr, scsi3addr, 8); 3846 memcpy(this_device->vendor, &inq_buff[8], 3847 sizeof(this_device->vendor)); 3848 memcpy(this_device->model, &inq_buff[16], 3849 sizeof(this_device->model)); 3850 this_device->rev = inq_buff[2]; 3851 memset(this_device->device_id, 0, 3852 sizeof(this_device->device_id)); 3853 if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, 3854 sizeof(this_device->device_id)) < 0) 3855 dev_err(&h->pdev->dev, 3856 "hpsa%d: %s: can't get device id for host %d:C0:T%d:L%d\t%s\t%.16s\n", 3857 h->ctlr, __func__, 3858 h->scsi_host->host_no, 3859 this_device->target, this_device->lun, 3860 scsi_device_type(this_device->devtype), 3861 this_device->model); 3862 3863 if ((this_device->devtype == TYPE_DISK || 3864 this_device->devtype == TYPE_ZBC) && 3865 is_logical_dev_addr_mode(scsi3addr)) { 3866 unsigned char volume_offline; 3867 3868 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); 3869 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) 3870 hpsa_get_ioaccel_status(h, scsi3addr, this_device); 3871 volume_offline = hpsa_volume_offline(h, scsi3addr); 3872 if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED && 3873 h->legacy_board) { 3874 /* 3875 * Legacy boards might not support volume status 3876 */ 3877 dev_info(&h->pdev->dev, 3878 "C0:T%d:L%d Volume status not available, assuming online.\n", 3879 this_device->target, this_device->lun); 3880 volume_offline = 0; 3881 } 3882 this_device->volume_offline = volume_offline; 3883 if (volume_offline == HPSA_LV_FAILED) { 3884 rc = HPSA_LV_FAILED; 3885 dev_err(&h->pdev->dev, 3886 "%s: LV failed, device will be skipped.\n", 3887 __func__); 3888 goto bail_out; 3889 } 3890 } else { 3891 this_device->raid_level = RAID_UNKNOWN; 3892 this_device->offload_config = 0; 3893 this_device->offload_enabled = 0; 3894 this_device->offload_to_be_enabled = 0; 3895 this_device->hba_ioaccel_enabled = 0; 3896 this_device->volume_offline = 0; 3897 this_device->queue_depth = h->nr_cmds; 3898 } 3899 3900 if (this_device->external) 3901 this_device->queue_depth = EXTERNAL_QD; 3902 3903 if (is_OBDR_device) { 3904 /* See if this is a One-Button-Disaster-Recovery device 3905 * by looking for "$DR-10" at offset 43 in inquiry data. 3906 */ 3907 obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; 3908 *is_OBDR_device = (this_device->devtype == TYPE_ROM && 3909 strncmp(obdr_sig, OBDR_TAPE_SIG, 3910 OBDR_SIG_LEN) == 0); 3911 } 3912 kfree(inq_buff); 3913 return 0; 3914 3915 bail_out: 3916 kfree(inq_buff); 3917 return rc; 3918 } 3919 3920 /* 3921 * Helper function to assign bus, target, lun mapping of devices. 3922 * Logical drive target and lun are assigned at this time, but 3923 * physical device lun and target assignment are deferred (assigned 3924 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) 3925 */ 3926 static void figure_bus_target_lun(struct ctlr_info *h, 3927 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) 3928 { 3929 u32 lunid = get_unaligned_le32(lunaddrbytes); 3930 3931 if (!is_logical_dev_addr_mode(lunaddrbytes)) { 3932 /* physical device, target and lun filled in later */ 3933 if (is_hba_lunid(lunaddrbytes)) { 3934 int bus = HPSA_HBA_BUS; 3935 3936 if (!device->rev) 3937 bus = HPSA_LEGACY_HBA_BUS; 3938 hpsa_set_bus_target_lun(device, 3939 bus, 0, lunid & 0x3fff); 3940 } else 3941 /* defer target, lun assignment for physical devices */ 3942 hpsa_set_bus_target_lun(device, 3943 HPSA_PHYSICAL_DEVICE_BUS, -1, -1); 3944 return; 3945 } 3946 /* It's a logical device */ 3947 if (device->external) { 3948 hpsa_set_bus_target_lun(device, 3949 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, 3950 lunid & 0x00ff); 3951 return; 3952 } 3953 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, 3954 0, lunid & 0x3fff); 3955 } 3956 3957 static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, 3958 int i, int nphysicals, int nlocal_logicals) 3959 { 3960 /* In report logicals, local logicals are listed first, 3961 * then any externals. 3962 */ 3963 int logicals_start = nphysicals + (raid_ctlr_position == 0); 3964 3965 if (i == raid_ctlr_position) 3966 return 0; 3967 3968 if (i < logicals_start) 3969 return 0; 3970 3971 /* i is in logicals range, but still within local logicals */ 3972 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) 3973 return 0; 3974 3975 return 1; /* it's an external lun */ 3976 } 3977 3978 /* 3979 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, 3980 * logdev. The number of luns in physdev and logdev are returned in 3981 * *nphysicals and *nlogicals, respectively. 3982 * Returns 0 on success, -1 otherwise. 3983 */ 3984 static int hpsa_gather_lun_info(struct ctlr_info *h, 3985 struct ReportExtendedLUNdata *physdev, u32 *nphysicals, 3986 struct ReportLUNdata *logdev, u32 *nlogicals) 3987 { 3988 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 3989 dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 3990 return -1; 3991 } 3992 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; 3993 if (*nphysicals > HPSA_MAX_PHYS_LUN) { 3994 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", 3995 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); 3996 *nphysicals = HPSA_MAX_PHYS_LUN; 3997 } 3998 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { 3999 dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); 4000 return -1; 4001 } 4002 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; 4003 /* Reject Logicals in excess of our max capability. */ 4004 if (*nlogicals > HPSA_MAX_LUN) { 4005 dev_warn(&h->pdev->dev, 4006 "maximum logical LUNs (%d) exceeded. " 4007 "%d LUNs ignored.\n", HPSA_MAX_LUN, 4008 *nlogicals - HPSA_MAX_LUN); 4009 *nlogicals = HPSA_MAX_LUN; 4010 } 4011 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { 4012 dev_warn(&h->pdev->dev, 4013 "maximum logical + physical LUNs (%d) exceeded. " 4014 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, 4015 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); 4016 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; 4017 } 4018 return 0; 4019 } 4020 4021 static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, 4022 int i, int nphysicals, int nlogicals, 4023 struct ReportExtendedLUNdata *physdev_list, 4024 struct ReportLUNdata *logdev_list) 4025 { 4026 /* Helper function, figure out where the LUN ID info is coming from 4027 * given index i, lists of physical and logical devices, where in 4028 * the list the raid controller is supposed to appear (first or last) 4029 */ 4030 4031 int logicals_start = nphysicals + (raid_ctlr_position == 0); 4032 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); 4033 4034 if (i == raid_ctlr_position) 4035 return RAID_CTLR_LUNID; 4036 4037 if (i < logicals_start) 4038 return &physdev_list->LUN[i - 4039 (raid_ctlr_position == 0)].lunid[0]; 4040 4041 if (i < last_device) 4042 return &logdev_list->LUN[i - nphysicals - 4043 (raid_ctlr_position == 0)][0]; 4044 BUG(); 4045 return NULL; 4046 } 4047 4048 /* get physical drive ioaccel handle and queue depth */ 4049 static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, 4050 struct hpsa_scsi_dev_t *dev, 4051 struct ReportExtendedLUNdata *rlep, int rle_index, 4052 struct bmic_identify_physical_device *id_phys) 4053 { 4054 int rc; 4055 struct ext_report_lun_entry *rle; 4056 4057 rle = &rlep->LUN[rle_index]; 4058 4059 dev->ioaccel_handle = rle->ioaccel_handle; 4060 if ((rle->device_flags & 0x08) && dev->ioaccel_handle) 4061 dev->hba_ioaccel_enabled = 1; 4062 memset(id_phys, 0, sizeof(*id_phys)); 4063 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], 4064 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, 4065 sizeof(*id_phys)); 4066 if (!rc) 4067 /* Reserve space for FW operations */ 4068 #define DRIVE_CMDS_RESERVED_FOR_FW 2 4069 #define DRIVE_QUEUE_DEPTH 7 4070 dev->queue_depth = 4071 le16_to_cpu(id_phys->current_queue_depth_limit) - 4072 DRIVE_CMDS_RESERVED_FOR_FW; 4073 else 4074 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ 4075 } 4076 4077 static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, 4078 struct ReportExtendedLUNdata *rlep, int rle_index, 4079 struct bmic_identify_physical_device *id_phys) 4080 { 4081 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; 4082 4083 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) 4084 this_device->hba_ioaccel_enabled = 1; 4085 4086 memcpy(&this_device->active_path_index, 4087 &id_phys->active_path_number, 4088 sizeof(this_device->active_path_index)); 4089 memcpy(&this_device->path_map, 4090 &id_phys->redundant_path_present_map, 4091 sizeof(this_device->path_map)); 4092 memcpy(&this_device->box, 4093 &id_phys->alternate_paths_phys_box_on_port, 4094 sizeof(this_device->box)); 4095 memcpy(&this_device->phys_connector, 4096 &id_phys->alternate_paths_phys_connector, 4097 sizeof(this_device->phys_connector)); 4098 memcpy(&this_device->bay, 4099 &id_phys->phys_bay_in_box, 4100 sizeof(this_device->bay)); 4101 } 4102 4103 /* get number of local logical disks. */ 4104 static int hpsa_set_local_logical_count(struct ctlr_info *h, 4105 struct bmic_identify_controller *id_ctlr, 4106 u32 *nlocals) 4107 { 4108 int rc; 4109 4110 if (!id_ctlr) { 4111 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", 4112 __func__); 4113 return -ENOMEM; 4114 } 4115 memset(id_ctlr, 0, sizeof(*id_ctlr)); 4116 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); 4117 if (!rc) 4118 if (id_ctlr->configured_logical_drive_count < 256) 4119 *nlocals = id_ctlr->configured_logical_drive_count; 4120 else 4121 *nlocals = le16_to_cpu( 4122 id_ctlr->extended_logical_unit_count); 4123 else 4124 *nlocals = -1; 4125 return rc; 4126 } 4127 4128 static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes) 4129 { 4130 struct bmic_identify_physical_device *id_phys; 4131 bool is_spare = false; 4132 int rc; 4133 4134 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 4135 if (!id_phys) 4136 return false; 4137 4138 rc = hpsa_bmic_id_physical_device(h, 4139 lunaddrbytes, 4140 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), 4141 id_phys, sizeof(*id_phys)); 4142 if (rc == 0) 4143 is_spare = (id_phys->more_flags >> 6) & 0x01; 4144 4145 kfree(id_phys); 4146 return is_spare; 4147 } 4148 4149 #define RPL_DEV_FLAG_NON_DISK 0x1 4150 #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2 4151 #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4 4152 4153 #define BMIC_DEVICE_TYPE_ENCLOSURE 6 4154 4155 static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes, 4156 struct ext_report_lun_entry *rle) 4157 { 4158 u8 device_flags; 4159 u8 device_type; 4160 4161 if (!MASKED_DEVICE(lunaddrbytes)) 4162 return false; 4163 4164 device_flags = rle->device_flags; 4165 device_type = rle->device_type; 4166 4167 if (device_flags & RPL_DEV_FLAG_NON_DISK) { 4168 if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE) 4169 return false; 4170 return true; 4171 } 4172 4173 if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED)) 4174 return false; 4175 4176 if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK) 4177 return false; 4178 4179 /* 4180 * Spares may be spun down, we do not want to 4181 * do an Inquiry to a RAID set spare drive as 4182 * that would have them spun up, that is a 4183 * performance hit because I/O to the RAID device 4184 * stops while the spin up occurs which can take 4185 * over 50 seconds. 4186 */ 4187 if (hpsa_is_disk_spare(h, lunaddrbytes)) 4188 return true; 4189 4190 return false; 4191 } 4192 4193 static void hpsa_update_scsi_devices(struct ctlr_info *h) 4194 { 4195 /* the idea here is we could get notified 4196 * that some devices have changed, so we do a report 4197 * physical luns and report logical luns cmd, and adjust 4198 * our list of devices accordingly. 4199 * 4200 * The scsi3addr's of devices won't change so long as the 4201 * adapter is not reset. That means we can rescan and 4202 * tell which devices we already know about, vs. new 4203 * devices, vs. disappearing devices. 4204 */ 4205 struct ReportExtendedLUNdata *physdev_list = NULL; 4206 struct ReportLUNdata *logdev_list = NULL; 4207 struct bmic_identify_physical_device *id_phys = NULL; 4208 struct bmic_identify_controller *id_ctlr = NULL; 4209 u32 nphysicals = 0; 4210 u32 nlogicals = 0; 4211 u32 nlocal_logicals = 0; 4212 u32 ndev_allocated = 0; 4213 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; 4214 int ncurrent = 0; 4215 int i, n_ext_target_devs, ndevs_to_allocate; 4216 int raid_ctlr_position; 4217 bool physical_device; 4218 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); 4219 4220 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); 4221 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); 4222 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); 4223 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); 4224 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 4225 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); 4226 4227 if (!currentsd || !physdev_list || !logdev_list || 4228 !tmpdevice || !id_phys || !id_ctlr) { 4229 dev_err(&h->pdev->dev, "out of memory\n"); 4230 goto out; 4231 } 4232 memset(lunzerobits, 0, sizeof(lunzerobits)); 4233 4234 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ 4235 4236 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, 4237 logdev_list, &nlogicals)) { 4238 h->drv_req_rescan = 1; 4239 goto out; 4240 } 4241 4242 /* Set number of local logicals (non PTRAID) */ 4243 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { 4244 dev_warn(&h->pdev->dev, 4245 "%s: Can't determine number of local logical devices.\n", 4246 __func__); 4247 } 4248 4249 /* We might see up to the maximum number of logical and physical disks 4250 * plus external target devices, and a device for the local RAID 4251 * controller. 4252 */ 4253 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; 4254 4255 hpsa_ext_ctrl_present(h, physdev_list); 4256 4257 /* Allocate the per device structures */ 4258 for (i = 0; i < ndevs_to_allocate; i++) { 4259 if (i >= HPSA_MAX_DEVICES) { 4260 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." 4261 " %d devices ignored.\n", HPSA_MAX_DEVICES, 4262 ndevs_to_allocate - HPSA_MAX_DEVICES); 4263 break; 4264 } 4265 4266 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); 4267 if (!currentsd[i]) { 4268 h->drv_req_rescan = 1; 4269 goto out; 4270 } 4271 ndev_allocated++; 4272 } 4273 4274 if (is_scsi_rev_5(h)) 4275 raid_ctlr_position = 0; 4276 else 4277 raid_ctlr_position = nphysicals + nlogicals; 4278 4279 /* adjust our table of devices */ 4280 n_ext_target_devs = 0; 4281 for (i = 0; i < nphysicals + nlogicals + 1; i++) { 4282 u8 *lunaddrbytes, is_OBDR = 0; 4283 int rc = 0; 4284 int phys_dev_index = i - (raid_ctlr_position == 0); 4285 bool skip_device = false; 4286 4287 memset(tmpdevice, 0, sizeof(*tmpdevice)); 4288 4289 physical_device = i < nphysicals + (raid_ctlr_position == 0); 4290 4291 /* Figure out where the LUN ID info is coming from */ 4292 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, 4293 i, nphysicals, nlogicals, physdev_list, logdev_list); 4294 4295 /* Determine if this is a lun from an external target array */ 4296 tmpdevice->external = 4297 figure_external_status(h, raid_ctlr_position, i, 4298 nphysicals, nlocal_logicals); 4299 4300 /* 4301 * Skip over some devices such as a spare. 4302 */ 4303 if (!tmpdevice->external && physical_device) { 4304 skip_device = hpsa_skip_device(h, lunaddrbytes, 4305 &physdev_list->LUN[phys_dev_index]); 4306 if (skip_device) 4307 continue; 4308 } 4309 4310 /* Get device type, vendor, model, device id */ 4311 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, 4312 &is_OBDR); 4313 if (rc == -ENOMEM) { 4314 dev_warn(&h->pdev->dev, 4315 "Out of memory, rescan deferred.\n"); 4316 h->drv_req_rescan = 1; 4317 goto out; 4318 } 4319 if (rc) { 4320 h->drv_req_rescan = 1; 4321 continue; 4322 } 4323 4324 figure_bus_target_lun(h, lunaddrbytes, tmpdevice); 4325 this_device = currentsd[ncurrent]; 4326 4327 *this_device = *tmpdevice; 4328 this_device->physical_device = physical_device; 4329 4330 /* 4331 * Expose all devices except for physical devices that 4332 * are masked. 4333 */ 4334 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) 4335 this_device->expose_device = 0; 4336 else 4337 this_device->expose_device = 1; 4338 4339 4340 /* 4341 * Get the SAS address for physical devices that are exposed. 4342 */ 4343 if (this_device->physical_device && this_device->expose_device) 4344 hpsa_get_sas_address(h, lunaddrbytes, this_device); 4345 4346 switch (this_device->devtype) { 4347 case TYPE_ROM: 4348 /* We don't *really* support actual CD-ROM devices, 4349 * just "One Button Disaster Recovery" tape drive 4350 * which temporarily pretends to be a CD-ROM drive. 4351 * So we check that the device is really an OBDR tape 4352 * device by checking for "$DR-10" in bytes 43-48 of 4353 * the inquiry data. 4354 */ 4355 if (is_OBDR) 4356 ncurrent++; 4357 break; 4358 case TYPE_DISK: 4359 case TYPE_ZBC: 4360 if (this_device->physical_device) { 4361 /* The disk is in HBA mode. */ 4362 /* Never use RAID mapper in HBA mode. */ 4363 this_device->offload_enabled = 0; 4364 hpsa_get_ioaccel_drive_info(h, this_device, 4365 physdev_list, phys_dev_index, id_phys); 4366 hpsa_get_path_info(this_device, 4367 physdev_list, phys_dev_index, id_phys); 4368 } 4369 ncurrent++; 4370 break; 4371 case TYPE_TAPE: 4372 case TYPE_MEDIUM_CHANGER: 4373 ncurrent++; 4374 break; 4375 case TYPE_ENCLOSURE: 4376 if (!this_device->external) 4377 hpsa_get_enclosure_info(h, lunaddrbytes, 4378 physdev_list, phys_dev_index, 4379 this_device); 4380 ncurrent++; 4381 break; 4382 case TYPE_RAID: 4383 /* Only present the Smartarray HBA as a RAID controller. 4384 * If it's a RAID controller other than the HBA itself 4385 * (an external RAID controller, MSA500 or similar) 4386 * don't present it. 4387 */ 4388 if (!is_hba_lunid(lunaddrbytes)) 4389 break; 4390 ncurrent++; 4391 break; 4392 default: 4393 break; 4394 } 4395 if (ncurrent >= HPSA_MAX_DEVICES) 4396 break; 4397 } 4398 4399 if (h->sas_host == NULL) { 4400 int rc = 0; 4401 4402 rc = hpsa_add_sas_host(h); 4403 if (rc) { 4404 dev_warn(&h->pdev->dev, 4405 "Could not add sas host %d\n", rc); 4406 goto out; 4407 } 4408 } 4409 4410 adjust_hpsa_scsi_table(h, currentsd, ncurrent); 4411 out: 4412 kfree(tmpdevice); 4413 for (i = 0; i < ndev_allocated; i++) 4414 kfree(currentsd[i]); 4415 kfree(currentsd); 4416 kfree(physdev_list); 4417 kfree(logdev_list); 4418 kfree(id_ctlr); 4419 kfree(id_phys); 4420 } 4421 4422 static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, 4423 struct scatterlist *sg) 4424 { 4425 u64 addr64 = (u64) sg_dma_address(sg); 4426 unsigned int len = sg_dma_len(sg); 4427 4428 desc->Addr = cpu_to_le64(addr64); 4429 desc->Len = cpu_to_le32(len); 4430 desc->Ext = 0; 4431 } 4432 4433 /* 4434 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci 4435 * dma mapping and fills in the scatter gather entries of the 4436 * hpsa command, cp. 4437 */ 4438 static int hpsa_scatter_gather(struct ctlr_info *h, 4439 struct CommandList *cp, 4440 struct scsi_cmnd *cmd) 4441 { 4442 struct scatterlist *sg; 4443 int use_sg, i, sg_limit, chained, last_sg; 4444 struct SGDescriptor *curr_sg; 4445 4446 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4447 4448 use_sg = scsi_dma_map(cmd); 4449 if (use_sg < 0) 4450 return use_sg; 4451 4452 if (!use_sg) 4453 goto sglist_finished; 4454 4455 /* 4456 * If the number of entries is greater than the max for a single list, 4457 * then we have a chained list; we will set up all but one entry in the 4458 * first list (the last entry is saved for link information); 4459 * otherwise, we don't have a chained list and we'll set up at each of 4460 * the entries in the one list. 4461 */ 4462 curr_sg = cp->SG; 4463 chained = use_sg > h->max_cmd_sg_entries; 4464 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; 4465 last_sg = scsi_sg_count(cmd) - 1; 4466 scsi_for_each_sg(cmd, sg, sg_limit, i) { 4467 hpsa_set_sg_descriptor(curr_sg, sg); 4468 curr_sg++; 4469 } 4470 4471 if (chained) { 4472 /* 4473 * Continue with the chained list. Set curr_sg to the chained 4474 * list. Modify the limit to the total count less the entries 4475 * we've already set up. Resume the scan at the list entry 4476 * where the previous loop left off. 4477 */ 4478 curr_sg = h->cmd_sg_list[cp->cmdindex]; 4479 sg_limit = use_sg - sg_limit; 4480 for_each_sg(sg, sg, sg_limit, i) { 4481 hpsa_set_sg_descriptor(curr_sg, sg); 4482 curr_sg++; 4483 } 4484 } 4485 4486 /* Back the pointer up to the last entry and mark it as "last". */ 4487 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); 4488 4489 if (use_sg + chained > h->maxSG) 4490 h->maxSG = use_sg + chained; 4491 4492 if (chained) { 4493 cp->Header.SGList = h->max_cmd_sg_entries; 4494 cp->Header.SGTotal = cpu_to_le16(use_sg + 1); 4495 if (hpsa_map_sg_chain_block(h, cp)) { 4496 scsi_dma_unmap(cmd); 4497 return -1; 4498 } 4499 return 0; 4500 } 4501 4502 sglist_finished: 4503 4504 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ 4505 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ 4506 return 0; 4507 } 4508 4509 #define BUFLEN 128 4510 static inline void warn_zero_length_transfer(struct ctlr_info *h, 4511 u8 *cdb, int cdb_len, 4512 const char *func) 4513 { 4514 char buf[BUFLEN]; 4515 int outlen; 4516 int i; 4517 4518 outlen = scnprintf(buf, BUFLEN, 4519 "%s: Blocking zero-length request: CDB:", func); 4520 for (i = 0; i < cdb_len; i++) 4521 outlen += scnprintf(buf+outlen, BUFLEN - outlen, 4522 "%02hhx", cdb[i]); 4523 dev_warn(&h->pdev->dev, "%s\n", buf); 4524 } 4525 4526 #define IO_ACCEL_INELIGIBLE 1 4527 /* zero-length transfers trigger hardware errors. */ 4528 static bool is_zero_length_transfer(u8 *cdb) 4529 { 4530 u32 block_cnt; 4531 4532 /* Block zero-length transfer sizes on certain commands. */ 4533 switch (cdb[0]) { 4534 case READ_10: 4535 case WRITE_10: 4536 case VERIFY: /* 0x2F */ 4537 case WRITE_VERIFY: /* 0x2E */ 4538 block_cnt = get_unaligned_be16(&cdb[7]); 4539 break; 4540 case READ_12: 4541 case WRITE_12: 4542 case VERIFY_12: /* 0xAF */ 4543 case WRITE_VERIFY_12: /* 0xAE */ 4544 block_cnt = get_unaligned_be32(&cdb[6]); 4545 break; 4546 case READ_16: 4547 case WRITE_16: 4548 case VERIFY_16: /* 0x8F */ 4549 block_cnt = get_unaligned_be32(&cdb[10]); 4550 break; 4551 default: 4552 return false; 4553 } 4554 4555 return block_cnt == 0; 4556 } 4557 4558 static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) 4559 { 4560 int is_write = 0; 4561 u32 block; 4562 u32 block_cnt; 4563 4564 /* Perform some CDB fixups if needed using 10 byte reads/writes only */ 4565 switch (cdb[0]) { 4566 case WRITE_6: 4567 case WRITE_12: 4568 is_write = 1; 4569 case READ_6: 4570 case READ_12: 4571 if (*cdb_len == 6) { 4572 block = (((cdb[1] & 0x1F) << 16) | 4573 (cdb[2] << 8) | 4574 cdb[3]); 4575 block_cnt = cdb[4]; 4576 if (block_cnt == 0) 4577 block_cnt = 256; 4578 } else { 4579 BUG_ON(*cdb_len != 12); 4580 block = get_unaligned_be32(&cdb[2]); 4581 block_cnt = get_unaligned_be32(&cdb[6]); 4582 } 4583 if (block_cnt > 0xffff) 4584 return IO_ACCEL_INELIGIBLE; 4585 4586 cdb[0] = is_write ? WRITE_10 : READ_10; 4587 cdb[1] = 0; 4588 cdb[2] = (u8) (block >> 24); 4589 cdb[3] = (u8) (block >> 16); 4590 cdb[4] = (u8) (block >> 8); 4591 cdb[5] = (u8) (block); 4592 cdb[6] = 0; 4593 cdb[7] = (u8) (block_cnt >> 8); 4594 cdb[8] = (u8) (block_cnt); 4595 cdb[9] = 0; 4596 *cdb_len = 10; 4597 break; 4598 } 4599 return 0; 4600 } 4601 4602 static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, 4603 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4604 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4605 { 4606 struct scsi_cmnd *cmd = c->scsi_cmd; 4607 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 4608 unsigned int len; 4609 unsigned int total_len = 0; 4610 struct scatterlist *sg; 4611 u64 addr64; 4612 int use_sg, i; 4613 struct SGDescriptor *curr_sg; 4614 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; 4615 4616 /* TODO: implement chaining support */ 4617 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { 4618 atomic_dec(&phys_disk->ioaccel_cmds_out); 4619 return IO_ACCEL_INELIGIBLE; 4620 } 4621 4622 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); 4623 4624 if (is_zero_length_transfer(cdb)) { 4625 warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4626 atomic_dec(&phys_disk->ioaccel_cmds_out); 4627 return IO_ACCEL_INELIGIBLE; 4628 } 4629 4630 if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 4631 atomic_dec(&phys_disk->ioaccel_cmds_out); 4632 return IO_ACCEL_INELIGIBLE; 4633 } 4634 4635 c->cmd_type = CMD_IOACCEL1; 4636 4637 /* Adjust the DMA address to point to the accelerated command buffer */ 4638 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + 4639 (c->cmdindex * sizeof(*cp)); 4640 BUG_ON(c->busaddr & 0x0000007F); 4641 4642 use_sg = scsi_dma_map(cmd); 4643 if (use_sg < 0) { 4644 atomic_dec(&phys_disk->ioaccel_cmds_out); 4645 return use_sg; 4646 } 4647 4648 if (use_sg) { 4649 curr_sg = cp->SG; 4650 scsi_for_each_sg(cmd, sg, use_sg, i) { 4651 addr64 = (u64) sg_dma_address(sg); 4652 len = sg_dma_len(sg); 4653 total_len += len; 4654 curr_sg->Addr = cpu_to_le64(addr64); 4655 curr_sg->Len = cpu_to_le32(len); 4656 curr_sg->Ext = cpu_to_le32(0); 4657 curr_sg++; 4658 } 4659 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); 4660 4661 switch (cmd->sc_data_direction) { 4662 case DMA_TO_DEVICE: 4663 control |= IOACCEL1_CONTROL_DATA_OUT; 4664 break; 4665 case DMA_FROM_DEVICE: 4666 control |= IOACCEL1_CONTROL_DATA_IN; 4667 break; 4668 case DMA_NONE: 4669 control |= IOACCEL1_CONTROL_NODATAXFER; 4670 break; 4671 default: 4672 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 4673 cmd->sc_data_direction); 4674 BUG(); 4675 break; 4676 } 4677 } else { 4678 control |= IOACCEL1_CONTROL_NODATAXFER; 4679 } 4680 4681 c->Header.SGList = use_sg; 4682 /* Fill out the command structure to submit */ 4683 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); 4684 cp->transfer_len = cpu_to_le32(total_len); 4685 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | 4686 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); 4687 cp->control = cpu_to_le32(control); 4688 memcpy(cp->CDB, cdb, cdb_len); 4689 memcpy(cp->CISS_LUN, scsi3addr, 8); 4690 /* Tag was already set at init time. */ 4691 enqueue_cmd_and_start_io(h, c); 4692 return 0; 4693 } 4694 4695 /* 4696 * Queue a command directly to a device behind the controller using the 4697 * I/O accelerator path. 4698 */ 4699 static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, 4700 struct CommandList *c) 4701 { 4702 struct scsi_cmnd *cmd = c->scsi_cmd; 4703 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4704 4705 if (!dev) 4706 return -1; 4707 4708 c->phys_disk = dev; 4709 4710 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, 4711 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); 4712 } 4713 4714 /* 4715 * Set encryption parameters for the ioaccel2 request 4716 */ 4717 static void set_encrypt_ioaccel2(struct ctlr_info *h, 4718 struct CommandList *c, struct io_accel2_cmd *cp) 4719 { 4720 struct scsi_cmnd *cmd = c->scsi_cmd; 4721 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4722 struct raid_map_data *map = &dev->raid_map; 4723 u64 first_block; 4724 4725 /* Are we doing encryption on this device */ 4726 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) 4727 return; 4728 /* Set the data encryption key index. */ 4729 cp->dekindex = map->dekindex; 4730 4731 /* Set the encryption enable flag, encoded into direction field. */ 4732 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; 4733 4734 /* Set encryption tweak values based on logical block address 4735 * If block size is 512, tweak value is LBA. 4736 * For other block sizes, tweak is (LBA * block size)/ 512) 4737 */ 4738 switch (cmd->cmnd[0]) { 4739 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ 4740 case READ_6: 4741 case WRITE_6: 4742 first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 4743 (cmd->cmnd[2] << 8) | 4744 cmd->cmnd[3]); 4745 break; 4746 case WRITE_10: 4747 case READ_10: 4748 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ 4749 case WRITE_12: 4750 case READ_12: 4751 first_block = get_unaligned_be32(&cmd->cmnd[2]); 4752 break; 4753 case WRITE_16: 4754 case READ_16: 4755 first_block = get_unaligned_be64(&cmd->cmnd[2]); 4756 break; 4757 default: 4758 dev_err(&h->pdev->dev, 4759 "ERROR: %s: size (0x%x) not supported for encryption\n", 4760 __func__, cmd->cmnd[0]); 4761 BUG(); 4762 break; 4763 } 4764 4765 if (le32_to_cpu(map->volume_blk_size) != 512) 4766 first_block = first_block * 4767 le32_to_cpu(map->volume_blk_size)/512; 4768 4769 cp->tweak_lower = cpu_to_le32(first_block); 4770 cp->tweak_upper = cpu_to_le32(first_block >> 32); 4771 } 4772 4773 static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, 4774 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4775 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4776 { 4777 struct scsi_cmnd *cmd = c->scsi_cmd; 4778 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 4779 struct ioaccel2_sg_element *curr_sg; 4780 int use_sg, i; 4781 struct scatterlist *sg; 4782 u64 addr64; 4783 u32 len; 4784 u32 total_len = 0; 4785 4786 if (!cmd->device) 4787 return -1; 4788 4789 if (!cmd->device->hostdata) 4790 return -1; 4791 4792 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4793 4794 if (is_zero_length_transfer(cdb)) { 4795 warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4796 atomic_dec(&phys_disk->ioaccel_cmds_out); 4797 return IO_ACCEL_INELIGIBLE; 4798 } 4799 4800 if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 4801 atomic_dec(&phys_disk->ioaccel_cmds_out); 4802 return IO_ACCEL_INELIGIBLE; 4803 } 4804 4805 c->cmd_type = CMD_IOACCEL2; 4806 /* Adjust the DMA address to point to the accelerated command buffer */ 4807 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + 4808 (c->cmdindex * sizeof(*cp)); 4809 BUG_ON(c->busaddr & 0x0000007F); 4810 4811 memset(cp, 0, sizeof(*cp)); 4812 cp->IU_type = IOACCEL2_IU_TYPE; 4813 4814 use_sg = scsi_dma_map(cmd); 4815 if (use_sg < 0) { 4816 atomic_dec(&phys_disk->ioaccel_cmds_out); 4817 return use_sg; 4818 } 4819 4820 if (use_sg) { 4821 curr_sg = cp->sg; 4822 if (use_sg > h->ioaccel_maxsg) { 4823 addr64 = le64_to_cpu( 4824 h->ioaccel2_cmd_sg_list[c->cmdindex]->address); 4825 curr_sg->address = cpu_to_le64(addr64); 4826 curr_sg->length = 0; 4827 curr_sg->reserved[0] = 0; 4828 curr_sg->reserved[1] = 0; 4829 curr_sg->reserved[2] = 0; 4830 curr_sg->chain_indicator = 0x80; 4831 4832 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; 4833 } 4834 scsi_for_each_sg(cmd, sg, use_sg, i) { 4835 addr64 = (u64) sg_dma_address(sg); 4836 len = sg_dma_len(sg); 4837 total_len += len; 4838 curr_sg->address = cpu_to_le64(addr64); 4839 curr_sg->length = cpu_to_le32(len); 4840 curr_sg->reserved[0] = 0; 4841 curr_sg->reserved[1] = 0; 4842 curr_sg->reserved[2] = 0; 4843 curr_sg->chain_indicator = 0; 4844 curr_sg++; 4845 } 4846 4847 switch (cmd->sc_data_direction) { 4848 case DMA_TO_DEVICE: 4849 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4850 cp->direction |= IOACCEL2_DIR_DATA_OUT; 4851 break; 4852 case DMA_FROM_DEVICE: 4853 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4854 cp->direction |= IOACCEL2_DIR_DATA_IN; 4855 break; 4856 case DMA_NONE: 4857 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4858 cp->direction |= IOACCEL2_DIR_NO_DATA; 4859 break; 4860 default: 4861 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 4862 cmd->sc_data_direction); 4863 BUG(); 4864 break; 4865 } 4866 } else { 4867 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4868 cp->direction |= IOACCEL2_DIR_NO_DATA; 4869 } 4870 4871 /* Set encryption parameters, if necessary */ 4872 set_encrypt_ioaccel2(h, c, cp); 4873 4874 cp->scsi_nexus = cpu_to_le32(ioaccel_handle); 4875 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); 4876 memcpy(cp->cdb, cdb, sizeof(cp->cdb)); 4877 4878 cp->data_len = cpu_to_le32(total_len); 4879 cp->err_ptr = cpu_to_le64(c->busaddr + 4880 offsetof(struct io_accel2_cmd, error_data)); 4881 cp->err_len = cpu_to_le32(sizeof(cp->error_data)); 4882 4883 /* fill in sg elements */ 4884 if (use_sg > h->ioaccel_maxsg) { 4885 cp->sg_count = 1; 4886 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); 4887 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { 4888 atomic_dec(&phys_disk->ioaccel_cmds_out); 4889 scsi_dma_unmap(cmd); 4890 return -1; 4891 } 4892 } else 4893 cp->sg_count = (u8) use_sg; 4894 4895 enqueue_cmd_and_start_io(h, c); 4896 return 0; 4897 } 4898 4899 /* 4900 * Queue a command to the correct I/O accelerator path. 4901 */ 4902 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 4903 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4904 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4905 { 4906 if (!c->scsi_cmd->device) 4907 return -1; 4908 4909 if (!c->scsi_cmd->device->hostdata) 4910 return -1; 4911 4912 /* Try to honor the device's queue depth */ 4913 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > 4914 phys_disk->queue_depth) { 4915 atomic_dec(&phys_disk->ioaccel_cmds_out); 4916 return IO_ACCEL_INELIGIBLE; 4917 } 4918 if (h->transMethod & CFGTBL_Trans_io_accel1) 4919 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, 4920 cdb, cdb_len, scsi3addr, 4921 phys_disk); 4922 else 4923 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, 4924 cdb, cdb_len, scsi3addr, 4925 phys_disk); 4926 } 4927 4928 static void raid_map_helper(struct raid_map_data *map, 4929 int offload_to_mirror, u32 *map_index, u32 *current_group) 4930 { 4931 if (offload_to_mirror == 0) { 4932 /* use physical disk in the first mirrored group. */ 4933 *map_index %= le16_to_cpu(map->data_disks_per_row); 4934 return; 4935 } 4936 do { 4937 /* determine mirror group that *map_index indicates */ 4938 *current_group = *map_index / 4939 le16_to_cpu(map->data_disks_per_row); 4940 if (offload_to_mirror == *current_group) 4941 continue; 4942 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { 4943 /* select map index from next group */ 4944 *map_index += le16_to_cpu(map->data_disks_per_row); 4945 (*current_group)++; 4946 } else { 4947 /* select map index from first group */ 4948 *map_index %= le16_to_cpu(map->data_disks_per_row); 4949 *current_group = 0; 4950 } 4951 } while (offload_to_mirror != *current_group); 4952 } 4953 4954 /* 4955 * Attempt to perform offload RAID mapping for a logical volume I/O. 4956 */ 4957 static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, 4958 struct CommandList *c) 4959 { 4960 struct scsi_cmnd *cmd = c->scsi_cmd; 4961 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4962 struct raid_map_data *map = &dev->raid_map; 4963 struct raid_map_disk_data *dd = &map->data[0]; 4964 int is_write = 0; 4965 u32 map_index; 4966 u64 first_block, last_block; 4967 u32 block_cnt; 4968 u32 blocks_per_row; 4969 u64 first_row, last_row; 4970 u32 first_row_offset, last_row_offset; 4971 u32 first_column, last_column; 4972 u64 r0_first_row, r0_last_row; 4973 u32 r5or6_blocks_per_row; 4974 u64 r5or6_first_row, r5or6_last_row; 4975 u32 r5or6_first_row_offset, r5or6_last_row_offset; 4976 u32 r5or6_first_column, r5or6_last_column; 4977 u32 total_disks_per_row; 4978 u32 stripesize; 4979 u32 first_group, last_group, current_group; 4980 u32 map_row; 4981 u32 disk_handle; 4982 u64 disk_block; 4983 u32 disk_block_cnt; 4984 u8 cdb[16]; 4985 u8 cdb_len; 4986 u16 strip_size; 4987 #if BITS_PER_LONG == 32 4988 u64 tmpdiv; 4989 #endif 4990 int offload_to_mirror; 4991 4992 if (!dev) 4993 return -1; 4994 4995 /* check for valid opcode, get LBA and block count */ 4996 switch (cmd->cmnd[0]) { 4997 case WRITE_6: 4998 is_write = 1; 4999 case READ_6: 5000 first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 5001 (cmd->cmnd[2] << 8) | 5002 cmd->cmnd[3]); 5003 block_cnt = cmd->cmnd[4]; 5004 if (block_cnt == 0) 5005 block_cnt = 256; 5006 break; 5007 case WRITE_10: 5008 is_write = 1; 5009 case READ_10: 5010 first_block = 5011 (((u64) cmd->cmnd[2]) << 24) | 5012 (((u64) cmd->cmnd[3]) << 16) | 5013 (((u64) cmd->cmnd[4]) << 8) | 5014 cmd->cmnd[5]; 5015 block_cnt = 5016 (((u32) cmd->cmnd[7]) << 8) | 5017 cmd->cmnd[8]; 5018 break; 5019 case WRITE_12: 5020 is_write = 1; 5021 case READ_12: 5022 first_block = 5023 (((u64) cmd->cmnd[2]) << 24) | 5024 (((u64) cmd->cmnd[3]) << 16) | 5025 (((u64) cmd->cmnd[4]) << 8) | 5026 cmd->cmnd[5]; 5027 block_cnt = 5028 (((u32) cmd->cmnd[6]) << 24) | 5029 (((u32) cmd->cmnd[7]) << 16) | 5030 (((u32) cmd->cmnd[8]) << 8) | 5031 cmd->cmnd[9]; 5032 break; 5033 case WRITE_16: 5034 is_write = 1; 5035 case READ_16: 5036 first_block = 5037 (((u64) cmd->cmnd[2]) << 56) | 5038 (((u64) cmd->cmnd[3]) << 48) | 5039 (((u64) cmd->cmnd[4]) << 40) | 5040 (((u64) cmd->cmnd[5]) << 32) | 5041 (((u64) cmd->cmnd[6]) << 24) | 5042 (((u64) cmd->cmnd[7]) << 16) | 5043 (((u64) cmd->cmnd[8]) << 8) | 5044 cmd->cmnd[9]; 5045 block_cnt = 5046 (((u32) cmd->cmnd[10]) << 24) | 5047 (((u32) cmd->cmnd[11]) << 16) | 5048 (((u32) cmd->cmnd[12]) << 8) | 5049 cmd->cmnd[13]; 5050 break; 5051 default: 5052 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ 5053 } 5054 last_block = first_block + block_cnt - 1; 5055 5056 /* check for write to non-RAID-0 */ 5057 if (is_write && dev->raid_level != 0) 5058 return IO_ACCEL_INELIGIBLE; 5059 5060 /* check for invalid block or wraparound */ 5061 if (last_block >= le64_to_cpu(map->volume_blk_cnt) || 5062 last_block < first_block) 5063 return IO_ACCEL_INELIGIBLE; 5064 5065 /* calculate stripe information for the request */ 5066 blocks_per_row = le16_to_cpu(map->data_disks_per_row) * 5067 le16_to_cpu(map->strip_size); 5068 strip_size = le16_to_cpu(map->strip_size); 5069 #if BITS_PER_LONG == 32 5070 tmpdiv = first_block; 5071 (void) do_div(tmpdiv, blocks_per_row); 5072 first_row = tmpdiv; 5073 tmpdiv = last_block; 5074 (void) do_div(tmpdiv, blocks_per_row); 5075 last_row = tmpdiv; 5076 first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5077 last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 5078 tmpdiv = first_row_offset; 5079 (void) do_div(tmpdiv, strip_size); 5080 first_column = tmpdiv; 5081 tmpdiv = last_row_offset; 5082 (void) do_div(tmpdiv, strip_size); 5083 last_column = tmpdiv; 5084 #else 5085 first_row = first_block / blocks_per_row; 5086 last_row = last_block / blocks_per_row; 5087 first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5088 last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 5089 first_column = first_row_offset / strip_size; 5090 last_column = last_row_offset / strip_size; 5091 #endif 5092 5093 /* if this isn't a single row/column then give to the controller */ 5094 if ((first_row != last_row) || (first_column != last_column)) 5095 return IO_ACCEL_INELIGIBLE; 5096 5097 /* proceeding with driver mapping */ 5098 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 5099 le16_to_cpu(map->metadata_disks_per_row); 5100 map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 5101 le16_to_cpu(map->row_cnt); 5102 map_index = (map_row * total_disks_per_row) + first_column; 5103 5104 switch (dev->raid_level) { 5105 case HPSA_RAID_0: 5106 break; /* nothing special to do */ 5107 case HPSA_RAID_1: 5108 /* Handles load balance across RAID 1 members. 5109 * (2-drive R1 and R10 with even # of drives.) 5110 * Appropriate for SSDs, not optimal for HDDs 5111 */ 5112 BUG_ON(le16_to_cpu(map->layout_map_count) != 2); 5113 if (dev->offload_to_mirror) 5114 map_index += le16_to_cpu(map->data_disks_per_row); 5115 dev->offload_to_mirror = !dev->offload_to_mirror; 5116 break; 5117 case HPSA_RAID_ADM: 5118 /* Handles N-way mirrors (R1-ADM) 5119 * and R10 with # of drives divisible by 3.) 5120 */ 5121 BUG_ON(le16_to_cpu(map->layout_map_count) != 3); 5122 5123 offload_to_mirror = dev->offload_to_mirror; 5124 raid_map_helper(map, offload_to_mirror, 5125 &map_index, ¤t_group); 5126 /* set mirror group to use next time */ 5127 offload_to_mirror = 5128 (offload_to_mirror >= 5129 le16_to_cpu(map->layout_map_count) - 1) 5130 ? 0 : offload_to_mirror + 1; 5131 dev->offload_to_mirror = offload_to_mirror; 5132 /* Avoid direct use of dev->offload_to_mirror within this 5133 * function since multiple threads might simultaneously 5134 * increment it beyond the range of dev->layout_map_count -1. 5135 */ 5136 break; 5137 case HPSA_RAID_5: 5138 case HPSA_RAID_6: 5139 if (le16_to_cpu(map->layout_map_count) <= 1) 5140 break; 5141 5142 /* Verify first and last block are in same RAID group */ 5143 r5or6_blocks_per_row = 5144 le16_to_cpu(map->strip_size) * 5145 le16_to_cpu(map->data_disks_per_row); 5146 BUG_ON(r5or6_blocks_per_row == 0); 5147 stripesize = r5or6_blocks_per_row * 5148 le16_to_cpu(map->layout_map_count); 5149 #if BITS_PER_LONG == 32 5150 tmpdiv = first_block; 5151 first_group = do_div(tmpdiv, stripesize); 5152 tmpdiv = first_group; 5153 (void) do_div(tmpdiv, r5or6_blocks_per_row); 5154 first_group = tmpdiv; 5155 tmpdiv = last_block; 5156 last_group = do_div(tmpdiv, stripesize); 5157 tmpdiv = last_group; 5158 (void) do_div(tmpdiv, r5or6_blocks_per_row); 5159 last_group = tmpdiv; 5160 #else 5161 first_group = (first_block % stripesize) / r5or6_blocks_per_row; 5162 last_group = (last_block % stripesize) / r5or6_blocks_per_row; 5163 #endif 5164 if (first_group != last_group) 5165 return IO_ACCEL_INELIGIBLE; 5166 5167 /* Verify request is in a single row of RAID 5/6 */ 5168 #if BITS_PER_LONG == 32 5169 tmpdiv = first_block; 5170 (void) do_div(tmpdiv, stripesize); 5171 first_row = r5or6_first_row = r0_first_row = tmpdiv; 5172 tmpdiv = last_block; 5173 (void) do_div(tmpdiv, stripesize); 5174 r5or6_last_row = r0_last_row = tmpdiv; 5175 #else 5176 first_row = r5or6_first_row = r0_first_row = 5177 first_block / stripesize; 5178 r5or6_last_row = r0_last_row = last_block / stripesize; 5179 #endif 5180 if (r5or6_first_row != r5or6_last_row) 5181 return IO_ACCEL_INELIGIBLE; 5182 5183 5184 /* Verify request is in a single column */ 5185 #if BITS_PER_LONG == 32 5186 tmpdiv = first_block; 5187 first_row_offset = do_div(tmpdiv, stripesize); 5188 tmpdiv = first_row_offset; 5189 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); 5190 r5or6_first_row_offset = first_row_offset; 5191 tmpdiv = last_block; 5192 r5or6_last_row_offset = do_div(tmpdiv, stripesize); 5193 tmpdiv = r5or6_last_row_offset; 5194 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); 5195 tmpdiv = r5or6_first_row_offset; 5196 (void) do_div(tmpdiv, map->strip_size); 5197 first_column = r5or6_first_column = tmpdiv; 5198 tmpdiv = r5or6_last_row_offset; 5199 (void) do_div(tmpdiv, map->strip_size); 5200 r5or6_last_column = tmpdiv; 5201 #else 5202 first_row_offset = r5or6_first_row_offset = 5203 (u32)((first_block % stripesize) % 5204 r5or6_blocks_per_row); 5205 5206 r5or6_last_row_offset = 5207 (u32)((last_block % stripesize) % 5208 r5or6_blocks_per_row); 5209 5210 first_column = r5or6_first_column = 5211 r5or6_first_row_offset / le16_to_cpu(map->strip_size); 5212 r5or6_last_column = 5213 r5or6_last_row_offset / le16_to_cpu(map->strip_size); 5214 #endif 5215 if (r5or6_first_column != r5or6_last_column) 5216 return IO_ACCEL_INELIGIBLE; 5217 5218 /* Request is eligible */ 5219 map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 5220 le16_to_cpu(map->row_cnt); 5221 5222 map_index = (first_group * 5223 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + 5224 (map_row * total_disks_per_row) + first_column; 5225 break; 5226 default: 5227 return IO_ACCEL_INELIGIBLE; 5228 } 5229 5230 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) 5231 return IO_ACCEL_INELIGIBLE; 5232 5233 c->phys_disk = dev->phys_disk[map_index]; 5234 if (!c->phys_disk) 5235 return IO_ACCEL_INELIGIBLE; 5236 5237 disk_handle = dd[map_index].ioaccel_handle; 5238 disk_block = le64_to_cpu(map->disk_starting_blk) + 5239 first_row * le16_to_cpu(map->strip_size) + 5240 (first_row_offset - first_column * 5241 le16_to_cpu(map->strip_size)); 5242 disk_block_cnt = block_cnt; 5243 5244 /* handle differing logical/physical block sizes */ 5245 if (map->phys_blk_shift) { 5246 disk_block <<= map->phys_blk_shift; 5247 disk_block_cnt <<= map->phys_blk_shift; 5248 } 5249 BUG_ON(disk_block_cnt > 0xffff); 5250 5251 /* build the new CDB for the physical disk I/O */ 5252 if (disk_block > 0xffffffff) { 5253 cdb[0] = is_write ? WRITE_16 : READ_16; 5254 cdb[1] = 0; 5255 cdb[2] = (u8) (disk_block >> 56); 5256 cdb[3] = (u8) (disk_block >> 48); 5257 cdb[4] = (u8) (disk_block >> 40); 5258 cdb[5] = (u8) (disk_block >> 32); 5259 cdb[6] = (u8) (disk_block >> 24); 5260 cdb[7] = (u8) (disk_block >> 16); 5261 cdb[8] = (u8) (disk_block >> 8); 5262 cdb[9] = (u8) (disk_block); 5263 cdb[10] = (u8) (disk_block_cnt >> 24); 5264 cdb[11] = (u8) (disk_block_cnt >> 16); 5265 cdb[12] = (u8) (disk_block_cnt >> 8); 5266 cdb[13] = (u8) (disk_block_cnt); 5267 cdb[14] = 0; 5268 cdb[15] = 0; 5269 cdb_len = 16; 5270 } else { 5271 cdb[0] = is_write ? WRITE_10 : READ_10; 5272 cdb[1] = 0; 5273 cdb[2] = (u8) (disk_block >> 24); 5274 cdb[3] = (u8) (disk_block >> 16); 5275 cdb[4] = (u8) (disk_block >> 8); 5276 cdb[5] = (u8) (disk_block); 5277 cdb[6] = 0; 5278 cdb[7] = (u8) (disk_block_cnt >> 8); 5279 cdb[8] = (u8) (disk_block_cnt); 5280 cdb[9] = 0; 5281 cdb_len = 10; 5282 } 5283 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, 5284 dev->scsi3addr, 5285 dev->phys_disk[map_index]); 5286 } 5287 5288 /* 5289 * Submit commands down the "normal" RAID stack path 5290 * All callers to hpsa_ciss_submit must check lockup_detected 5291 * beforehand, before (opt.) and after calling cmd_alloc 5292 */ 5293 static int hpsa_ciss_submit(struct ctlr_info *h, 5294 struct CommandList *c, struct scsi_cmnd *cmd, 5295 unsigned char scsi3addr[]) 5296 { 5297 cmd->host_scribble = (unsigned char *) c; 5298 c->cmd_type = CMD_SCSI; 5299 c->scsi_cmd = cmd; 5300 c->Header.ReplyQueue = 0; /* unused in simple mode */ 5301 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); 5302 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); 5303 5304 /* Fill in the request block... */ 5305 5306 c->Request.Timeout = 0; 5307 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); 5308 c->Request.CDBLen = cmd->cmd_len; 5309 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); 5310 switch (cmd->sc_data_direction) { 5311 case DMA_TO_DEVICE: 5312 c->Request.type_attr_dir = 5313 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); 5314 break; 5315 case DMA_FROM_DEVICE: 5316 c->Request.type_attr_dir = 5317 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); 5318 break; 5319 case DMA_NONE: 5320 c->Request.type_attr_dir = 5321 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); 5322 break; 5323 case DMA_BIDIRECTIONAL: 5324 /* This can happen if a buggy application does a scsi passthru 5325 * and sets both inlen and outlen to non-zero. ( see 5326 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) 5327 */ 5328 5329 c->Request.type_attr_dir = 5330 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); 5331 /* This is technically wrong, and hpsa controllers should 5332 * reject it with CMD_INVALID, which is the most correct 5333 * response, but non-fibre backends appear to let it 5334 * slide by, and give the same results as if this field 5335 * were set correctly. Either way is acceptable for 5336 * our purposes here. 5337 */ 5338 5339 break; 5340 5341 default: 5342 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 5343 cmd->sc_data_direction); 5344 BUG(); 5345 break; 5346 } 5347 5348 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ 5349 hpsa_cmd_resolve_and_free(h, c); 5350 return SCSI_MLQUEUE_HOST_BUSY; 5351 } 5352 enqueue_cmd_and_start_io(h, c); 5353 /* the cmd'll come back via intr handler in complete_scsi_command() */ 5354 return 0; 5355 } 5356 5357 static void hpsa_cmd_init(struct ctlr_info *h, int index, 5358 struct CommandList *c) 5359 { 5360 dma_addr_t cmd_dma_handle, err_dma_handle; 5361 5362 /* Zero out all of commandlist except the last field, refcount */ 5363 memset(c, 0, offsetof(struct CommandList, refcount)); 5364 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); 5365 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5366 c->err_info = h->errinfo_pool + index; 5367 memset(c->err_info, 0, sizeof(*c->err_info)); 5368 err_dma_handle = h->errinfo_pool_dhandle 5369 + index * sizeof(*c->err_info); 5370 c->cmdindex = index; 5371 c->busaddr = (u32) cmd_dma_handle; 5372 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); 5373 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); 5374 c->h = h; 5375 c->scsi_cmd = SCSI_CMD_IDLE; 5376 } 5377 5378 static void hpsa_preinitialize_commands(struct ctlr_info *h) 5379 { 5380 int i; 5381 5382 for (i = 0; i < h->nr_cmds; i++) { 5383 struct CommandList *c = h->cmd_pool + i; 5384 5385 hpsa_cmd_init(h, i, c); 5386 atomic_set(&c->refcount, 0); 5387 } 5388 } 5389 5390 static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, 5391 struct CommandList *c) 5392 { 5393 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5394 5395 BUG_ON(c->cmdindex != index); 5396 5397 memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); 5398 memset(c->err_info, 0, sizeof(*c->err_info)); 5399 c->busaddr = (u32) cmd_dma_handle; 5400 } 5401 5402 static int hpsa_ioaccel_submit(struct ctlr_info *h, 5403 struct CommandList *c, struct scsi_cmnd *cmd, 5404 unsigned char *scsi3addr) 5405 { 5406 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 5407 int rc = IO_ACCEL_INELIGIBLE; 5408 5409 if (!dev) 5410 return SCSI_MLQUEUE_HOST_BUSY; 5411 5412 cmd->host_scribble = (unsigned char *) c; 5413 5414 if (dev->offload_enabled) { 5415 hpsa_cmd_init(h, c->cmdindex, c); 5416 c->cmd_type = CMD_SCSI; 5417 c->scsi_cmd = cmd; 5418 rc = hpsa_scsi_ioaccel_raid_map(h, c); 5419 if (rc < 0) /* scsi_dma_map failed. */ 5420 rc = SCSI_MLQUEUE_HOST_BUSY; 5421 } else if (dev->hba_ioaccel_enabled) { 5422 hpsa_cmd_init(h, c->cmdindex, c); 5423 c->cmd_type = CMD_SCSI; 5424 c->scsi_cmd = cmd; 5425 rc = hpsa_scsi_ioaccel_direct_map(h, c); 5426 if (rc < 0) /* scsi_dma_map failed. */ 5427 rc = SCSI_MLQUEUE_HOST_BUSY; 5428 } 5429 return rc; 5430 } 5431 5432 static void hpsa_command_resubmit_worker(struct work_struct *work) 5433 { 5434 struct scsi_cmnd *cmd; 5435 struct hpsa_scsi_dev_t *dev; 5436 struct CommandList *c = container_of(work, struct CommandList, work); 5437 5438 cmd = c->scsi_cmd; 5439 dev = cmd->device->hostdata; 5440 if (!dev) { 5441 cmd->result = DID_NO_CONNECT << 16; 5442 return hpsa_cmd_free_and_done(c->h, c, cmd); 5443 } 5444 if (c->reset_pending) 5445 return hpsa_cmd_free_and_done(c->h, c, cmd); 5446 if (c->cmd_type == CMD_IOACCEL2) { 5447 struct ctlr_info *h = c->h; 5448 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 5449 int rc; 5450 5451 if (c2->error_data.serv_response == 5452 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { 5453 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr); 5454 if (rc == 0) 5455 return; 5456 if (rc == SCSI_MLQUEUE_HOST_BUSY) { 5457 /* 5458 * If we get here, it means dma mapping failed. 5459 * Try again via scsi mid layer, which will 5460 * then get SCSI_MLQUEUE_HOST_BUSY. 5461 */ 5462 cmd->result = DID_IMM_RETRY << 16; 5463 return hpsa_cmd_free_and_done(h, c, cmd); 5464 } 5465 /* else, fall thru and resubmit down CISS path */ 5466 } 5467 } 5468 hpsa_cmd_partial_init(c->h, c->cmdindex, c); 5469 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) { 5470 /* 5471 * If we get here, it means dma mapping failed. Try 5472 * again via scsi mid layer, which will then get 5473 * SCSI_MLQUEUE_HOST_BUSY. 5474 * 5475 * hpsa_ciss_submit will have already freed c 5476 * if it encountered a dma mapping failure. 5477 */ 5478 cmd->result = DID_IMM_RETRY << 16; 5479 cmd->scsi_done(cmd); 5480 } 5481 } 5482 5483 /* Running in struct Scsi_Host->host_lock less mode */ 5484 static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) 5485 { 5486 struct ctlr_info *h; 5487 struct hpsa_scsi_dev_t *dev; 5488 unsigned char scsi3addr[8]; 5489 struct CommandList *c; 5490 int rc = 0; 5491 5492 /* Get the ptr to our adapter structure out of cmd->host. */ 5493 h = sdev_to_hba(cmd->device); 5494 5495 BUG_ON(cmd->request->tag < 0); 5496 5497 dev = cmd->device->hostdata; 5498 if (!dev) { 5499 cmd->result = DID_NO_CONNECT << 16; 5500 cmd->scsi_done(cmd); 5501 return 0; 5502 } 5503 5504 if (dev->removed) { 5505 cmd->result = DID_NO_CONNECT << 16; 5506 cmd->scsi_done(cmd); 5507 return 0; 5508 } 5509 5510 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); 5511 5512 if (unlikely(lockup_detected(h))) { 5513 cmd->result = DID_NO_CONNECT << 16; 5514 cmd->scsi_done(cmd); 5515 return 0; 5516 } 5517 c = cmd_tagged_alloc(h, cmd); 5518 5519 /* 5520 * Call alternate submit routine for I/O accelerated commands. 5521 * Retries always go down the normal I/O path. 5522 */ 5523 if (likely(cmd->retries == 0 && 5524 !blk_rq_is_passthrough(cmd->request) && 5525 h->acciopath_status)) { 5526 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr); 5527 if (rc == 0) 5528 return 0; 5529 if (rc == SCSI_MLQUEUE_HOST_BUSY) { 5530 hpsa_cmd_resolve_and_free(h, c); 5531 return SCSI_MLQUEUE_HOST_BUSY; 5532 } 5533 } 5534 return hpsa_ciss_submit(h, c, cmd, scsi3addr); 5535 } 5536 5537 static void hpsa_scan_complete(struct ctlr_info *h) 5538 { 5539 unsigned long flags; 5540 5541 spin_lock_irqsave(&h->scan_lock, flags); 5542 h->scan_finished = 1; 5543 wake_up(&h->scan_wait_queue); 5544 spin_unlock_irqrestore(&h->scan_lock, flags); 5545 } 5546 5547 static void hpsa_scan_start(struct Scsi_Host *sh) 5548 { 5549 struct ctlr_info *h = shost_to_hba(sh); 5550 unsigned long flags; 5551 5552 /* 5553 * Don't let rescans be initiated on a controller known to be locked 5554 * up. If the controller locks up *during* a rescan, that thread is 5555 * probably hosed, but at least we can prevent new rescan threads from 5556 * piling up on a locked up controller. 5557 */ 5558 if (unlikely(lockup_detected(h))) 5559 return hpsa_scan_complete(h); 5560 5561 /* 5562 * If a scan is already waiting to run, no need to add another 5563 */ 5564 spin_lock_irqsave(&h->scan_lock, flags); 5565 if (h->scan_waiting) { 5566 spin_unlock_irqrestore(&h->scan_lock, flags); 5567 return; 5568 } 5569 5570 spin_unlock_irqrestore(&h->scan_lock, flags); 5571 5572 /* wait until any scan already in progress is finished. */ 5573 while (1) { 5574 spin_lock_irqsave(&h->scan_lock, flags); 5575 if (h->scan_finished) 5576 break; 5577 h->scan_waiting = 1; 5578 spin_unlock_irqrestore(&h->scan_lock, flags); 5579 wait_event(h->scan_wait_queue, h->scan_finished); 5580 /* Note: We don't need to worry about a race between this 5581 * thread and driver unload because the midlayer will 5582 * have incremented the reference count, so unload won't 5583 * happen if we're in here. 5584 */ 5585 } 5586 h->scan_finished = 0; /* mark scan as in progress */ 5587 h->scan_waiting = 0; 5588 spin_unlock_irqrestore(&h->scan_lock, flags); 5589 5590 if (unlikely(lockup_detected(h))) 5591 return hpsa_scan_complete(h); 5592 5593 /* 5594 * Do the scan after a reset completion 5595 */ 5596 spin_lock_irqsave(&h->reset_lock, flags); 5597 if (h->reset_in_progress) { 5598 h->drv_req_rescan = 1; 5599 spin_unlock_irqrestore(&h->reset_lock, flags); 5600 hpsa_scan_complete(h); 5601 return; 5602 } 5603 spin_unlock_irqrestore(&h->reset_lock, flags); 5604 5605 hpsa_update_scsi_devices(h); 5606 5607 hpsa_scan_complete(h); 5608 } 5609 5610 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) 5611 { 5612 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; 5613 5614 if (!logical_drive) 5615 return -ENODEV; 5616 5617 if (qdepth < 1) 5618 qdepth = 1; 5619 else if (qdepth > logical_drive->queue_depth) 5620 qdepth = logical_drive->queue_depth; 5621 5622 return scsi_change_queue_depth(sdev, qdepth); 5623 } 5624 5625 static int hpsa_scan_finished(struct Scsi_Host *sh, 5626 unsigned long elapsed_time) 5627 { 5628 struct ctlr_info *h = shost_to_hba(sh); 5629 unsigned long flags; 5630 int finished; 5631 5632 spin_lock_irqsave(&h->scan_lock, flags); 5633 finished = h->scan_finished; 5634 spin_unlock_irqrestore(&h->scan_lock, flags); 5635 return finished; 5636 } 5637 5638 static int hpsa_scsi_host_alloc(struct ctlr_info *h) 5639 { 5640 struct Scsi_Host *sh; 5641 5642 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); 5643 if (sh == NULL) { 5644 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); 5645 return -ENOMEM; 5646 } 5647 5648 sh->io_port = 0; 5649 sh->n_io_port = 0; 5650 sh->this_id = -1; 5651 sh->max_channel = 3; 5652 sh->max_cmd_len = MAX_COMMAND_SIZE; 5653 sh->max_lun = HPSA_MAX_LUN; 5654 sh->max_id = HPSA_MAX_LUN; 5655 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; 5656 sh->cmd_per_lun = sh->can_queue; 5657 sh->sg_tablesize = h->maxsgentries; 5658 sh->transportt = hpsa_sas_transport_template; 5659 sh->hostdata[0] = (unsigned long) h; 5660 sh->irq = pci_irq_vector(h->pdev, 0); 5661 sh->unique_id = sh->irq; 5662 5663 h->scsi_host = sh; 5664 return 0; 5665 } 5666 5667 static int hpsa_scsi_add_host(struct ctlr_info *h) 5668 { 5669 int rv; 5670 5671 rv = scsi_add_host(h->scsi_host, &h->pdev->dev); 5672 if (rv) { 5673 dev_err(&h->pdev->dev, "scsi_add_host failed\n"); 5674 return rv; 5675 } 5676 scsi_scan_host(h->scsi_host); 5677 return 0; 5678 } 5679 5680 /* 5681 * The block layer has already gone to the trouble of picking out a unique, 5682 * small-integer tag for this request. We use an offset from that value as 5683 * an index to select our command block. (The offset allows us to reserve the 5684 * low-numbered entries for our own uses.) 5685 */ 5686 static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) 5687 { 5688 int idx = scmd->request->tag; 5689 5690 if (idx < 0) 5691 return idx; 5692 5693 /* Offset to leave space for internal cmds. */ 5694 return idx += HPSA_NRESERVED_CMDS; 5695 } 5696 5697 /* 5698 * Send a TEST_UNIT_READY command to the specified LUN using the specified 5699 * reply queue; returns zero if the unit is ready, and non-zero otherwise. 5700 */ 5701 static int hpsa_send_test_unit_ready(struct ctlr_info *h, 5702 struct CommandList *c, unsigned char lunaddr[], 5703 int reply_queue) 5704 { 5705 int rc; 5706 5707 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ 5708 (void) fill_cmd(c, TEST_UNIT_READY, h, 5709 NULL, 0, 0, lunaddr, TYPE_CMD); 5710 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); 5711 if (rc) 5712 return rc; 5713 /* no unmap needed here because no data xfer. */ 5714 5715 /* Check if the unit is already ready. */ 5716 if (c->err_info->CommandStatus == CMD_SUCCESS) 5717 return 0; 5718 5719 /* 5720 * The first command sent after reset will receive "unit attention" to 5721 * indicate that the LUN has been reset...this is actually what we're 5722 * looking for (but, success is good too). 5723 */ 5724 if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 5725 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && 5726 (c->err_info->SenseInfo[2] == NO_SENSE || 5727 c->err_info->SenseInfo[2] == UNIT_ATTENTION)) 5728 return 0; 5729 5730 return 1; 5731 } 5732 5733 /* 5734 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; 5735 * returns zero when the unit is ready, and non-zero when giving up. 5736 */ 5737 static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, 5738 struct CommandList *c, 5739 unsigned char lunaddr[], int reply_queue) 5740 { 5741 int rc; 5742 int count = 0; 5743 int waittime = 1; /* seconds */ 5744 5745 /* Send test unit ready until device ready, or give up. */ 5746 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { 5747 5748 /* 5749 * Wait for a bit. do this first, because if we send 5750 * the TUR right away, the reset will just abort it. 5751 */ 5752 msleep(1000 * waittime); 5753 5754 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); 5755 if (!rc) 5756 break; 5757 5758 /* Increase wait time with each try, up to a point. */ 5759 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) 5760 waittime *= 2; 5761 5762 dev_warn(&h->pdev->dev, 5763 "waiting %d secs for device to become ready.\n", 5764 waittime); 5765 } 5766 5767 return rc; 5768 } 5769 5770 static int wait_for_device_to_become_ready(struct ctlr_info *h, 5771 unsigned char lunaddr[], 5772 int reply_queue) 5773 { 5774 int first_queue; 5775 int last_queue; 5776 int rq; 5777 int rc = 0; 5778 struct CommandList *c; 5779 5780 c = cmd_alloc(h); 5781 5782 /* 5783 * If no specific reply queue was requested, then send the TUR 5784 * repeatedly, requesting a reply on each reply queue; otherwise execute 5785 * the loop exactly once using only the specified queue. 5786 */ 5787 if (reply_queue == DEFAULT_REPLY_QUEUE) { 5788 first_queue = 0; 5789 last_queue = h->nreply_queues - 1; 5790 } else { 5791 first_queue = reply_queue; 5792 last_queue = reply_queue; 5793 } 5794 5795 for (rq = first_queue; rq <= last_queue; rq++) { 5796 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); 5797 if (rc) 5798 break; 5799 } 5800 5801 if (rc) 5802 dev_warn(&h->pdev->dev, "giving up on device.\n"); 5803 else 5804 dev_warn(&h->pdev->dev, "device is ready.\n"); 5805 5806 cmd_free(h, c); 5807 return rc; 5808 } 5809 5810 /* Need at least one of these error handlers to keep ../scsi/hosts.c from 5811 * complaining. Doing a host- or bus-reset can't do anything good here. 5812 */ 5813 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) 5814 { 5815 int rc = SUCCESS; 5816 struct ctlr_info *h; 5817 struct hpsa_scsi_dev_t *dev; 5818 u8 reset_type; 5819 char msg[48]; 5820 unsigned long flags; 5821 5822 /* find the controller to which the command to be aborted was sent */ 5823 h = sdev_to_hba(scsicmd->device); 5824 if (h == NULL) /* paranoia */ 5825 return FAILED; 5826 5827 spin_lock_irqsave(&h->reset_lock, flags); 5828 h->reset_in_progress = 1; 5829 spin_unlock_irqrestore(&h->reset_lock, flags); 5830 5831 if (lockup_detected(h)) { 5832 rc = FAILED; 5833 goto return_reset_status; 5834 } 5835 5836 dev = scsicmd->device->hostdata; 5837 if (!dev) { 5838 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); 5839 rc = FAILED; 5840 goto return_reset_status; 5841 } 5842 5843 if (dev->devtype == TYPE_ENCLOSURE) { 5844 rc = SUCCESS; 5845 goto return_reset_status; 5846 } 5847 5848 /* if controller locked up, we can guarantee command won't complete */ 5849 if (lockup_detected(h)) { 5850 snprintf(msg, sizeof(msg), 5851 "cmd %d RESET FAILED, lockup detected", 5852 hpsa_get_cmd_index(scsicmd)); 5853 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5854 rc = FAILED; 5855 goto return_reset_status; 5856 } 5857 5858 /* this reset request might be the result of a lockup; check */ 5859 if (detect_controller_lockup(h)) { 5860 snprintf(msg, sizeof(msg), 5861 "cmd %d RESET FAILED, new lockup detected", 5862 hpsa_get_cmd_index(scsicmd)); 5863 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5864 rc = FAILED; 5865 goto return_reset_status; 5866 } 5867 5868 /* Do not attempt on controller */ 5869 if (is_hba_lunid(dev->scsi3addr)) { 5870 rc = SUCCESS; 5871 goto return_reset_status; 5872 } 5873 5874 if (is_logical_dev_addr_mode(dev->scsi3addr)) 5875 reset_type = HPSA_DEVICE_RESET_MSG; 5876 else 5877 reset_type = HPSA_PHYS_TARGET_RESET; 5878 5879 sprintf(msg, "resetting %s", 5880 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); 5881 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5882 5883 /* send a reset to the SCSI LUN which the command was sent to */ 5884 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type, 5885 DEFAULT_REPLY_QUEUE); 5886 if (rc == 0) 5887 rc = SUCCESS; 5888 else 5889 rc = FAILED; 5890 5891 sprintf(msg, "reset %s %s", 5892 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", 5893 rc == SUCCESS ? "completed successfully" : "failed"); 5894 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5895 5896 return_reset_status: 5897 spin_lock_irqsave(&h->reset_lock, flags); 5898 h->reset_in_progress = 0; 5899 spin_unlock_irqrestore(&h->reset_lock, flags); 5900 return rc; 5901 } 5902 5903 /* 5904 * For operations with an associated SCSI command, a command block is allocated 5905 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the 5906 * block request tag as an index into a table of entries. cmd_tagged_free() is 5907 * the complement, although cmd_free() may be called instead. 5908 */ 5909 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 5910 struct scsi_cmnd *scmd) 5911 { 5912 int idx = hpsa_get_cmd_index(scmd); 5913 struct CommandList *c = h->cmd_pool + idx; 5914 5915 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { 5916 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", 5917 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); 5918 /* The index value comes from the block layer, so if it's out of 5919 * bounds, it's probably not our bug. 5920 */ 5921 BUG(); 5922 } 5923 5924 atomic_inc(&c->refcount); 5925 if (unlikely(!hpsa_is_cmd_idle(c))) { 5926 /* 5927 * We expect that the SCSI layer will hand us a unique tag 5928 * value. Thus, there should never be a collision here between 5929 * two requests...because if the selected command isn't idle 5930 * then someone is going to be very disappointed. 5931 */ 5932 dev_err(&h->pdev->dev, 5933 "tag collision (tag=%d) in cmd_tagged_alloc().\n", 5934 idx); 5935 if (c->scsi_cmd != NULL) 5936 scsi_print_command(c->scsi_cmd); 5937 scsi_print_command(scmd); 5938 } 5939 5940 hpsa_cmd_partial_init(h, idx, c); 5941 return c; 5942 } 5943 5944 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) 5945 { 5946 /* 5947 * Release our reference to the block. We don't need to do anything 5948 * else to free it, because it is accessed by index. 5949 */ 5950 (void)atomic_dec(&c->refcount); 5951 } 5952 5953 /* 5954 * For operations that cannot sleep, a command block is allocated at init, 5955 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track 5956 * which ones are free or in use. Lock must be held when calling this. 5957 * cmd_free() is the complement. 5958 * This function never gives up and returns NULL. If it hangs, 5959 * another thread must call cmd_free() to free some tags. 5960 */ 5961 5962 static struct CommandList *cmd_alloc(struct ctlr_info *h) 5963 { 5964 struct CommandList *c; 5965 int refcount, i; 5966 int offset = 0; 5967 5968 /* 5969 * There is some *extremely* small but non-zero chance that that 5970 * multiple threads could get in here, and one thread could 5971 * be scanning through the list of bits looking for a free 5972 * one, but the free ones are always behind him, and other 5973 * threads sneak in behind him and eat them before he can 5974 * get to them, so that while there is always a free one, a 5975 * very unlucky thread might be starved anyway, never able to 5976 * beat the other threads. In reality, this happens so 5977 * infrequently as to be indistinguishable from never. 5978 * 5979 * Note that we start allocating commands before the SCSI host structure 5980 * is initialized. Since the search starts at bit zero, this 5981 * all works, since we have at least one command structure available; 5982 * however, it means that the structures with the low indexes have to be 5983 * reserved for driver-initiated requests, while requests from the block 5984 * layer will use the higher indexes. 5985 */ 5986 5987 for (;;) { 5988 i = find_next_zero_bit(h->cmd_pool_bits, 5989 HPSA_NRESERVED_CMDS, 5990 offset); 5991 if (unlikely(i >= HPSA_NRESERVED_CMDS)) { 5992 offset = 0; 5993 continue; 5994 } 5995 c = h->cmd_pool + i; 5996 refcount = atomic_inc_return(&c->refcount); 5997 if (unlikely(refcount > 1)) { 5998 cmd_free(h, c); /* already in use */ 5999 offset = (i + 1) % HPSA_NRESERVED_CMDS; 6000 continue; 6001 } 6002 set_bit(i & (BITS_PER_LONG - 1), 6003 h->cmd_pool_bits + (i / BITS_PER_LONG)); 6004 break; /* it's ours now. */ 6005 } 6006 hpsa_cmd_partial_init(h, i, c); 6007 return c; 6008 } 6009 6010 /* 6011 * This is the complementary operation to cmd_alloc(). Note, however, in some 6012 * corner cases it may also be used to free blocks allocated by 6013 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and 6014 * the clear-bit is harmless. 6015 */ 6016 static void cmd_free(struct ctlr_info *h, struct CommandList *c) 6017 { 6018 if (atomic_dec_and_test(&c->refcount)) { 6019 int i; 6020 6021 i = c - h->cmd_pool; 6022 clear_bit(i & (BITS_PER_LONG - 1), 6023 h->cmd_pool_bits + (i / BITS_PER_LONG)); 6024 } 6025 } 6026 6027 #ifdef CONFIG_COMPAT 6028 6029 static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, 6030 void __user *arg) 6031 { 6032 IOCTL32_Command_struct __user *arg32 = 6033 (IOCTL32_Command_struct __user *) arg; 6034 IOCTL_Command_struct arg64; 6035 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); 6036 int err; 6037 u32 cp; 6038 6039 memset(&arg64, 0, sizeof(arg64)); 6040 err = 0; 6041 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, 6042 sizeof(arg64.LUN_info)); 6043 err |= copy_from_user(&arg64.Request, &arg32->Request, 6044 sizeof(arg64.Request)); 6045 err |= copy_from_user(&arg64.error_info, &arg32->error_info, 6046 sizeof(arg64.error_info)); 6047 err |= get_user(arg64.buf_size, &arg32->buf_size); 6048 err |= get_user(cp, &arg32->buf); 6049 arg64.buf = compat_ptr(cp); 6050 err |= copy_to_user(p, &arg64, sizeof(arg64)); 6051 6052 if (err) 6053 return -EFAULT; 6054 6055 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); 6056 if (err) 6057 return err; 6058 err |= copy_in_user(&arg32->error_info, &p->error_info, 6059 sizeof(arg32->error_info)); 6060 if (err) 6061 return -EFAULT; 6062 return err; 6063 } 6064 6065 static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, 6066 int cmd, void __user *arg) 6067 { 6068 BIG_IOCTL32_Command_struct __user *arg32 = 6069 (BIG_IOCTL32_Command_struct __user *) arg; 6070 BIG_IOCTL_Command_struct arg64; 6071 BIG_IOCTL_Command_struct __user *p = 6072 compat_alloc_user_space(sizeof(arg64)); 6073 int err; 6074 u32 cp; 6075 6076 memset(&arg64, 0, sizeof(arg64)); 6077 err = 0; 6078 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, 6079 sizeof(arg64.LUN_info)); 6080 err |= copy_from_user(&arg64.Request, &arg32->Request, 6081 sizeof(arg64.Request)); 6082 err |= copy_from_user(&arg64.error_info, &arg32->error_info, 6083 sizeof(arg64.error_info)); 6084 err |= get_user(arg64.buf_size, &arg32->buf_size); 6085 err |= get_user(arg64.malloc_size, &arg32->malloc_size); 6086 err |= get_user(cp, &arg32->buf); 6087 arg64.buf = compat_ptr(cp); 6088 err |= copy_to_user(p, &arg64, sizeof(arg64)); 6089 6090 if (err) 6091 return -EFAULT; 6092 6093 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); 6094 if (err) 6095 return err; 6096 err |= copy_in_user(&arg32->error_info, &p->error_info, 6097 sizeof(arg32->error_info)); 6098 if (err) 6099 return -EFAULT; 6100 return err; 6101 } 6102 6103 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg) 6104 { 6105 switch (cmd) { 6106 case CCISS_GETPCIINFO: 6107 case CCISS_GETINTINFO: 6108 case CCISS_SETINTINFO: 6109 case CCISS_GETNODENAME: 6110 case CCISS_SETNODENAME: 6111 case CCISS_GETHEARTBEAT: 6112 case CCISS_GETBUSTYPES: 6113 case CCISS_GETFIRMVER: 6114 case CCISS_GETDRIVVER: 6115 case CCISS_REVALIDVOLS: 6116 case CCISS_DEREGDISK: 6117 case CCISS_REGNEWDISK: 6118 case CCISS_REGNEWD: 6119 case CCISS_RESCANDISK: 6120 case CCISS_GETLUNINFO: 6121 return hpsa_ioctl(dev, cmd, arg); 6122 6123 case CCISS_PASSTHRU32: 6124 return hpsa_ioctl32_passthru(dev, cmd, arg); 6125 case CCISS_BIG_PASSTHRU32: 6126 return hpsa_ioctl32_big_passthru(dev, cmd, arg); 6127 6128 default: 6129 return -ENOIOCTLCMD; 6130 } 6131 } 6132 #endif 6133 6134 static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) 6135 { 6136 struct hpsa_pci_info pciinfo; 6137 6138 if (!argp) 6139 return -EINVAL; 6140 pciinfo.domain = pci_domain_nr(h->pdev->bus); 6141 pciinfo.bus = h->pdev->bus->number; 6142 pciinfo.dev_fn = h->pdev->devfn; 6143 pciinfo.board_id = h->board_id; 6144 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) 6145 return -EFAULT; 6146 return 0; 6147 } 6148 6149 static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) 6150 { 6151 DriverVer_type DriverVer; 6152 unsigned char vmaj, vmin, vsubmin; 6153 int rc; 6154 6155 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", 6156 &vmaj, &vmin, &vsubmin); 6157 if (rc != 3) { 6158 dev_info(&h->pdev->dev, "driver version string '%s' " 6159 "unrecognized.", HPSA_DRIVER_VERSION); 6160 vmaj = 0; 6161 vmin = 0; 6162 vsubmin = 0; 6163 } 6164 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; 6165 if (!argp) 6166 return -EINVAL; 6167 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) 6168 return -EFAULT; 6169 return 0; 6170 } 6171 6172 static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) 6173 { 6174 IOCTL_Command_struct iocommand; 6175 struct CommandList *c; 6176 char *buff = NULL; 6177 u64 temp64; 6178 int rc = 0; 6179 6180 if (!argp) 6181 return -EINVAL; 6182 if (!capable(CAP_SYS_RAWIO)) 6183 return -EPERM; 6184 if (copy_from_user(&iocommand, argp, sizeof(iocommand))) 6185 return -EFAULT; 6186 if ((iocommand.buf_size < 1) && 6187 (iocommand.Request.Type.Direction != XFER_NONE)) { 6188 return -EINVAL; 6189 } 6190 if (iocommand.buf_size > 0) { 6191 buff = kmalloc(iocommand.buf_size, GFP_KERNEL); 6192 if (buff == NULL) 6193 return -ENOMEM; 6194 if (iocommand.Request.Type.Direction & XFER_WRITE) { 6195 /* Copy the data into the buffer we created */ 6196 if (copy_from_user(buff, iocommand.buf, 6197 iocommand.buf_size)) { 6198 rc = -EFAULT; 6199 goto out_kfree; 6200 } 6201 } else { 6202 memset(buff, 0, iocommand.buf_size); 6203 } 6204 } 6205 c = cmd_alloc(h); 6206 6207 /* Fill in the command type */ 6208 c->cmd_type = CMD_IOCTL_PEND; 6209 c->scsi_cmd = SCSI_CMD_BUSY; 6210 /* Fill in Command Header */ 6211 c->Header.ReplyQueue = 0; /* unused in simple mode */ 6212 if (iocommand.buf_size > 0) { /* buffer to fill */ 6213 c->Header.SGList = 1; 6214 c->Header.SGTotal = cpu_to_le16(1); 6215 } else { /* no buffers to fill */ 6216 c->Header.SGList = 0; 6217 c->Header.SGTotal = cpu_to_le16(0); 6218 } 6219 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); 6220 6221 /* Fill in Request block */ 6222 memcpy(&c->Request, &iocommand.Request, 6223 sizeof(c->Request)); 6224 6225 /* Fill in the scatter gather information */ 6226 if (iocommand.buf_size > 0) { 6227 temp64 = pci_map_single(h->pdev, buff, 6228 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); 6229 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { 6230 c->SG[0].Addr = cpu_to_le64(0); 6231 c->SG[0].Len = cpu_to_le32(0); 6232 rc = -ENOMEM; 6233 goto out; 6234 } 6235 c->SG[0].Addr = cpu_to_le64(temp64); 6236 c->SG[0].Len = cpu_to_le32(iocommand.buf_size); 6237 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ 6238 } 6239 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 6240 NO_TIMEOUT); 6241 if (iocommand.buf_size > 0) 6242 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); 6243 check_ioctl_unit_attention(h, c); 6244 if (rc) { 6245 rc = -EIO; 6246 goto out; 6247 } 6248 6249 /* Copy the error information out */ 6250 memcpy(&iocommand.error_info, c->err_info, 6251 sizeof(iocommand.error_info)); 6252 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { 6253 rc = -EFAULT; 6254 goto out; 6255 } 6256 if ((iocommand.Request.Type.Direction & XFER_READ) && 6257 iocommand.buf_size > 0) { 6258 /* Copy the data out of the buffer we created */ 6259 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { 6260 rc = -EFAULT; 6261 goto out; 6262 } 6263 } 6264 out: 6265 cmd_free(h, c); 6266 out_kfree: 6267 kfree(buff); 6268 return rc; 6269 } 6270 6271 static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) 6272 { 6273 BIG_IOCTL_Command_struct *ioc; 6274 struct CommandList *c; 6275 unsigned char **buff = NULL; 6276 int *buff_size = NULL; 6277 u64 temp64; 6278 BYTE sg_used = 0; 6279 int status = 0; 6280 u32 left; 6281 u32 sz; 6282 BYTE __user *data_ptr; 6283 6284 if (!argp) 6285 return -EINVAL; 6286 if (!capable(CAP_SYS_RAWIO)) 6287 return -EPERM; 6288 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL); 6289 if (!ioc) { 6290 status = -ENOMEM; 6291 goto cleanup1; 6292 } 6293 if (copy_from_user(ioc, argp, sizeof(*ioc))) { 6294 status = -EFAULT; 6295 goto cleanup1; 6296 } 6297 if ((ioc->buf_size < 1) && 6298 (ioc->Request.Type.Direction != XFER_NONE)) { 6299 status = -EINVAL; 6300 goto cleanup1; 6301 } 6302 /* Check kmalloc limits using all SGs */ 6303 if (ioc->malloc_size > MAX_KMALLOC_SIZE) { 6304 status = -EINVAL; 6305 goto cleanup1; 6306 } 6307 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { 6308 status = -EINVAL; 6309 goto cleanup1; 6310 } 6311 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); 6312 if (!buff) { 6313 status = -ENOMEM; 6314 goto cleanup1; 6315 } 6316 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); 6317 if (!buff_size) { 6318 status = -ENOMEM; 6319 goto cleanup1; 6320 } 6321 left = ioc->buf_size; 6322 data_ptr = ioc->buf; 6323 while (left) { 6324 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; 6325 buff_size[sg_used] = sz; 6326 buff[sg_used] = kmalloc(sz, GFP_KERNEL); 6327 if (buff[sg_used] == NULL) { 6328 status = -ENOMEM; 6329 goto cleanup1; 6330 } 6331 if (ioc->Request.Type.Direction & XFER_WRITE) { 6332 if (copy_from_user(buff[sg_used], data_ptr, sz)) { 6333 status = -EFAULT; 6334 goto cleanup1; 6335 } 6336 } else 6337 memset(buff[sg_used], 0, sz); 6338 left -= sz; 6339 data_ptr += sz; 6340 sg_used++; 6341 } 6342 c = cmd_alloc(h); 6343 6344 c->cmd_type = CMD_IOCTL_PEND; 6345 c->scsi_cmd = SCSI_CMD_BUSY; 6346 c->Header.ReplyQueue = 0; 6347 c->Header.SGList = (u8) sg_used; 6348 c->Header.SGTotal = cpu_to_le16(sg_used); 6349 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); 6350 memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); 6351 if (ioc->buf_size > 0) { 6352 int i; 6353 for (i = 0; i < sg_used; i++) { 6354 temp64 = pci_map_single(h->pdev, buff[i], 6355 buff_size[i], PCI_DMA_BIDIRECTIONAL); 6356 if (dma_mapping_error(&h->pdev->dev, 6357 (dma_addr_t) temp64)) { 6358 c->SG[i].Addr = cpu_to_le64(0); 6359 c->SG[i].Len = cpu_to_le32(0); 6360 hpsa_pci_unmap(h->pdev, c, i, 6361 PCI_DMA_BIDIRECTIONAL); 6362 status = -ENOMEM; 6363 goto cleanup0; 6364 } 6365 c->SG[i].Addr = cpu_to_le64(temp64); 6366 c->SG[i].Len = cpu_to_le32(buff_size[i]); 6367 c->SG[i].Ext = cpu_to_le32(0); 6368 } 6369 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); 6370 } 6371 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 6372 NO_TIMEOUT); 6373 if (sg_used) 6374 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); 6375 check_ioctl_unit_attention(h, c); 6376 if (status) { 6377 status = -EIO; 6378 goto cleanup0; 6379 } 6380 6381 /* Copy the error information out */ 6382 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); 6383 if (copy_to_user(argp, ioc, sizeof(*ioc))) { 6384 status = -EFAULT; 6385 goto cleanup0; 6386 } 6387 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { 6388 int i; 6389 6390 /* Copy the data out of the buffer we created */ 6391 BYTE __user *ptr = ioc->buf; 6392 for (i = 0; i < sg_used; i++) { 6393 if (copy_to_user(ptr, buff[i], buff_size[i])) { 6394 status = -EFAULT; 6395 goto cleanup0; 6396 } 6397 ptr += buff_size[i]; 6398 } 6399 } 6400 status = 0; 6401 cleanup0: 6402 cmd_free(h, c); 6403 cleanup1: 6404 if (buff) { 6405 int i; 6406 6407 for (i = 0; i < sg_used; i++) 6408 kfree(buff[i]); 6409 kfree(buff); 6410 } 6411 kfree(buff_size); 6412 kfree(ioc); 6413 return status; 6414 } 6415 6416 static void check_ioctl_unit_attention(struct ctlr_info *h, 6417 struct CommandList *c) 6418 { 6419 if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 6420 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) 6421 (void) check_for_unit_attention(h, c); 6422 } 6423 6424 /* 6425 * ioctl 6426 */ 6427 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg) 6428 { 6429 struct ctlr_info *h; 6430 void __user *argp = (void __user *)arg; 6431 int rc; 6432 6433 h = sdev_to_hba(dev); 6434 6435 switch (cmd) { 6436 case CCISS_DEREGDISK: 6437 case CCISS_REGNEWDISK: 6438 case CCISS_REGNEWD: 6439 hpsa_scan_start(h->scsi_host); 6440 return 0; 6441 case CCISS_GETPCIINFO: 6442 return hpsa_getpciinfo_ioctl(h, argp); 6443 case CCISS_GETDRIVVER: 6444 return hpsa_getdrivver_ioctl(h, argp); 6445 case CCISS_PASSTHRU: 6446 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 6447 return -EAGAIN; 6448 rc = hpsa_passthru_ioctl(h, argp); 6449 atomic_inc(&h->passthru_cmds_avail); 6450 return rc; 6451 case CCISS_BIG_PASSTHRU: 6452 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 6453 return -EAGAIN; 6454 rc = hpsa_big_passthru_ioctl(h, argp); 6455 atomic_inc(&h->passthru_cmds_avail); 6456 return rc; 6457 default: 6458 return -ENOTTY; 6459 } 6460 } 6461 6462 static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, 6463 u8 reset_type) 6464 { 6465 struct CommandList *c; 6466 6467 c = cmd_alloc(h); 6468 6469 /* fill_cmd can't fail here, no data buffer to map */ 6470 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, 6471 RAID_CTLR_LUNID, TYPE_MSG); 6472 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ 6473 c->waiting = NULL; 6474 enqueue_cmd_and_start_io(h, c); 6475 /* Don't wait for completion, the reset won't complete. Don't free 6476 * the command either. This is the last command we will send before 6477 * re-initializing everything, so it doesn't matter and won't leak. 6478 */ 6479 return; 6480 } 6481 6482 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 6483 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 6484 int cmd_type) 6485 { 6486 int pci_dir = XFER_NONE; 6487 6488 c->cmd_type = CMD_IOCTL_PEND; 6489 c->scsi_cmd = SCSI_CMD_BUSY; 6490 c->Header.ReplyQueue = 0; 6491 if (buff != NULL && size > 0) { 6492 c->Header.SGList = 1; 6493 c->Header.SGTotal = cpu_to_le16(1); 6494 } else { 6495 c->Header.SGList = 0; 6496 c->Header.SGTotal = cpu_to_le16(0); 6497 } 6498 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); 6499 6500 if (cmd_type == TYPE_CMD) { 6501 switch (cmd) { 6502 case HPSA_INQUIRY: 6503 /* are we trying to read a vital product page */ 6504 if (page_code & VPD_PAGE) { 6505 c->Request.CDB[1] = 0x01; 6506 c->Request.CDB[2] = (page_code & 0xff); 6507 } 6508 c->Request.CDBLen = 6; 6509 c->Request.type_attr_dir = 6510 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6511 c->Request.Timeout = 0; 6512 c->Request.CDB[0] = HPSA_INQUIRY; 6513 c->Request.CDB[4] = size & 0xFF; 6514 break; 6515 case HPSA_REPORT_LOG: 6516 case HPSA_REPORT_PHYS: 6517 /* Talking to controller so It's a physical command 6518 mode = 00 target = 0. Nothing to write. 6519 */ 6520 c->Request.CDBLen = 12; 6521 c->Request.type_attr_dir = 6522 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6523 c->Request.Timeout = 0; 6524 c->Request.CDB[0] = cmd; 6525 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6526 c->Request.CDB[7] = (size >> 16) & 0xFF; 6527 c->Request.CDB[8] = (size >> 8) & 0xFF; 6528 c->Request.CDB[9] = size & 0xFF; 6529 break; 6530 case BMIC_SENSE_DIAG_OPTIONS: 6531 c->Request.CDBLen = 16; 6532 c->Request.type_attr_dir = 6533 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6534 c->Request.Timeout = 0; 6535 /* Spec says this should be BMIC_WRITE */ 6536 c->Request.CDB[0] = BMIC_READ; 6537 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; 6538 break; 6539 case BMIC_SET_DIAG_OPTIONS: 6540 c->Request.CDBLen = 16; 6541 c->Request.type_attr_dir = 6542 TYPE_ATTR_DIR(cmd_type, 6543 ATTR_SIMPLE, XFER_WRITE); 6544 c->Request.Timeout = 0; 6545 c->Request.CDB[0] = BMIC_WRITE; 6546 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; 6547 break; 6548 case HPSA_CACHE_FLUSH: 6549 c->Request.CDBLen = 12; 6550 c->Request.type_attr_dir = 6551 TYPE_ATTR_DIR(cmd_type, 6552 ATTR_SIMPLE, XFER_WRITE); 6553 c->Request.Timeout = 0; 6554 c->Request.CDB[0] = BMIC_WRITE; 6555 c->Request.CDB[6] = BMIC_CACHE_FLUSH; 6556 c->Request.CDB[7] = (size >> 8) & 0xFF; 6557 c->Request.CDB[8] = size & 0xFF; 6558 break; 6559 case TEST_UNIT_READY: 6560 c->Request.CDBLen = 6; 6561 c->Request.type_attr_dir = 6562 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6563 c->Request.Timeout = 0; 6564 break; 6565 case HPSA_GET_RAID_MAP: 6566 c->Request.CDBLen = 12; 6567 c->Request.type_attr_dir = 6568 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6569 c->Request.Timeout = 0; 6570 c->Request.CDB[0] = HPSA_CISS_READ; 6571 c->Request.CDB[1] = cmd; 6572 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6573 c->Request.CDB[7] = (size >> 16) & 0xFF; 6574 c->Request.CDB[8] = (size >> 8) & 0xFF; 6575 c->Request.CDB[9] = size & 0xFF; 6576 break; 6577 case BMIC_SENSE_CONTROLLER_PARAMETERS: 6578 c->Request.CDBLen = 10; 6579 c->Request.type_attr_dir = 6580 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6581 c->Request.Timeout = 0; 6582 c->Request.CDB[0] = BMIC_READ; 6583 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; 6584 c->Request.CDB[7] = (size >> 16) & 0xFF; 6585 c->Request.CDB[8] = (size >> 8) & 0xFF; 6586 break; 6587 case BMIC_IDENTIFY_PHYSICAL_DEVICE: 6588 c->Request.CDBLen = 10; 6589 c->Request.type_attr_dir = 6590 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6591 c->Request.Timeout = 0; 6592 c->Request.CDB[0] = BMIC_READ; 6593 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; 6594 c->Request.CDB[7] = (size >> 16) & 0xFF; 6595 c->Request.CDB[8] = (size >> 8) & 0XFF; 6596 break; 6597 case BMIC_SENSE_SUBSYSTEM_INFORMATION: 6598 c->Request.CDBLen = 10; 6599 c->Request.type_attr_dir = 6600 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6601 c->Request.Timeout = 0; 6602 c->Request.CDB[0] = BMIC_READ; 6603 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; 6604 c->Request.CDB[7] = (size >> 16) & 0xFF; 6605 c->Request.CDB[8] = (size >> 8) & 0XFF; 6606 break; 6607 case BMIC_SENSE_STORAGE_BOX_PARAMS: 6608 c->Request.CDBLen = 10; 6609 c->Request.type_attr_dir = 6610 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6611 c->Request.Timeout = 0; 6612 c->Request.CDB[0] = BMIC_READ; 6613 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS; 6614 c->Request.CDB[7] = (size >> 16) & 0xFF; 6615 c->Request.CDB[8] = (size >> 8) & 0XFF; 6616 break; 6617 case BMIC_IDENTIFY_CONTROLLER: 6618 c->Request.CDBLen = 10; 6619 c->Request.type_attr_dir = 6620 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6621 c->Request.Timeout = 0; 6622 c->Request.CDB[0] = BMIC_READ; 6623 c->Request.CDB[1] = 0; 6624 c->Request.CDB[2] = 0; 6625 c->Request.CDB[3] = 0; 6626 c->Request.CDB[4] = 0; 6627 c->Request.CDB[5] = 0; 6628 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; 6629 c->Request.CDB[7] = (size >> 16) & 0xFF; 6630 c->Request.CDB[8] = (size >> 8) & 0XFF; 6631 c->Request.CDB[9] = 0; 6632 break; 6633 default: 6634 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); 6635 BUG(); 6636 } 6637 } else if (cmd_type == TYPE_MSG) { 6638 switch (cmd) { 6639 6640 case HPSA_PHYS_TARGET_RESET: 6641 c->Request.CDBLen = 16; 6642 c->Request.type_attr_dir = 6643 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6644 c->Request.Timeout = 0; /* Don't time out */ 6645 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 6646 c->Request.CDB[0] = HPSA_RESET; 6647 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; 6648 /* Physical target reset needs no control bytes 4-7*/ 6649 c->Request.CDB[4] = 0x00; 6650 c->Request.CDB[5] = 0x00; 6651 c->Request.CDB[6] = 0x00; 6652 c->Request.CDB[7] = 0x00; 6653 break; 6654 case HPSA_DEVICE_RESET_MSG: 6655 c->Request.CDBLen = 16; 6656 c->Request.type_attr_dir = 6657 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6658 c->Request.Timeout = 0; /* Don't time out */ 6659 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 6660 c->Request.CDB[0] = cmd; 6661 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; 6662 /* If bytes 4-7 are zero, it means reset the */ 6663 /* LunID device */ 6664 c->Request.CDB[4] = 0x00; 6665 c->Request.CDB[5] = 0x00; 6666 c->Request.CDB[6] = 0x00; 6667 c->Request.CDB[7] = 0x00; 6668 break; 6669 default: 6670 dev_warn(&h->pdev->dev, "unknown message type %d\n", 6671 cmd); 6672 BUG(); 6673 } 6674 } else { 6675 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); 6676 BUG(); 6677 } 6678 6679 switch (GET_DIR(c->Request.type_attr_dir)) { 6680 case XFER_READ: 6681 pci_dir = PCI_DMA_FROMDEVICE; 6682 break; 6683 case XFER_WRITE: 6684 pci_dir = PCI_DMA_TODEVICE; 6685 break; 6686 case XFER_NONE: 6687 pci_dir = PCI_DMA_NONE; 6688 break; 6689 default: 6690 pci_dir = PCI_DMA_BIDIRECTIONAL; 6691 } 6692 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) 6693 return -1; 6694 return 0; 6695 } 6696 6697 /* 6698 * Map (physical) PCI mem into (virtual) kernel space 6699 */ 6700 static void __iomem *remap_pci_mem(ulong base, ulong size) 6701 { 6702 ulong page_base = ((ulong) base) & PAGE_MASK; 6703 ulong page_offs = ((ulong) base) - page_base; 6704 void __iomem *page_remapped = ioremap_nocache(page_base, 6705 page_offs + size); 6706 6707 return page_remapped ? (page_remapped + page_offs) : NULL; 6708 } 6709 6710 static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) 6711 { 6712 return h->access.command_completed(h, q); 6713 } 6714 6715 static inline bool interrupt_pending(struct ctlr_info *h) 6716 { 6717 return h->access.intr_pending(h); 6718 } 6719 6720 static inline long interrupt_not_for_us(struct ctlr_info *h) 6721 { 6722 return (h->access.intr_pending(h) == 0) || 6723 (h->interrupts_enabled == 0); 6724 } 6725 6726 static inline int bad_tag(struct ctlr_info *h, u32 tag_index, 6727 u32 raw_tag) 6728 { 6729 if (unlikely(tag_index >= h->nr_cmds)) { 6730 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); 6731 return 1; 6732 } 6733 return 0; 6734 } 6735 6736 static inline void finish_cmd(struct CommandList *c) 6737 { 6738 dial_up_lockup_detection_on_fw_flash_complete(c->h, c); 6739 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI 6740 || c->cmd_type == CMD_IOACCEL2)) 6741 complete_scsi_command(c); 6742 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) 6743 complete(c->waiting); 6744 } 6745 6746 /* process completion of an indexed ("direct lookup") command */ 6747 static inline void process_indexed_cmd(struct ctlr_info *h, 6748 u32 raw_tag) 6749 { 6750 u32 tag_index; 6751 struct CommandList *c; 6752 6753 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; 6754 if (!bad_tag(h, tag_index, raw_tag)) { 6755 c = h->cmd_pool + tag_index; 6756 finish_cmd(c); 6757 } 6758 } 6759 6760 /* Some controllers, like p400, will give us one interrupt 6761 * after a soft reset, even if we turned interrupts off. 6762 * Only need to check for this in the hpsa_xxx_discard_completions 6763 * functions. 6764 */ 6765 static int ignore_bogus_interrupt(struct ctlr_info *h) 6766 { 6767 if (likely(!reset_devices)) 6768 return 0; 6769 6770 if (likely(h->interrupts_enabled)) 6771 return 0; 6772 6773 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " 6774 "(known firmware bug.) Ignoring.\n"); 6775 6776 return 1; 6777 } 6778 6779 /* 6780 * Convert &h->q[x] (passed to interrupt handlers) back to h. 6781 * Relies on (h-q[x] == x) being true for x such that 6782 * 0 <= x < MAX_REPLY_QUEUES. 6783 */ 6784 static struct ctlr_info *queue_to_hba(u8 *queue) 6785 { 6786 return container_of((queue - *queue), struct ctlr_info, q[0]); 6787 } 6788 6789 static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) 6790 { 6791 struct ctlr_info *h = queue_to_hba(queue); 6792 u8 q = *(u8 *) queue; 6793 u32 raw_tag; 6794 6795 if (ignore_bogus_interrupt(h)) 6796 return IRQ_NONE; 6797 6798 if (interrupt_not_for_us(h)) 6799 return IRQ_NONE; 6800 h->last_intr_timestamp = get_jiffies_64(); 6801 while (interrupt_pending(h)) { 6802 raw_tag = get_next_completion(h, q); 6803 while (raw_tag != FIFO_EMPTY) 6804 raw_tag = next_command(h, q); 6805 } 6806 return IRQ_HANDLED; 6807 } 6808 6809 static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) 6810 { 6811 struct ctlr_info *h = queue_to_hba(queue); 6812 u32 raw_tag; 6813 u8 q = *(u8 *) queue; 6814 6815 if (ignore_bogus_interrupt(h)) 6816 return IRQ_NONE; 6817 6818 h->last_intr_timestamp = get_jiffies_64(); 6819 raw_tag = get_next_completion(h, q); 6820 while (raw_tag != FIFO_EMPTY) 6821 raw_tag = next_command(h, q); 6822 return IRQ_HANDLED; 6823 } 6824 6825 static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) 6826 { 6827 struct ctlr_info *h = queue_to_hba((u8 *) queue); 6828 u32 raw_tag; 6829 u8 q = *(u8 *) queue; 6830 6831 if (interrupt_not_for_us(h)) 6832 return IRQ_NONE; 6833 h->last_intr_timestamp = get_jiffies_64(); 6834 while (interrupt_pending(h)) { 6835 raw_tag = get_next_completion(h, q); 6836 while (raw_tag != FIFO_EMPTY) { 6837 process_indexed_cmd(h, raw_tag); 6838 raw_tag = next_command(h, q); 6839 } 6840 } 6841 return IRQ_HANDLED; 6842 } 6843 6844 static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) 6845 { 6846 struct ctlr_info *h = queue_to_hba(queue); 6847 u32 raw_tag; 6848 u8 q = *(u8 *) queue; 6849 6850 h->last_intr_timestamp = get_jiffies_64(); 6851 raw_tag = get_next_completion(h, q); 6852 while (raw_tag != FIFO_EMPTY) { 6853 process_indexed_cmd(h, raw_tag); 6854 raw_tag = next_command(h, q); 6855 } 6856 return IRQ_HANDLED; 6857 } 6858 6859 /* Send a message CDB to the firmware. Careful, this only works 6860 * in simple mode, not performant mode due to the tag lookup. 6861 * We only ever use this immediately after a controller reset. 6862 */ 6863 static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, 6864 unsigned char type) 6865 { 6866 struct Command { 6867 struct CommandListHeader CommandHeader; 6868 struct RequestBlock Request; 6869 struct ErrDescriptor ErrorDescriptor; 6870 }; 6871 struct Command *cmd; 6872 static const size_t cmd_sz = sizeof(*cmd) + 6873 sizeof(cmd->ErrorDescriptor); 6874 dma_addr_t paddr64; 6875 __le32 paddr32; 6876 u32 tag; 6877 void __iomem *vaddr; 6878 int i, err; 6879 6880 vaddr = pci_ioremap_bar(pdev, 0); 6881 if (vaddr == NULL) 6882 return -ENOMEM; 6883 6884 /* The Inbound Post Queue only accepts 32-bit physical addresses for the 6885 * CCISS commands, so they must be allocated from the lower 4GiB of 6886 * memory. 6887 */ 6888 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 6889 if (err) { 6890 iounmap(vaddr); 6891 return err; 6892 } 6893 6894 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); 6895 if (cmd == NULL) { 6896 iounmap(vaddr); 6897 return -ENOMEM; 6898 } 6899 6900 /* This must fit, because of the 32-bit consistent DMA mask. Also, 6901 * although there's no guarantee, we assume that the address is at 6902 * least 4-byte aligned (most likely, it's page-aligned). 6903 */ 6904 paddr32 = cpu_to_le32(paddr64); 6905 6906 cmd->CommandHeader.ReplyQueue = 0; 6907 cmd->CommandHeader.SGList = 0; 6908 cmd->CommandHeader.SGTotal = cpu_to_le16(0); 6909 cmd->CommandHeader.tag = cpu_to_le64(paddr64); 6910 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); 6911 6912 cmd->Request.CDBLen = 16; 6913 cmd->Request.type_attr_dir = 6914 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); 6915 cmd->Request.Timeout = 0; /* Don't time out */ 6916 cmd->Request.CDB[0] = opcode; 6917 cmd->Request.CDB[1] = type; 6918 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ 6919 cmd->ErrorDescriptor.Addr = 6920 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); 6921 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); 6922 6923 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); 6924 6925 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { 6926 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); 6927 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) 6928 break; 6929 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); 6930 } 6931 6932 iounmap(vaddr); 6933 6934 /* we leak the DMA buffer here ... no choice since the controller could 6935 * still complete the command. 6936 */ 6937 if (i == HPSA_MSG_SEND_RETRY_LIMIT) { 6938 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", 6939 opcode, type); 6940 return -ETIMEDOUT; 6941 } 6942 6943 pci_free_consistent(pdev, cmd_sz, cmd, paddr64); 6944 6945 if (tag & HPSA_ERROR_BIT) { 6946 dev_err(&pdev->dev, "controller message %02x:%02x failed\n", 6947 opcode, type); 6948 return -EIO; 6949 } 6950 6951 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", 6952 opcode, type); 6953 return 0; 6954 } 6955 6956 #define hpsa_noop(p) hpsa_message(p, 3, 0) 6957 6958 static int hpsa_controller_hard_reset(struct pci_dev *pdev, 6959 void __iomem *vaddr, u32 use_doorbell) 6960 { 6961 6962 if (use_doorbell) { 6963 /* For everything after the P600, the PCI power state method 6964 * of resetting the controller doesn't work, so we have this 6965 * other way using the doorbell register. 6966 */ 6967 dev_info(&pdev->dev, "using doorbell to reset controller\n"); 6968 writel(use_doorbell, vaddr + SA5_DOORBELL); 6969 6970 /* PMC hardware guys tell us we need a 10 second delay after 6971 * doorbell reset and before any attempt to talk to the board 6972 * at all to ensure that this actually works and doesn't fall 6973 * over in some weird corner cases. 6974 */ 6975 msleep(10000); 6976 } else { /* Try to do it the PCI power state way */ 6977 6978 /* Quoting from the Open CISS Specification: "The Power 6979 * Management Control/Status Register (CSR) controls the power 6980 * state of the device. The normal operating state is D0, 6981 * CSR=00h. The software off state is D3, CSR=03h. To reset 6982 * the controller, place the interface device in D3 then to D0, 6983 * this causes a secondary PCI reset which will reset the 6984 * controller." */ 6985 6986 int rc = 0; 6987 6988 dev_info(&pdev->dev, "using PCI PM to reset controller\n"); 6989 6990 /* enter the D3hot power management state */ 6991 rc = pci_set_power_state(pdev, PCI_D3hot); 6992 if (rc) 6993 return rc; 6994 6995 msleep(500); 6996 6997 /* enter the D0 power management state */ 6998 rc = pci_set_power_state(pdev, PCI_D0); 6999 if (rc) 7000 return rc; 7001 7002 /* 7003 * The P600 requires a small delay when changing states. 7004 * Otherwise we may think the board did not reset and we bail. 7005 * This for kdump only and is particular to the P600. 7006 */ 7007 msleep(500); 7008 } 7009 return 0; 7010 } 7011 7012 static void init_driver_version(char *driver_version, int len) 7013 { 7014 memset(driver_version, 0, len); 7015 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); 7016 } 7017 7018 static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) 7019 { 7020 char *driver_version; 7021 int i, size = sizeof(cfgtable->driver_version); 7022 7023 driver_version = kmalloc(size, GFP_KERNEL); 7024 if (!driver_version) 7025 return -ENOMEM; 7026 7027 init_driver_version(driver_version, size); 7028 for (i = 0; i < size; i++) 7029 writeb(driver_version[i], &cfgtable->driver_version[i]); 7030 kfree(driver_version); 7031 return 0; 7032 } 7033 7034 static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, 7035 unsigned char *driver_ver) 7036 { 7037 int i; 7038 7039 for (i = 0; i < sizeof(cfgtable->driver_version); i++) 7040 driver_ver[i] = readb(&cfgtable->driver_version[i]); 7041 } 7042 7043 static int controller_reset_failed(struct CfgTable __iomem *cfgtable) 7044 { 7045 7046 char *driver_ver, *old_driver_ver; 7047 int rc, size = sizeof(cfgtable->driver_version); 7048 7049 old_driver_ver = kmalloc(2 * size, GFP_KERNEL); 7050 if (!old_driver_ver) 7051 return -ENOMEM; 7052 driver_ver = old_driver_ver + size; 7053 7054 /* After a reset, the 32 bytes of "driver version" in the cfgtable 7055 * should have been changed, otherwise we know the reset failed. 7056 */ 7057 init_driver_version(old_driver_ver, size); 7058 read_driver_ver_from_cfgtable(cfgtable, driver_ver); 7059 rc = !memcmp(driver_ver, old_driver_ver, size); 7060 kfree(old_driver_ver); 7061 return rc; 7062 } 7063 /* This does a hard reset of the controller using PCI power management 7064 * states or the using the doorbell register. 7065 */ 7066 static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) 7067 { 7068 u64 cfg_offset; 7069 u32 cfg_base_addr; 7070 u64 cfg_base_addr_index; 7071 void __iomem *vaddr; 7072 unsigned long paddr; 7073 u32 misc_fw_support; 7074 int rc; 7075 struct CfgTable __iomem *cfgtable; 7076 u32 use_doorbell; 7077 u16 command_register; 7078 7079 /* For controllers as old as the P600, this is very nearly 7080 * the same thing as 7081 * 7082 * pci_save_state(pci_dev); 7083 * pci_set_power_state(pci_dev, PCI_D3hot); 7084 * pci_set_power_state(pci_dev, PCI_D0); 7085 * pci_restore_state(pci_dev); 7086 * 7087 * For controllers newer than the P600, the pci power state 7088 * method of resetting doesn't work so we have another way 7089 * using the doorbell register. 7090 */ 7091 7092 if (!ctlr_is_resettable(board_id)) { 7093 dev_warn(&pdev->dev, "Controller not resettable\n"); 7094 return -ENODEV; 7095 } 7096 7097 /* if controller is soft- but not hard resettable... */ 7098 if (!ctlr_is_hard_resettable(board_id)) 7099 return -ENOTSUPP; /* try soft reset later. */ 7100 7101 /* Save the PCI command register */ 7102 pci_read_config_word(pdev, 4, &command_register); 7103 pci_save_state(pdev); 7104 7105 /* find the first memory BAR, so we can find the cfg table */ 7106 rc = hpsa_pci_find_memory_BAR(pdev, &paddr); 7107 if (rc) 7108 return rc; 7109 vaddr = remap_pci_mem(paddr, 0x250); 7110 if (!vaddr) 7111 return -ENOMEM; 7112 7113 /* find cfgtable in order to check if reset via doorbell is supported */ 7114 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, 7115 &cfg_base_addr_index, &cfg_offset); 7116 if (rc) 7117 goto unmap_vaddr; 7118 cfgtable = remap_pci_mem(pci_resource_start(pdev, 7119 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); 7120 if (!cfgtable) { 7121 rc = -ENOMEM; 7122 goto unmap_vaddr; 7123 } 7124 rc = write_driver_ver_to_cfgtable(cfgtable); 7125 if (rc) 7126 goto unmap_cfgtable; 7127 7128 /* If reset via doorbell register is supported, use that. 7129 * There are two such methods. Favor the newest method. 7130 */ 7131 misc_fw_support = readl(&cfgtable->misc_fw_support); 7132 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; 7133 if (use_doorbell) { 7134 use_doorbell = DOORBELL_CTLR_RESET2; 7135 } else { 7136 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; 7137 if (use_doorbell) { 7138 dev_warn(&pdev->dev, 7139 "Soft reset not supported. Firmware update is required.\n"); 7140 rc = -ENOTSUPP; /* try soft reset */ 7141 goto unmap_cfgtable; 7142 } 7143 } 7144 7145 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); 7146 if (rc) 7147 goto unmap_cfgtable; 7148 7149 pci_restore_state(pdev); 7150 pci_write_config_word(pdev, 4, command_register); 7151 7152 /* Some devices (notably the HP Smart Array 5i Controller) 7153 need a little pause here */ 7154 msleep(HPSA_POST_RESET_PAUSE_MSECS); 7155 7156 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); 7157 if (rc) { 7158 dev_warn(&pdev->dev, 7159 "Failed waiting for board to become ready after hard reset\n"); 7160 goto unmap_cfgtable; 7161 } 7162 7163 rc = controller_reset_failed(vaddr); 7164 if (rc < 0) 7165 goto unmap_cfgtable; 7166 if (rc) { 7167 dev_warn(&pdev->dev, "Unable to successfully reset " 7168 "controller. Will try soft reset.\n"); 7169 rc = -ENOTSUPP; 7170 } else { 7171 dev_info(&pdev->dev, "board ready after hard reset.\n"); 7172 } 7173 7174 unmap_cfgtable: 7175 iounmap(cfgtable); 7176 7177 unmap_vaddr: 7178 iounmap(vaddr); 7179 return rc; 7180 } 7181 7182 /* 7183 * We cannot read the structure directly, for portability we must use 7184 * the io functions. 7185 * This is for debug only. 7186 */ 7187 static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) 7188 { 7189 #ifdef HPSA_DEBUG 7190 int i; 7191 char temp_name[17]; 7192 7193 dev_info(dev, "Controller Configuration information\n"); 7194 dev_info(dev, "------------------------------------\n"); 7195 for (i = 0; i < 4; i++) 7196 temp_name[i] = readb(&(tb->Signature[i])); 7197 temp_name[4] = '\0'; 7198 dev_info(dev, " Signature = %s\n", temp_name); 7199 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); 7200 dev_info(dev, " Transport methods supported = 0x%x\n", 7201 readl(&(tb->TransportSupport))); 7202 dev_info(dev, " Transport methods active = 0x%x\n", 7203 readl(&(tb->TransportActive))); 7204 dev_info(dev, " Requested transport Method = 0x%x\n", 7205 readl(&(tb->HostWrite.TransportRequest))); 7206 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", 7207 readl(&(tb->HostWrite.CoalIntDelay))); 7208 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", 7209 readl(&(tb->HostWrite.CoalIntCount))); 7210 dev_info(dev, " Max outstanding commands = %d\n", 7211 readl(&(tb->CmdsOutMax))); 7212 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); 7213 for (i = 0; i < 16; i++) 7214 temp_name[i] = readb(&(tb->ServerName[i])); 7215 temp_name[16] = '\0'; 7216 dev_info(dev, " Server Name = %s\n", temp_name); 7217 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", 7218 readl(&(tb->HeartBeat))); 7219 #endif /* HPSA_DEBUG */ 7220 } 7221 7222 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) 7223 { 7224 int i, offset, mem_type, bar_type; 7225 7226 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ 7227 return 0; 7228 offset = 0; 7229 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 7230 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; 7231 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) 7232 offset += 4; 7233 else { 7234 mem_type = pci_resource_flags(pdev, i) & 7235 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 7236 switch (mem_type) { 7237 case PCI_BASE_ADDRESS_MEM_TYPE_32: 7238 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 7239 offset += 4; /* 32 bit */ 7240 break; 7241 case PCI_BASE_ADDRESS_MEM_TYPE_64: 7242 offset += 8; 7243 break; 7244 default: /* reserved in PCI 2.2 */ 7245 dev_warn(&pdev->dev, 7246 "base address is invalid\n"); 7247 return -1; 7248 break; 7249 } 7250 } 7251 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) 7252 return i + 1; 7253 } 7254 return -1; 7255 } 7256 7257 static void hpsa_disable_interrupt_mode(struct ctlr_info *h) 7258 { 7259 pci_free_irq_vectors(h->pdev); 7260 h->msix_vectors = 0; 7261 } 7262 7263 /* If MSI/MSI-X is supported by the kernel we will try to enable it on 7264 * controllers that are capable. If not, we use legacy INTx mode. 7265 */ 7266 static int hpsa_interrupt_mode(struct ctlr_info *h) 7267 { 7268 unsigned int flags = PCI_IRQ_LEGACY; 7269 int ret; 7270 7271 /* Some boards advertise MSI but don't really support it */ 7272 switch (h->board_id) { 7273 case 0x40700E11: 7274 case 0x40800E11: 7275 case 0x40820E11: 7276 case 0x40830E11: 7277 break; 7278 default: 7279 ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES, 7280 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY); 7281 if (ret > 0) { 7282 h->msix_vectors = ret; 7283 return 0; 7284 } 7285 7286 flags |= PCI_IRQ_MSI; 7287 break; 7288 } 7289 7290 ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags); 7291 if (ret < 0) 7292 return ret; 7293 return 0; 7294 } 7295 7296 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 7297 bool *legacy_board) 7298 { 7299 int i; 7300 u32 subsystem_vendor_id, subsystem_device_id; 7301 7302 subsystem_vendor_id = pdev->subsystem_vendor; 7303 subsystem_device_id = pdev->subsystem_device; 7304 *board_id = ((subsystem_device_id << 16) & 0xffff0000) | 7305 subsystem_vendor_id; 7306 7307 if (legacy_board) 7308 *legacy_board = false; 7309 for (i = 0; i < ARRAY_SIZE(products); i++) 7310 if (*board_id == products[i].board_id) { 7311 if (products[i].access != &SA5A_access && 7312 products[i].access != &SA5B_access) 7313 return i; 7314 dev_warn(&pdev->dev, 7315 "legacy board ID: 0x%08x\n", 7316 *board_id); 7317 if (legacy_board) 7318 *legacy_board = true; 7319 return i; 7320 } 7321 7322 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id); 7323 if (legacy_board) 7324 *legacy_board = true; 7325 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ 7326 } 7327 7328 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 7329 unsigned long *memory_bar) 7330 { 7331 int i; 7332 7333 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 7334 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 7335 /* addressing mode bits already removed */ 7336 *memory_bar = pci_resource_start(pdev, i); 7337 dev_dbg(&pdev->dev, "memory BAR = %lx\n", 7338 *memory_bar); 7339 return 0; 7340 } 7341 dev_warn(&pdev->dev, "no memory BAR found\n"); 7342 return -ENODEV; 7343 } 7344 7345 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 7346 int wait_for_ready) 7347 { 7348 int i, iterations; 7349 u32 scratchpad; 7350 if (wait_for_ready) 7351 iterations = HPSA_BOARD_READY_ITERATIONS; 7352 else 7353 iterations = HPSA_BOARD_NOT_READY_ITERATIONS; 7354 7355 for (i = 0; i < iterations; i++) { 7356 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); 7357 if (wait_for_ready) { 7358 if (scratchpad == HPSA_FIRMWARE_READY) 7359 return 0; 7360 } else { 7361 if (scratchpad != HPSA_FIRMWARE_READY) 7362 return 0; 7363 } 7364 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); 7365 } 7366 dev_warn(&pdev->dev, "board not ready, timed out.\n"); 7367 return -ENODEV; 7368 } 7369 7370 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 7371 u32 *cfg_base_addr, u64 *cfg_base_addr_index, 7372 u64 *cfg_offset) 7373 { 7374 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); 7375 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); 7376 *cfg_base_addr &= (u32) 0x0000ffff; 7377 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); 7378 if (*cfg_base_addr_index == -1) { 7379 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); 7380 return -ENODEV; 7381 } 7382 return 0; 7383 } 7384 7385 static void hpsa_free_cfgtables(struct ctlr_info *h) 7386 { 7387 if (h->transtable) { 7388 iounmap(h->transtable); 7389 h->transtable = NULL; 7390 } 7391 if (h->cfgtable) { 7392 iounmap(h->cfgtable); 7393 h->cfgtable = NULL; 7394 } 7395 } 7396 7397 /* Find and map CISS config table and transfer table 7398 + * several items must be unmapped (freed) later 7399 + * */ 7400 static int hpsa_find_cfgtables(struct ctlr_info *h) 7401 { 7402 u64 cfg_offset; 7403 u32 cfg_base_addr; 7404 u64 cfg_base_addr_index; 7405 u32 trans_offset; 7406 int rc; 7407 7408 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 7409 &cfg_base_addr_index, &cfg_offset); 7410 if (rc) 7411 return rc; 7412 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, 7413 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); 7414 if (!h->cfgtable) { 7415 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); 7416 return -ENOMEM; 7417 } 7418 rc = write_driver_ver_to_cfgtable(h->cfgtable); 7419 if (rc) 7420 return rc; 7421 /* Find performant mode table. */ 7422 trans_offset = readl(&h->cfgtable->TransMethodOffset); 7423 h->transtable = remap_pci_mem(pci_resource_start(h->pdev, 7424 cfg_base_addr_index)+cfg_offset+trans_offset, 7425 sizeof(*h->transtable)); 7426 if (!h->transtable) { 7427 dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); 7428 hpsa_free_cfgtables(h); 7429 return -ENOMEM; 7430 } 7431 return 0; 7432 } 7433 7434 static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) 7435 { 7436 #define MIN_MAX_COMMANDS 16 7437 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); 7438 7439 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); 7440 7441 /* Limit commands in memory limited kdump scenario. */ 7442 if (reset_devices && h->max_commands > 32) 7443 h->max_commands = 32; 7444 7445 if (h->max_commands < MIN_MAX_COMMANDS) { 7446 dev_warn(&h->pdev->dev, 7447 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", 7448 h->max_commands, 7449 MIN_MAX_COMMANDS); 7450 h->max_commands = MIN_MAX_COMMANDS; 7451 } 7452 } 7453 7454 /* If the controller reports that the total max sg entries is greater than 512, 7455 * then we know that chained SG blocks work. (Original smart arrays did not 7456 * support chained SG blocks and would return zero for max sg entries.) 7457 */ 7458 static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) 7459 { 7460 return h->maxsgentries > 512; 7461 } 7462 7463 /* Interrogate the hardware for some limits: 7464 * max commands, max SG elements without chaining, and with chaining, 7465 * SG chain block size, etc. 7466 */ 7467 static void hpsa_find_board_params(struct ctlr_info *h) 7468 { 7469 hpsa_get_max_perf_mode_cmds(h); 7470 h->nr_cmds = h->max_commands; 7471 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); 7472 h->fw_support = readl(&(h->cfgtable->misc_fw_support)); 7473 if (hpsa_supports_chained_sg_blocks(h)) { 7474 /* Limit in-command s/g elements to 32 save dma'able memory. */ 7475 h->max_cmd_sg_entries = 32; 7476 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; 7477 h->maxsgentries--; /* save one for chain pointer */ 7478 } else { 7479 /* 7480 * Original smart arrays supported at most 31 s/g entries 7481 * embedded inline in the command (trying to use more 7482 * would lock up the controller) 7483 */ 7484 h->max_cmd_sg_entries = 31; 7485 h->maxsgentries = 31; /* default to traditional values */ 7486 h->chainsize = 0; 7487 } 7488 7489 /* Find out what task management functions are supported and cache */ 7490 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); 7491 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) 7492 dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); 7493 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) 7494 dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); 7495 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) 7496 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); 7497 } 7498 7499 static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) 7500 { 7501 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { 7502 dev_err(&h->pdev->dev, "not a valid CISS config table\n"); 7503 return false; 7504 } 7505 return true; 7506 } 7507 7508 static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) 7509 { 7510 u32 driver_support; 7511 7512 driver_support = readl(&(h->cfgtable->driver_support)); 7513 /* Need to enable prefetch in the SCSI core for 6400 in x86 */ 7514 #ifdef CONFIG_X86 7515 driver_support |= ENABLE_SCSI_PREFETCH; 7516 #endif 7517 driver_support |= ENABLE_UNIT_ATTN; 7518 writel(driver_support, &(h->cfgtable->driver_support)); 7519 } 7520 7521 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result 7522 * in a prefetch beyond physical memory. 7523 */ 7524 static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) 7525 { 7526 u32 dma_prefetch; 7527 7528 if (h->board_id != 0x3225103C) 7529 return; 7530 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); 7531 dma_prefetch |= 0x8000; 7532 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); 7533 } 7534 7535 static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) 7536 { 7537 int i; 7538 u32 doorbell_value; 7539 unsigned long flags; 7540 /* wait until the clear_event_notify bit 6 is cleared by controller. */ 7541 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { 7542 spin_lock_irqsave(&h->lock, flags); 7543 doorbell_value = readl(h->vaddr + SA5_DOORBELL); 7544 spin_unlock_irqrestore(&h->lock, flags); 7545 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) 7546 goto done; 7547 /* delay and try again */ 7548 msleep(CLEAR_EVENT_WAIT_INTERVAL); 7549 } 7550 return -ENODEV; 7551 done: 7552 return 0; 7553 } 7554 7555 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) 7556 { 7557 int i; 7558 u32 doorbell_value; 7559 unsigned long flags; 7560 7561 /* under certain very rare conditions, this can take awhile. 7562 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right 7563 * as we enter this code.) 7564 */ 7565 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { 7566 if (h->remove_in_progress) 7567 goto done; 7568 spin_lock_irqsave(&h->lock, flags); 7569 doorbell_value = readl(h->vaddr + SA5_DOORBELL); 7570 spin_unlock_irqrestore(&h->lock, flags); 7571 if (!(doorbell_value & CFGTBL_ChangeReq)) 7572 goto done; 7573 /* delay and try again */ 7574 msleep(MODE_CHANGE_WAIT_INTERVAL); 7575 } 7576 return -ENODEV; 7577 done: 7578 return 0; 7579 } 7580 7581 /* return -ENODEV or other reason on error, 0 on success */ 7582 static int hpsa_enter_simple_mode(struct ctlr_info *h) 7583 { 7584 u32 trans_support; 7585 7586 trans_support = readl(&(h->cfgtable->TransportSupport)); 7587 if (!(trans_support & SIMPLE_MODE)) 7588 return -ENOTSUPP; 7589 7590 h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); 7591 7592 /* Update the field, and then ring the doorbell */ 7593 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); 7594 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 7595 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 7596 if (hpsa_wait_for_mode_change_ack(h)) 7597 goto error; 7598 print_cfg_table(&h->pdev->dev, h->cfgtable); 7599 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) 7600 goto error; 7601 h->transMethod = CFGTBL_Trans_Simple; 7602 return 0; 7603 error: 7604 dev_err(&h->pdev->dev, "failed to enter simple mode\n"); 7605 return -ENODEV; 7606 } 7607 7608 /* free items allocated or mapped by hpsa_pci_init */ 7609 static void hpsa_free_pci_init(struct ctlr_info *h) 7610 { 7611 hpsa_free_cfgtables(h); /* pci_init 4 */ 7612 iounmap(h->vaddr); /* pci_init 3 */ 7613 h->vaddr = NULL; 7614 hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 7615 /* 7616 * call pci_disable_device before pci_release_regions per 7617 * Documentation/PCI/pci.txt 7618 */ 7619 pci_disable_device(h->pdev); /* pci_init 1 */ 7620 pci_release_regions(h->pdev); /* pci_init 2 */ 7621 } 7622 7623 /* several items must be freed later */ 7624 static int hpsa_pci_init(struct ctlr_info *h) 7625 { 7626 int prod_index, err; 7627 bool legacy_board; 7628 7629 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board); 7630 if (prod_index < 0) 7631 return prod_index; 7632 h->product_name = products[prod_index].product_name; 7633 h->access = *(products[prod_index].access); 7634 h->legacy_board = legacy_board; 7635 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | 7636 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); 7637 7638 err = pci_enable_device(h->pdev); 7639 if (err) { 7640 dev_err(&h->pdev->dev, "failed to enable PCI device\n"); 7641 pci_disable_device(h->pdev); 7642 return err; 7643 } 7644 7645 err = pci_request_regions(h->pdev, HPSA); 7646 if (err) { 7647 dev_err(&h->pdev->dev, 7648 "failed to obtain PCI resources\n"); 7649 pci_disable_device(h->pdev); 7650 return err; 7651 } 7652 7653 pci_set_master(h->pdev); 7654 7655 err = hpsa_interrupt_mode(h); 7656 if (err) 7657 goto clean1; 7658 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); 7659 if (err) 7660 goto clean2; /* intmode+region, pci */ 7661 h->vaddr = remap_pci_mem(h->paddr, 0x250); 7662 if (!h->vaddr) { 7663 dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); 7664 err = -ENOMEM; 7665 goto clean2; /* intmode+region, pci */ 7666 } 7667 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 7668 if (err) 7669 goto clean3; /* vaddr, intmode+region, pci */ 7670 err = hpsa_find_cfgtables(h); 7671 if (err) 7672 goto clean3; /* vaddr, intmode+region, pci */ 7673 hpsa_find_board_params(h); 7674 7675 if (!hpsa_CISS_signature_present(h)) { 7676 err = -ENODEV; 7677 goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7678 } 7679 hpsa_set_driver_support_bits(h); 7680 hpsa_p600_dma_prefetch_quirk(h); 7681 err = hpsa_enter_simple_mode(h); 7682 if (err) 7683 goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7684 return 0; 7685 7686 clean4: /* cfgtables, vaddr, intmode+region, pci */ 7687 hpsa_free_cfgtables(h); 7688 clean3: /* vaddr, intmode+region, pci */ 7689 iounmap(h->vaddr); 7690 h->vaddr = NULL; 7691 clean2: /* intmode+region, pci */ 7692 hpsa_disable_interrupt_mode(h); 7693 clean1: 7694 /* 7695 * call pci_disable_device before pci_release_regions per 7696 * Documentation/PCI/pci.txt 7697 */ 7698 pci_disable_device(h->pdev); 7699 pci_release_regions(h->pdev); 7700 return err; 7701 } 7702 7703 static void hpsa_hba_inquiry(struct ctlr_info *h) 7704 { 7705 int rc; 7706 7707 #define HBA_INQUIRY_BYTE_COUNT 64 7708 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); 7709 if (!h->hba_inquiry_data) 7710 return; 7711 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, 7712 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); 7713 if (rc != 0) { 7714 kfree(h->hba_inquiry_data); 7715 h->hba_inquiry_data = NULL; 7716 } 7717 } 7718 7719 static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) 7720 { 7721 int rc, i; 7722 void __iomem *vaddr; 7723 7724 if (!reset_devices) 7725 return 0; 7726 7727 /* kdump kernel is loading, we don't know in which state is 7728 * the pci interface. The dev->enable_cnt is equal zero 7729 * so we call enable+disable, wait a while and switch it on. 7730 */ 7731 rc = pci_enable_device(pdev); 7732 if (rc) { 7733 dev_warn(&pdev->dev, "Failed to enable PCI device\n"); 7734 return -ENODEV; 7735 } 7736 pci_disable_device(pdev); 7737 msleep(260); /* a randomly chosen number */ 7738 rc = pci_enable_device(pdev); 7739 if (rc) { 7740 dev_warn(&pdev->dev, "failed to enable device.\n"); 7741 return -ENODEV; 7742 } 7743 7744 pci_set_master(pdev); 7745 7746 vaddr = pci_ioremap_bar(pdev, 0); 7747 if (vaddr == NULL) { 7748 rc = -ENOMEM; 7749 goto out_disable; 7750 } 7751 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); 7752 iounmap(vaddr); 7753 7754 /* Reset the controller with a PCI power-cycle or via doorbell */ 7755 rc = hpsa_kdump_hard_reset_controller(pdev, board_id); 7756 7757 /* -ENOTSUPP here means we cannot reset the controller 7758 * but it's already (and still) up and running in 7759 * "performant mode". Or, it might be 640x, which can't reset 7760 * due to concerns about shared bbwc between 6402/6404 pair. 7761 */ 7762 if (rc) 7763 goto out_disable; 7764 7765 /* Now try to get the controller to respond to a no-op */ 7766 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); 7767 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { 7768 if (hpsa_noop(pdev) == 0) 7769 break; 7770 else 7771 dev_warn(&pdev->dev, "no-op failed%s\n", 7772 (i < 11 ? "; re-trying" : "")); 7773 } 7774 7775 out_disable: 7776 7777 pci_disable_device(pdev); 7778 return rc; 7779 } 7780 7781 static void hpsa_free_cmd_pool(struct ctlr_info *h) 7782 { 7783 kfree(h->cmd_pool_bits); 7784 h->cmd_pool_bits = NULL; 7785 if (h->cmd_pool) { 7786 pci_free_consistent(h->pdev, 7787 h->nr_cmds * sizeof(struct CommandList), 7788 h->cmd_pool, 7789 h->cmd_pool_dhandle); 7790 h->cmd_pool = NULL; 7791 h->cmd_pool_dhandle = 0; 7792 } 7793 if (h->errinfo_pool) { 7794 pci_free_consistent(h->pdev, 7795 h->nr_cmds * sizeof(struct ErrorInfo), 7796 h->errinfo_pool, 7797 h->errinfo_pool_dhandle); 7798 h->errinfo_pool = NULL; 7799 h->errinfo_pool_dhandle = 0; 7800 } 7801 } 7802 7803 static int hpsa_alloc_cmd_pool(struct ctlr_info *h) 7804 { 7805 h->cmd_pool_bits = kzalloc( 7806 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * 7807 sizeof(unsigned long), GFP_KERNEL); 7808 h->cmd_pool = pci_alloc_consistent(h->pdev, 7809 h->nr_cmds * sizeof(*h->cmd_pool), 7810 &(h->cmd_pool_dhandle)); 7811 h->errinfo_pool = pci_alloc_consistent(h->pdev, 7812 h->nr_cmds * sizeof(*h->errinfo_pool), 7813 &(h->errinfo_pool_dhandle)); 7814 if ((h->cmd_pool_bits == NULL) 7815 || (h->cmd_pool == NULL) 7816 || (h->errinfo_pool == NULL)) { 7817 dev_err(&h->pdev->dev, "out of memory in %s", __func__); 7818 goto clean_up; 7819 } 7820 hpsa_preinitialize_commands(h); 7821 return 0; 7822 clean_up: 7823 hpsa_free_cmd_pool(h); 7824 return -ENOMEM; 7825 } 7826 7827 /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ 7828 static void hpsa_free_irqs(struct ctlr_info *h) 7829 { 7830 int i; 7831 7832 if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) { 7833 /* Single reply queue, only one irq to free */ 7834 free_irq(pci_irq_vector(h->pdev, 0), &h->q[h->intr_mode]); 7835 h->q[h->intr_mode] = 0; 7836 return; 7837 } 7838 7839 for (i = 0; i < h->msix_vectors; i++) { 7840 free_irq(pci_irq_vector(h->pdev, i), &h->q[i]); 7841 h->q[i] = 0; 7842 } 7843 for (; i < MAX_REPLY_QUEUES; i++) 7844 h->q[i] = 0; 7845 } 7846 7847 /* returns 0 on success; cleans up and returns -Enn on error */ 7848 static int hpsa_request_irqs(struct ctlr_info *h, 7849 irqreturn_t (*msixhandler)(int, void *), 7850 irqreturn_t (*intxhandler)(int, void *)) 7851 { 7852 int rc, i; 7853 7854 /* 7855 * initialize h->q[x] = x so that interrupt handlers know which 7856 * queue to process. 7857 */ 7858 for (i = 0; i < MAX_REPLY_QUEUES; i++) 7859 h->q[i] = (u8) i; 7860 7861 if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) { 7862 /* If performant mode and MSI-X, use multiple reply queues */ 7863 for (i = 0; i < h->msix_vectors; i++) { 7864 sprintf(h->intrname[i], "%s-msix%d", h->devname, i); 7865 rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler, 7866 0, h->intrname[i], 7867 &h->q[i]); 7868 if (rc) { 7869 int j; 7870 7871 dev_err(&h->pdev->dev, 7872 "failed to get irq %d for %s\n", 7873 pci_irq_vector(h->pdev, i), h->devname); 7874 for (j = 0; j < i; j++) { 7875 free_irq(pci_irq_vector(h->pdev, j), &h->q[j]); 7876 h->q[j] = 0; 7877 } 7878 for (; j < MAX_REPLY_QUEUES; j++) 7879 h->q[j] = 0; 7880 return rc; 7881 } 7882 } 7883 } else { 7884 /* Use single reply pool */ 7885 if (h->msix_vectors > 0 || h->pdev->msi_enabled) { 7886 sprintf(h->intrname[0], "%s-msi%s", h->devname, 7887 h->msix_vectors ? "x" : ""); 7888 rc = request_irq(pci_irq_vector(h->pdev, 0), 7889 msixhandler, 0, 7890 h->intrname[0], 7891 &h->q[h->intr_mode]); 7892 } else { 7893 sprintf(h->intrname[h->intr_mode], 7894 "%s-intx", h->devname); 7895 rc = request_irq(pci_irq_vector(h->pdev, 0), 7896 intxhandler, IRQF_SHARED, 7897 h->intrname[0], 7898 &h->q[h->intr_mode]); 7899 } 7900 } 7901 if (rc) { 7902 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", 7903 pci_irq_vector(h->pdev, 0), h->devname); 7904 hpsa_free_irqs(h); 7905 return -ENODEV; 7906 } 7907 return 0; 7908 } 7909 7910 static int hpsa_kdump_soft_reset(struct ctlr_info *h) 7911 { 7912 int rc; 7913 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER); 7914 7915 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); 7916 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); 7917 if (rc) { 7918 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); 7919 return rc; 7920 } 7921 7922 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); 7923 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 7924 if (rc) { 7925 dev_warn(&h->pdev->dev, "Board failed to become ready " 7926 "after soft reset.\n"); 7927 return rc; 7928 } 7929 7930 return 0; 7931 } 7932 7933 static void hpsa_free_reply_queues(struct ctlr_info *h) 7934 { 7935 int i; 7936 7937 for (i = 0; i < h->nreply_queues; i++) { 7938 if (!h->reply_queue[i].head) 7939 continue; 7940 pci_free_consistent(h->pdev, 7941 h->reply_queue_size, 7942 h->reply_queue[i].head, 7943 h->reply_queue[i].busaddr); 7944 h->reply_queue[i].head = NULL; 7945 h->reply_queue[i].busaddr = 0; 7946 } 7947 h->reply_queue_size = 0; 7948 } 7949 7950 static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) 7951 { 7952 hpsa_free_performant_mode(h); /* init_one 7 */ 7953 hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 7954 hpsa_free_cmd_pool(h); /* init_one 5 */ 7955 hpsa_free_irqs(h); /* init_one 4 */ 7956 scsi_host_put(h->scsi_host); /* init_one 3 */ 7957 h->scsi_host = NULL; /* init_one 3 */ 7958 hpsa_free_pci_init(h); /* init_one 2_5 */ 7959 free_percpu(h->lockup_detected); /* init_one 2 */ 7960 h->lockup_detected = NULL; /* init_one 2 */ 7961 if (h->resubmit_wq) { 7962 destroy_workqueue(h->resubmit_wq); /* init_one 1 */ 7963 h->resubmit_wq = NULL; 7964 } 7965 if (h->rescan_ctlr_wq) { 7966 destroy_workqueue(h->rescan_ctlr_wq); 7967 h->rescan_ctlr_wq = NULL; 7968 } 7969 kfree(h); /* init_one 1 */ 7970 } 7971 7972 /* Called when controller lockup detected. */ 7973 static void fail_all_outstanding_cmds(struct ctlr_info *h) 7974 { 7975 int i, refcount; 7976 struct CommandList *c; 7977 int failcount = 0; 7978 7979 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ 7980 for (i = 0; i < h->nr_cmds; i++) { 7981 c = h->cmd_pool + i; 7982 refcount = atomic_inc_return(&c->refcount); 7983 if (refcount > 1) { 7984 c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 7985 finish_cmd(c); 7986 atomic_dec(&h->commands_outstanding); 7987 failcount++; 7988 } 7989 cmd_free(h, c); 7990 } 7991 dev_warn(&h->pdev->dev, 7992 "failed %d commands in fail_all\n", failcount); 7993 } 7994 7995 static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) 7996 { 7997 int cpu; 7998 7999 for_each_online_cpu(cpu) { 8000 u32 *lockup_detected; 8001 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 8002 *lockup_detected = value; 8003 } 8004 wmb(); /* be sure the per-cpu variables are out to memory */ 8005 } 8006 8007 static void controller_lockup_detected(struct ctlr_info *h) 8008 { 8009 unsigned long flags; 8010 u32 lockup_detected; 8011 8012 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8013 spin_lock_irqsave(&h->lock, flags); 8014 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 8015 if (!lockup_detected) { 8016 /* no heartbeat, but controller gave us a zero. */ 8017 dev_warn(&h->pdev->dev, 8018 "lockup detected after %d but scratchpad register is zero\n", 8019 h->heartbeat_sample_interval / HZ); 8020 lockup_detected = 0xffffffff; 8021 } 8022 set_lockup_detected_for_all_cpus(h, lockup_detected); 8023 spin_unlock_irqrestore(&h->lock, flags); 8024 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", 8025 lockup_detected, h->heartbeat_sample_interval / HZ); 8026 if (lockup_detected == 0xffff0000) { 8027 dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n"); 8028 writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL); 8029 } 8030 pci_disable_device(h->pdev); 8031 fail_all_outstanding_cmds(h); 8032 } 8033 8034 static int detect_controller_lockup(struct ctlr_info *h) 8035 { 8036 u64 now; 8037 u32 heartbeat; 8038 unsigned long flags; 8039 8040 now = get_jiffies_64(); 8041 /* If we've received an interrupt recently, we're ok. */ 8042 if (time_after64(h->last_intr_timestamp + 8043 (h->heartbeat_sample_interval), now)) 8044 return false; 8045 8046 /* 8047 * If we've already checked the heartbeat recently, we're ok. 8048 * This could happen if someone sends us a signal. We 8049 * otherwise don't care about signals in this thread. 8050 */ 8051 if (time_after64(h->last_heartbeat_timestamp + 8052 (h->heartbeat_sample_interval), now)) 8053 return false; 8054 8055 /* If heartbeat has not changed since we last looked, we're not ok. */ 8056 spin_lock_irqsave(&h->lock, flags); 8057 heartbeat = readl(&h->cfgtable->HeartBeat); 8058 spin_unlock_irqrestore(&h->lock, flags); 8059 if (h->last_heartbeat == heartbeat) { 8060 controller_lockup_detected(h); 8061 return true; 8062 } 8063 8064 /* We're ok. */ 8065 h->last_heartbeat = heartbeat; 8066 h->last_heartbeat_timestamp = now; 8067 return false; 8068 } 8069 8070 static void hpsa_ack_ctlr_events(struct ctlr_info *h) 8071 { 8072 int i; 8073 char *event_type; 8074 8075 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 8076 return; 8077 8078 /* Ask the controller to clear the events we're handling. */ 8079 if ((h->transMethod & (CFGTBL_Trans_io_accel1 8080 | CFGTBL_Trans_io_accel2)) && 8081 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || 8082 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { 8083 8084 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) 8085 event_type = "state change"; 8086 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) 8087 event_type = "configuration change"; 8088 /* Stop sending new RAID offload reqs via the IO accelerator */ 8089 scsi_block_requests(h->scsi_host); 8090 for (i = 0; i < h->ndevices; i++) { 8091 h->dev[i]->offload_enabled = 0; 8092 h->dev[i]->offload_to_be_enabled = 0; 8093 } 8094 hpsa_drain_accel_commands(h); 8095 /* Set 'accelerator path config change' bit */ 8096 dev_warn(&h->pdev->dev, 8097 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", 8098 h->events, event_type); 8099 writel(h->events, &(h->cfgtable->clear_event_notify)); 8100 /* Set the "clear event notify field update" bit 6 */ 8101 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 8102 /* Wait until ctlr clears 'clear event notify field', bit 6 */ 8103 hpsa_wait_for_clear_event_notify_ack(h); 8104 scsi_unblock_requests(h->scsi_host); 8105 } else { 8106 /* Acknowledge controller notification events. */ 8107 writel(h->events, &(h->cfgtable->clear_event_notify)); 8108 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 8109 hpsa_wait_for_clear_event_notify_ack(h); 8110 #if 0 8111 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8112 hpsa_wait_for_mode_change_ack(h); 8113 #endif 8114 } 8115 return; 8116 } 8117 8118 /* Check a register on the controller to see if there are configuration 8119 * changes (added/changed/removed logical drives, etc.) which mean that 8120 * we should rescan the controller for devices. 8121 * Also check flag for driver-initiated rescan. 8122 */ 8123 static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) 8124 { 8125 if (h->drv_req_rescan) { 8126 h->drv_req_rescan = 0; 8127 return 1; 8128 } 8129 8130 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 8131 return 0; 8132 8133 h->events = readl(&(h->cfgtable->event_notify)); 8134 return h->events & RESCAN_REQUIRED_EVENT_BITS; 8135 } 8136 8137 /* 8138 * Check if any of the offline devices have become ready 8139 */ 8140 static int hpsa_offline_devices_ready(struct ctlr_info *h) 8141 { 8142 unsigned long flags; 8143 struct offline_device_entry *d; 8144 struct list_head *this, *tmp; 8145 8146 spin_lock_irqsave(&h->offline_device_lock, flags); 8147 list_for_each_safe(this, tmp, &h->offline_device_list) { 8148 d = list_entry(this, struct offline_device_entry, 8149 offline_list); 8150 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8151 if (!hpsa_volume_offline(h, d->scsi3addr)) { 8152 spin_lock_irqsave(&h->offline_device_lock, flags); 8153 list_del(&d->offline_list); 8154 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8155 return 1; 8156 } 8157 spin_lock_irqsave(&h->offline_device_lock, flags); 8158 } 8159 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8160 return 0; 8161 } 8162 8163 static int hpsa_luns_changed(struct ctlr_info *h) 8164 { 8165 int rc = 1; /* assume there are changes */ 8166 struct ReportLUNdata *logdev = NULL; 8167 8168 /* if we can't find out if lun data has changed, 8169 * assume that it has. 8170 */ 8171 8172 if (!h->lastlogicals) 8173 return rc; 8174 8175 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); 8176 if (!logdev) 8177 return rc; 8178 8179 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { 8180 dev_warn(&h->pdev->dev, 8181 "report luns failed, can't track lun changes.\n"); 8182 goto out; 8183 } 8184 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { 8185 dev_info(&h->pdev->dev, 8186 "Lun changes detected.\n"); 8187 memcpy(h->lastlogicals, logdev, sizeof(*logdev)); 8188 goto out; 8189 } else 8190 rc = 0; /* no changes detected. */ 8191 out: 8192 kfree(logdev); 8193 return rc; 8194 } 8195 8196 static void hpsa_perform_rescan(struct ctlr_info *h) 8197 { 8198 struct Scsi_Host *sh = NULL; 8199 unsigned long flags; 8200 8201 /* 8202 * Do the scan after the reset 8203 */ 8204 spin_lock_irqsave(&h->reset_lock, flags); 8205 if (h->reset_in_progress) { 8206 h->drv_req_rescan = 1; 8207 spin_unlock_irqrestore(&h->reset_lock, flags); 8208 return; 8209 } 8210 spin_unlock_irqrestore(&h->reset_lock, flags); 8211 8212 sh = scsi_host_get(h->scsi_host); 8213 if (sh != NULL) { 8214 hpsa_scan_start(sh); 8215 scsi_host_put(sh); 8216 h->drv_req_rescan = 0; 8217 } 8218 } 8219 8220 /* 8221 * watch for controller events 8222 */ 8223 static void hpsa_event_monitor_worker(struct work_struct *work) 8224 { 8225 struct ctlr_info *h = container_of(to_delayed_work(work), 8226 struct ctlr_info, event_monitor_work); 8227 unsigned long flags; 8228 8229 spin_lock_irqsave(&h->lock, flags); 8230 if (h->remove_in_progress) { 8231 spin_unlock_irqrestore(&h->lock, flags); 8232 return; 8233 } 8234 spin_unlock_irqrestore(&h->lock, flags); 8235 8236 if (hpsa_ctlr_needs_rescan(h)) { 8237 hpsa_ack_ctlr_events(h); 8238 hpsa_perform_rescan(h); 8239 } 8240 8241 spin_lock_irqsave(&h->lock, flags); 8242 if (!h->remove_in_progress) 8243 schedule_delayed_work(&h->event_monitor_work, 8244 HPSA_EVENT_MONITOR_INTERVAL); 8245 spin_unlock_irqrestore(&h->lock, flags); 8246 } 8247 8248 static void hpsa_rescan_ctlr_worker(struct work_struct *work) 8249 { 8250 unsigned long flags; 8251 struct ctlr_info *h = container_of(to_delayed_work(work), 8252 struct ctlr_info, rescan_ctlr_work); 8253 8254 spin_lock_irqsave(&h->lock, flags); 8255 if (h->remove_in_progress) { 8256 spin_unlock_irqrestore(&h->lock, flags); 8257 return; 8258 } 8259 spin_unlock_irqrestore(&h->lock, flags); 8260 8261 if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) { 8262 hpsa_perform_rescan(h); 8263 } else if (h->discovery_polling) { 8264 if (hpsa_luns_changed(h)) { 8265 dev_info(&h->pdev->dev, 8266 "driver discovery polling rescan.\n"); 8267 hpsa_perform_rescan(h); 8268 } 8269 } 8270 spin_lock_irqsave(&h->lock, flags); 8271 if (!h->remove_in_progress) 8272 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 8273 h->heartbeat_sample_interval); 8274 spin_unlock_irqrestore(&h->lock, flags); 8275 } 8276 8277 static void hpsa_monitor_ctlr_worker(struct work_struct *work) 8278 { 8279 unsigned long flags; 8280 struct ctlr_info *h = container_of(to_delayed_work(work), 8281 struct ctlr_info, monitor_ctlr_work); 8282 8283 detect_controller_lockup(h); 8284 if (lockup_detected(h)) 8285 return; 8286 8287 spin_lock_irqsave(&h->lock, flags); 8288 if (!h->remove_in_progress) 8289 schedule_delayed_work(&h->monitor_ctlr_work, 8290 h->heartbeat_sample_interval); 8291 spin_unlock_irqrestore(&h->lock, flags); 8292 } 8293 8294 static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, 8295 char *name) 8296 { 8297 struct workqueue_struct *wq = NULL; 8298 8299 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); 8300 if (!wq) 8301 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); 8302 8303 return wq; 8304 } 8305 8306 static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8307 { 8308 int dac, rc; 8309 struct ctlr_info *h; 8310 int try_soft_reset = 0; 8311 unsigned long flags; 8312 u32 board_id; 8313 8314 if (number_of_controllers == 0) 8315 printk(KERN_INFO DRIVER_NAME "\n"); 8316 8317 rc = hpsa_lookup_board_id(pdev, &board_id, NULL); 8318 if (rc < 0) { 8319 dev_warn(&pdev->dev, "Board ID not found\n"); 8320 return rc; 8321 } 8322 8323 rc = hpsa_init_reset_devices(pdev, board_id); 8324 if (rc) { 8325 if (rc != -ENOTSUPP) 8326 return rc; 8327 /* If the reset fails in a particular way (it has no way to do 8328 * a proper hard reset, so returns -ENOTSUPP) we can try to do 8329 * a soft reset once we get the controller configured up to the 8330 * point that it can accept a command. 8331 */ 8332 try_soft_reset = 1; 8333 rc = 0; 8334 } 8335 8336 reinit_after_soft_reset: 8337 8338 /* Command structures must be aligned on a 32-byte boundary because 8339 * the 5 lower bits of the address are used by the hardware. and by 8340 * the driver. See comments in hpsa.h for more info. 8341 */ 8342 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); 8343 h = kzalloc(sizeof(*h), GFP_KERNEL); 8344 if (!h) { 8345 dev_err(&pdev->dev, "Failed to allocate controller head\n"); 8346 return -ENOMEM; 8347 } 8348 8349 h->pdev = pdev; 8350 8351 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; 8352 INIT_LIST_HEAD(&h->offline_device_list); 8353 spin_lock_init(&h->lock); 8354 spin_lock_init(&h->offline_device_lock); 8355 spin_lock_init(&h->scan_lock); 8356 spin_lock_init(&h->reset_lock); 8357 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); 8358 8359 /* Allocate and clear per-cpu variable lockup_detected */ 8360 h->lockup_detected = alloc_percpu(u32); 8361 if (!h->lockup_detected) { 8362 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); 8363 rc = -ENOMEM; 8364 goto clean1; /* aer/h */ 8365 } 8366 set_lockup_detected_for_all_cpus(h, 0); 8367 8368 rc = hpsa_pci_init(h); 8369 if (rc) 8370 goto clean2; /* lu, aer/h */ 8371 8372 /* relies on h-> settings made by hpsa_pci_init, including 8373 * interrupt_mode h->intr */ 8374 rc = hpsa_scsi_host_alloc(h); 8375 if (rc) 8376 goto clean2_5; /* pci, lu, aer/h */ 8377 8378 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); 8379 h->ctlr = number_of_controllers; 8380 number_of_controllers++; 8381 8382 /* configure PCI DMA stuff */ 8383 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 8384 if (rc == 0) { 8385 dac = 1; 8386 } else { 8387 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 8388 if (rc == 0) { 8389 dac = 0; 8390 } else { 8391 dev_err(&pdev->dev, "no suitable DMA available\n"); 8392 goto clean3; /* shost, pci, lu, aer/h */ 8393 } 8394 } 8395 8396 /* make sure the board interrupts are off */ 8397 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8398 8399 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); 8400 if (rc) 8401 goto clean3; /* shost, pci, lu, aer/h */ 8402 rc = hpsa_alloc_cmd_pool(h); 8403 if (rc) 8404 goto clean4; /* irq, shost, pci, lu, aer/h */ 8405 rc = hpsa_alloc_sg_chain_blocks(h); 8406 if (rc) 8407 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ 8408 init_waitqueue_head(&h->scan_wait_queue); 8409 init_waitqueue_head(&h->event_sync_wait_queue); 8410 mutex_init(&h->reset_mutex); 8411 h->scan_finished = 1; /* no scan currently in progress */ 8412 h->scan_waiting = 0; 8413 8414 pci_set_drvdata(pdev, h); 8415 h->ndevices = 0; 8416 8417 spin_lock_init(&h->devlock); 8418 rc = hpsa_put_ctlr_into_performant_mode(h); 8419 if (rc) 8420 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ 8421 8422 /* create the resubmit workqueue */ 8423 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); 8424 if (!h->rescan_ctlr_wq) { 8425 rc = -ENOMEM; 8426 goto clean7; 8427 } 8428 8429 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); 8430 if (!h->resubmit_wq) { 8431 rc = -ENOMEM; 8432 goto clean7; /* aer/h */ 8433 } 8434 8435 /* 8436 * At this point, the controller is ready to take commands. 8437 * Now, if reset_devices and the hard reset didn't work, try 8438 * the soft reset and see if that works. 8439 */ 8440 if (try_soft_reset) { 8441 8442 /* This is kind of gross. We may or may not get a completion 8443 * from the soft reset command, and if we do, then the value 8444 * from the fifo may or may not be valid. So, we wait 10 secs 8445 * after the reset throwing away any completions we get during 8446 * that time. Unregister the interrupt handler and register 8447 * fake ones to scoop up any residual completions. 8448 */ 8449 spin_lock_irqsave(&h->lock, flags); 8450 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8451 spin_unlock_irqrestore(&h->lock, flags); 8452 hpsa_free_irqs(h); 8453 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, 8454 hpsa_intx_discard_completions); 8455 if (rc) { 8456 dev_warn(&h->pdev->dev, 8457 "Failed to request_irq after soft reset.\n"); 8458 /* 8459 * cannot goto clean7 or free_irqs will be called 8460 * again. Instead, do its work 8461 */ 8462 hpsa_free_performant_mode(h); /* clean7 */ 8463 hpsa_free_sg_chain_blocks(h); /* clean6 */ 8464 hpsa_free_cmd_pool(h); /* clean5 */ 8465 /* 8466 * skip hpsa_free_irqs(h) clean4 since that 8467 * was just called before request_irqs failed 8468 */ 8469 goto clean3; 8470 } 8471 8472 rc = hpsa_kdump_soft_reset(h); 8473 if (rc) 8474 /* Neither hard nor soft reset worked, we're hosed. */ 8475 goto clean7; 8476 8477 dev_info(&h->pdev->dev, "Board READY.\n"); 8478 dev_info(&h->pdev->dev, 8479 "Waiting for stale completions to drain.\n"); 8480 h->access.set_intr_mask(h, HPSA_INTR_ON); 8481 msleep(10000); 8482 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8483 8484 rc = controller_reset_failed(h->cfgtable); 8485 if (rc) 8486 dev_info(&h->pdev->dev, 8487 "Soft reset appears to have failed.\n"); 8488 8489 /* since the controller's reset, we have to go back and re-init 8490 * everything. Easiest to just forget what we've done and do it 8491 * all over again. 8492 */ 8493 hpsa_undo_allocations_after_kdump_soft_reset(h); 8494 try_soft_reset = 0; 8495 if (rc) 8496 /* don't goto clean, we already unallocated */ 8497 return -ENODEV; 8498 8499 goto reinit_after_soft_reset; 8500 } 8501 8502 /* Enable Accelerated IO path at driver layer */ 8503 h->acciopath_status = 1; 8504 /* Disable discovery polling.*/ 8505 h->discovery_polling = 0; 8506 8507 8508 /* Turn the interrupts on so we can service requests */ 8509 h->access.set_intr_mask(h, HPSA_INTR_ON); 8510 8511 hpsa_hba_inquiry(h); 8512 8513 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); 8514 if (!h->lastlogicals) 8515 dev_info(&h->pdev->dev, 8516 "Can't track change to report lun data\n"); 8517 8518 /* hook into SCSI subsystem */ 8519 rc = hpsa_scsi_add_host(h); 8520 if (rc) 8521 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8522 8523 /* Monitor the controller for firmware lockups */ 8524 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 8525 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); 8526 schedule_delayed_work(&h->monitor_ctlr_work, 8527 h->heartbeat_sample_interval); 8528 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); 8529 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 8530 h->heartbeat_sample_interval); 8531 INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker); 8532 schedule_delayed_work(&h->event_monitor_work, 8533 HPSA_EVENT_MONITOR_INTERVAL); 8534 return 0; 8535 8536 clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8537 hpsa_free_performant_mode(h); 8538 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8539 clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ 8540 hpsa_free_sg_chain_blocks(h); 8541 clean5: /* cmd, irq, shost, pci, lu, aer/h */ 8542 hpsa_free_cmd_pool(h); 8543 clean4: /* irq, shost, pci, lu, aer/h */ 8544 hpsa_free_irqs(h); 8545 clean3: /* shost, pci, lu, aer/h */ 8546 scsi_host_put(h->scsi_host); 8547 h->scsi_host = NULL; 8548 clean2_5: /* pci, lu, aer/h */ 8549 hpsa_free_pci_init(h); 8550 clean2: /* lu, aer/h */ 8551 if (h->lockup_detected) { 8552 free_percpu(h->lockup_detected); 8553 h->lockup_detected = NULL; 8554 } 8555 clean1: /* wq/aer/h */ 8556 if (h->resubmit_wq) { 8557 destroy_workqueue(h->resubmit_wq); 8558 h->resubmit_wq = NULL; 8559 } 8560 if (h->rescan_ctlr_wq) { 8561 destroy_workqueue(h->rescan_ctlr_wq); 8562 h->rescan_ctlr_wq = NULL; 8563 } 8564 kfree(h); 8565 return rc; 8566 } 8567 8568 static void hpsa_flush_cache(struct ctlr_info *h) 8569 { 8570 char *flush_buf; 8571 struct CommandList *c; 8572 int rc; 8573 8574 if (unlikely(lockup_detected(h))) 8575 return; 8576 flush_buf = kzalloc(4, GFP_KERNEL); 8577 if (!flush_buf) 8578 return; 8579 8580 c = cmd_alloc(h); 8581 8582 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, 8583 RAID_CTLR_LUNID, TYPE_CMD)) { 8584 goto out; 8585 } 8586 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8587 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT); 8588 if (rc) 8589 goto out; 8590 if (c->err_info->CommandStatus != 0) 8591 out: 8592 dev_warn(&h->pdev->dev, 8593 "error flushing cache on controller\n"); 8594 cmd_free(h, c); 8595 kfree(flush_buf); 8596 } 8597 8598 /* Make controller gather fresh report lun data each time we 8599 * send down a report luns request 8600 */ 8601 static void hpsa_disable_rld_caching(struct ctlr_info *h) 8602 { 8603 u32 *options; 8604 struct CommandList *c; 8605 int rc; 8606 8607 /* Don't bother trying to set diag options if locked up */ 8608 if (unlikely(h->lockup_detected)) 8609 return; 8610 8611 options = kzalloc(sizeof(*options), GFP_KERNEL); 8612 if (!options) 8613 return; 8614 8615 c = cmd_alloc(h); 8616 8617 /* first, get the current diag options settings */ 8618 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8619 RAID_CTLR_LUNID, TYPE_CMD)) 8620 goto errout; 8621 8622 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8623 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 8624 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8625 goto errout; 8626 8627 /* Now, set the bit for disabling the RLD caching */ 8628 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; 8629 8630 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, 8631 RAID_CTLR_LUNID, TYPE_CMD)) 8632 goto errout; 8633 8634 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8635 PCI_DMA_TODEVICE, NO_TIMEOUT); 8636 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8637 goto errout; 8638 8639 /* Now verify that it got set: */ 8640 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8641 RAID_CTLR_LUNID, TYPE_CMD)) 8642 goto errout; 8643 8644 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8645 PCI_DMA_FROMDEVICE, NO_TIMEOUT); 8646 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8647 goto errout; 8648 8649 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) 8650 goto out; 8651 8652 errout: 8653 dev_err(&h->pdev->dev, 8654 "Error: failed to disable report lun data caching.\n"); 8655 out: 8656 cmd_free(h, c); 8657 kfree(options); 8658 } 8659 8660 static void hpsa_shutdown(struct pci_dev *pdev) 8661 { 8662 struct ctlr_info *h; 8663 8664 h = pci_get_drvdata(pdev); 8665 /* Turn board interrupts off and send the flush cache command 8666 * sendcmd will turn off interrupt, and send the flush... 8667 * To write all data in the battery backed cache to disks 8668 */ 8669 hpsa_flush_cache(h); 8670 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8671 hpsa_free_irqs(h); /* init_one 4 */ 8672 hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 8673 } 8674 8675 static void hpsa_free_device_info(struct ctlr_info *h) 8676 { 8677 int i; 8678 8679 for (i = 0; i < h->ndevices; i++) { 8680 kfree(h->dev[i]); 8681 h->dev[i] = NULL; 8682 } 8683 } 8684 8685 static void hpsa_remove_one(struct pci_dev *pdev) 8686 { 8687 struct ctlr_info *h; 8688 unsigned long flags; 8689 8690 if (pci_get_drvdata(pdev) == NULL) { 8691 dev_err(&pdev->dev, "unable to remove device\n"); 8692 return; 8693 } 8694 h = pci_get_drvdata(pdev); 8695 8696 /* Get rid of any controller monitoring work items */ 8697 spin_lock_irqsave(&h->lock, flags); 8698 h->remove_in_progress = 1; 8699 spin_unlock_irqrestore(&h->lock, flags); 8700 cancel_delayed_work_sync(&h->monitor_ctlr_work); 8701 cancel_delayed_work_sync(&h->rescan_ctlr_work); 8702 cancel_delayed_work_sync(&h->event_monitor_work); 8703 destroy_workqueue(h->rescan_ctlr_wq); 8704 destroy_workqueue(h->resubmit_wq); 8705 8706 hpsa_delete_sas_host(h); 8707 8708 /* 8709 * Call before disabling interrupts. 8710 * scsi_remove_host can trigger I/O operations especially 8711 * when multipath is enabled. There can be SYNCHRONIZE CACHE 8712 * operations which cannot complete and will hang the system. 8713 */ 8714 if (h->scsi_host) 8715 scsi_remove_host(h->scsi_host); /* init_one 8 */ 8716 /* includes hpsa_free_irqs - init_one 4 */ 8717 /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 8718 hpsa_shutdown(pdev); 8719 8720 hpsa_free_device_info(h); /* scan */ 8721 8722 kfree(h->hba_inquiry_data); /* init_one 10 */ 8723 h->hba_inquiry_data = NULL; /* init_one 10 */ 8724 hpsa_free_ioaccel2_sg_chain_blocks(h); 8725 hpsa_free_performant_mode(h); /* init_one 7 */ 8726 hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 8727 hpsa_free_cmd_pool(h); /* init_one 5 */ 8728 kfree(h->lastlogicals); 8729 8730 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ 8731 8732 scsi_host_put(h->scsi_host); /* init_one 3 */ 8733 h->scsi_host = NULL; /* init_one 3 */ 8734 8735 /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 8736 hpsa_free_pci_init(h); /* init_one 2.5 */ 8737 8738 free_percpu(h->lockup_detected); /* init_one 2 */ 8739 h->lockup_detected = NULL; /* init_one 2 */ 8740 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ 8741 8742 kfree(h); /* init_one 1 */ 8743 } 8744 8745 static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, 8746 __attribute__((unused)) pm_message_t state) 8747 { 8748 return -ENOSYS; 8749 } 8750 8751 static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) 8752 { 8753 return -ENOSYS; 8754 } 8755 8756 static struct pci_driver hpsa_pci_driver = { 8757 .name = HPSA, 8758 .probe = hpsa_init_one, 8759 .remove = hpsa_remove_one, 8760 .id_table = hpsa_pci_device_id, /* id_table */ 8761 .shutdown = hpsa_shutdown, 8762 .suspend = hpsa_suspend, 8763 .resume = hpsa_resume, 8764 }; 8765 8766 /* Fill in bucket_map[], given nsgs (the max number of 8767 * scatter gather elements supported) and bucket[], 8768 * which is an array of 8 integers. The bucket[] array 8769 * contains 8 different DMA transfer sizes (in 16 8770 * byte increments) which the controller uses to fetch 8771 * commands. This function fills in bucket_map[], which 8772 * maps a given number of scatter gather elements to one of 8773 * the 8 DMA transfer sizes. The point of it is to allow the 8774 * controller to only do as much DMA as needed to fetch the 8775 * command, with the DMA transfer size encoded in the lower 8776 * bits of the command address. 8777 */ 8778 static void calc_bucket_map(int bucket[], int num_buckets, 8779 int nsgs, int min_blocks, u32 *bucket_map) 8780 { 8781 int i, j, b, size; 8782 8783 /* Note, bucket_map must have nsgs+1 entries. */ 8784 for (i = 0; i <= nsgs; i++) { 8785 /* Compute size of a command with i SG entries */ 8786 size = i + min_blocks; 8787 b = num_buckets; /* Assume the biggest bucket */ 8788 /* Find the bucket that is just big enough */ 8789 for (j = 0; j < num_buckets; j++) { 8790 if (bucket[j] >= size) { 8791 b = j; 8792 break; 8793 } 8794 } 8795 /* for a command with i SG entries, use bucket b. */ 8796 bucket_map[i] = b; 8797 } 8798 } 8799 8800 /* 8801 * return -ENODEV on err, 0 on success (or no action) 8802 * allocates numerous items that must be freed later 8803 */ 8804 static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) 8805 { 8806 int i; 8807 unsigned long register_value; 8808 unsigned long transMethod = CFGTBL_Trans_Performant | 8809 (trans_support & CFGTBL_Trans_use_short_tags) | 8810 CFGTBL_Trans_enable_directed_msix | 8811 (trans_support & (CFGTBL_Trans_io_accel1 | 8812 CFGTBL_Trans_io_accel2)); 8813 struct access_method access = SA5_performant_access; 8814 8815 /* This is a bit complicated. There are 8 registers on 8816 * the controller which we write to to tell it 8 different 8817 * sizes of commands which there may be. It's a way of 8818 * reducing the DMA done to fetch each command. Encoded into 8819 * each command's tag are 3 bits which communicate to the controller 8820 * which of the eight sizes that command fits within. The size of 8821 * each command depends on how many scatter gather entries there are. 8822 * Each SG entry requires 16 bytes. The eight registers are programmed 8823 * with the number of 16-byte blocks a command of that size requires. 8824 * The smallest command possible requires 5 such 16 byte blocks. 8825 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte 8826 * blocks. Note, this only extends to the SG entries contained 8827 * within the command block, and does not extend to chained blocks 8828 * of SG elements. bft[] contains the eight values we write to 8829 * the registers. They are not evenly distributed, but have more 8830 * sizes for small commands, and fewer sizes for larger commands. 8831 */ 8832 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; 8833 #define MIN_IOACCEL2_BFT_ENTRY 5 8834 #define HPSA_IOACCEL2_HEADER_SZ 4 8835 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, 8836 13, 14, 15, 16, 17, 18, 19, 8837 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; 8838 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); 8839 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); 8840 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > 8841 16 * MIN_IOACCEL2_BFT_ENTRY); 8842 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); 8843 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); 8844 /* 5 = 1 s/g entry or 4k 8845 * 6 = 2 s/g entry or 8k 8846 * 8 = 4 s/g entry or 16k 8847 * 10 = 6 s/g entry or 24k 8848 */ 8849 8850 /* If the controller supports either ioaccel method then 8851 * we can also use the RAID stack submit path that does not 8852 * perform the superfluous readl() after each command submission. 8853 */ 8854 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) 8855 access = SA5_performant_access_no_read; 8856 8857 /* Controller spec: zero out this buffer. */ 8858 for (i = 0; i < h->nreply_queues; i++) 8859 memset(h->reply_queue[i].head, 0, h->reply_queue_size); 8860 8861 bft[7] = SG_ENTRIES_IN_CMD + 4; 8862 calc_bucket_map(bft, ARRAY_SIZE(bft), 8863 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); 8864 for (i = 0; i < 8; i++) 8865 writel(bft[i], &h->transtable->BlockFetch[i]); 8866 8867 /* size of controller ring buffer */ 8868 writel(h->max_commands, &h->transtable->RepQSize); 8869 writel(h->nreply_queues, &h->transtable->RepQCount); 8870 writel(0, &h->transtable->RepQCtrAddrLow32); 8871 writel(0, &h->transtable->RepQCtrAddrHigh32); 8872 8873 for (i = 0; i < h->nreply_queues; i++) { 8874 writel(0, &h->transtable->RepQAddr[i].upper); 8875 writel(h->reply_queue[i].busaddr, 8876 &h->transtable->RepQAddr[i].lower); 8877 } 8878 8879 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 8880 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); 8881 /* 8882 * enable outbound interrupt coalescing in accelerator mode; 8883 */ 8884 if (trans_support & CFGTBL_Trans_io_accel1) { 8885 access = SA5_ioaccel_mode1_access; 8886 writel(10, &h->cfgtable->HostWrite.CoalIntDelay); 8887 writel(4, &h->cfgtable->HostWrite.CoalIntCount); 8888 } else 8889 if (trans_support & CFGTBL_Trans_io_accel2) 8890 access = SA5_ioaccel_mode2_access; 8891 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8892 if (hpsa_wait_for_mode_change_ack(h)) { 8893 dev_err(&h->pdev->dev, 8894 "performant mode problem - doorbell timeout\n"); 8895 return -ENODEV; 8896 } 8897 register_value = readl(&(h->cfgtable->TransportActive)); 8898 if (!(register_value & CFGTBL_Trans_Performant)) { 8899 dev_err(&h->pdev->dev, 8900 "performant mode problem - transport not active\n"); 8901 return -ENODEV; 8902 } 8903 /* Change the access methods to the performant access methods */ 8904 h->access = access; 8905 h->transMethod = transMethod; 8906 8907 if (!((trans_support & CFGTBL_Trans_io_accel1) || 8908 (trans_support & CFGTBL_Trans_io_accel2))) 8909 return 0; 8910 8911 if (trans_support & CFGTBL_Trans_io_accel1) { 8912 /* Set up I/O accelerator mode */ 8913 for (i = 0; i < h->nreply_queues; i++) { 8914 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); 8915 h->reply_queue[i].current_entry = 8916 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); 8917 } 8918 bft[7] = h->ioaccel_maxsg + 8; 8919 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, 8920 h->ioaccel1_blockFetchTable); 8921 8922 /* initialize all reply queue entries to unused */ 8923 for (i = 0; i < h->nreply_queues; i++) 8924 memset(h->reply_queue[i].head, 8925 (u8) IOACCEL_MODE1_REPLY_UNUSED, 8926 h->reply_queue_size); 8927 8928 /* set all the constant fields in the accelerator command 8929 * frames once at init time to save CPU cycles later. 8930 */ 8931 for (i = 0; i < h->nr_cmds; i++) { 8932 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; 8933 8934 cp->function = IOACCEL1_FUNCTION_SCSIIO; 8935 cp->err_info = (u32) (h->errinfo_pool_dhandle + 8936 (i * sizeof(struct ErrorInfo))); 8937 cp->err_info_len = sizeof(struct ErrorInfo); 8938 cp->sgl_offset = IOACCEL1_SGLOFFSET; 8939 cp->host_context_flags = 8940 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); 8941 cp->timeout_sec = 0; 8942 cp->ReplyQueue = 0; 8943 cp->tag = 8944 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); 8945 cp->host_addr = 8946 cpu_to_le64(h->ioaccel_cmd_pool_dhandle + 8947 (i * sizeof(struct io_accel1_cmd))); 8948 } 8949 } else if (trans_support & CFGTBL_Trans_io_accel2) { 8950 u64 cfg_offset, cfg_base_addr_index; 8951 u32 bft2_offset, cfg_base_addr; 8952 int rc; 8953 8954 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 8955 &cfg_base_addr_index, &cfg_offset); 8956 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); 8957 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; 8958 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, 8959 4, h->ioaccel2_blockFetchTable); 8960 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); 8961 BUILD_BUG_ON(offsetof(struct CfgTable, 8962 io_accel_request_size_offset) != 0xb8); 8963 h->ioaccel2_bft2_regs = 8964 remap_pci_mem(pci_resource_start(h->pdev, 8965 cfg_base_addr_index) + 8966 cfg_offset + bft2_offset, 8967 ARRAY_SIZE(bft2) * 8968 sizeof(*h->ioaccel2_bft2_regs)); 8969 for (i = 0; i < ARRAY_SIZE(bft2); i++) 8970 writel(bft2[i], &h->ioaccel2_bft2_regs[i]); 8971 } 8972 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8973 if (hpsa_wait_for_mode_change_ack(h)) { 8974 dev_err(&h->pdev->dev, 8975 "performant mode problem - enabling ioaccel mode\n"); 8976 return -ENODEV; 8977 } 8978 return 0; 8979 } 8980 8981 /* Free ioaccel1 mode command blocks and block fetch table */ 8982 static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) 8983 { 8984 if (h->ioaccel_cmd_pool) { 8985 pci_free_consistent(h->pdev, 8986 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 8987 h->ioaccel_cmd_pool, 8988 h->ioaccel_cmd_pool_dhandle); 8989 h->ioaccel_cmd_pool = NULL; 8990 h->ioaccel_cmd_pool_dhandle = 0; 8991 } 8992 kfree(h->ioaccel1_blockFetchTable); 8993 h->ioaccel1_blockFetchTable = NULL; 8994 } 8995 8996 /* Allocate ioaccel1 mode command blocks and block fetch table */ 8997 static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) 8998 { 8999 h->ioaccel_maxsg = 9000 readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 9001 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) 9002 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; 9003 9004 /* Command structures must be aligned on a 128-byte boundary 9005 * because the 7 lower bits of the address are used by the 9006 * hardware. 9007 */ 9008 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % 9009 IOACCEL1_COMMANDLIST_ALIGNMENT); 9010 h->ioaccel_cmd_pool = 9011 pci_alloc_consistent(h->pdev, 9012 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 9013 &(h->ioaccel_cmd_pool_dhandle)); 9014 9015 h->ioaccel1_blockFetchTable = 9016 kmalloc(((h->ioaccel_maxsg + 1) * 9017 sizeof(u32)), GFP_KERNEL); 9018 9019 if ((h->ioaccel_cmd_pool == NULL) || 9020 (h->ioaccel1_blockFetchTable == NULL)) 9021 goto clean_up; 9022 9023 memset(h->ioaccel_cmd_pool, 0, 9024 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); 9025 return 0; 9026 9027 clean_up: 9028 hpsa_free_ioaccel1_cmd_and_bft(h); 9029 return -ENOMEM; 9030 } 9031 9032 /* Free ioaccel2 mode command blocks and block fetch table */ 9033 static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) 9034 { 9035 hpsa_free_ioaccel2_sg_chain_blocks(h); 9036 9037 if (h->ioaccel2_cmd_pool) { 9038 pci_free_consistent(h->pdev, 9039 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 9040 h->ioaccel2_cmd_pool, 9041 h->ioaccel2_cmd_pool_dhandle); 9042 h->ioaccel2_cmd_pool = NULL; 9043 h->ioaccel2_cmd_pool_dhandle = 0; 9044 } 9045 kfree(h->ioaccel2_blockFetchTable); 9046 h->ioaccel2_blockFetchTable = NULL; 9047 } 9048 9049 /* Allocate ioaccel2 mode command blocks and block fetch table */ 9050 static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) 9051 { 9052 int rc; 9053 9054 /* Allocate ioaccel2 mode command blocks and block fetch table */ 9055 9056 h->ioaccel_maxsg = 9057 readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 9058 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) 9059 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; 9060 9061 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % 9062 IOACCEL2_COMMANDLIST_ALIGNMENT); 9063 h->ioaccel2_cmd_pool = 9064 pci_alloc_consistent(h->pdev, 9065 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 9066 &(h->ioaccel2_cmd_pool_dhandle)); 9067 9068 h->ioaccel2_blockFetchTable = 9069 kmalloc(((h->ioaccel_maxsg + 1) * 9070 sizeof(u32)), GFP_KERNEL); 9071 9072 if ((h->ioaccel2_cmd_pool == NULL) || 9073 (h->ioaccel2_blockFetchTable == NULL)) { 9074 rc = -ENOMEM; 9075 goto clean_up; 9076 } 9077 9078 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); 9079 if (rc) 9080 goto clean_up; 9081 9082 memset(h->ioaccel2_cmd_pool, 0, 9083 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); 9084 return 0; 9085 9086 clean_up: 9087 hpsa_free_ioaccel2_cmd_and_bft(h); 9088 return rc; 9089 } 9090 9091 /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ 9092 static void hpsa_free_performant_mode(struct ctlr_info *h) 9093 { 9094 kfree(h->blockFetchTable); 9095 h->blockFetchTable = NULL; 9096 hpsa_free_reply_queues(h); 9097 hpsa_free_ioaccel1_cmd_and_bft(h); 9098 hpsa_free_ioaccel2_cmd_and_bft(h); 9099 } 9100 9101 /* return -ENODEV on error, 0 on success (or no action) 9102 * allocates numerous items that must be freed later 9103 */ 9104 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) 9105 { 9106 u32 trans_support; 9107 unsigned long transMethod = CFGTBL_Trans_Performant | 9108 CFGTBL_Trans_use_short_tags; 9109 int i, rc; 9110 9111 if (hpsa_simple_mode) 9112 return 0; 9113 9114 trans_support = readl(&(h->cfgtable->TransportSupport)); 9115 if (!(trans_support & PERFORMANT_MODE)) 9116 return 0; 9117 9118 /* Check for I/O accelerator mode support */ 9119 if (trans_support & CFGTBL_Trans_io_accel1) { 9120 transMethod |= CFGTBL_Trans_io_accel1 | 9121 CFGTBL_Trans_enable_directed_msix; 9122 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); 9123 if (rc) 9124 return rc; 9125 } else if (trans_support & CFGTBL_Trans_io_accel2) { 9126 transMethod |= CFGTBL_Trans_io_accel2 | 9127 CFGTBL_Trans_enable_directed_msix; 9128 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); 9129 if (rc) 9130 return rc; 9131 } 9132 9133 h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1; 9134 hpsa_get_max_perf_mode_cmds(h); 9135 /* Performant mode ring buffer and supporting data structures */ 9136 h->reply_queue_size = h->max_commands * sizeof(u64); 9137 9138 for (i = 0; i < h->nreply_queues; i++) { 9139 h->reply_queue[i].head = pci_alloc_consistent(h->pdev, 9140 h->reply_queue_size, 9141 &(h->reply_queue[i].busaddr)); 9142 if (!h->reply_queue[i].head) { 9143 rc = -ENOMEM; 9144 goto clean1; /* rq, ioaccel */ 9145 } 9146 h->reply_queue[i].size = h->max_commands; 9147 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ 9148 h->reply_queue[i].current_entry = 0; 9149 } 9150 9151 /* Need a block fetch table for performant mode */ 9152 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * 9153 sizeof(u32)), GFP_KERNEL); 9154 if (!h->blockFetchTable) { 9155 rc = -ENOMEM; 9156 goto clean1; /* rq, ioaccel */ 9157 } 9158 9159 rc = hpsa_enter_performant_mode(h, trans_support); 9160 if (rc) 9161 goto clean2; /* bft, rq, ioaccel */ 9162 return 0; 9163 9164 clean2: /* bft, rq, ioaccel */ 9165 kfree(h->blockFetchTable); 9166 h->blockFetchTable = NULL; 9167 clean1: /* rq, ioaccel */ 9168 hpsa_free_reply_queues(h); 9169 hpsa_free_ioaccel1_cmd_and_bft(h); 9170 hpsa_free_ioaccel2_cmd_and_bft(h); 9171 return rc; 9172 } 9173 9174 static int is_accelerated_cmd(struct CommandList *c) 9175 { 9176 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; 9177 } 9178 9179 static void hpsa_drain_accel_commands(struct ctlr_info *h) 9180 { 9181 struct CommandList *c = NULL; 9182 int i, accel_cmds_out; 9183 int refcount; 9184 9185 do { /* wait for all outstanding ioaccel commands to drain out */ 9186 accel_cmds_out = 0; 9187 for (i = 0; i < h->nr_cmds; i++) { 9188 c = h->cmd_pool + i; 9189 refcount = atomic_inc_return(&c->refcount); 9190 if (refcount > 1) /* Command is allocated */ 9191 accel_cmds_out += is_accelerated_cmd(c); 9192 cmd_free(h, c); 9193 } 9194 if (accel_cmds_out <= 0) 9195 break; 9196 msleep(100); 9197 } while (1); 9198 } 9199 9200 static struct hpsa_sas_phy *hpsa_alloc_sas_phy( 9201 struct hpsa_sas_port *hpsa_sas_port) 9202 { 9203 struct hpsa_sas_phy *hpsa_sas_phy; 9204 struct sas_phy *phy; 9205 9206 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); 9207 if (!hpsa_sas_phy) 9208 return NULL; 9209 9210 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, 9211 hpsa_sas_port->next_phy_index); 9212 if (!phy) { 9213 kfree(hpsa_sas_phy); 9214 return NULL; 9215 } 9216 9217 hpsa_sas_port->next_phy_index++; 9218 hpsa_sas_phy->phy = phy; 9219 hpsa_sas_phy->parent_port = hpsa_sas_port; 9220 9221 return hpsa_sas_phy; 9222 } 9223 9224 static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9225 { 9226 struct sas_phy *phy = hpsa_sas_phy->phy; 9227 9228 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); 9229 if (hpsa_sas_phy->added_to_port) 9230 list_del(&hpsa_sas_phy->phy_list_entry); 9231 sas_phy_delete(phy); 9232 kfree(hpsa_sas_phy); 9233 } 9234 9235 static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9236 { 9237 int rc; 9238 struct hpsa_sas_port *hpsa_sas_port; 9239 struct sas_phy *phy; 9240 struct sas_identify *identify; 9241 9242 hpsa_sas_port = hpsa_sas_phy->parent_port; 9243 phy = hpsa_sas_phy->phy; 9244 9245 identify = &phy->identify; 9246 memset(identify, 0, sizeof(*identify)); 9247 identify->sas_address = hpsa_sas_port->sas_address; 9248 identify->device_type = SAS_END_DEVICE; 9249 identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9250 identify->target_port_protocols = SAS_PROTOCOL_STP; 9251 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9252 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9253 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; 9254 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; 9255 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; 9256 9257 rc = sas_phy_add(hpsa_sas_phy->phy); 9258 if (rc) 9259 return rc; 9260 9261 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); 9262 list_add_tail(&hpsa_sas_phy->phy_list_entry, 9263 &hpsa_sas_port->phy_list_head); 9264 hpsa_sas_phy->added_to_port = true; 9265 9266 return 0; 9267 } 9268 9269 static int 9270 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, 9271 struct sas_rphy *rphy) 9272 { 9273 struct sas_identify *identify; 9274 9275 identify = &rphy->identify; 9276 identify->sas_address = hpsa_sas_port->sas_address; 9277 identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9278 identify->target_port_protocols = SAS_PROTOCOL_STP; 9279 9280 return sas_rphy_add(rphy); 9281 } 9282 9283 static struct hpsa_sas_port 9284 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, 9285 u64 sas_address) 9286 { 9287 int rc; 9288 struct hpsa_sas_port *hpsa_sas_port; 9289 struct sas_port *port; 9290 9291 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); 9292 if (!hpsa_sas_port) 9293 return NULL; 9294 9295 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); 9296 hpsa_sas_port->parent_node = hpsa_sas_node; 9297 9298 port = sas_port_alloc_num(hpsa_sas_node->parent_dev); 9299 if (!port) 9300 goto free_hpsa_port; 9301 9302 rc = sas_port_add(port); 9303 if (rc) 9304 goto free_sas_port; 9305 9306 hpsa_sas_port->port = port; 9307 hpsa_sas_port->sas_address = sas_address; 9308 list_add_tail(&hpsa_sas_port->port_list_entry, 9309 &hpsa_sas_node->port_list_head); 9310 9311 return hpsa_sas_port; 9312 9313 free_sas_port: 9314 sas_port_free(port); 9315 free_hpsa_port: 9316 kfree(hpsa_sas_port); 9317 9318 return NULL; 9319 } 9320 9321 static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) 9322 { 9323 struct hpsa_sas_phy *hpsa_sas_phy; 9324 struct hpsa_sas_phy *next; 9325 9326 list_for_each_entry_safe(hpsa_sas_phy, next, 9327 &hpsa_sas_port->phy_list_head, phy_list_entry) 9328 hpsa_free_sas_phy(hpsa_sas_phy); 9329 9330 sas_port_delete(hpsa_sas_port->port); 9331 list_del(&hpsa_sas_port->port_list_entry); 9332 kfree(hpsa_sas_port); 9333 } 9334 9335 static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) 9336 { 9337 struct hpsa_sas_node *hpsa_sas_node; 9338 9339 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); 9340 if (hpsa_sas_node) { 9341 hpsa_sas_node->parent_dev = parent_dev; 9342 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); 9343 } 9344 9345 return hpsa_sas_node; 9346 } 9347 9348 static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) 9349 { 9350 struct hpsa_sas_port *hpsa_sas_port; 9351 struct hpsa_sas_port *next; 9352 9353 if (!hpsa_sas_node) 9354 return; 9355 9356 list_for_each_entry_safe(hpsa_sas_port, next, 9357 &hpsa_sas_node->port_list_head, port_list_entry) 9358 hpsa_free_sas_port(hpsa_sas_port); 9359 9360 kfree(hpsa_sas_node); 9361 } 9362 9363 static struct hpsa_scsi_dev_t 9364 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 9365 struct sas_rphy *rphy) 9366 { 9367 int i; 9368 struct hpsa_scsi_dev_t *device; 9369 9370 for (i = 0; i < h->ndevices; i++) { 9371 device = h->dev[i]; 9372 if (!device->sas_port) 9373 continue; 9374 if (device->sas_port->rphy == rphy) 9375 return device; 9376 } 9377 9378 return NULL; 9379 } 9380 9381 static int hpsa_add_sas_host(struct ctlr_info *h) 9382 { 9383 int rc; 9384 struct device *parent_dev; 9385 struct hpsa_sas_node *hpsa_sas_node; 9386 struct hpsa_sas_port *hpsa_sas_port; 9387 struct hpsa_sas_phy *hpsa_sas_phy; 9388 9389 parent_dev = &h->scsi_host->shost_gendev; 9390 9391 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); 9392 if (!hpsa_sas_node) 9393 return -ENOMEM; 9394 9395 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); 9396 if (!hpsa_sas_port) { 9397 rc = -ENODEV; 9398 goto free_sas_node; 9399 } 9400 9401 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); 9402 if (!hpsa_sas_phy) { 9403 rc = -ENODEV; 9404 goto free_sas_port; 9405 } 9406 9407 rc = hpsa_sas_port_add_phy(hpsa_sas_phy); 9408 if (rc) 9409 goto free_sas_phy; 9410 9411 h->sas_host = hpsa_sas_node; 9412 9413 return 0; 9414 9415 free_sas_phy: 9416 hpsa_free_sas_phy(hpsa_sas_phy); 9417 free_sas_port: 9418 hpsa_free_sas_port(hpsa_sas_port); 9419 free_sas_node: 9420 hpsa_free_sas_node(hpsa_sas_node); 9421 9422 return rc; 9423 } 9424 9425 static void hpsa_delete_sas_host(struct ctlr_info *h) 9426 { 9427 hpsa_free_sas_node(h->sas_host); 9428 } 9429 9430 static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 9431 struct hpsa_scsi_dev_t *device) 9432 { 9433 int rc; 9434 struct hpsa_sas_port *hpsa_sas_port; 9435 struct sas_rphy *rphy; 9436 9437 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); 9438 if (!hpsa_sas_port) 9439 return -ENOMEM; 9440 9441 rphy = sas_end_device_alloc(hpsa_sas_port->port); 9442 if (!rphy) { 9443 rc = -ENODEV; 9444 goto free_sas_port; 9445 } 9446 9447 hpsa_sas_port->rphy = rphy; 9448 device->sas_port = hpsa_sas_port; 9449 9450 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); 9451 if (rc) 9452 goto free_sas_port; 9453 9454 return 0; 9455 9456 free_sas_port: 9457 hpsa_free_sas_port(hpsa_sas_port); 9458 device->sas_port = NULL; 9459 9460 return rc; 9461 } 9462 9463 static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) 9464 { 9465 if (device->sas_port) { 9466 hpsa_free_sas_port(device->sas_port); 9467 device->sas_port = NULL; 9468 } 9469 } 9470 9471 static int 9472 hpsa_sas_get_linkerrors(struct sas_phy *phy) 9473 { 9474 return 0; 9475 } 9476 9477 static int 9478 hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) 9479 { 9480 *identifier = 0; 9481 return 0; 9482 } 9483 9484 static int 9485 hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) 9486 { 9487 return -ENXIO; 9488 } 9489 9490 static int 9491 hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) 9492 { 9493 return 0; 9494 } 9495 9496 static int 9497 hpsa_sas_phy_enable(struct sas_phy *phy, int enable) 9498 { 9499 return 0; 9500 } 9501 9502 static int 9503 hpsa_sas_phy_setup(struct sas_phy *phy) 9504 { 9505 return 0; 9506 } 9507 9508 static void 9509 hpsa_sas_phy_release(struct sas_phy *phy) 9510 { 9511 } 9512 9513 static int 9514 hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) 9515 { 9516 return -EINVAL; 9517 } 9518 9519 static struct sas_function_template hpsa_sas_transport_functions = { 9520 .get_linkerrors = hpsa_sas_get_linkerrors, 9521 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, 9522 .get_bay_identifier = hpsa_sas_get_bay_identifier, 9523 .phy_reset = hpsa_sas_phy_reset, 9524 .phy_enable = hpsa_sas_phy_enable, 9525 .phy_setup = hpsa_sas_phy_setup, 9526 .phy_release = hpsa_sas_phy_release, 9527 .set_phy_speed = hpsa_sas_phy_speed, 9528 }; 9529 9530 /* 9531 * This is it. Register the PCI driver information for the cards we control 9532 * the OS will call our registered routines when it finds one of our cards. 9533 */ 9534 static int __init hpsa_init(void) 9535 { 9536 int rc; 9537 9538 hpsa_sas_transport_template = 9539 sas_attach_transport(&hpsa_sas_transport_functions); 9540 if (!hpsa_sas_transport_template) 9541 return -ENODEV; 9542 9543 rc = pci_register_driver(&hpsa_pci_driver); 9544 9545 if (rc) 9546 sas_release_transport(hpsa_sas_transport_template); 9547 9548 return rc; 9549 } 9550 9551 static void __exit hpsa_cleanup(void) 9552 { 9553 pci_unregister_driver(&hpsa_pci_driver); 9554 sas_release_transport(hpsa_sas_transport_template); 9555 } 9556 9557 static void __attribute__((unused)) verify_offsets(void) 9558 { 9559 #define VERIFY_OFFSET(member, offset) \ 9560 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) 9561 9562 VERIFY_OFFSET(structure_size, 0); 9563 VERIFY_OFFSET(volume_blk_size, 4); 9564 VERIFY_OFFSET(volume_blk_cnt, 8); 9565 VERIFY_OFFSET(phys_blk_shift, 16); 9566 VERIFY_OFFSET(parity_rotation_shift, 17); 9567 VERIFY_OFFSET(strip_size, 18); 9568 VERIFY_OFFSET(disk_starting_blk, 20); 9569 VERIFY_OFFSET(disk_blk_cnt, 28); 9570 VERIFY_OFFSET(data_disks_per_row, 36); 9571 VERIFY_OFFSET(metadata_disks_per_row, 38); 9572 VERIFY_OFFSET(row_cnt, 40); 9573 VERIFY_OFFSET(layout_map_count, 42); 9574 VERIFY_OFFSET(flags, 44); 9575 VERIFY_OFFSET(dekindex, 46); 9576 /* VERIFY_OFFSET(reserved, 48 */ 9577 VERIFY_OFFSET(data, 64); 9578 9579 #undef VERIFY_OFFSET 9580 9581 #define VERIFY_OFFSET(member, offset) \ 9582 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) 9583 9584 VERIFY_OFFSET(IU_type, 0); 9585 VERIFY_OFFSET(direction, 1); 9586 VERIFY_OFFSET(reply_queue, 2); 9587 /* VERIFY_OFFSET(reserved1, 3); */ 9588 VERIFY_OFFSET(scsi_nexus, 4); 9589 VERIFY_OFFSET(Tag, 8); 9590 VERIFY_OFFSET(cdb, 16); 9591 VERIFY_OFFSET(cciss_lun, 32); 9592 VERIFY_OFFSET(data_len, 40); 9593 VERIFY_OFFSET(cmd_priority_task_attr, 44); 9594 VERIFY_OFFSET(sg_count, 45); 9595 /* VERIFY_OFFSET(reserved3 */ 9596 VERIFY_OFFSET(err_ptr, 48); 9597 VERIFY_OFFSET(err_len, 56); 9598 /* VERIFY_OFFSET(reserved4 */ 9599 VERIFY_OFFSET(sg, 64); 9600 9601 #undef VERIFY_OFFSET 9602 9603 #define VERIFY_OFFSET(member, offset) \ 9604 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) 9605 9606 VERIFY_OFFSET(dev_handle, 0x00); 9607 VERIFY_OFFSET(reserved1, 0x02); 9608 VERIFY_OFFSET(function, 0x03); 9609 VERIFY_OFFSET(reserved2, 0x04); 9610 VERIFY_OFFSET(err_info, 0x0C); 9611 VERIFY_OFFSET(reserved3, 0x10); 9612 VERIFY_OFFSET(err_info_len, 0x12); 9613 VERIFY_OFFSET(reserved4, 0x13); 9614 VERIFY_OFFSET(sgl_offset, 0x14); 9615 VERIFY_OFFSET(reserved5, 0x15); 9616 VERIFY_OFFSET(transfer_len, 0x1C); 9617 VERIFY_OFFSET(reserved6, 0x20); 9618 VERIFY_OFFSET(io_flags, 0x24); 9619 VERIFY_OFFSET(reserved7, 0x26); 9620 VERIFY_OFFSET(LUN, 0x34); 9621 VERIFY_OFFSET(control, 0x3C); 9622 VERIFY_OFFSET(CDB, 0x40); 9623 VERIFY_OFFSET(reserved8, 0x50); 9624 VERIFY_OFFSET(host_context_flags, 0x60); 9625 VERIFY_OFFSET(timeout_sec, 0x62); 9626 VERIFY_OFFSET(ReplyQueue, 0x64); 9627 VERIFY_OFFSET(reserved9, 0x65); 9628 VERIFY_OFFSET(tag, 0x68); 9629 VERIFY_OFFSET(host_addr, 0x70); 9630 VERIFY_OFFSET(CISS_LUN, 0x78); 9631 VERIFY_OFFSET(SG, 0x78 + 8); 9632 #undef VERIFY_OFFSET 9633 } 9634 9635 module_init(hpsa_init); 9636 module_exit(hpsa_cleanup); 9637