1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 39e21760eSDon Brace * Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries 494c7bc31SDon Brace * Copyright 2016 Microsemi Corporation 51358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 61358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 7edd16368SStephen M. Cameron * 8edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 9edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 10edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 11edd16368SStephen M. Cameron * 12edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 13edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 14edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 15edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 16edd16368SStephen M. Cameron * 1794c7bc31SDon Brace * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 18edd16368SStephen M. Cameron * 19edd16368SStephen M. Cameron */ 20edd16368SStephen M. Cameron 21edd16368SStephen M. Cameron #include <linux/module.h> 22edd16368SStephen M. Cameron #include <linux/interrupt.h> 23edd16368SStephen M. Cameron #include <linux/types.h> 24edd16368SStephen M. Cameron #include <linux/pci.h> 25edd16368SStephen M. Cameron #include <linux/kernel.h> 26edd16368SStephen M. Cameron #include <linux/slab.h> 27edd16368SStephen M. Cameron #include <linux/delay.h> 28edd16368SStephen M. Cameron #include <linux/fs.h> 29edd16368SStephen M. Cameron #include <linux/timer.h> 30edd16368SStephen M. Cameron #include <linux/init.h> 31edd16368SStephen M. Cameron #include <linux/spinlock.h> 32edd16368SStephen M. Cameron #include <linux/compat.h> 33edd16368SStephen M. Cameron #include <linux/blktrace_api.h> 34edd16368SStephen M. Cameron #include <linux/uaccess.h> 35edd16368SStephen M. Cameron #include <linux/io.h> 36edd16368SStephen M. Cameron #include <linux/dma-mapping.h> 37edd16368SStephen M. Cameron #include <linux/completion.h> 38edd16368SStephen M. Cameron #include <linux/moduleparam.h> 39edd16368SStephen M. Cameron #include <scsi/scsi.h> 40edd16368SStephen M. Cameron #include <scsi/scsi_cmnd.h> 41edd16368SStephen M. Cameron #include <scsi/scsi_device.h> 42edd16368SStephen M. Cameron #include <scsi/scsi_host.h> 43667e23d4SStephen M. Cameron #include <scsi/scsi_tcq.h> 449437ac43SStephen Cameron #include <scsi/scsi_eh.h> 45d04e62b9SKevin Barnett #include <scsi/scsi_transport_sas.h> 4673153fe5SWebb Scales #include <scsi/scsi_dbg.h> 47edd16368SStephen M. Cameron #include <linux/cciss_ioctl.h> 48edd16368SStephen M. Cameron #include <linux/string.h> 49edd16368SStephen M. Cameron #include <linux/bitmap.h> 5060063497SArun Sharma #include <linux/atomic.h> 51a0c12413SStephen M. Cameron #include <linux/jiffies.h> 5242a91641SDon Brace #include <linux/percpu-defs.h> 53094963daSStephen M. Cameron #include <linux/percpu.h> 542b08b3e9SDon Brace #include <asm/unaligned.h> 55283b4a9bSStephen M. Cameron #include <asm/div64.h> 56edd16368SStephen M. Cameron #include "hpsa_cmd.h" 57edd16368SStephen M. Cameron #include "hpsa.h" 58edd16368SStephen M. Cameron 59ec2c3aa9SDon Brace /* 60ec2c3aa9SDon Brace * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' 61ec2c3aa9SDon Brace * with an optional trailing '-' followed by a byte value (0-255). 62ec2c3aa9SDon Brace */ 63654cc541SDon Brace #define HPSA_DRIVER_VERSION "3.4.20-200" 64edd16368SStephen M. Cameron #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" 65f79cfec6SStephen M. Cameron #define HPSA "hpsa" 66edd16368SStephen M. Cameron 67007e7aa9SRobert Elliott /* How long to wait for CISS doorbell communication */ 68007e7aa9SRobert Elliott #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ 69007e7aa9SRobert Elliott #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ 70007e7aa9SRobert Elliott #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ 71007e7aa9SRobert Elliott #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ 72edd16368SStephen M. Cameron #define MAX_IOCTL_CONFIG_WAIT 1000 73edd16368SStephen M. Cameron 74edd16368SStephen M. Cameron /*define how many times we will try a command because of bus resets */ 75edd16368SStephen M. Cameron #define MAX_CMD_RETRIES 3 76b443d3eaSDon Brace /* How long to wait before giving up on a command */ 77b443d3eaSDon Brace #define HPSA_EH_PTRAID_TIMEOUT (240 * HZ) 78edd16368SStephen M. Cameron 79edd16368SStephen M. Cameron /* Embedded module documentation macros - see modules.h */ 80edd16368SStephen M. Cameron MODULE_AUTHOR("Hewlett-Packard Company"); 81edd16368SStephen M. Cameron MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ 82edd16368SStephen M. Cameron HPSA_DRIVER_VERSION); 83edd16368SStephen M. Cameron MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); 84edd16368SStephen M. Cameron MODULE_VERSION(HPSA_DRIVER_VERSION); 85edd16368SStephen M. Cameron MODULE_LICENSE("GPL"); 86253d2464SHannes Reinecke MODULE_ALIAS("cciss"); 87edd16368SStephen M. Cameron 8802ec19c8SStephen M. Cameron static int hpsa_simple_mode; 8902ec19c8SStephen M. Cameron module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); 9002ec19c8SStephen M. Cameron MODULE_PARM_DESC(hpsa_simple_mode, 9102ec19c8SStephen M. Cameron "Use 'simple mode' rather than 'performant mode'"); 92edd16368SStephen M. Cameron 93edd16368SStephen M. Cameron /* define the PCI info for the cards we can control */ 94edd16368SStephen M. Cameron static const struct pci_device_id hpsa_pci_device_id[] = { 95edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, 96edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, 97edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, 98edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, 99edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, 100163dbcd8SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, 101163dbcd8SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, 102f8b01eb9SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, 1039143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, 1049143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, 1059143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, 1069143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, 1079143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, 1089143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, 1099143a961Sscameron@beardog.cce.hp.com {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, 1107f1974a7SDon Brace {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920}, 111fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, 112fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, 113fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, 114fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, 1157f1974a7SDon Brace {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925}, 116fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, 117fe0c9610SMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, 11897b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, 11997b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, 12097b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, 12197b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, 12297b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, 12397b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, 12497b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, 12597b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, 12697b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, 12797b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, 1283b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, 12997b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, 13097b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, 13197b9f53dSMike Miller {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, 1323b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, 1333b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, 1343b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, 1353b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, 1363b7a45e5SJoe Handzik {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, 137fdfa4b6dSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, 138cbb47dcbSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, 139cbb47dcbSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, 140cbb47dcbSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, 141cbb47dcbSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, 142cbb47dcbSDon Brace {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, 1438e616a5eSStephen M. Cameron {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, 1448e616a5eSStephen M. Cameron {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, 1458e616a5eSStephen M. Cameron {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, 1468e616a5eSStephen M. Cameron {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, 1478e616a5eSStephen M. Cameron {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, 148edd16368SStephen M. Cameron {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 149edd16368SStephen M. Cameron PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 150135ae6edSHannes Reinecke {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 151135ae6edSHannes Reinecke PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 152edd16368SStephen M. Cameron {0,} 153edd16368SStephen M. Cameron }; 154edd16368SStephen M. Cameron 155edd16368SStephen M. Cameron MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); 156edd16368SStephen M. Cameron 157edd16368SStephen M. Cameron /* board_id = Subsystem Device ID & Vendor ID 158edd16368SStephen M. Cameron * product = Marketing Name for the board 159edd16368SStephen M. Cameron * access = Address of the struct of function pointers 160edd16368SStephen M. Cameron */ 161edd16368SStephen M. Cameron static struct board_type products[] = { 162135ae6edSHannes Reinecke {0x40700E11, "Smart Array 5300", &SA5A_access}, 163135ae6edSHannes Reinecke {0x40800E11, "Smart Array 5i", &SA5B_access}, 164135ae6edSHannes Reinecke {0x40820E11, "Smart Array 532", &SA5B_access}, 165135ae6edSHannes Reinecke {0x40830E11, "Smart Array 5312", &SA5B_access}, 166135ae6edSHannes Reinecke {0x409A0E11, "Smart Array 641", &SA5A_access}, 167135ae6edSHannes Reinecke {0x409B0E11, "Smart Array 642", &SA5A_access}, 168135ae6edSHannes Reinecke {0x409C0E11, "Smart Array 6400", &SA5A_access}, 169135ae6edSHannes Reinecke {0x409D0E11, "Smart Array 6400 EM", &SA5A_access}, 170135ae6edSHannes Reinecke {0x40910E11, "Smart Array 6i", &SA5A_access}, 171135ae6edSHannes Reinecke {0x3225103C, "Smart Array P600", &SA5A_access}, 172135ae6edSHannes Reinecke {0x3223103C, "Smart Array P800", &SA5A_access}, 173135ae6edSHannes Reinecke {0x3234103C, "Smart Array P400", &SA5A_access}, 174135ae6edSHannes Reinecke {0x3235103C, "Smart Array P400i", &SA5A_access}, 175135ae6edSHannes Reinecke {0x3211103C, "Smart Array E200i", &SA5A_access}, 176135ae6edSHannes Reinecke {0x3212103C, "Smart Array E200", &SA5A_access}, 177135ae6edSHannes Reinecke {0x3213103C, "Smart Array E200i", &SA5A_access}, 178135ae6edSHannes Reinecke {0x3214103C, "Smart Array E200i", &SA5A_access}, 179135ae6edSHannes Reinecke {0x3215103C, "Smart Array E200i", &SA5A_access}, 180135ae6edSHannes Reinecke {0x3237103C, "Smart Array E500", &SA5A_access}, 181135ae6edSHannes Reinecke {0x323D103C, "Smart Array P700m", &SA5A_access}, 182edd16368SStephen M. Cameron {0x3241103C, "Smart Array P212", &SA5_access}, 183edd16368SStephen M. Cameron {0x3243103C, "Smart Array P410", &SA5_access}, 184edd16368SStephen M. Cameron {0x3245103C, "Smart Array P410i", &SA5_access}, 185edd16368SStephen M. Cameron {0x3247103C, "Smart Array P411", &SA5_access}, 186edd16368SStephen M. Cameron {0x3249103C, "Smart Array P812", &SA5_access}, 187163dbcd8SMike Miller {0x324A103C, "Smart Array P712m", &SA5_access}, 188163dbcd8SMike Miller {0x324B103C, "Smart Array P711m", &SA5_access}, 1897d2cce58SStephen M. Cameron {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ 190fe0c9610SMike Miller {0x3350103C, "Smart Array P222", &SA5_access}, 191fe0c9610SMike Miller {0x3351103C, "Smart Array P420", &SA5_access}, 192fe0c9610SMike Miller {0x3352103C, "Smart Array P421", &SA5_access}, 193fe0c9610SMike Miller {0x3353103C, "Smart Array P822", &SA5_access}, 194fe0c9610SMike Miller {0x3354103C, "Smart Array P420i", &SA5_access}, 195fe0c9610SMike Miller {0x3355103C, "Smart Array P220i", &SA5_access}, 196fe0c9610SMike Miller {0x3356103C, "Smart Array P721m", &SA5_access}, 1977f1974a7SDon Brace {0x1920103C, "Smart Array P430i", &SA5_access}, 1981fd6c8e3SMike Miller {0x1921103C, "Smart Array P830i", &SA5_access}, 1991fd6c8e3SMike Miller {0x1922103C, "Smart Array P430", &SA5_access}, 2001fd6c8e3SMike Miller {0x1923103C, "Smart Array P431", &SA5_access}, 2011fd6c8e3SMike Miller {0x1924103C, "Smart Array P830", &SA5_access}, 2027f1974a7SDon Brace {0x1925103C, "Smart Array P831", &SA5_access}, 2031fd6c8e3SMike Miller {0x1926103C, "Smart Array P731m", &SA5_access}, 2041fd6c8e3SMike Miller {0x1928103C, "Smart Array P230i", &SA5_access}, 2051fd6c8e3SMike Miller {0x1929103C, "Smart Array P530", &SA5_access}, 20627fb8137SDon Brace {0x21BD103C, "Smart Array P244br", &SA5_access}, 20727fb8137SDon Brace {0x21BE103C, "Smart Array P741m", &SA5_access}, 20827fb8137SDon Brace {0x21BF103C, "Smart HBA H240ar", &SA5_access}, 20927fb8137SDon Brace {0x21C0103C, "Smart Array P440ar", &SA5_access}, 210c8ae0ab1SDon Brace {0x21C1103C, "Smart Array P840ar", &SA5_access}, 21127fb8137SDon Brace {0x21C2103C, "Smart Array P440", &SA5_access}, 21227fb8137SDon Brace {0x21C3103C, "Smart Array P441", &SA5_access}, 21397b9f53dSMike Miller {0x21C4103C, "Smart Array", &SA5_access}, 21427fb8137SDon Brace {0x21C5103C, "Smart Array P841", &SA5_access}, 21527fb8137SDon Brace {0x21C6103C, "Smart HBA H244br", &SA5_access}, 21627fb8137SDon Brace {0x21C7103C, "Smart HBA H240", &SA5_access}, 21727fb8137SDon Brace {0x21C8103C, "Smart HBA H241", &SA5_access}, 21897b9f53dSMike Miller {0x21C9103C, "Smart Array", &SA5_access}, 21927fb8137SDon Brace {0x21CA103C, "Smart Array P246br", &SA5_access}, 22027fb8137SDon Brace {0x21CB103C, "Smart Array P840", &SA5_access}, 2213b7a45e5SJoe Handzik {0x21CC103C, "Smart Array", &SA5_access}, 2223b7a45e5SJoe Handzik {0x21CD103C, "Smart Array", &SA5_access}, 22327fb8137SDon Brace {0x21CE103C, "Smart HBA", &SA5_access}, 224fdfa4b6dSDon Brace {0x05809005, "SmartHBA-SA", &SA5_access}, 225cbb47dcbSDon Brace {0x05819005, "SmartHBA-SA 8i", &SA5_access}, 226cbb47dcbSDon Brace {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, 227cbb47dcbSDon Brace {0x05839005, "SmartHBA-SA 8e", &SA5_access}, 228cbb47dcbSDon Brace {0x05849005, "SmartHBA-SA 16i", &SA5_access}, 229cbb47dcbSDon Brace {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, 2308e616a5eSStephen M. Cameron {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, 2318e616a5eSStephen M. Cameron {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, 2328e616a5eSStephen M. Cameron {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, 2338e616a5eSStephen M. Cameron {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, 2348e616a5eSStephen M. Cameron {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, 235edd16368SStephen M. Cameron {0xFFFF103C, "Unknown Smart Array", &SA5_access}, 236edd16368SStephen M. Cameron }; 237edd16368SStephen M. Cameron 238d04e62b9SKevin Barnett static struct scsi_transport_template *hpsa_sas_transport_template; 239d04e62b9SKevin Barnett static int hpsa_add_sas_host(struct ctlr_info *h); 240d04e62b9SKevin Barnett static void hpsa_delete_sas_host(struct ctlr_info *h); 241d04e62b9SKevin Barnett static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 242d04e62b9SKevin Barnett struct hpsa_scsi_dev_t *device); 243d04e62b9SKevin Barnett static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); 244d04e62b9SKevin Barnett static struct hpsa_scsi_dev_t 245d04e62b9SKevin Barnett *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 246d04e62b9SKevin Barnett struct sas_rphy *rphy); 247d04e62b9SKevin Barnett 248a58e7e53SWebb Scales #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) 249a58e7e53SWebb Scales static const struct scsi_cmnd hpsa_cmd_busy; 250a58e7e53SWebb Scales #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) 251a58e7e53SWebb Scales static const struct scsi_cmnd hpsa_cmd_idle; 252edd16368SStephen M. Cameron static int number_of_controllers; 253edd16368SStephen M. Cameron 25410f66018SStephen M. Cameron static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); 25510f66018SStephen M. Cameron static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); 2566f4e626fSNathan Chancellor static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd, 2576f4e626fSNathan Chancellor void __user *arg); 25810100ffdSAl Viro static int hpsa_passthru_ioctl(struct ctlr_info *h, 25910100ffdSAl Viro IOCTL_Command_struct *iocommand); 26010100ffdSAl Viro static int hpsa_big_passthru_ioctl(struct ctlr_info *h, 26110100ffdSAl Viro BIG_IOCTL_Command_struct *ioc); 262edd16368SStephen M. Cameron 263edd16368SStephen M. Cameron #ifdef CONFIG_COMPAT 2646f4e626fSNathan Chancellor static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd, 26542a91641SDon Brace void __user *arg); 266edd16368SStephen M. Cameron #endif 267edd16368SStephen M. Cameron 268edd16368SStephen M. Cameron static void cmd_free(struct ctlr_info *h, struct CommandList *c); 269edd16368SStephen M. Cameron static struct CommandList *cmd_alloc(struct ctlr_info *h); 27073153fe5SWebb Scales static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); 27173153fe5SWebb Scales static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 27273153fe5SWebb Scales struct scsi_cmnd *scmd); 273a2dac136SStephen M. Cameron static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 274b7bb24ebSStephen M. Cameron void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 275edd16368SStephen M. Cameron int cmd_type); 2762c143342SRobert Elliott static void hpsa_free_cmd_pool(struct ctlr_info *h); 277b7bb24ebSStephen M. Cameron #define VPD_PAGE (1 << 8) 278b48d9804SDon Brace #define HPSA_SIMPLE_ERROR_BITS 0x03 279edd16368SStephen M. Cameron 280f281233dSJeff Garzik static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 281a08a8471SStephen M. Cameron static void hpsa_scan_start(struct Scsi_Host *); 282a08a8471SStephen M. Cameron static int hpsa_scan_finished(struct Scsi_Host *sh, 283a08a8471SStephen M. Cameron unsigned long elapsed_time); 2847c0a0229SDon Brace static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); 285edd16368SStephen M. Cameron 286edd16368SStephen M. Cameron static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); 287edd16368SStephen M. Cameron static int hpsa_slave_alloc(struct scsi_device *sdev); 28841ce4c35SStephen Cameron static int hpsa_slave_configure(struct scsi_device *sdev); 289edd16368SStephen M. Cameron static void hpsa_slave_destroy(struct scsi_device *sdev); 290edd16368SStephen M. Cameron 2918aa60681SDon Brace static void hpsa_update_scsi_devices(struct ctlr_info *h); 292edd16368SStephen M. Cameron static int check_for_unit_attention(struct ctlr_info *h, 293edd16368SStephen M. Cameron struct CommandList *c); 294edd16368SStephen M. Cameron static void check_ioctl_unit_attention(struct ctlr_info *h, 295edd16368SStephen M. Cameron struct CommandList *c); 296303932fdSDon Brace /* performant mode helper functions */ 297303932fdSDon Brace static void calc_bucket_map(int *bucket, int num_buckets, 2982b08b3e9SDon Brace int nsgs, int min_blocks, u32 *bucket_map); 299105a3dbcSRobert Elliott static void hpsa_free_performant_mode(struct ctlr_info *h); 300105a3dbcSRobert Elliott static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); 301254f796bSMatt Gates static inline u32 next_command(struct ctlr_info *h, u8 q); 3026f039790SGreg Kroah-Hartman static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 3036f039790SGreg Kroah-Hartman u32 *cfg_base_addr, u64 *cfg_base_addr_index, 3041df8552aSStephen M. Cameron u64 *cfg_offset); 3056f039790SGreg Kroah-Hartman static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 3061df8552aSStephen M. Cameron unsigned long *memory_bar); 307135ae6edSHannes Reinecke static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 308135ae6edSHannes Reinecke bool *legacy_board); 309bfd7546cSDon Brace static int wait_for_device_to_become_ready(struct ctlr_info *h, 310bfd7546cSDon Brace unsigned char lunaddr[], 311bfd7546cSDon Brace int reply_queue); 3126f039790SGreg Kroah-Hartman static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 3136f039790SGreg Kroah-Hartman int wait_for_ready); 31475167d2cSStephen M. Cameron static inline void finish_cmd(struct CommandList *c); 315c706a795SRobert Elliott static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); 316fe5389c8SStephen M. Cameron #define BOARD_NOT_READY 0 317fe5389c8SStephen M. Cameron #define BOARD_READY 1 31823100dd9SStephen M. Cameron static void hpsa_drain_accel_commands(struct ctlr_info *h); 31976438d08SStephen M. Cameron static void hpsa_flush_cache(struct ctlr_info *h); 320c349775eSScott Teel static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 321c349775eSScott Teel struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 32203383736SDon Brace u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); 323080ef1ccSDon Brace static void hpsa_command_resubmit_worker(struct work_struct *work); 32425163bd5SWebb Scales static u32 lockup_detected(struct ctlr_info *h); 32525163bd5SWebb Scales static int detect_controller_lockup(struct ctlr_info *h); 326c2adae44SScott Teel static void hpsa_disable_rld_caching(struct ctlr_info *h); 327d04e62b9SKevin Barnett static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 328d04e62b9SKevin Barnett struct ReportExtendedLUNdata *buf, int bufsize); 3298383278dSScott Teel static bool hpsa_vpd_page_supported(struct ctlr_info *h, 3308383278dSScott Teel unsigned char scsi3addr[], u8 page); 33134592254SScott Teel static int hpsa_luns_changed(struct ctlr_info *h); 332ba74fdc4SDon Brace static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 333ba74fdc4SDon Brace struct hpsa_scsi_dev_t *dev, 334ba74fdc4SDon Brace unsigned char *scsi3addr); 335edd16368SStephen M. Cameron 336edd16368SStephen M. Cameron static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) 337edd16368SStephen M. Cameron { 338edd16368SStephen M. Cameron unsigned long *priv = shost_priv(sdev->host); 339edd16368SStephen M. Cameron return (struct ctlr_info *) *priv; 340edd16368SStephen M. Cameron } 341edd16368SStephen M. Cameron 342a23513e8SStephen M. Cameron static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) 343a23513e8SStephen M. Cameron { 344a23513e8SStephen M. Cameron unsigned long *priv = shost_priv(sh); 345a23513e8SStephen M. Cameron return (struct ctlr_info *) *priv; 346a23513e8SStephen M. Cameron } 347a23513e8SStephen M. Cameron 348a58e7e53SWebb Scales static inline bool hpsa_is_cmd_idle(struct CommandList *c) 349a58e7e53SWebb Scales { 350a58e7e53SWebb Scales return c->scsi_cmd == SCSI_CMD_IDLE; 351a58e7e53SWebb Scales } 352a58e7e53SWebb Scales 3539437ac43SStephen Cameron /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ 3549437ac43SStephen Cameron static void decode_sense_data(const u8 *sense_data, int sense_data_len, 3559437ac43SStephen Cameron u8 *sense_key, u8 *asc, u8 *ascq) 3569437ac43SStephen Cameron { 3579437ac43SStephen Cameron struct scsi_sense_hdr sshdr; 3589437ac43SStephen Cameron bool rc; 3599437ac43SStephen Cameron 3609437ac43SStephen Cameron *sense_key = -1; 3619437ac43SStephen Cameron *asc = -1; 3629437ac43SStephen Cameron *ascq = -1; 3639437ac43SStephen Cameron 3649437ac43SStephen Cameron if (sense_data_len < 1) 3659437ac43SStephen Cameron return; 3669437ac43SStephen Cameron 3679437ac43SStephen Cameron rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); 3689437ac43SStephen Cameron if (rc) { 3699437ac43SStephen Cameron *sense_key = sshdr.sense_key; 3709437ac43SStephen Cameron *asc = sshdr.asc; 3719437ac43SStephen Cameron *ascq = sshdr.ascq; 3729437ac43SStephen Cameron } 3739437ac43SStephen Cameron } 3749437ac43SStephen Cameron 375edd16368SStephen M. Cameron static int check_for_unit_attention(struct ctlr_info *h, 376edd16368SStephen M. Cameron struct CommandList *c) 377edd16368SStephen M. Cameron { 3789437ac43SStephen Cameron u8 sense_key, asc, ascq; 3799437ac43SStephen Cameron int sense_len; 3809437ac43SStephen Cameron 3819437ac43SStephen Cameron if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 3829437ac43SStephen Cameron sense_len = sizeof(c->err_info->SenseInfo); 3839437ac43SStephen Cameron else 3849437ac43SStephen Cameron sense_len = c->err_info->SenseLen; 3859437ac43SStephen Cameron 3869437ac43SStephen Cameron decode_sense_data(c->err_info->SenseInfo, sense_len, 3879437ac43SStephen Cameron &sense_key, &asc, &ascq); 38881c27557SDon Brace if (sense_key != UNIT_ATTENTION || asc == 0xff) 389edd16368SStephen M. Cameron return 0; 390edd16368SStephen M. Cameron 3919437ac43SStephen Cameron switch (asc) { 392edd16368SStephen M. Cameron case STATE_CHANGED: 3939437ac43SStephen Cameron dev_warn(&h->pdev->dev, 3942946e82bSRobert Elliott "%s: a state change detected, command retried\n", 3952946e82bSRobert Elliott h->devname); 396edd16368SStephen M. Cameron break; 397edd16368SStephen M. Cameron case LUN_FAILED: 3987f73695aSStephen M. Cameron dev_warn(&h->pdev->dev, 3992946e82bSRobert Elliott "%s: LUN failure detected\n", h->devname); 400edd16368SStephen M. Cameron break; 401edd16368SStephen M. Cameron case REPORT_LUNS_CHANGED: 4027f73695aSStephen M. Cameron dev_warn(&h->pdev->dev, 4032946e82bSRobert Elliott "%s: report LUN data changed\n", h->devname); 404edd16368SStephen M. Cameron /* 4054f4eb9f1SScott Teel * Note: this REPORT_LUNS_CHANGED condition only occurs on the external 4064f4eb9f1SScott Teel * target (array) devices. 407edd16368SStephen M. Cameron */ 408edd16368SStephen M. Cameron break; 409edd16368SStephen M. Cameron case POWER_OR_RESET: 4102946e82bSRobert Elliott dev_warn(&h->pdev->dev, 4112946e82bSRobert Elliott "%s: a power on or device reset detected\n", 4122946e82bSRobert Elliott h->devname); 413edd16368SStephen M. Cameron break; 414edd16368SStephen M. Cameron case UNIT_ATTENTION_CLEARED: 4152946e82bSRobert Elliott dev_warn(&h->pdev->dev, 4162946e82bSRobert Elliott "%s: unit attention cleared by another initiator\n", 4172946e82bSRobert Elliott h->devname); 418edd16368SStephen M. Cameron break; 419edd16368SStephen M. Cameron default: 4202946e82bSRobert Elliott dev_warn(&h->pdev->dev, 4212946e82bSRobert Elliott "%s: unknown unit attention detected\n", 4222946e82bSRobert Elliott h->devname); 423edd16368SStephen M. Cameron break; 424edd16368SStephen M. Cameron } 425edd16368SStephen M. Cameron return 1; 426edd16368SStephen M. Cameron } 427edd16368SStephen M. Cameron 428852af20aSMatt Bondurant static int check_for_busy(struct ctlr_info *h, struct CommandList *c) 429852af20aSMatt Bondurant { 430852af20aSMatt Bondurant if (c->err_info->CommandStatus != CMD_TARGET_STATUS || 431852af20aSMatt Bondurant (c->err_info->ScsiStatus != SAM_STAT_BUSY && 432852af20aSMatt Bondurant c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) 433852af20aSMatt Bondurant return 0; 434852af20aSMatt Bondurant dev_warn(&h->pdev->dev, HPSA "device busy"); 435852af20aSMatt Bondurant return 1; 436852af20aSMatt Bondurant } 437852af20aSMatt Bondurant 438e985c58fSStephen Cameron static u32 lockup_detected(struct ctlr_info *h); 439e985c58fSStephen Cameron static ssize_t host_show_lockup_detected(struct device *dev, 440e985c58fSStephen Cameron struct device_attribute *attr, char *buf) 441e985c58fSStephen Cameron { 442e985c58fSStephen Cameron int ld; 443e985c58fSStephen Cameron struct ctlr_info *h; 444e985c58fSStephen Cameron struct Scsi_Host *shost = class_to_shost(dev); 445e985c58fSStephen Cameron 446e985c58fSStephen Cameron h = shost_to_hba(shost); 447e985c58fSStephen Cameron ld = lockup_detected(h); 448e985c58fSStephen Cameron 449e985c58fSStephen Cameron return sprintf(buf, "ld=%d\n", ld); 450e985c58fSStephen Cameron } 451e985c58fSStephen Cameron 452da0697bdSScott Teel static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, 453da0697bdSScott Teel struct device_attribute *attr, 454da0697bdSScott Teel const char *buf, size_t count) 455da0697bdSScott Teel { 456da0697bdSScott Teel int status, len; 457da0697bdSScott Teel struct ctlr_info *h; 458da0697bdSScott Teel struct Scsi_Host *shost = class_to_shost(dev); 459da0697bdSScott Teel char tmpbuf[10]; 460da0697bdSScott Teel 461da0697bdSScott Teel if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 462da0697bdSScott Teel return -EACCES; 463da0697bdSScott Teel len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 464da0697bdSScott Teel strncpy(tmpbuf, buf, len); 465da0697bdSScott Teel tmpbuf[len] = '\0'; 466da0697bdSScott Teel if (sscanf(tmpbuf, "%d", &status) != 1) 467da0697bdSScott Teel return -EINVAL; 468da0697bdSScott Teel h = shost_to_hba(shost); 469da0697bdSScott Teel h->acciopath_status = !!status; 470da0697bdSScott Teel dev_warn(&h->pdev->dev, 471da0697bdSScott Teel "hpsa: HP SSD Smart Path %s via sysfs update.\n", 472da0697bdSScott Teel h->acciopath_status ? "enabled" : "disabled"); 473da0697bdSScott Teel return count; 474da0697bdSScott Teel } 475da0697bdSScott Teel 4762ba8bfc8SStephen M. Cameron static ssize_t host_store_raid_offload_debug(struct device *dev, 4772ba8bfc8SStephen M. Cameron struct device_attribute *attr, 4782ba8bfc8SStephen M. Cameron const char *buf, size_t count) 4792ba8bfc8SStephen M. Cameron { 4802ba8bfc8SStephen M. Cameron int debug_level, len; 4812ba8bfc8SStephen M. Cameron struct ctlr_info *h; 4822ba8bfc8SStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 4832ba8bfc8SStephen M. Cameron char tmpbuf[10]; 4842ba8bfc8SStephen M. Cameron 4852ba8bfc8SStephen M. Cameron if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 4862ba8bfc8SStephen M. Cameron return -EACCES; 4872ba8bfc8SStephen M. Cameron len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 4882ba8bfc8SStephen M. Cameron strncpy(tmpbuf, buf, len); 4892ba8bfc8SStephen M. Cameron tmpbuf[len] = '\0'; 4902ba8bfc8SStephen M. Cameron if (sscanf(tmpbuf, "%d", &debug_level) != 1) 4912ba8bfc8SStephen M. Cameron return -EINVAL; 4922ba8bfc8SStephen M. Cameron if (debug_level < 0) 4932ba8bfc8SStephen M. Cameron debug_level = 0; 4942ba8bfc8SStephen M. Cameron h = shost_to_hba(shost); 4952ba8bfc8SStephen M. Cameron h->raid_offload_debug = debug_level; 4962ba8bfc8SStephen M. Cameron dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", 4972ba8bfc8SStephen M. Cameron h->raid_offload_debug); 4982ba8bfc8SStephen M. Cameron return count; 4992ba8bfc8SStephen M. Cameron } 5002ba8bfc8SStephen M. Cameron 501edd16368SStephen M. Cameron static ssize_t host_store_rescan(struct device *dev, 502edd16368SStephen M. Cameron struct device_attribute *attr, 503edd16368SStephen M. Cameron const char *buf, size_t count) 504edd16368SStephen M. Cameron { 505edd16368SStephen M. Cameron struct ctlr_info *h; 506edd16368SStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 507a23513e8SStephen M. Cameron h = shost_to_hba(shost); 50831468401SMike Miller hpsa_scan_start(h->scsi_host); 509edd16368SStephen M. Cameron return count; 510edd16368SStephen M. Cameron } 511edd16368SStephen M. Cameron 5123e16e83aSDon Brace static void hpsa_turn_off_ioaccel_for_device(struct hpsa_scsi_dev_t *device) 5133e16e83aSDon Brace { 5143e16e83aSDon Brace device->offload_enabled = 0; 5153e16e83aSDon Brace device->offload_to_be_enabled = 0; 5163e16e83aSDon Brace } 5173e16e83aSDon Brace 518d28ce020SStephen M. Cameron static ssize_t host_show_firmware_revision(struct device *dev, 519d28ce020SStephen M. Cameron struct device_attribute *attr, char *buf) 520d28ce020SStephen M. Cameron { 521d28ce020SStephen M. Cameron struct ctlr_info *h; 522d28ce020SStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 523d28ce020SStephen M. Cameron unsigned char *fwrev; 524d28ce020SStephen M. Cameron 525d28ce020SStephen M. Cameron h = shost_to_hba(shost); 526d28ce020SStephen M. Cameron if (!h->hba_inquiry_data) 527d28ce020SStephen M. Cameron return 0; 528d28ce020SStephen M. Cameron fwrev = &h->hba_inquiry_data[32]; 529d28ce020SStephen M. Cameron return snprintf(buf, 20, "%c%c%c%c\n", 530d28ce020SStephen M. Cameron fwrev[0], fwrev[1], fwrev[2], fwrev[3]); 531d28ce020SStephen M. Cameron } 532d28ce020SStephen M. Cameron 53394a13649SStephen M. Cameron static ssize_t host_show_commands_outstanding(struct device *dev, 53494a13649SStephen M. Cameron struct device_attribute *attr, char *buf) 53594a13649SStephen M. Cameron { 53694a13649SStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 53794a13649SStephen M. Cameron struct ctlr_info *h = shost_to_hba(shost); 53894a13649SStephen M. Cameron 5390cbf768eSStephen M. Cameron return snprintf(buf, 20, "%d\n", 5400cbf768eSStephen M. Cameron atomic_read(&h->commands_outstanding)); 54194a13649SStephen M. Cameron } 54294a13649SStephen M. Cameron 543745a7a25SStephen M. Cameron static ssize_t host_show_transport_mode(struct device *dev, 544745a7a25SStephen M. Cameron struct device_attribute *attr, char *buf) 545745a7a25SStephen M. Cameron { 546745a7a25SStephen M. Cameron struct ctlr_info *h; 547745a7a25SStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 548745a7a25SStephen M. Cameron 549745a7a25SStephen M. Cameron h = shost_to_hba(shost); 550745a7a25SStephen M. Cameron return snprintf(buf, 20, "%s\n", 551960a30e7SStephen M. Cameron h->transMethod & CFGTBL_Trans_Performant ? 552745a7a25SStephen M. Cameron "performant" : "simple"); 553745a7a25SStephen M. Cameron } 554745a7a25SStephen M. Cameron 555da0697bdSScott Teel static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, 556da0697bdSScott Teel struct device_attribute *attr, char *buf) 557da0697bdSScott Teel { 558da0697bdSScott Teel struct ctlr_info *h; 559da0697bdSScott Teel struct Scsi_Host *shost = class_to_shost(dev); 560da0697bdSScott Teel 561da0697bdSScott Teel h = shost_to_hba(shost); 562da0697bdSScott Teel return snprintf(buf, 30, "HP SSD Smart Path %s\n", 563da0697bdSScott Teel (h->acciopath_status == 1) ? "enabled" : "disabled"); 564da0697bdSScott Teel } 565da0697bdSScott Teel 56646380786SStephen M. Cameron /* List of controllers which cannot be hard reset on kexec with reset_devices */ 567941b1cdaSStephen M. Cameron static u32 unresettable_controller[] = { 568941b1cdaSStephen M. Cameron 0x324a103C, /* Smart Array P712m */ 569941b1cdaSStephen M. Cameron 0x324b103C, /* Smart Array P711m */ 570941b1cdaSStephen M. Cameron 0x3223103C, /* Smart Array P800 */ 571941b1cdaSStephen M. Cameron 0x3234103C, /* Smart Array P400 */ 572941b1cdaSStephen M. Cameron 0x3235103C, /* Smart Array P400i */ 573941b1cdaSStephen M. Cameron 0x3211103C, /* Smart Array E200i */ 574941b1cdaSStephen M. Cameron 0x3212103C, /* Smart Array E200 */ 575941b1cdaSStephen M. Cameron 0x3213103C, /* Smart Array E200i */ 576941b1cdaSStephen M. Cameron 0x3214103C, /* Smart Array E200i */ 577941b1cdaSStephen M. Cameron 0x3215103C, /* Smart Array E200i */ 578941b1cdaSStephen M. Cameron 0x3237103C, /* Smart Array E500 */ 579941b1cdaSStephen M. Cameron 0x323D103C, /* Smart Array P700m */ 5807af0abbcSTomas Henzl 0x40800E11, /* Smart Array 5i */ 581941b1cdaSStephen M. Cameron 0x409C0E11, /* Smart Array 6400 */ 582941b1cdaSStephen M. Cameron 0x409D0E11, /* Smart Array 6400 EM */ 5835a4f934eSTomas Henzl 0x40700E11, /* Smart Array 5300 */ 5845a4f934eSTomas Henzl 0x40820E11, /* Smart Array 532 */ 5855a4f934eSTomas Henzl 0x40830E11, /* Smart Array 5312 */ 5865a4f934eSTomas Henzl 0x409A0E11, /* Smart Array 641 */ 5875a4f934eSTomas Henzl 0x409B0E11, /* Smart Array 642 */ 5885a4f934eSTomas Henzl 0x40910E11, /* Smart Array 6i */ 589941b1cdaSStephen M. Cameron }; 590941b1cdaSStephen M. Cameron 59146380786SStephen M. Cameron /* List of controllers which cannot even be soft reset */ 59246380786SStephen M. Cameron static u32 soft_unresettable_controller[] = { 5937af0abbcSTomas Henzl 0x40800E11, /* Smart Array 5i */ 5945a4f934eSTomas Henzl 0x40700E11, /* Smart Array 5300 */ 5955a4f934eSTomas Henzl 0x40820E11, /* Smart Array 532 */ 5965a4f934eSTomas Henzl 0x40830E11, /* Smart Array 5312 */ 5975a4f934eSTomas Henzl 0x409A0E11, /* Smart Array 641 */ 5985a4f934eSTomas Henzl 0x409B0E11, /* Smart Array 642 */ 5995a4f934eSTomas Henzl 0x40910E11, /* Smart Array 6i */ 60046380786SStephen M. Cameron /* Exclude 640x boards. These are two pci devices in one slot 60146380786SStephen M. Cameron * which share a battery backed cache module. One controls the 60246380786SStephen M. Cameron * cache, the other accesses the cache through the one that controls 60346380786SStephen M. Cameron * it. If we reset the one controlling the cache, the other will 60446380786SStephen M. Cameron * likely not be happy. Just forbid resetting this conjoined mess. 60546380786SStephen M. Cameron * The 640x isn't really supported by hpsa anyway. 60646380786SStephen M. Cameron */ 60746380786SStephen M. Cameron 0x409C0E11, /* Smart Array 6400 */ 60846380786SStephen M. Cameron 0x409D0E11, /* Smart Array 6400 EM */ 60946380786SStephen M. Cameron }; 61046380786SStephen M. Cameron 6119b5c48c2SStephen Cameron static int board_id_in_array(u32 a[], int nelems, u32 board_id) 612941b1cdaSStephen M. Cameron { 613941b1cdaSStephen M. Cameron int i; 614941b1cdaSStephen M. Cameron 6159b5c48c2SStephen Cameron for (i = 0; i < nelems; i++) 6169b5c48c2SStephen Cameron if (a[i] == board_id) 617941b1cdaSStephen M. Cameron return 1; 6189b5c48c2SStephen Cameron return 0; 6199b5c48c2SStephen Cameron } 6209b5c48c2SStephen Cameron 6219b5c48c2SStephen Cameron static int ctlr_is_hard_resettable(u32 board_id) 6229b5c48c2SStephen Cameron { 6239b5c48c2SStephen Cameron return !board_id_in_array(unresettable_controller, 6249b5c48c2SStephen Cameron ARRAY_SIZE(unresettable_controller), board_id); 625941b1cdaSStephen M. Cameron } 626941b1cdaSStephen M. Cameron 62746380786SStephen M. Cameron static int ctlr_is_soft_resettable(u32 board_id) 62846380786SStephen M. Cameron { 6299b5c48c2SStephen Cameron return !board_id_in_array(soft_unresettable_controller, 6309b5c48c2SStephen Cameron ARRAY_SIZE(soft_unresettable_controller), board_id); 63146380786SStephen M. Cameron } 63246380786SStephen M. Cameron 63346380786SStephen M. Cameron static int ctlr_is_resettable(u32 board_id) 63446380786SStephen M. Cameron { 63546380786SStephen M. Cameron return ctlr_is_hard_resettable(board_id) || 63646380786SStephen M. Cameron ctlr_is_soft_resettable(board_id); 63746380786SStephen M. Cameron } 63846380786SStephen M. Cameron 639941b1cdaSStephen M. Cameron static ssize_t host_show_resettable(struct device *dev, 640941b1cdaSStephen M. Cameron struct device_attribute *attr, char *buf) 641941b1cdaSStephen M. Cameron { 642941b1cdaSStephen M. Cameron struct ctlr_info *h; 643941b1cdaSStephen M. Cameron struct Scsi_Host *shost = class_to_shost(dev); 644941b1cdaSStephen M. Cameron 645941b1cdaSStephen M. Cameron h = shost_to_hba(shost); 64646380786SStephen M. Cameron return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); 647941b1cdaSStephen M. Cameron } 648941b1cdaSStephen M. Cameron 649edd16368SStephen M. Cameron static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) 650edd16368SStephen M. Cameron { 651edd16368SStephen M. Cameron return (scsi3addr[3] & 0xC0) == 0x40; 652edd16368SStephen M. Cameron } 653edd16368SStephen M. Cameron 654f2ef0ce7SRobert Elliott static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", 6557c59a0d4SDon Brace "1(+0)ADM", "UNKNOWN", "PHYS DRV" 656edd16368SStephen M. Cameron }; 6576b80b18fSScott Teel #define HPSA_RAID_0 0 6586b80b18fSScott Teel #define HPSA_RAID_4 1 6596b80b18fSScott Teel #define HPSA_RAID_1 2 /* also used for RAID 10 */ 6606b80b18fSScott Teel #define HPSA_RAID_5 3 /* also used for RAID 50 */ 6616b80b18fSScott Teel #define HPSA_RAID_51 4 6626b80b18fSScott Teel #define HPSA_RAID_6 5 /* also used for RAID 60 */ 6636b80b18fSScott Teel #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 6647c59a0d4SDon Brace #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) 6657c59a0d4SDon Brace #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) 666edd16368SStephen M. Cameron 667f3f01730SKevin Barnett static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) 668f3f01730SKevin Barnett { 669f3f01730SKevin Barnett return !device->physical_device; 670f3f01730SKevin Barnett } 671edd16368SStephen M. Cameron 672edd16368SStephen M. Cameron static ssize_t raid_level_show(struct device *dev, 673edd16368SStephen M. Cameron struct device_attribute *attr, char *buf) 674edd16368SStephen M. Cameron { 675edd16368SStephen M. Cameron ssize_t l = 0; 67682a72c0aSStephen M. Cameron unsigned char rlevel; 677edd16368SStephen M. Cameron struct ctlr_info *h; 678edd16368SStephen M. Cameron struct scsi_device *sdev; 679edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *hdev; 680edd16368SStephen M. Cameron unsigned long flags; 681edd16368SStephen M. Cameron 682edd16368SStephen M. Cameron sdev = to_scsi_device(dev); 683edd16368SStephen M. Cameron h = sdev_to_hba(sdev); 684edd16368SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 685edd16368SStephen M. Cameron hdev = sdev->hostdata; 686edd16368SStephen M. Cameron if (!hdev) { 687edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 688edd16368SStephen M. Cameron return -ENODEV; 689edd16368SStephen M. Cameron } 690edd16368SStephen M. Cameron 691edd16368SStephen M. Cameron /* Is this even a logical drive? */ 692f3f01730SKevin Barnett if (!is_logical_device(hdev)) { 693edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 694edd16368SStephen M. Cameron l = snprintf(buf, PAGE_SIZE, "N/A\n"); 695edd16368SStephen M. Cameron return l; 696edd16368SStephen M. Cameron } 697edd16368SStephen M. Cameron 698edd16368SStephen M. Cameron rlevel = hdev->raid_level; 699edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 70082a72c0aSStephen M. Cameron if (rlevel > RAID_UNKNOWN) 701edd16368SStephen M. Cameron rlevel = RAID_UNKNOWN; 702edd16368SStephen M. Cameron l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); 703edd16368SStephen M. Cameron return l; 704edd16368SStephen M. Cameron } 705edd16368SStephen M. Cameron 706edd16368SStephen M. Cameron static ssize_t lunid_show(struct device *dev, 707edd16368SStephen M. Cameron struct device_attribute *attr, char *buf) 708edd16368SStephen M. Cameron { 709edd16368SStephen M. Cameron struct ctlr_info *h; 710edd16368SStephen M. Cameron struct scsi_device *sdev; 711edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *hdev; 712edd16368SStephen M. Cameron unsigned long flags; 713edd16368SStephen M. Cameron unsigned char lunid[8]; 714edd16368SStephen M. Cameron 715edd16368SStephen M. Cameron sdev = to_scsi_device(dev); 716edd16368SStephen M. Cameron h = sdev_to_hba(sdev); 717edd16368SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 718edd16368SStephen M. Cameron hdev = sdev->hostdata; 719edd16368SStephen M. Cameron if (!hdev) { 720edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 721edd16368SStephen M. Cameron return -ENODEV; 722edd16368SStephen M. Cameron } 723edd16368SStephen M. Cameron memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); 724edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 725609a70dfSRasmus Villemoes return snprintf(buf, 20, "0x%8phN\n", lunid); 726edd16368SStephen M. Cameron } 727edd16368SStephen M. Cameron 728edd16368SStephen M. Cameron static ssize_t unique_id_show(struct device *dev, 729edd16368SStephen M. Cameron struct device_attribute *attr, char *buf) 730edd16368SStephen M. Cameron { 731edd16368SStephen M. Cameron struct ctlr_info *h; 732edd16368SStephen M. Cameron struct scsi_device *sdev; 733edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *hdev; 734edd16368SStephen M. Cameron unsigned long flags; 735edd16368SStephen M. Cameron unsigned char sn[16]; 736edd16368SStephen M. Cameron 737edd16368SStephen M. Cameron sdev = to_scsi_device(dev); 738edd16368SStephen M. Cameron h = sdev_to_hba(sdev); 739edd16368SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 740edd16368SStephen M. Cameron hdev = sdev->hostdata; 741edd16368SStephen M. Cameron if (!hdev) { 742edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 743edd16368SStephen M. Cameron return -ENODEV; 744edd16368SStephen M. Cameron } 745edd16368SStephen M. Cameron memcpy(sn, hdev->device_id, sizeof(sn)); 746edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 747edd16368SStephen M. Cameron return snprintf(buf, 16 * 2 + 2, 748edd16368SStephen M. Cameron "%02X%02X%02X%02X%02X%02X%02X%02X" 749edd16368SStephen M. Cameron "%02X%02X%02X%02X%02X%02X%02X%02X\n", 750edd16368SStephen M. Cameron sn[0], sn[1], sn[2], sn[3], 751edd16368SStephen M. Cameron sn[4], sn[5], sn[6], sn[7], 752edd16368SStephen M. Cameron sn[8], sn[9], sn[10], sn[11], 753edd16368SStephen M. Cameron sn[12], sn[13], sn[14], sn[15]); 754edd16368SStephen M. Cameron } 755edd16368SStephen M. Cameron 756ded1be4aSJoseph T Handzik static ssize_t sas_address_show(struct device *dev, 757ded1be4aSJoseph T Handzik struct device_attribute *attr, char *buf) 758ded1be4aSJoseph T Handzik { 759ded1be4aSJoseph T Handzik struct ctlr_info *h; 760ded1be4aSJoseph T Handzik struct scsi_device *sdev; 761ded1be4aSJoseph T Handzik struct hpsa_scsi_dev_t *hdev; 762ded1be4aSJoseph T Handzik unsigned long flags; 763ded1be4aSJoseph T Handzik u64 sas_address; 764ded1be4aSJoseph T Handzik 765ded1be4aSJoseph T Handzik sdev = to_scsi_device(dev); 766ded1be4aSJoseph T Handzik h = sdev_to_hba(sdev); 767ded1be4aSJoseph T Handzik spin_lock_irqsave(&h->lock, flags); 768ded1be4aSJoseph T Handzik hdev = sdev->hostdata; 769ded1be4aSJoseph T Handzik if (!hdev || is_logical_device(hdev) || !hdev->expose_device) { 770ded1be4aSJoseph T Handzik spin_unlock_irqrestore(&h->lock, flags); 771ded1be4aSJoseph T Handzik return -ENODEV; 772ded1be4aSJoseph T Handzik } 773ded1be4aSJoseph T Handzik sas_address = hdev->sas_address; 774ded1be4aSJoseph T Handzik spin_unlock_irqrestore(&h->lock, flags); 775ded1be4aSJoseph T Handzik 776ded1be4aSJoseph T Handzik return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address); 777ded1be4aSJoseph T Handzik } 778ded1be4aSJoseph T Handzik 779c1988684SScott Teel static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, 780c1988684SScott Teel struct device_attribute *attr, char *buf) 781c1988684SScott Teel { 782c1988684SScott Teel struct ctlr_info *h; 783c1988684SScott Teel struct scsi_device *sdev; 784c1988684SScott Teel struct hpsa_scsi_dev_t *hdev; 785c1988684SScott Teel unsigned long flags; 786c1988684SScott Teel int offload_enabled; 787c1988684SScott Teel 788c1988684SScott Teel sdev = to_scsi_device(dev); 789c1988684SScott Teel h = sdev_to_hba(sdev); 790c1988684SScott Teel spin_lock_irqsave(&h->lock, flags); 791c1988684SScott Teel hdev = sdev->hostdata; 792c1988684SScott Teel if (!hdev) { 793c1988684SScott Teel spin_unlock_irqrestore(&h->lock, flags); 794c1988684SScott Teel return -ENODEV; 795c1988684SScott Teel } 796c1988684SScott Teel offload_enabled = hdev->offload_enabled; 797c1988684SScott Teel spin_unlock_irqrestore(&h->lock, flags); 798b2582a65SDon Brace 799b2582a65SDon Brace if (hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) 800c1988684SScott Teel return snprintf(buf, 20, "%d\n", offload_enabled); 801b2582a65SDon Brace else 802b2582a65SDon Brace return snprintf(buf, 40, "%s\n", 803b2582a65SDon Brace "Not applicable for a controller"); 804c1988684SScott Teel } 805c1988684SScott Teel 8068270b862SJoe Handzik #define MAX_PATHS 8 8078270b862SJoe Handzik static ssize_t path_info_show(struct device *dev, 8088270b862SJoe Handzik struct device_attribute *attr, char *buf) 8098270b862SJoe Handzik { 8108270b862SJoe Handzik struct ctlr_info *h; 8118270b862SJoe Handzik struct scsi_device *sdev; 8128270b862SJoe Handzik struct hpsa_scsi_dev_t *hdev; 8138270b862SJoe Handzik unsigned long flags; 8148270b862SJoe Handzik int i; 8158270b862SJoe Handzik int output_len = 0; 8168270b862SJoe Handzik u8 box; 8178270b862SJoe Handzik u8 bay; 8188270b862SJoe Handzik u8 path_map_index = 0; 8198270b862SJoe Handzik char *active; 8208270b862SJoe Handzik unsigned char phys_connector[2]; 8218270b862SJoe Handzik 8228270b862SJoe Handzik sdev = to_scsi_device(dev); 8238270b862SJoe Handzik h = sdev_to_hba(sdev); 8248270b862SJoe Handzik spin_lock_irqsave(&h->devlock, flags); 8258270b862SJoe Handzik hdev = sdev->hostdata; 8268270b862SJoe Handzik if (!hdev) { 8278270b862SJoe Handzik spin_unlock_irqrestore(&h->devlock, flags); 8288270b862SJoe Handzik return -ENODEV; 8298270b862SJoe Handzik } 8308270b862SJoe Handzik 8318270b862SJoe Handzik bay = hdev->bay; 8328270b862SJoe Handzik for (i = 0; i < MAX_PATHS; i++) { 8338270b862SJoe Handzik path_map_index = 1<<i; 8348270b862SJoe Handzik if (i == hdev->active_path_index) 8358270b862SJoe Handzik active = "Active"; 8368270b862SJoe Handzik else if (hdev->path_map & path_map_index) 8378270b862SJoe Handzik active = "Inactive"; 8388270b862SJoe Handzik else 8398270b862SJoe Handzik continue; 8408270b862SJoe Handzik 8411faf072cSRasmus Villemoes output_len += scnprintf(buf + output_len, 8421faf072cSRasmus Villemoes PAGE_SIZE - output_len, 8431faf072cSRasmus Villemoes "[%d:%d:%d:%d] %20.20s ", 8448270b862SJoe Handzik h->scsi_host->host_no, 8458270b862SJoe Handzik hdev->bus, hdev->target, hdev->lun, 8468270b862SJoe Handzik scsi_device_type(hdev->devtype)); 8478270b862SJoe Handzik 848cca8f13bSDon Brace if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) { 8492708f295SDon Brace output_len += scnprintf(buf + output_len, 8501faf072cSRasmus Villemoes PAGE_SIZE - output_len, 8511faf072cSRasmus Villemoes "%s\n", active); 8528270b862SJoe Handzik continue; 8538270b862SJoe Handzik } 8548270b862SJoe Handzik 8558270b862SJoe Handzik box = hdev->box[i]; 8568270b862SJoe Handzik memcpy(&phys_connector, &hdev->phys_connector[i], 8578270b862SJoe Handzik sizeof(phys_connector)); 8588270b862SJoe Handzik if (phys_connector[0] < '0') 8598270b862SJoe Handzik phys_connector[0] = '0'; 8608270b862SJoe Handzik if (phys_connector[1] < '0') 8618270b862SJoe Handzik phys_connector[1] = '0'; 8622708f295SDon Brace output_len += scnprintf(buf + output_len, 8631faf072cSRasmus Villemoes PAGE_SIZE - output_len, 8648270b862SJoe Handzik "PORT: %.2s ", 8658270b862SJoe Handzik phys_connector); 866af15ed36SDon Brace if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) && 867af15ed36SDon Brace hdev->expose_device) { 8688270b862SJoe Handzik if (box == 0 || box == 0xFF) { 8692708f295SDon Brace output_len += scnprintf(buf + output_len, 8701faf072cSRasmus Villemoes PAGE_SIZE - output_len, 8718270b862SJoe Handzik "BAY: %hhu %s\n", 8728270b862SJoe Handzik bay, active); 8738270b862SJoe Handzik } else { 8742708f295SDon Brace output_len += scnprintf(buf + output_len, 8751faf072cSRasmus Villemoes PAGE_SIZE - output_len, 8768270b862SJoe Handzik "BOX: %hhu BAY: %hhu %s\n", 8778270b862SJoe Handzik box, bay, active); 8788270b862SJoe Handzik } 8798270b862SJoe Handzik } else if (box != 0 && box != 0xFF) { 8802708f295SDon Brace output_len += scnprintf(buf + output_len, 8811faf072cSRasmus Villemoes PAGE_SIZE - output_len, "BOX: %hhu %s\n", 8828270b862SJoe Handzik box, active); 8838270b862SJoe Handzik } else 8842708f295SDon Brace output_len += scnprintf(buf + output_len, 8851faf072cSRasmus Villemoes PAGE_SIZE - output_len, "%s\n", active); 8868270b862SJoe Handzik } 8878270b862SJoe Handzik 8888270b862SJoe Handzik spin_unlock_irqrestore(&h->devlock, flags); 8891faf072cSRasmus Villemoes return output_len; 8908270b862SJoe Handzik } 8918270b862SJoe Handzik 89216961204SHannes Reinecke static ssize_t host_show_ctlr_num(struct device *dev, 89316961204SHannes Reinecke struct device_attribute *attr, char *buf) 89416961204SHannes Reinecke { 89516961204SHannes Reinecke struct ctlr_info *h; 89616961204SHannes Reinecke struct Scsi_Host *shost = class_to_shost(dev); 89716961204SHannes Reinecke 89816961204SHannes Reinecke h = shost_to_hba(shost); 89916961204SHannes Reinecke return snprintf(buf, 20, "%d\n", h->ctlr); 90016961204SHannes Reinecke } 90116961204SHannes Reinecke 902135ae6edSHannes Reinecke static ssize_t host_show_legacy_board(struct device *dev, 903135ae6edSHannes Reinecke struct device_attribute *attr, char *buf) 904135ae6edSHannes Reinecke { 905135ae6edSHannes Reinecke struct ctlr_info *h; 906135ae6edSHannes Reinecke struct Scsi_Host *shost = class_to_shost(dev); 907135ae6edSHannes Reinecke 908135ae6edSHannes Reinecke h = shost_to_hba(shost); 909135ae6edSHannes Reinecke return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0); 910135ae6edSHannes Reinecke } 911135ae6edSHannes Reinecke 912c828a892SJoe Perches static DEVICE_ATTR_RO(raid_level); 913c828a892SJoe Perches static DEVICE_ATTR_RO(lunid); 914c828a892SJoe Perches static DEVICE_ATTR_RO(unique_id); 9153f5eac3aSStephen M. Cameron static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); 916c828a892SJoe Perches static DEVICE_ATTR_RO(sas_address); 917c1988684SScott Teel static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, 918c1988684SScott Teel host_show_hp_ssd_smart_path_enabled, NULL); 919c828a892SJoe Perches static DEVICE_ATTR_RO(path_info); 920da0697bdSScott Teel static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, 921da0697bdSScott Teel host_show_hp_ssd_smart_path_status, 922da0697bdSScott Teel host_store_hp_ssd_smart_path_status); 9232ba8bfc8SStephen M. Cameron static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, 9242ba8bfc8SStephen M. Cameron host_store_raid_offload_debug); 9253f5eac3aSStephen M. Cameron static DEVICE_ATTR(firmware_revision, S_IRUGO, 9263f5eac3aSStephen M. Cameron host_show_firmware_revision, NULL); 9273f5eac3aSStephen M. Cameron static DEVICE_ATTR(commands_outstanding, S_IRUGO, 9283f5eac3aSStephen M. Cameron host_show_commands_outstanding, NULL); 9293f5eac3aSStephen M. Cameron static DEVICE_ATTR(transport_mode, S_IRUGO, 9303f5eac3aSStephen M. Cameron host_show_transport_mode, NULL); 931941b1cdaSStephen M. Cameron static DEVICE_ATTR(resettable, S_IRUGO, 932941b1cdaSStephen M. Cameron host_show_resettable, NULL); 933e985c58fSStephen Cameron static DEVICE_ATTR(lockup_detected, S_IRUGO, 934e985c58fSStephen Cameron host_show_lockup_detected, NULL); 93516961204SHannes Reinecke static DEVICE_ATTR(ctlr_num, S_IRUGO, 93616961204SHannes Reinecke host_show_ctlr_num, NULL); 937135ae6edSHannes Reinecke static DEVICE_ATTR(legacy_board, S_IRUGO, 938135ae6edSHannes Reinecke host_show_legacy_board, NULL); 9393f5eac3aSStephen M. Cameron 9403f5eac3aSStephen M. Cameron static struct device_attribute *hpsa_sdev_attrs[] = { 9413f5eac3aSStephen M. Cameron &dev_attr_raid_level, 9423f5eac3aSStephen M. Cameron &dev_attr_lunid, 9433f5eac3aSStephen M. Cameron &dev_attr_unique_id, 944c1988684SScott Teel &dev_attr_hp_ssd_smart_path_enabled, 9458270b862SJoe Handzik &dev_attr_path_info, 946ded1be4aSJoseph T Handzik &dev_attr_sas_address, 9473f5eac3aSStephen M. Cameron NULL, 9483f5eac3aSStephen M. Cameron }; 9493f5eac3aSStephen M. Cameron 9503f5eac3aSStephen M. Cameron static struct device_attribute *hpsa_shost_attrs[] = { 9513f5eac3aSStephen M. Cameron &dev_attr_rescan, 9523f5eac3aSStephen M. Cameron &dev_attr_firmware_revision, 9533f5eac3aSStephen M. Cameron &dev_attr_commands_outstanding, 9543f5eac3aSStephen M. Cameron &dev_attr_transport_mode, 955941b1cdaSStephen M. Cameron &dev_attr_resettable, 956da0697bdSScott Teel &dev_attr_hp_ssd_smart_path_status, 9572ba8bfc8SStephen M. Cameron &dev_attr_raid_offload_debug, 958fb53c439STomas Henzl &dev_attr_lockup_detected, 95916961204SHannes Reinecke &dev_attr_ctlr_num, 960135ae6edSHannes Reinecke &dev_attr_legacy_board, 9613f5eac3aSStephen M. Cameron NULL, 9623f5eac3aSStephen M. Cameron }; 9633f5eac3aSStephen M. Cameron 96408ec46f6SDon Brace #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\ 96508ec46f6SDon Brace HPSA_MAX_CONCURRENT_PASSTHRUS) 96641ce4c35SStephen Cameron 9673f5eac3aSStephen M. Cameron static struct scsi_host_template hpsa_driver_template = { 9683f5eac3aSStephen M. Cameron .module = THIS_MODULE, 969f79cfec6SStephen M. Cameron .name = HPSA, 970f79cfec6SStephen M. Cameron .proc_name = HPSA, 9713f5eac3aSStephen M. Cameron .queuecommand = hpsa_scsi_queue_command, 9723f5eac3aSStephen M. Cameron .scan_start = hpsa_scan_start, 9733f5eac3aSStephen M. Cameron .scan_finished = hpsa_scan_finished, 9747c0a0229SDon Brace .change_queue_depth = hpsa_change_queue_depth, 9753f5eac3aSStephen M. Cameron .this_id = -1, 9763f5eac3aSStephen M. Cameron .eh_device_reset_handler = hpsa_eh_device_reset_handler, 9773f5eac3aSStephen M. Cameron .ioctl = hpsa_ioctl, 9783f5eac3aSStephen M. Cameron .slave_alloc = hpsa_slave_alloc, 97941ce4c35SStephen Cameron .slave_configure = hpsa_slave_configure, 9803f5eac3aSStephen M. Cameron .slave_destroy = hpsa_slave_destroy, 9813f5eac3aSStephen M. Cameron #ifdef CONFIG_COMPAT 9823f5eac3aSStephen M. Cameron .compat_ioctl = hpsa_compat_ioctl, 9833f5eac3aSStephen M. Cameron #endif 9843f5eac3aSStephen M. Cameron .sdev_attrs = hpsa_sdev_attrs, 9853f5eac3aSStephen M. Cameron .shost_attrs = hpsa_shost_attrs, 986eb53a3eaSMartin Wilck .max_sectors = 2048, 98754b2b50cSMartin K. Petersen .no_write_same = 1, 9883f5eac3aSStephen M. Cameron }; 9893f5eac3aSStephen M. Cameron 990254f796bSMatt Gates static inline u32 next_command(struct ctlr_info *h, u8 q) 9913f5eac3aSStephen M. Cameron { 9923f5eac3aSStephen M. Cameron u32 a; 993072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 9943f5eac3aSStephen M. Cameron 995e1f7de0cSMatt Gates if (h->transMethod & CFGTBL_Trans_io_accel1) 996e1f7de0cSMatt Gates return h->access.command_completed(h, q); 997e1f7de0cSMatt Gates 9983f5eac3aSStephen M. Cameron if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) 999254f796bSMatt Gates return h->access.command_completed(h, q); 10003f5eac3aSStephen M. Cameron 1001254f796bSMatt Gates if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { 1002254f796bSMatt Gates a = rq->head[rq->current_entry]; 1003254f796bSMatt Gates rq->current_entry++; 10040cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 10053f5eac3aSStephen M. Cameron } else { 10063f5eac3aSStephen M. Cameron a = FIFO_EMPTY; 10073f5eac3aSStephen M. Cameron } 10083f5eac3aSStephen M. Cameron /* Check for wraparound */ 1009254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 1010254f796bSMatt Gates rq->current_entry = 0; 1011254f796bSMatt Gates rq->wraparound ^= 1; 10123f5eac3aSStephen M. Cameron } 10133f5eac3aSStephen M. Cameron return a; 10143f5eac3aSStephen M. Cameron } 10153f5eac3aSStephen M. Cameron 1016c349775eSScott Teel /* 1017c349775eSScott Teel * There are some special bits in the bus address of the 1018c349775eSScott Teel * command that we have to set for the controller to know 1019c349775eSScott Teel * how to process the command: 1020c349775eSScott Teel * 1021c349775eSScott Teel * Normal performant mode: 1022c349775eSScott Teel * bit 0: 1 means performant mode, 0 means simple mode. 1023c349775eSScott Teel * bits 1-3 = block fetch table entry 1024c349775eSScott Teel * bits 4-6 = command type (== 0) 1025c349775eSScott Teel * 1026c349775eSScott Teel * ioaccel1 mode: 1027c349775eSScott Teel * bit 0 = "performant mode" bit. 1028c349775eSScott Teel * bits 1-3 = block fetch table entry 1029c349775eSScott Teel * bits 4-6 = command type (== 110) 1030c349775eSScott Teel * (command type is needed because ioaccel1 mode 1031c349775eSScott Teel * commands are submitted through the same register as normal 1032c349775eSScott Teel * mode commands, so this is how the controller knows whether 1033c349775eSScott Teel * the command is normal mode or ioaccel1 mode.) 1034c349775eSScott Teel * 1035c349775eSScott Teel * ioaccel2 mode: 1036c349775eSScott Teel * bit 0 = "performant mode" bit. 1037c349775eSScott Teel * bits 1-4 = block fetch table entry (note extra bit) 1038c349775eSScott Teel * bits 4-6 = not needed, because ioaccel2 mode has 1039c349775eSScott Teel * a separate special register for submitting commands. 1040c349775eSScott Teel */ 1041c349775eSScott Teel 104225163bd5SWebb Scales /* 104325163bd5SWebb Scales * set_performant_mode: Modify the tag for cciss performant 10443f5eac3aSStephen M. Cameron * set bit 0 for pull model, bits 3-1 for block fetch 10453f5eac3aSStephen M. Cameron * register number 10463f5eac3aSStephen M. Cameron */ 104725163bd5SWebb Scales #define DEFAULT_REPLY_QUEUE (-1) 104825163bd5SWebb Scales static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, 104925163bd5SWebb Scales int reply_queue) 10503f5eac3aSStephen M. Cameron { 1051254f796bSMatt Gates if (likely(h->transMethod & CFGTBL_Trans_Performant)) { 10523f5eac3aSStephen M. Cameron c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); 1053bc2bb154SChristoph Hellwig if (unlikely(!h->msix_vectors)) 105425163bd5SWebb Scales return; 10558b834bffSMing Lei c->Header.ReplyQueue = reply_queue; 1056254f796bSMatt Gates } 10573f5eac3aSStephen M. Cameron } 10583f5eac3aSStephen M. Cameron 1059c349775eSScott Teel static void set_ioaccel1_performant_mode(struct ctlr_info *h, 106025163bd5SWebb Scales struct CommandList *c, 106125163bd5SWebb Scales int reply_queue) 1062c349775eSScott Teel { 1063c349775eSScott Teel struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 1064c349775eSScott Teel 106525163bd5SWebb Scales /* 106625163bd5SWebb Scales * Tell the controller to post the reply to the queue for this 1067c349775eSScott Teel * processor. This seems to give the best I/O throughput. 1068c349775eSScott Teel */ 10698b834bffSMing Lei cp->ReplyQueue = reply_queue; 107025163bd5SWebb Scales /* 107125163bd5SWebb Scales * Set the bits in the address sent down to include: 1072c349775eSScott Teel * - performant mode bit (bit 0) 1073c349775eSScott Teel * - pull count (bits 1-3) 1074c349775eSScott Teel * - command type (bits 4-6) 1075c349775eSScott Teel */ 1076c349775eSScott Teel c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | 1077c349775eSScott Teel IOACCEL1_BUSADDR_CMDTYPE; 1078c349775eSScott Teel } 1079c349775eSScott Teel 10808be986ccSStephen Cameron static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, 10818be986ccSStephen Cameron struct CommandList *c, 10828be986ccSStephen Cameron int reply_queue) 10838be986ccSStephen Cameron { 10848be986ccSStephen Cameron struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) 10858be986ccSStephen Cameron &h->ioaccel2_cmd_pool[c->cmdindex]; 10868be986ccSStephen Cameron 10878be986ccSStephen Cameron /* Tell the controller to post the reply to the queue for this 10888be986ccSStephen Cameron * processor. This seems to give the best I/O throughput. 10898be986ccSStephen Cameron */ 10908b834bffSMing Lei cp->reply_queue = reply_queue; 10918be986ccSStephen Cameron /* Set the bits in the address sent down to include: 10928be986ccSStephen Cameron * - performant mode bit not used in ioaccel mode 2 10938be986ccSStephen Cameron * - pull count (bits 0-3) 10948be986ccSStephen Cameron * - command type isn't needed for ioaccel2 10958be986ccSStephen Cameron */ 10968be986ccSStephen Cameron c->busaddr |= h->ioaccel2_blockFetchTable[0]; 10978be986ccSStephen Cameron } 10988be986ccSStephen Cameron 1099c349775eSScott Teel static void set_ioaccel2_performant_mode(struct ctlr_info *h, 110025163bd5SWebb Scales struct CommandList *c, 110125163bd5SWebb Scales int reply_queue) 1102c349775eSScott Teel { 1103c349775eSScott Teel struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 1104c349775eSScott Teel 110525163bd5SWebb Scales /* 110625163bd5SWebb Scales * Tell the controller to post the reply to the queue for this 1107c349775eSScott Teel * processor. This seems to give the best I/O throughput. 1108c349775eSScott Teel */ 11098b834bffSMing Lei cp->reply_queue = reply_queue; 111025163bd5SWebb Scales /* 111125163bd5SWebb Scales * Set the bits in the address sent down to include: 1112c349775eSScott Teel * - performant mode bit not used in ioaccel mode 2 1113c349775eSScott Teel * - pull count (bits 0-3) 1114c349775eSScott Teel * - command type isn't needed for ioaccel2 1115c349775eSScott Teel */ 1116c349775eSScott Teel c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); 1117c349775eSScott Teel } 1118c349775eSScott Teel 1119e85c5974SStephen M. Cameron static int is_firmware_flash_cmd(u8 *cdb) 1120e85c5974SStephen M. Cameron { 1121e85c5974SStephen M. Cameron return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; 1122e85c5974SStephen M. Cameron } 1123e85c5974SStephen M. Cameron 1124e85c5974SStephen M. Cameron /* 1125e85c5974SStephen M. Cameron * During firmware flash, the heartbeat register may not update as frequently 1126e85c5974SStephen M. Cameron * as it should. So we dial down lockup detection during firmware flash. and 1127e85c5974SStephen M. Cameron * dial it back up when firmware flash completes. 1128e85c5974SStephen M. Cameron */ 1129e85c5974SStephen M. Cameron #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) 1130e85c5974SStephen M. Cameron #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) 11313d38f00cSScott Teel #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ) 1132e85c5974SStephen M. Cameron static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, 1133e85c5974SStephen M. Cameron struct CommandList *c) 1134e85c5974SStephen M. Cameron { 1135e85c5974SStephen M. Cameron if (!is_firmware_flash_cmd(c->Request.CDB)) 1136e85c5974SStephen M. Cameron return; 1137e85c5974SStephen M. Cameron atomic_inc(&h->firmware_flash_in_progress); 1138e85c5974SStephen M. Cameron h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; 1139e85c5974SStephen M. Cameron } 1140e85c5974SStephen M. Cameron 1141e85c5974SStephen M. Cameron static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, 1142e85c5974SStephen M. Cameron struct CommandList *c) 1143e85c5974SStephen M. Cameron { 1144e85c5974SStephen M. Cameron if (is_firmware_flash_cmd(c->Request.CDB) && 1145e85c5974SStephen M. Cameron atomic_dec_and_test(&h->firmware_flash_in_progress)) 1146e85c5974SStephen M. Cameron h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 1147e85c5974SStephen M. Cameron } 1148e85c5974SStephen M. Cameron 114925163bd5SWebb Scales static void __enqueue_cmd_and_start_io(struct ctlr_info *h, 115025163bd5SWebb Scales struct CommandList *c, int reply_queue) 11513f5eac3aSStephen M. Cameron { 1152c05e8866SStephen Cameron dial_down_lockup_detection_during_fw_flash(h, c); 1153c05e8866SStephen Cameron atomic_inc(&h->commands_outstanding); 1154c5dfd106SDon Brace if (c->device) 1155c5dfd106SDon Brace atomic_inc(&c->device->commands_outstanding); 11568b834bffSMing Lei 11578b834bffSMing Lei reply_queue = h->reply_map[raw_smp_processor_id()]; 1158c349775eSScott Teel switch (c->cmd_type) { 1159c349775eSScott Teel case CMD_IOACCEL1: 116025163bd5SWebb Scales set_ioaccel1_performant_mode(h, c, reply_queue); 1161c05e8866SStephen Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 1162c349775eSScott Teel break; 1163c349775eSScott Teel case CMD_IOACCEL2: 116425163bd5SWebb Scales set_ioaccel2_performant_mode(h, c, reply_queue); 1165c05e8866SStephen Cameron writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 1166c349775eSScott Teel break; 11678be986ccSStephen Cameron case IOACCEL2_TMF: 11688be986ccSStephen Cameron set_ioaccel2_tmf_performant_mode(h, c, reply_queue); 11698be986ccSStephen Cameron writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 11708be986ccSStephen Cameron break; 1171c349775eSScott Teel default: 117225163bd5SWebb Scales set_performant_mode(h, c, reply_queue); 1173f2405db8SDon Brace h->access.submit_command(h, c); 11743f5eac3aSStephen M. Cameron } 1175c05e8866SStephen Cameron } 11763f5eac3aSStephen M. Cameron 1177a58e7e53SWebb Scales static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) 117825163bd5SWebb Scales { 117925163bd5SWebb Scales __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); 118025163bd5SWebb Scales } 118125163bd5SWebb Scales 11823f5eac3aSStephen M. Cameron static inline int is_hba_lunid(unsigned char scsi3addr[]) 11833f5eac3aSStephen M. Cameron { 11843f5eac3aSStephen M. Cameron return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; 11853f5eac3aSStephen M. Cameron } 11863f5eac3aSStephen M. Cameron 11873f5eac3aSStephen M. Cameron static inline int is_scsi_rev_5(struct ctlr_info *h) 11883f5eac3aSStephen M. Cameron { 11893f5eac3aSStephen M. Cameron if (!h->hba_inquiry_data) 11903f5eac3aSStephen M. Cameron return 0; 11913f5eac3aSStephen M. Cameron if ((h->hba_inquiry_data[2] & 0x07) == 5) 11923f5eac3aSStephen M. Cameron return 1; 11933f5eac3aSStephen M. Cameron return 0; 11943f5eac3aSStephen M. Cameron } 11953f5eac3aSStephen M. Cameron 1196edd16368SStephen M. Cameron static int hpsa_find_target_lun(struct ctlr_info *h, 1197edd16368SStephen M. Cameron unsigned char scsi3addr[], int bus, int *target, int *lun) 1198edd16368SStephen M. Cameron { 1199edd16368SStephen M. Cameron /* finds an unused bus, target, lun for a new physical device 1200edd16368SStephen M. Cameron * assumes h->devlock is held 1201edd16368SStephen M. Cameron */ 1202edd16368SStephen M. Cameron int i, found = 0; 1203cfe5badcSScott Teel DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); 1204edd16368SStephen M. Cameron 1205263d9401SAkinobu Mita bitmap_zero(lun_taken, HPSA_MAX_DEVICES); 1206edd16368SStephen M. Cameron 1207edd16368SStephen M. Cameron for (i = 0; i < h->ndevices; i++) { 1208edd16368SStephen M. Cameron if (h->dev[i]->bus == bus && h->dev[i]->target != -1) 1209263d9401SAkinobu Mita __set_bit(h->dev[i]->target, lun_taken); 1210edd16368SStephen M. Cameron } 1211edd16368SStephen M. Cameron 1212263d9401SAkinobu Mita i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); 1213263d9401SAkinobu Mita if (i < HPSA_MAX_DEVICES) { 1214edd16368SStephen M. Cameron /* *bus = 1; */ 1215edd16368SStephen M. Cameron *target = i; 1216edd16368SStephen M. Cameron *lun = 0; 1217edd16368SStephen M. Cameron found = 1; 1218edd16368SStephen M. Cameron } 1219edd16368SStephen M. Cameron return !found; 1220edd16368SStephen M. Cameron } 1221edd16368SStephen M. Cameron 12221d33d85dSDon Brace static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, 12230d96ef5fSWebb Scales struct hpsa_scsi_dev_t *dev, char *description) 12240d96ef5fSWebb Scales { 12257c59a0d4SDon Brace #define LABEL_SIZE 25 12267c59a0d4SDon Brace char label[LABEL_SIZE]; 12277c59a0d4SDon Brace 12289975ec9dSDon Brace if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) 12299975ec9dSDon Brace return; 12309975ec9dSDon Brace 12317c59a0d4SDon Brace switch (dev->devtype) { 12327c59a0d4SDon Brace case TYPE_RAID: 12337c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "controller"); 12347c59a0d4SDon Brace break; 12357c59a0d4SDon Brace case TYPE_ENCLOSURE: 12367c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "enclosure"); 12377c59a0d4SDon Brace break; 12387c59a0d4SDon Brace case TYPE_DISK: 1239af15ed36SDon Brace case TYPE_ZBC: 12407c59a0d4SDon Brace if (dev->external) 12417c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "external"); 12427c59a0d4SDon Brace else if (!is_logical_dev_addr_mode(dev->scsi3addr)) 12437c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "%s", 12447c59a0d4SDon Brace raid_label[PHYSICAL_DRIVE]); 12457c59a0d4SDon Brace else 12467c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "RAID-%s", 12477c59a0d4SDon Brace dev->raid_level > RAID_UNKNOWN ? "?" : 12487c59a0d4SDon Brace raid_label[dev->raid_level]); 12497c59a0d4SDon Brace break; 12507c59a0d4SDon Brace case TYPE_ROM: 12517c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "rom"); 12527c59a0d4SDon Brace break; 12537c59a0d4SDon Brace case TYPE_TAPE: 12547c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "tape"); 12557c59a0d4SDon Brace break; 12567c59a0d4SDon Brace case TYPE_MEDIUM_CHANGER: 12577c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "changer"); 12587c59a0d4SDon Brace break; 12597c59a0d4SDon Brace default: 12607c59a0d4SDon Brace snprintf(label, LABEL_SIZE, "UNKNOWN"); 12617c59a0d4SDon Brace break; 12627c59a0d4SDon Brace } 12637c59a0d4SDon Brace 12640d96ef5fSWebb Scales dev_printk(level, &h->pdev->dev, 12657c59a0d4SDon Brace "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", 12660d96ef5fSWebb Scales h->scsi_host->host_no, dev->bus, dev->target, dev->lun, 12670d96ef5fSWebb Scales description, 12680d96ef5fSWebb Scales scsi_device_type(dev->devtype), 12690d96ef5fSWebb Scales dev->vendor, 12700d96ef5fSWebb Scales dev->model, 12717c59a0d4SDon Brace label, 12720d96ef5fSWebb Scales dev->offload_config ? '+' : '-', 1273b2582a65SDon Brace dev->offload_to_be_enabled ? '+' : '-', 12742a168208SKevin Barnett dev->expose_device); 12750d96ef5fSWebb Scales } 12760d96ef5fSWebb Scales 1277edd16368SStephen M. Cameron /* Add an entry into h->dev[] array. */ 12788aa60681SDon Brace static int hpsa_scsi_add_entry(struct ctlr_info *h, 1279edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *device, 1280edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *added[], int *nadded) 1281edd16368SStephen M. Cameron { 1282edd16368SStephen M. Cameron /* assumes h->devlock is held */ 1283edd16368SStephen M. Cameron int n = h->ndevices; 1284edd16368SStephen M. Cameron int i; 1285edd16368SStephen M. Cameron unsigned char addr1[8], addr2[8]; 1286edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *sd; 1287edd16368SStephen M. Cameron 1288cfe5badcSScott Teel if (n >= HPSA_MAX_DEVICES) { 1289edd16368SStephen M. Cameron dev_err(&h->pdev->dev, "too many devices, some will be " 1290edd16368SStephen M. Cameron "inaccessible.\n"); 1291edd16368SStephen M. Cameron return -1; 1292edd16368SStephen M. Cameron } 1293edd16368SStephen M. Cameron 1294edd16368SStephen M. Cameron /* physical devices do not have lun or target assigned until now. */ 1295edd16368SStephen M. Cameron if (device->lun != -1) 1296edd16368SStephen M. Cameron /* Logical device, lun is already assigned. */ 1297edd16368SStephen M. Cameron goto lun_assigned; 1298edd16368SStephen M. Cameron 1299edd16368SStephen M. Cameron /* If this device a non-zero lun of a multi-lun device 1300edd16368SStephen M. Cameron * byte 4 of the 8-byte LUN addr will contain the logical 13012b08b3e9SDon Brace * unit no, zero otherwise. 1302edd16368SStephen M. Cameron */ 1303edd16368SStephen M. Cameron if (device->scsi3addr[4] == 0) { 1304edd16368SStephen M. Cameron /* This is not a non-zero lun of a multi-lun device */ 1305edd16368SStephen M. Cameron if (hpsa_find_target_lun(h, device->scsi3addr, 1306edd16368SStephen M. Cameron device->bus, &device->target, &device->lun) != 0) 1307edd16368SStephen M. Cameron return -1; 1308edd16368SStephen M. Cameron goto lun_assigned; 1309edd16368SStephen M. Cameron } 1310edd16368SStephen M. Cameron 1311edd16368SStephen M. Cameron /* This is a non-zero lun of a multi-lun device. 1312edd16368SStephen M. Cameron * Search through our list and find the device which 13139a4178b7Sshane.seymour * has the same 8 byte LUN address, excepting byte 4 and 5. 1314edd16368SStephen M. Cameron * Assign the same bus and target for this new LUN. 1315edd16368SStephen M. Cameron * Use the logical unit number from the firmware. 1316edd16368SStephen M. Cameron */ 1317edd16368SStephen M. Cameron memcpy(addr1, device->scsi3addr, 8); 1318edd16368SStephen M. Cameron addr1[4] = 0; 13199a4178b7Sshane.seymour addr1[5] = 0; 1320edd16368SStephen M. Cameron for (i = 0; i < n; i++) { 1321edd16368SStephen M. Cameron sd = h->dev[i]; 1322edd16368SStephen M. Cameron memcpy(addr2, sd->scsi3addr, 8); 1323edd16368SStephen M. Cameron addr2[4] = 0; 13249a4178b7Sshane.seymour addr2[5] = 0; 13259a4178b7Sshane.seymour /* differ only in byte 4 and 5? */ 1326edd16368SStephen M. Cameron if (memcmp(addr1, addr2, 8) == 0) { 1327edd16368SStephen M. Cameron device->bus = sd->bus; 1328edd16368SStephen M. Cameron device->target = sd->target; 1329edd16368SStephen M. Cameron device->lun = device->scsi3addr[4]; 1330edd16368SStephen M. Cameron break; 1331edd16368SStephen M. Cameron } 1332edd16368SStephen M. Cameron } 1333edd16368SStephen M. Cameron if (device->lun == -1) { 1334edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "physical device with no LUN=0," 1335edd16368SStephen M. Cameron " suspect firmware bug or unsupported hardware " 1336edd16368SStephen M. Cameron "configuration.\n"); 1337edd16368SStephen M. Cameron return -1; 1338edd16368SStephen M. Cameron } 1339edd16368SStephen M. Cameron 1340edd16368SStephen M. Cameron lun_assigned: 1341edd16368SStephen M. Cameron 1342edd16368SStephen M. Cameron h->dev[n] = device; 1343edd16368SStephen M. Cameron h->ndevices++; 1344edd16368SStephen M. Cameron added[*nadded] = device; 1345edd16368SStephen M. Cameron (*nadded)++; 13460d96ef5fSWebb Scales hpsa_show_dev_msg(KERN_INFO, h, device, 13472a168208SKevin Barnett device->expose_device ? "added" : "masked"); 1348edd16368SStephen M. Cameron return 0; 1349edd16368SStephen M. Cameron } 1350edd16368SStephen M. Cameron 1351b2582a65SDon Brace /* 1352b2582a65SDon Brace * Called during a scan operation. 1353b2582a65SDon Brace * 1354b2582a65SDon Brace * Update an entry in h->dev[] array. 1355b2582a65SDon Brace */ 13568aa60681SDon Brace static void hpsa_scsi_update_entry(struct ctlr_info *h, 1357bd9244f7SScott Teel int entry, struct hpsa_scsi_dev_t *new_entry) 1358bd9244f7SScott Teel { 1359bd9244f7SScott Teel /* assumes h->devlock is held */ 1360bd9244f7SScott Teel BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1361bd9244f7SScott Teel 1362bd9244f7SScott Teel /* Raid level changed. */ 1363bd9244f7SScott Teel h->dev[entry]->raid_level = new_entry->raid_level; 1364250fb125SStephen M. Cameron 1365b2582a65SDon Brace /* 1366b2582a65SDon Brace * ioacccel_handle may have changed for a dual domain disk 1367b2582a65SDon Brace */ 1368b2582a65SDon Brace h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1369b2582a65SDon Brace 137003383736SDon Brace /* Raid offload parameters changed. Careful about the ordering. */ 1371b2582a65SDon Brace if (new_entry->offload_config && new_entry->offload_to_be_enabled) { 137203383736SDon Brace /* 137303383736SDon Brace * if drive is newly offload_enabled, we want to copy the 137403383736SDon Brace * raid map data first. If previously offload_enabled and 137503383736SDon Brace * offload_config were set, raid map data had better be 1376b2582a65SDon Brace * the same as it was before. If raid map data has changed 137703383736SDon Brace * then it had better be the case that 137803383736SDon Brace * h->dev[entry]->offload_enabled is currently 0. 137903383736SDon Brace */ 13809fb0de2dSStephen M. Cameron h->dev[entry]->raid_map = new_entry->raid_map; 138103383736SDon Brace h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 138203383736SDon Brace } 1383b2582a65SDon Brace if (new_entry->offload_to_be_enabled) { 1384a3144e0bSJoe Handzik h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1385a3144e0bSJoe Handzik wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ 1386a3144e0bSJoe Handzik } 1387a3144e0bSJoe Handzik h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; 138803383736SDon Brace h->dev[entry]->offload_config = new_entry->offload_config; 138903383736SDon Brace h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; 139003383736SDon Brace h->dev[entry]->queue_depth = new_entry->queue_depth; 1391250fb125SStephen M. Cameron 139241ce4c35SStephen Cameron /* 139341ce4c35SStephen Cameron * We can turn off ioaccel offload now, but need to delay turning 1394b2582a65SDon Brace * ioaccel on until we can update h->dev[entry]->phys_disk[], but we 139541ce4c35SStephen Cameron * can't do that until all the devices are updated. 139641ce4c35SStephen Cameron */ 1397b2582a65SDon Brace h->dev[entry]->offload_to_be_enabled = new_entry->offload_to_be_enabled; 1398b2582a65SDon Brace 1399b2582a65SDon Brace /* 1400b2582a65SDon Brace * turn ioaccel off immediately if told to do so. 1401b2582a65SDon Brace */ 1402b2582a65SDon Brace if (!new_entry->offload_to_be_enabled) 140341ce4c35SStephen Cameron h->dev[entry]->offload_enabled = 0; 140441ce4c35SStephen Cameron 14050d96ef5fSWebb Scales hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); 1406bd9244f7SScott Teel } 1407bd9244f7SScott Teel 14082a8ccf31SStephen M. Cameron /* Replace an entry from h->dev[] array. */ 14098aa60681SDon Brace static void hpsa_scsi_replace_entry(struct ctlr_info *h, 14102a8ccf31SStephen M. Cameron int entry, struct hpsa_scsi_dev_t *new_entry, 14112a8ccf31SStephen M. Cameron struct hpsa_scsi_dev_t *added[], int *nadded, 14122a8ccf31SStephen M. Cameron struct hpsa_scsi_dev_t *removed[], int *nremoved) 14132a8ccf31SStephen M. Cameron { 14142a8ccf31SStephen M. Cameron /* assumes h->devlock is held */ 1415cfe5badcSScott Teel BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 14162a8ccf31SStephen M. Cameron removed[*nremoved] = h->dev[entry]; 14172a8ccf31SStephen M. Cameron (*nremoved)++; 141801350d05SStephen M. Cameron 141901350d05SStephen M. Cameron /* 142001350d05SStephen M. Cameron * New physical devices won't have target/lun assigned yet 142101350d05SStephen M. Cameron * so we need to preserve the values in the slot we are replacing. 142201350d05SStephen M. Cameron */ 142301350d05SStephen M. Cameron if (new_entry->target == -1) { 142401350d05SStephen M. Cameron new_entry->target = h->dev[entry]->target; 142501350d05SStephen M. Cameron new_entry->lun = h->dev[entry]->lun; 142601350d05SStephen M. Cameron } 142701350d05SStephen M. Cameron 14282a8ccf31SStephen M. Cameron h->dev[entry] = new_entry; 14292a8ccf31SStephen M. Cameron added[*nadded] = new_entry; 14302a8ccf31SStephen M. Cameron (*nadded)++; 1431b2582a65SDon Brace 14320d96ef5fSWebb Scales hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); 14332a8ccf31SStephen M. Cameron } 14342a8ccf31SStephen M. Cameron 1435edd16368SStephen M. Cameron /* Remove an entry from h->dev[] array. */ 14368aa60681SDon Brace static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, 1437edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *removed[], int *nremoved) 1438edd16368SStephen M. Cameron { 1439edd16368SStephen M. Cameron /* assumes h->devlock is held */ 1440edd16368SStephen M. Cameron int i; 1441edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *sd; 1442edd16368SStephen M. Cameron 1443cfe5badcSScott Teel BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1444edd16368SStephen M. Cameron 1445edd16368SStephen M. Cameron sd = h->dev[entry]; 1446edd16368SStephen M. Cameron removed[*nremoved] = h->dev[entry]; 1447edd16368SStephen M. Cameron (*nremoved)++; 1448edd16368SStephen M. Cameron 1449edd16368SStephen M. Cameron for (i = entry; i < h->ndevices-1; i++) 1450edd16368SStephen M. Cameron h->dev[i] = h->dev[i+1]; 1451edd16368SStephen M. Cameron h->ndevices--; 14520d96ef5fSWebb Scales hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); 1453edd16368SStephen M. Cameron } 1454edd16368SStephen M. Cameron 1455edd16368SStephen M. Cameron #define SCSI3ADDR_EQ(a, b) ( \ 1456edd16368SStephen M. Cameron (a)[7] == (b)[7] && \ 1457edd16368SStephen M. Cameron (a)[6] == (b)[6] && \ 1458edd16368SStephen M. Cameron (a)[5] == (b)[5] && \ 1459edd16368SStephen M. Cameron (a)[4] == (b)[4] && \ 1460edd16368SStephen M. Cameron (a)[3] == (b)[3] && \ 1461edd16368SStephen M. Cameron (a)[2] == (b)[2] && \ 1462edd16368SStephen M. Cameron (a)[1] == (b)[1] && \ 1463edd16368SStephen M. Cameron (a)[0] == (b)[0]) 1464edd16368SStephen M. Cameron 1465edd16368SStephen M. Cameron static void fixup_botched_add(struct ctlr_info *h, 1466edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *added) 1467edd16368SStephen M. Cameron { 1468edd16368SStephen M. Cameron /* called when scsi_add_device fails in order to re-adjust 1469edd16368SStephen M. Cameron * h->dev[] to match the mid layer's view. 1470edd16368SStephen M. Cameron */ 1471edd16368SStephen M. Cameron unsigned long flags; 1472edd16368SStephen M. Cameron int i, j; 1473edd16368SStephen M. Cameron 1474edd16368SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 1475edd16368SStephen M. Cameron for (i = 0; i < h->ndevices; i++) { 1476edd16368SStephen M. Cameron if (h->dev[i] == added) { 1477edd16368SStephen M. Cameron for (j = i; j < h->ndevices-1; j++) 1478edd16368SStephen M. Cameron h->dev[j] = h->dev[j+1]; 1479edd16368SStephen M. Cameron h->ndevices--; 1480edd16368SStephen M. Cameron break; 1481edd16368SStephen M. Cameron } 1482edd16368SStephen M. Cameron } 1483edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 1484edd16368SStephen M. Cameron kfree(added); 1485edd16368SStephen M. Cameron } 1486edd16368SStephen M. Cameron 1487edd16368SStephen M. Cameron static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, 1488edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *dev2) 1489edd16368SStephen M. Cameron { 1490edd16368SStephen M. Cameron /* we compare everything except lun and target as these 1491edd16368SStephen M. Cameron * are not yet assigned. Compare parts likely 1492edd16368SStephen M. Cameron * to differ first 1493edd16368SStephen M. Cameron */ 1494edd16368SStephen M. Cameron if (memcmp(dev1->scsi3addr, dev2->scsi3addr, 1495edd16368SStephen M. Cameron sizeof(dev1->scsi3addr)) != 0) 1496edd16368SStephen M. Cameron return 0; 1497edd16368SStephen M. Cameron if (memcmp(dev1->device_id, dev2->device_id, 1498edd16368SStephen M. Cameron sizeof(dev1->device_id)) != 0) 1499edd16368SStephen M. Cameron return 0; 1500edd16368SStephen M. Cameron if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) 1501edd16368SStephen M. Cameron return 0; 1502edd16368SStephen M. Cameron if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) 1503edd16368SStephen M. Cameron return 0; 1504edd16368SStephen M. Cameron if (dev1->devtype != dev2->devtype) 1505edd16368SStephen M. Cameron return 0; 1506edd16368SStephen M. Cameron if (dev1->bus != dev2->bus) 1507edd16368SStephen M. Cameron return 0; 1508edd16368SStephen M. Cameron return 1; 1509edd16368SStephen M. Cameron } 1510edd16368SStephen M. Cameron 1511bd9244f7SScott Teel static inline int device_updated(struct hpsa_scsi_dev_t *dev1, 1512bd9244f7SScott Teel struct hpsa_scsi_dev_t *dev2) 1513bd9244f7SScott Teel { 1514bd9244f7SScott Teel /* Device attributes that can change, but don't mean 1515bd9244f7SScott Teel * that the device is a different device, nor that the OS 1516bd9244f7SScott Teel * needs to be told anything about the change. 1517bd9244f7SScott Teel */ 1518bd9244f7SScott Teel if (dev1->raid_level != dev2->raid_level) 1519bd9244f7SScott Teel return 1; 1520250fb125SStephen M. Cameron if (dev1->offload_config != dev2->offload_config) 1521250fb125SStephen M. Cameron return 1; 1522b2582a65SDon Brace if (dev1->offload_to_be_enabled != dev2->offload_to_be_enabled) 1523250fb125SStephen M. Cameron return 1; 152493849508SDon Brace if (!is_logical_dev_addr_mode(dev1->scsi3addr)) 152503383736SDon Brace if (dev1->queue_depth != dev2->queue_depth) 152603383736SDon Brace return 1; 1527b2582a65SDon Brace /* 1528b2582a65SDon Brace * This can happen for dual domain devices. An active 1529b2582a65SDon Brace * path change causes the ioaccel handle to change 1530b2582a65SDon Brace * 1531b2582a65SDon Brace * for example note the handle differences between p0 and p1 1532b2582a65SDon Brace * Device WWN ,WWN hash,Handle 1533b2582a65SDon Brace * D016 p0|0x3 [02]P2E:01:01,0x5000C5005FC4DACA,0x9B5616,0x01030003 1534b2582a65SDon Brace * p1 0x5000C5005FC4DAC9,0x6798C0,0x00040004 1535b2582a65SDon Brace */ 1536b2582a65SDon Brace if (dev1->ioaccel_handle != dev2->ioaccel_handle) 1537b2582a65SDon Brace return 1; 1538bd9244f7SScott Teel return 0; 1539bd9244f7SScott Teel } 1540bd9244f7SScott Teel 1541edd16368SStephen M. Cameron /* Find needle in haystack. If exact match found, return DEVICE_SAME, 1542edd16368SStephen M. Cameron * and return needle location in *index. If scsi3addr matches, but not 1543edd16368SStephen M. Cameron * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle 1544bd9244f7SScott Teel * location in *index. 1545bd9244f7SScott Teel * In the case of a minor device attribute change, such as RAID level, just 1546bd9244f7SScott Teel * return DEVICE_UPDATED, along with the updated device's location in index. 1547bd9244f7SScott Teel * If needle not found, return DEVICE_NOT_FOUND. 1548edd16368SStephen M. Cameron */ 1549edd16368SStephen M. Cameron static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, 1550edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *haystack[], int haystack_size, 1551edd16368SStephen M. Cameron int *index) 1552edd16368SStephen M. Cameron { 1553edd16368SStephen M. Cameron int i; 1554edd16368SStephen M. Cameron #define DEVICE_NOT_FOUND 0 1555edd16368SStephen M. Cameron #define DEVICE_CHANGED 1 1556edd16368SStephen M. Cameron #define DEVICE_SAME 2 1557bd9244f7SScott Teel #define DEVICE_UPDATED 3 15581d33d85dSDon Brace if (needle == NULL) 15591d33d85dSDon Brace return DEVICE_NOT_FOUND; 15601d33d85dSDon Brace 1561edd16368SStephen M. Cameron for (i = 0; i < haystack_size; i++) { 156223231048SStephen M. Cameron if (haystack[i] == NULL) /* previously removed. */ 156323231048SStephen M. Cameron continue; 1564edd16368SStephen M. Cameron if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { 1565edd16368SStephen M. Cameron *index = i; 1566bd9244f7SScott Teel if (device_is_the_same(needle, haystack[i])) { 1567bd9244f7SScott Teel if (device_updated(needle, haystack[i])) 1568bd9244f7SScott Teel return DEVICE_UPDATED; 1569edd16368SStephen M. Cameron return DEVICE_SAME; 1570bd9244f7SScott Teel } else { 15719846590eSStephen M. Cameron /* Keep offline devices offline */ 15729846590eSStephen M. Cameron if (needle->volume_offline) 15739846590eSStephen M. Cameron return DEVICE_NOT_FOUND; 1574edd16368SStephen M. Cameron return DEVICE_CHANGED; 1575edd16368SStephen M. Cameron } 1576edd16368SStephen M. Cameron } 1577bd9244f7SScott Teel } 1578edd16368SStephen M. Cameron *index = -1; 1579edd16368SStephen M. Cameron return DEVICE_NOT_FOUND; 1580edd16368SStephen M. Cameron } 1581edd16368SStephen M. Cameron 15829846590eSStephen M. Cameron static void hpsa_monitor_offline_device(struct ctlr_info *h, 15839846590eSStephen M. Cameron unsigned char scsi3addr[]) 15849846590eSStephen M. Cameron { 15859846590eSStephen M. Cameron struct offline_device_entry *device; 15869846590eSStephen M. Cameron unsigned long flags; 15879846590eSStephen M. Cameron 15889846590eSStephen M. Cameron /* Check to see if device is already on the list */ 15899846590eSStephen M. Cameron spin_lock_irqsave(&h->offline_device_lock, flags); 15909846590eSStephen M. Cameron list_for_each_entry(device, &h->offline_device_list, offline_list) { 15919846590eSStephen M. Cameron if (memcmp(device->scsi3addr, scsi3addr, 15929846590eSStephen M. Cameron sizeof(device->scsi3addr)) == 0) { 15939846590eSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 15949846590eSStephen M. Cameron return; 15959846590eSStephen M. Cameron } 15969846590eSStephen M. Cameron } 15979846590eSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 15989846590eSStephen M. Cameron 15999846590eSStephen M. Cameron /* Device is not on the list, add it. */ 16009846590eSStephen M. Cameron device = kmalloc(sizeof(*device), GFP_KERNEL); 16017e8a9486SAmit Kushwaha if (!device) 16029846590eSStephen M. Cameron return; 16037e8a9486SAmit Kushwaha 16049846590eSStephen M. Cameron memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); 16059846590eSStephen M. Cameron spin_lock_irqsave(&h->offline_device_lock, flags); 16069846590eSStephen M. Cameron list_add_tail(&device->offline_list, &h->offline_device_list); 16079846590eSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 16089846590eSStephen M. Cameron } 16099846590eSStephen M. Cameron 16109846590eSStephen M. Cameron /* Print a message explaining various offline volume states */ 16119846590eSStephen M. Cameron static void hpsa_show_volume_status(struct ctlr_info *h, 16129846590eSStephen M. Cameron struct hpsa_scsi_dev_t *sd) 16139846590eSStephen M. Cameron { 16149846590eSStephen M. Cameron if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) 16159846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16169846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", 16179846590eSStephen M. Cameron h->scsi_host->host_no, 16189846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16199846590eSStephen M. Cameron switch (sd->volume_offline) { 16209846590eSStephen M. Cameron case HPSA_LV_OK: 16219846590eSStephen M. Cameron break; 16229846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ERASE: 16239846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16249846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", 16259846590eSStephen M. Cameron h->scsi_host->host_no, 16269846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16279846590eSStephen M. Cameron break; 16285ca01204SScott Benesh case HPSA_LV_NOT_AVAILABLE: 16295ca01204SScott Benesh dev_info(&h->pdev->dev, 16305ca01204SScott Benesh "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", 16315ca01204SScott Benesh h->scsi_host->host_no, 16325ca01204SScott Benesh sd->bus, sd->target, sd->lun); 16335ca01204SScott Benesh break; 16349846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_RPI: 16359846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16365ca01204SScott Benesh "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", 16379846590eSStephen M. Cameron h->scsi_host->host_no, 16389846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16399846590eSStephen M. Cameron break; 16409846590eSStephen M. Cameron case HPSA_LV_PENDING_RPI: 16419846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16429846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", 16439846590eSStephen M. Cameron h->scsi_host->host_no, 16449846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16459846590eSStephen M. Cameron break; 16469846590eSStephen M. Cameron case HPSA_LV_ENCRYPTED_NO_KEY: 16479846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16489846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", 16499846590eSStephen M. Cameron h->scsi_host->host_no, 16509846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16519846590eSStephen M. Cameron break; 16529846590eSStephen M. Cameron case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 16539846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16549846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", 16559846590eSStephen M. Cameron h->scsi_host->host_no, 16569846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16579846590eSStephen M. Cameron break; 16589846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ENCRYPTION: 16599846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16609846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", 16619846590eSStephen M. Cameron h->scsi_host->host_no, 16629846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16639846590eSStephen M. Cameron break; 16649846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 16659846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16669846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", 16679846590eSStephen M. Cameron h->scsi_host->host_no, 16689846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16699846590eSStephen M. Cameron break; 16709846590eSStephen M. Cameron case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 16719846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16729846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", 16739846590eSStephen M. Cameron h->scsi_host->host_no, 16749846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16759846590eSStephen M. Cameron break; 16769846590eSStephen M. Cameron case HPSA_LV_PENDING_ENCRYPTION: 16779846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16789846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", 16799846590eSStephen M. Cameron h->scsi_host->host_no, 16809846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16819846590eSStephen M. Cameron break; 16829846590eSStephen M. Cameron case HPSA_LV_PENDING_ENCRYPTION_REKEYING: 16839846590eSStephen M. Cameron dev_info(&h->pdev->dev, 16849846590eSStephen M. Cameron "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", 16859846590eSStephen M. Cameron h->scsi_host->host_no, 16869846590eSStephen M. Cameron sd->bus, sd->target, sd->lun); 16879846590eSStephen M. Cameron break; 16889846590eSStephen M. Cameron } 16899846590eSStephen M. Cameron } 16909846590eSStephen M. Cameron 169103383736SDon Brace /* 169203383736SDon Brace * Figure the list of physical drive pointers for a logical drive with 169303383736SDon Brace * raid offload configured. 169403383736SDon Brace */ 169503383736SDon Brace static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, 169603383736SDon Brace struct hpsa_scsi_dev_t *dev[], int ndevices, 169703383736SDon Brace struct hpsa_scsi_dev_t *logical_drive) 169803383736SDon Brace { 169903383736SDon Brace struct raid_map_data *map = &logical_drive->raid_map; 170003383736SDon Brace struct raid_map_disk_data *dd = &map->data[0]; 170103383736SDon Brace int i, j; 170203383736SDon Brace int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 170303383736SDon Brace le16_to_cpu(map->metadata_disks_per_row); 170403383736SDon Brace int nraid_map_entries = le16_to_cpu(map->row_cnt) * 170503383736SDon Brace le16_to_cpu(map->layout_map_count) * 170603383736SDon Brace total_disks_per_row; 170703383736SDon Brace int nphys_disk = le16_to_cpu(map->layout_map_count) * 170803383736SDon Brace total_disks_per_row; 170903383736SDon Brace int qdepth; 171003383736SDon Brace 171103383736SDon Brace if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) 171203383736SDon Brace nraid_map_entries = RAID_MAP_MAX_ENTRIES; 171303383736SDon Brace 1714d604f533SWebb Scales logical_drive->nphysical_disks = nraid_map_entries; 1715d604f533SWebb Scales 171603383736SDon Brace qdepth = 0; 171703383736SDon Brace for (i = 0; i < nraid_map_entries; i++) { 171803383736SDon Brace logical_drive->phys_disk[i] = NULL; 171903383736SDon Brace if (!logical_drive->offload_config) 172003383736SDon Brace continue; 172103383736SDon Brace for (j = 0; j < ndevices; j++) { 17221d33d85dSDon Brace if (dev[j] == NULL) 17231d33d85dSDon Brace continue; 1724ff615f06SPetros Koutoupis if (dev[j]->devtype != TYPE_DISK && 1725ff615f06SPetros Koutoupis dev[j]->devtype != TYPE_ZBC) 1726af15ed36SDon Brace continue; 1727f3f01730SKevin Barnett if (is_logical_device(dev[j])) 172803383736SDon Brace continue; 172903383736SDon Brace if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) 173003383736SDon Brace continue; 173103383736SDon Brace 173203383736SDon Brace logical_drive->phys_disk[i] = dev[j]; 173303383736SDon Brace if (i < nphys_disk) 173403383736SDon Brace qdepth = min(h->nr_cmds, qdepth + 173503383736SDon Brace logical_drive->phys_disk[i]->queue_depth); 173603383736SDon Brace break; 173703383736SDon Brace } 173803383736SDon Brace 173903383736SDon Brace /* 174003383736SDon Brace * This can happen if a physical drive is removed and 174103383736SDon Brace * the logical drive is degraded. In that case, the RAID 174203383736SDon Brace * map data will refer to a physical disk which isn't actually 174303383736SDon Brace * present. And in that case offload_enabled should already 174403383736SDon Brace * be 0, but we'll turn it off here just in case 174503383736SDon Brace */ 174603383736SDon Brace if (!logical_drive->phys_disk[i]) { 1747b2582a65SDon Brace dev_warn(&h->pdev->dev, 1748b2582a65SDon Brace "%s: [%d:%d:%d:%d] A phys disk component of LV is missing, turning off offload_enabled for LV.\n", 1749b2582a65SDon Brace __func__, 1750b2582a65SDon Brace h->scsi_host->host_no, logical_drive->bus, 1751b2582a65SDon Brace logical_drive->target, logical_drive->lun); 17523e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(logical_drive); 175341ce4c35SStephen Cameron logical_drive->queue_depth = 8; 175403383736SDon Brace } 175503383736SDon Brace } 175603383736SDon Brace if (nraid_map_entries) 175703383736SDon Brace /* 175803383736SDon Brace * This is correct for reads, too high for full stripe writes, 175903383736SDon Brace * way too high for partial stripe writes 176003383736SDon Brace */ 176103383736SDon Brace logical_drive->queue_depth = qdepth; 17622c5fc363SDon Brace else { 17632c5fc363SDon Brace if (logical_drive->external) 17642c5fc363SDon Brace logical_drive->queue_depth = EXTERNAL_QD; 176503383736SDon Brace else 176603383736SDon Brace logical_drive->queue_depth = h->nr_cmds; 176703383736SDon Brace } 17682c5fc363SDon Brace } 176903383736SDon Brace 177003383736SDon Brace static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, 177103383736SDon Brace struct hpsa_scsi_dev_t *dev[], int ndevices) 177203383736SDon Brace { 177303383736SDon Brace int i; 177403383736SDon Brace 177503383736SDon Brace for (i = 0; i < ndevices; i++) { 17761d33d85dSDon Brace if (dev[i] == NULL) 17771d33d85dSDon Brace continue; 1778ff615f06SPetros Koutoupis if (dev[i]->devtype != TYPE_DISK && 1779ff615f06SPetros Koutoupis dev[i]->devtype != TYPE_ZBC) 1780af15ed36SDon Brace continue; 1781f3f01730SKevin Barnett if (!is_logical_device(dev[i])) 178203383736SDon Brace continue; 178341ce4c35SStephen Cameron 178441ce4c35SStephen Cameron /* 178541ce4c35SStephen Cameron * If offload is currently enabled, the RAID map and 178641ce4c35SStephen Cameron * phys_disk[] assignment *better* not be changing 1787b2582a65SDon Brace * because we would be changing ioaccel phsy_disk[] pointers 1788b2582a65SDon Brace * on a ioaccel volume processing I/O requests. 1789b2582a65SDon Brace * 1790b2582a65SDon Brace * If an ioaccel volume status changed, initially because it was 1791b2582a65SDon Brace * re-configured and thus underwent a transformation, or 1792b2582a65SDon Brace * a drive failed, we would have received a state change 1793b2582a65SDon Brace * request and ioaccel should have been turned off. When the 1794b2582a65SDon Brace * transformation completes, we get another state change 1795b2582a65SDon Brace * request to turn ioaccel back on. In this case, we need 1796b2582a65SDon Brace * to update the ioaccel information. 1797b2582a65SDon Brace * 1798b2582a65SDon Brace * Thus: If it is not currently enabled, but will be after 1799b2582a65SDon Brace * the scan completes, make sure the ioaccel pointers 1800b2582a65SDon Brace * are up to date. 180141ce4c35SStephen Cameron */ 180241ce4c35SStephen Cameron 1803b2582a65SDon Brace if (!dev[i]->offload_enabled && dev[i]->offload_to_be_enabled) 180403383736SDon Brace hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); 180503383736SDon Brace } 180603383736SDon Brace } 180703383736SDon Brace 1808096ccff4SKevin Barnett static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) 1809096ccff4SKevin Barnett { 1810096ccff4SKevin Barnett int rc = 0; 1811096ccff4SKevin Barnett 1812096ccff4SKevin Barnett if (!h->scsi_host) 1813096ccff4SKevin Barnett return 1; 1814096ccff4SKevin Barnett 1815d04e62b9SKevin Barnett if (is_logical_device(device)) /* RAID */ 1816096ccff4SKevin Barnett rc = scsi_add_device(h->scsi_host, device->bus, 1817096ccff4SKevin Barnett device->target, device->lun); 1818d04e62b9SKevin Barnett else /* HBA */ 1819d04e62b9SKevin Barnett rc = hpsa_add_sas_device(h->sas_host, device); 1820d04e62b9SKevin Barnett 1821096ccff4SKevin Barnett return rc; 1822096ccff4SKevin Barnett } 1823096ccff4SKevin Barnett 1824ba74fdc4SDon Brace static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h, 1825ba74fdc4SDon Brace struct hpsa_scsi_dev_t *dev) 1826ba74fdc4SDon Brace { 1827ba74fdc4SDon Brace int i; 1828ba74fdc4SDon Brace int count = 0; 1829ba74fdc4SDon Brace 1830ba74fdc4SDon Brace for (i = 0; i < h->nr_cmds; i++) { 1831ba74fdc4SDon Brace struct CommandList *c = h->cmd_pool + i; 1832ba74fdc4SDon Brace int refcount = atomic_inc_return(&c->refcount); 1833ba74fdc4SDon Brace 1834ba74fdc4SDon Brace if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, 1835ba74fdc4SDon Brace dev->scsi3addr)) { 1836ba74fdc4SDon Brace unsigned long flags; 1837ba74fdc4SDon Brace 1838ba74fdc4SDon Brace spin_lock_irqsave(&h->lock, flags); /* Implied MB */ 1839ba74fdc4SDon Brace if (!hpsa_is_cmd_idle(c)) 1840ba74fdc4SDon Brace ++count; 1841ba74fdc4SDon Brace spin_unlock_irqrestore(&h->lock, flags); 1842ba74fdc4SDon Brace } 1843ba74fdc4SDon Brace 1844ba74fdc4SDon Brace cmd_free(h, c); 1845ba74fdc4SDon Brace } 1846ba74fdc4SDon Brace 1847ba74fdc4SDon Brace return count; 1848ba74fdc4SDon Brace } 1849ba74fdc4SDon Brace 1850b443d3eaSDon Brace #define NUM_WAIT 20 1851ba74fdc4SDon Brace static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h, 1852ba74fdc4SDon Brace struct hpsa_scsi_dev_t *device) 1853ba74fdc4SDon Brace { 1854ba74fdc4SDon Brace int cmds = 0; 1855ba74fdc4SDon Brace int waits = 0; 1856b443d3eaSDon Brace int num_wait = NUM_WAIT; 1857b443d3eaSDon Brace 1858b443d3eaSDon Brace if (device->external) 1859b443d3eaSDon Brace num_wait = HPSA_EH_PTRAID_TIMEOUT; 1860ba74fdc4SDon Brace 1861ba74fdc4SDon Brace while (1) { 1862ba74fdc4SDon Brace cmds = hpsa_find_outstanding_commands_for_dev(h, device); 1863ba74fdc4SDon Brace if (cmds == 0) 1864ba74fdc4SDon Brace break; 1865b443d3eaSDon Brace if (++waits > num_wait) 1866ba74fdc4SDon Brace break; 18679211a07fSDon Brace msleep(1000); 18689211a07fSDon Brace } 18699211a07fSDon Brace 1870b443d3eaSDon Brace if (waits > num_wait) { 1871ba74fdc4SDon Brace dev_warn(&h->pdev->dev, 1872b443d3eaSDon Brace "%s: removing device [%d:%d:%d:%d] with %d outstanding commands!\n", 1873b443d3eaSDon Brace __func__, 1874b443d3eaSDon Brace h->scsi_host->host_no, 1875b443d3eaSDon Brace device->bus, device->target, device->lun, cmds); 1876b443d3eaSDon Brace } 1877ba74fdc4SDon Brace } 1878ba74fdc4SDon Brace 1879096ccff4SKevin Barnett static void hpsa_remove_device(struct ctlr_info *h, 1880096ccff4SKevin Barnett struct hpsa_scsi_dev_t *device) 1881096ccff4SKevin Barnett { 1882096ccff4SKevin Barnett struct scsi_device *sdev = NULL; 1883096ccff4SKevin Barnett 1884096ccff4SKevin Barnett if (!h->scsi_host) 1885096ccff4SKevin Barnett return; 1886096ccff4SKevin Barnett 18870ff365f5SDon Brace /* 18880ff365f5SDon Brace * Allow for commands to drain 18890ff365f5SDon Brace */ 18900ff365f5SDon Brace device->removed = 1; 18910ff365f5SDon Brace hpsa_wait_for_outstanding_commands_for_dev(h, device); 18920ff365f5SDon Brace 1893d04e62b9SKevin Barnett if (is_logical_device(device)) { /* RAID */ 1894096ccff4SKevin Barnett sdev = scsi_device_lookup(h->scsi_host, device->bus, 1895096ccff4SKevin Barnett device->target, device->lun); 1896096ccff4SKevin Barnett if (sdev) { 1897096ccff4SKevin Barnett scsi_remove_device(sdev); 1898096ccff4SKevin Barnett scsi_device_put(sdev); 1899096ccff4SKevin Barnett } else { 1900096ccff4SKevin Barnett /* 1901096ccff4SKevin Barnett * We don't expect to get here. Future commands 1902096ccff4SKevin Barnett * to this device will get a selection timeout as 1903096ccff4SKevin Barnett * if the device were gone. 1904096ccff4SKevin Barnett */ 1905096ccff4SKevin Barnett hpsa_show_dev_msg(KERN_WARNING, h, device, 1906096ccff4SKevin Barnett "didn't find device for removal."); 1907096ccff4SKevin Barnett } 1908ba74fdc4SDon Brace } else { /* HBA */ 1909ba74fdc4SDon Brace 1910d04e62b9SKevin Barnett hpsa_remove_sas_device(device); 1911096ccff4SKevin Barnett } 1912ba74fdc4SDon Brace } 1913096ccff4SKevin Barnett 19148aa60681SDon Brace static void adjust_hpsa_scsi_table(struct ctlr_info *h, 1915edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *sd[], int nsds) 1916edd16368SStephen M. Cameron { 1917edd16368SStephen M. Cameron /* sd contains scsi3 addresses and devtypes, and inquiry 1918edd16368SStephen M. Cameron * data. This function takes what's in sd to be the current 1919edd16368SStephen M. Cameron * reality and updates h->dev[] to reflect that reality. 1920edd16368SStephen M. Cameron */ 1921edd16368SStephen M. Cameron int i, entry, device_change, changes = 0; 1922edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *csd; 1923edd16368SStephen M. Cameron unsigned long flags; 1924edd16368SStephen M. Cameron struct hpsa_scsi_dev_t **added, **removed; 1925edd16368SStephen M. Cameron int nadded, nremoved; 1926edd16368SStephen M. Cameron 1927da03ded0SDon Brace /* 1928da03ded0SDon Brace * A reset can cause a device status to change 1929da03ded0SDon Brace * re-schedule the scan to see what happened. 1930da03ded0SDon Brace */ 1931c59d04f3SDon Brace spin_lock_irqsave(&h->reset_lock, flags); 1932da03ded0SDon Brace if (h->reset_in_progress) { 1933da03ded0SDon Brace h->drv_req_rescan = 1; 1934c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 1935da03ded0SDon Brace return; 1936da03ded0SDon Brace } 1937c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 1938edd16368SStephen M. Cameron 19396396bb22SKees Cook added = kcalloc(HPSA_MAX_DEVICES, sizeof(*added), GFP_KERNEL); 19406396bb22SKees Cook removed = kcalloc(HPSA_MAX_DEVICES, sizeof(*removed), GFP_KERNEL); 1941edd16368SStephen M. Cameron 1942edd16368SStephen M. Cameron if (!added || !removed) { 1943edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "out of memory in " 1944edd16368SStephen M. Cameron "adjust_hpsa_scsi_table\n"); 1945edd16368SStephen M. Cameron goto free_and_out; 1946edd16368SStephen M. Cameron } 1947edd16368SStephen M. Cameron 1948edd16368SStephen M. Cameron spin_lock_irqsave(&h->devlock, flags); 1949edd16368SStephen M. Cameron 1950edd16368SStephen M. Cameron /* find any devices in h->dev[] that are not in 1951edd16368SStephen M. Cameron * sd[] and remove them from h->dev[], and for any 1952edd16368SStephen M. Cameron * devices which have changed, remove the old device 1953edd16368SStephen M. Cameron * info and add the new device info. 1954bd9244f7SScott Teel * If minor device attributes change, just update 1955bd9244f7SScott Teel * the existing device structure. 1956edd16368SStephen M. Cameron */ 1957edd16368SStephen M. Cameron i = 0; 1958edd16368SStephen M. Cameron nremoved = 0; 1959edd16368SStephen M. Cameron nadded = 0; 1960edd16368SStephen M. Cameron while (i < h->ndevices) { 1961edd16368SStephen M. Cameron csd = h->dev[i]; 1962edd16368SStephen M. Cameron device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); 1963edd16368SStephen M. Cameron if (device_change == DEVICE_NOT_FOUND) { 1964edd16368SStephen M. Cameron changes++; 19658aa60681SDon Brace hpsa_scsi_remove_entry(h, i, removed, &nremoved); 1966edd16368SStephen M. Cameron continue; /* remove ^^^, hence i not incremented */ 1967edd16368SStephen M. Cameron } else if (device_change == DEVICE_CHANGED) { 1968edd16368SStephen M. Cameron changes++; 19698aa60681SDon Brace hpsa_scsi_replace_entry(h, i, sd[entry], 19702a8ccf31SStephen M. Cameron added, &nadded, removed, &nremoved); 1971c7f172dcSStephen M. Cameron /* Set it to NULL to prevent it from being freed 1972c7f172dcSStephen M. Cameron * at the bottom of hpsa_update_scsi_devices() 1973c7f172dcSStephen M. Cameron */ 1974c7f172dcSStephen M. Cameron sd[entry] = NULL; 1975bd9244f7SScott Teel } else if (device_change == DEVICE_UPDATED) { 19768aa60681SDon Brace hpsa_scsi_update_entry(h, i, sd[entry]); 1977edd16368SStephen M. Cameron } 1978edd16368SStephen M. Cameron i++; 1979edd16368SStephen M. Cameron } 1980edd16368SStephen M. Cameron 1981edd16368SStephen M. Cameron /* Now, make sure every device listed in sd[] is also 1982edd16368SStephen M. Cameron * listed in h->dev[], adding them if they aren't found 1983edd16368SStephen M. Cameron */ 1984edd16368SStephen M. Cameron 1985edd16368SStephen M. Cameron for (i = 0; i < nsds; i++) { 1986edd16368SStephen M. Cameron if (!sd[i]) /* if already added above. */ 1987edd16368SStephen M. Cameron continue; 19889846590eSStephen M. Cameron 19899846590eSStephen M. Cameron /* Don't add devices which are NOT READY, FORMAT IN PROGRESS 19909846590eSStephen M. Cameron * as the SCSI mid-layer does not handle such devices well. 19919846590eSStephen M. Cameron * It relentlessly loops sending TUR at 3Hz, then READ(10) 19929846590eSStephen M. Cameron * at 160Hz, and prevents the system from coming up. 19939846590eSStephen M. Cameron */ 19949846590eSStephen M. Cameron if (sd[i]->volume_offline) { 19959846590eSStephen M. Cameron hpsa_show_volume_status(h, sd[i]); 19960d96ef5fSWebb Scales hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); 19979846590eSStephen M. Cameron continue; 19989846590eSStephen M. Cameron } 19999846590eSStephen M. Cameron 2000edd16368SStephen M. Cameron device_change = hpsa_scsi_find_entry(sd[i], h->dev, 2001edd16368SStephen M. Cameron h->ndevices, &entry); 2002edd16368SStephen M. Cameron if (device_change == DEVICE_NOT_FOUND) { 2003edd16368SStephen M. Cameron changes++; 20048aa60681SDon Brace if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) 2005edd16368SStephen M. Cameron break; 2006edd16368SStephen M. Cameron sd[i] = NULL; /* prevent from being freed later. */ 2007edd16368SStephen M. Cameron } else if (device_change == DEVICE_CHANGED) { 2008edd16368SStephen M. Cameron /* should never happen... */ 2009edd16368SStephen M. Cameron changes++; 2010edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, 2011edd16368SStephen M. Cameron "device unexpectedly changed.\n"); 2012edd16368SStephen M. Cameron /* but if it does happen, we just ignore that device */ 2013edd16368SStephen M. Cameron } 2014edd16368SStephen M. Cameron } 201541ce4c35SStephen Cameron hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); 201641ce4c35SStephen Cameron 2017b2582a65SDon Brace /* 2018b2582a65SDon Brace * Now that h->dev[]->phys_disk[] is coherent, we can enable 201941ce4c35SStephen Cameron * any logical drives that need it enabled. 2020b2582a65SDon Brace * 2021b2582a65SDon Brace * The raid map should be current by now. 2022b2582a65SDon Brace * 2023b2582a65SDon Brace * We are updating the device list used for I/O requests. 202441ce4c35SStephen Cameron */ 20251d33d85dSDon Brace for (i = 0; i < h->ndevices; i++) { 20261d33d85dSDon Brace if (h->dev[i] == NULL) 20271d33d85dSDon Brace continue; 202841ce4c35SStephen Cameron h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; 20291d33d85dSDon Brace } 203041ce4c35SStephen Cameron 2031edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->devlock, flags); 2032edd16368SStephen M. Cameron 20339846590eSStephen M. Cameron /* Monitor devices which are in one of several NOT READY states to be 20349846590eSStephen M. Cameron * brought online later. This must be done without holding h->devlock, 20359846590eSStephen M. Cameron * so don't touch h->dev[] 20369846590eSStephen M. Cameron */ 20379846590eSStephen M. Cameron for (i = 0; i < nsds; i++) { 20389846590eSStephen M. Cameron if (!sd[i]) /* if already added above. */ 20399846590eSStephen M. Cameron continue; 20409846590eSStephen M. Cameron if (sd[i]->volume_offline) 20419846590eSStephen M. Cameron hpsa_monitor_offline_device(h, sd[i]->scsi3addr); 20429846590eSStephen M. Cameron } 20439846590eSStephen M. Cameron 2044edd16368SStephen M. Cameron /* Don't notify scsi mid layer of any changes the first time through 2045edd16368SStephen M. Cameron * (or if there are no changes) scsi_scan_host will do it later the 2046edd16368SStephen M. Cameron * first time through. 2047edd16368SStephen M. Cameron */ 20488aa60681SDon Brace if (!changes) 2049edd16368SStephen M. Cameron goto free_and_out; 2050edd16368SStephen M. Cameron 2051edd16368SStephen M. Cameron /* Notify scsi mid layer of any removed devices */ 2052edd16368SStephen M. Cameron for (i = 0; i < nremoved; i++) { 20531d33d85dSDon Brace if (removed[i] == NULL) 20541d33d85dSDon Brace continue; 2055096ccff4SKevin Barnett if (removed[i]->expose_device) 2056096ccff4SKevin Barnett hpsa_remove_device(h, removed[i]); 2057edd16368SStephen M. Cameron kfree(removed[i]); 2058edd16368SStephen M. Cameron removed[i] = NULL; 2059edd16368SStephen M. Cameron } 2060edd16368SStephen M. Cameron 2061edd16368SStephen M. Cameron /* Notify scsi mid layer of any added devices */ 2062edd16368SStephen M. Cameron for (i = 0; i < nadded; i++) { 2063096ccff4SKevin Barnett int rc = 0; 2064096ccff4SKevin Barnett 20651d33d85dSDon Brace if (added[i] == NULL) 206641ce4c35SStephen Cameron continue; 20672a168208SKevin Barnett if (!(added[i]->expose_device)) 2068edd16368SStephen M. Cameron continue; 2069096ccff4SKevin Barnett rc = hpsa_add_device(h, added[i]); 2070096ccff4SKevin Barnett if (!rc) 2071edd16368SStephen M. Cameron continue; 2072096ccff4SKevin Barnett dev_warn(&h->pdev->dev, 2073096ccff4SKevin Barnett "addition failed %d, device not added.", rc); 2074edd16368SStephen M. Cameron /* now we have to remove it from h->dev, 2075edd16368SStephen M. Cameron * since it didn't get added to scsi mid layer 2076edd16368SStephen M. Cameron */ 2077edd16368SStephen M. Cameron fixup_botched_add(h, added[i]); 2078853633e8SDon Brace h->drv_req_rescan = 1; 2079edd16368SStephen M. Cameron } 2080edd16368SStephen M. Cameron 2081edd16368SStephen M. Cameron free_and_out: 2082edd16368SStephen M. Cameron kfree(added); 2083edd16368SStephen M. Cameron kfree(removed); 2084edd16368SStephen M. Cameron } 2085edd16368SStephen M. Cameron 2086edd16368SStephen M. Cameron /* 20879e03aa2fSJoe Perches * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * 2088edd16368SStephen M. Cameron * Assume's h->devlock is held. 2089edd16368SStephen M. Cameron */ 2090edd16368SStephen M. Cameron static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, 2091edd16368SStephen M. Cameron int bus, int target, int lun) 2092edd16368SStephen M. Cameron { 2093edd16368SStephen M. Cameron int i; 2094edd16368SStephen M. Cameron struct hpsa_scsi_dev_t *sd; 2095edd16368SStephen M. Cameron 2096edd16368SStephen M. Cameron for (i = 0; i < h->ndevices; i++) { 2097edd16368SStephen M. Cameron sd = h->dev[i]; 2098edd16368SStephen M. Cameron if (sd->bus == bus && sd->target == target && sd->lun == lun) 2099edd16368SStephen M. Cameron return sd; 2100edd16368SStephen M. Cameron } 2101edd16368SStephen M. Cameron return NULL; 2102edd16368SStephen M. Cameron } 2103edd16368SStephen M. Cameron 2104edd16368SStephen M. Cameron static int hpsa_slave_alloc(struct scsi_device *sdev) 2105edd16368SStephen M. Cameron { 21067630b3a5SHannes Reinecke struct hpsa_scsi_dev_t *sd = NULL; 2107edd16368SStephen M. Cameron unsigned long flags; 2108edd16368SStephen M. Cameron struct ctlr_info *h; 2109edd16368SStephen M. Cameron 2110edd16368SStephen M. Cameron h = sdev_to_hba(sdev); 2111edd16368SStephen M. Cameron spin_lock_irqsave(&h->devlock, flags); 2112d04e62b9SKevin Barnett if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { 2113d04e62b9SKevin Barnett struct scsi_target *starget; 2114d04e62b9SKevin Barnett struct sas_rphy *rphy; 2115d04e62b9SKevin Barnett 2116d04e62b9SKevin Barnett starget = scsi_target(sdev); 2117d04e62b9SKevin Barnett rphy = target_to_rphy(starget); 2118d04e62b9SKevin Barnett sd = hpsa_find_device_by_sas_rphy(h, rphy); 2119d04e62b9SKevin Barnett if (sd) { 2120d04e62b9SKevin Barnett sd->target = sdev_id(sdev); 2121d04e62b9SKevin Barnett sd->lun = sdev->lun; 2122d04e62b9SKevin Barnett } 21237630b3a5SHannes Reinecke } 21247630b3a5SHannes Reinecke if (!sd) 2125edd16368SStephen M. Cameron sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), 2126edd16368SStephen M. Cameron sdev_id(sdev), sdev->lun); 2127d04e62b9SKevin Barnett 2128d04e62b9SKevin Barnett if (sd && sd->expose_device) { 212903383736SDon Brace atomic_set(&sd->ioaccel_cmds_out, 0); 2130d04e62b9SKevin Barnett sdev->hostdata = sd; 213141ce4c35SStephen Cameron } else 213241ce4c35SStephen Cameron sdev->hostdata = NULL; 2133edd16368SStephen M. Cameron spin_unlock_irqrestore(&h->devlock, flags); 2134edd16368SStephen M. Cameron return 0; 2135edd16368SStephen M. Cameron } 2136edd16368SStephen M. Cameron 213741ce4c35SStephen Cameron /* configure scsi device based on internal per-device structure */ 213830bda784SDon Brace #define CTLR_TIMEOUT (120 * HZ) 213941ce4c35SStephen Cameron static int hpsa_slave_configure(struct scsi_device *sdev) 214041ce4c35SStephen Cameron { 214141ce4c35SStephen Cameron struct hpsa_scsi_dev_t *sd; 214241ce4c35SStephen Cameron int queue_depth; 214341ce4c35SStephen Cameron 214441ce4c35SStephen Cameron sd = sdev->hostdata; 21452a168208SKevin Barnett sdev->no_uld_attach = !sd || !sd->expose_device; 214641ce4c35SStephen Cameron 21475086435eSDon Brace if (sd) { 21489e33f0d5SDon Brace sd->was_removed = 0; 21495759ff11SDon Brace queue_depth = sd->queue_depth != 0 ? 21505759ff11SDon Brace sd->queue_depth : sdev->host->can_queue; 2151b443d3eaSDon Brace if (sd->external) { 21525086435eSDon Brace queue_depth = EXTERNAL_QD; 2153b443d3eaSDon Brace sdev->eh_timeout = HPSA_EH_PTRAID_TIMEOUT; 2154b443d3eaSDon Brace blk_queue_rq_timeout(sdev->request_queue, 2155b443d3eaSDon Brace HPSA_EH_PTRAID_TIMEOUT); 21565759ff11SDon Brace } 21575759ff11SDon Brace if (is_hba_lunid(sd->scsi3addr)) { 215830bda784SDon Brace sdev->eh_timeout = CTLR_TIMEOUT; 215930bda784SDon Brace blk_queue_rq_timeout(sdev->request_queue, CTLR_TIMEOUT); 2160b443d3eaSDon Brace } 21615759ff11SDon Brace } else { 216241ce4c35SStephen Cameron queue_depth = sdev->host->can_queue; 21635759ff11SDon Brace } 216441ce4c35SStephen Cameron 216541ce4c35SStephen Cameron scsi_change_queue_depth(sdev, queue_depth); 216641ce4c35SStephen Cameron 216741ce4c35SStephen Cameron return 0; 216841ce4c35SStephen Cameron } 216941ce4c35SStephen Cameron 2170edd16368SStephen M. Cameron static void hpsa_slave_destroy(struct scsi_device *sdev) 2171edd16368SStephen M. Cameron { 21729e33f0d5SDon Brace struct hpsa_scsi_dev_t *hdev = NULL; 21739e33f0d5SDon Brace 21749e33f0d5SDon Brace hdev = sdev->hostdata; 21759e33f0d5SDon Brace 21769e33f0d5SDon Brace if (hdev) 21779e33f0d5SDon Brace hdev->was_removed = 1; 2178edd16368SStephen M. Cameron } 2179edd16368SStephen M. Cameron 2180d9a729f3SWebb Scales static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2181d9a729f3SWebb Scales { 2182d9a729f3SWebb Scales int i; 2183d9a729f3SWebb Scales 2184d9a729f3SWebb Scales if (!h->ioaccel2_cmd_sg_list) 2185d9a729f3SWebb Scales return; 2186d9a729f3SWebb Scales for (i = 0; i < h->nr_cmds; i++) { 2187d9a729f3SWebb Scales kfree(h->ioaccel2_cmd_sg_list[i]); 2188d9a729f3SWebb Scales h->ioaccel2_cmd_sg_list[i] = NULL; 2189d9a729f3SWebb Scales } 2190d9a729f3SWebb Scales kfree(h->ioaccel2_cmd_sg_list); 2191d9a729f3SWebb Scales h->ioaccel2_cmd_sg_list = NULL; 2192d9a729f3SWebb Scales } 2193d9a729f3SWebb Scales 2194d9a729f3SWebb Scales static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2195d9a729f3SWebb Scales { 2196d9a729f3SWebb Scales int i; 2197d9a729f3SWebb Scales 2198d9a729f3SWebb Scales if (h->chainsize <= 0) 2199d9a729f3SWebb Scales return 0; 2200d9a729f3SWebb Scales 2201d9a729f3SWebb Scales h->ioaccel2_cmd_sg_list = 22026396bb22SKees Cook kcalloc(h->nr_cmds, sizeof(*h->ioaccel2_cmd_sg_list), 2203d9a729f3SWebb Scales GFP_KERNEL); 2204d9a729f3SWebb Scales if (!h->ioaccel2_cmd_sg_list) 2205d9a729f3SWebb Scales return -ENOMEM; 2206d9a729f3SWebb Scales for (i = 0; i < h->nr_cmds; i++) { 2207d9a729f3SWebb Scales h->ioaccel2_cmd_sg_list[i] = 22086da2ec56SKees Cook kmalloc_array(h->maxsgentries, 22096da2ec56SKees Cook sizeof(*h->ioaccel2_cmd_sg_list[i]), 22106da2ec56SKees Cook GFP_KERNEL); 2211d9a729f3SWebb Scales if (!h->ioaccel2_cmd_sg_list[i]) 2212d9a729f3SWebb Scales goto clean; 2213d9a729f3SWebb Scales } 2214d9a729f3SWebb Scales return 0; 2215d9a729f3SWebb Scales 2216d9a729f3SWebb Scales clean: 2217d9a729f3SWebb Scales hpsa_free_ioaccel2_sg_chain_blocks(h); 2218d9a729f3SWebb Scales return -ENOMEM; 2219d9a729f3SWebb Scales } 2220d9a729f3SWebb Scales 222133a2ffceSStephen M. Cameron static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) 222233a2ffceSStephen M. Cameron { 222333a2ffceSStephen M. Cameron int i; 222433a2ffceSStephen M. Cameron 222533a2ffceSStephen M. Cameron if (!h->cmd_sg_list) 222633a2ffceSStephen M. Cameron return; 222733a2ffceSStephen M. Cameron for (i = 0; i < h->nr_cmds; i++) { 222833a2ffceSStephen M. Cameron kfree(h->cmd_sg_list[i]); 222933a2ffceSStephen M. Cameron h->cmd_sg_list[i] = NULL; 223033a2ffceSStephen M. Cameron } 223133a2ffceSStephen M. Cameron kfree(h->cmd_sg_list); 223233a2ffceSStephen M. Cameron h->cmd_sg_list = NULL; 223333a2ffceSStephen M. Cameron } 223433a2ffceSStephen M. Cameron 2235105a3dbcSRobert Elliott static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) 223633a2ffceSStephen M. Cameron { 223733a2ffceSStephen M. Cameron int i; 223833a2ffceSStephen M. Cameron 223933a2ffceSStephen M. Cameron if (h->chainsize <= 0) 224033a2ffceSStephen M. Cameron return 0; 224133a2ffceSStephen M. Cameron 22426396bb22SKees Cook h->cmd_sg_list = kcalloc(h->nr_cmds, sizeof(*h->cmd_sg_list), 224333a2ffceSStephen M. Cameron GFP_KERNEL); 22447e8a9486SAmit Kushwaha if (!h->cmd_sg_list) 224533a2ffceSStephen M. Cameron return -ENOMEM; 22467e8a9486SAmit Kushwaha 224733a2ffceSStephen M. Cameron for (i = 0; i < h->nr_cmds; i++) { 22486da2ec56SKees Cook h->cmd_sg_list[i] = kmalloc_array(h->chainsize, 22496da2ec56SKees Cook sizeof(*h->cmd_sg_list[i]), 22506da2ec56SKees Cook GFP_KERNEL); 22517e8a9486SAmit Kushwaha if (!h->cmd_sg_list[i]) 225233a2ffceSStephen M. Cameron goto clean; 22537e8a9486SAmit Kushwaha 22543d4e6af8SRobert Elliott } 225533a2ffceSStephen M. Cameron return 0; 225633a2ffceSStephen M. Cameron 225733a2ffceSStephen M. Cameron clean: 225833a2ffceSStephen M. Cameron hpsa_free_sg_chain_blocks(h); 225933a2ffceSStephen M. Cameron return -ENOMEM; 226033a2ffceSStephen M. Cameron } 226133a2ffceSStephen M. Cameron 2262d9a729f3SWebb Scales static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, 2263d9a729f3SWebb Scales struct io_accel2_cmd *cp, struct CommandList *c) 2264d9a729f3SWebb Scales { 2265d9a729f3SWebb Scales struct ioaccel2_sg_element *chain_block; 2266d9a729f3SWebb Scales u64 temp64; 2267d9a729f3SWebb Scales u32 chain_size; 2268d9a729f3SWebb Scales 2269d9a729f3SWebb Scales chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; 2270a736e9b6SDon Brace chain_size = le32_to_cpu(cp->sg[0].length); 22718bc8f47eSChristoph Hellwig temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_size, 22728bc8f47eSChristoph Hellwig DMA_TO_DEVICE); 2273d9a729f3SWebb Scales if (dma_mapping_error(&h->pdev->dev, temp64)) { 2274d9a729f3SWebb Scales /* prevent subsequent unmapping */ 2275d9a729f3SWebb Scales cp->sg->address = 0; 2276d9a729f3SWebb Scales return -1; 2277d9a729f3SWebb Scales } 2278d9a729f3SWebb Scales cp->sg->address = cpu_to_le64(temp64); 2279d9a729f3SWebb Scales return 0; 2280d9a729f3SWebb Scales } 2281d9a729f3SWebb Scales 2282d9a729f3SWebb Scales static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, 2283d9a729f3SWebb Scales struct io_accel2_cmd *cp) 2284d9a729f3SWebb Scales { 2285d9a729f3SWebb Scales struct ioaccel2_sg_element *chain_sg; 2286d9a729f3SWebb Scales u64 temp64; 2287d9a729f3SWebb Scales u32 chain_size; 2288d9a729f3SWebb Scales 2289d9a729f3SWebb Scales chain_sg = cp->sg; 2290d9a729f3SWebb Scales temp64 = le64_to_cpu(chain_sg->address); 2291a736e9b6SDon Brace chain_size = le32_to_cpu(cp->sg[0].length); 22928bc8f47eSChristoph Hellwig dma_unmap_single(&h->pdev->dev, temp64, chain_size, DMA_TO_DEVICE); 2293d9a729f3SWebb Scales } 2294d9a729f3SWebb Scales 2295e2bea6dfSStephen M. Cameron static int hpsa_map_sg_chain_block(struct ctlr_info *h, 229633a2ffceSStephen M. Cameron struct CommandList *c) 229733a2ffceSStephen M. Cameron { 229833a2ffceSStephen M. Cameron struct SGDescriptor *chain_sg, *chain_block; 229933a2ffceSStephen M. Cameron u64 temp64; 230050a0decfSStephen M. Cameron u32 chain_len; 230133a2ffceSStephen M. Cameron 230233a2ffceSStephen M. Cameron chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 230333a2ffceSStephen M. Cameron chain_block = h->cmd_sg_list[c->cmdindex]; 230450a0decfSStephen M. Cameron chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); 230550a0decfSStephen M. Cameron chain_len = sizeof(*chain_sg) * 23062b08b3e9SDon Brace (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); 230750a0decfSStephen M. Cameron chain_sg->Len = cpu_to_le32(chain_len); 23088bc8f47eSChristoph Hellwig temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_len, 23098bc8f47eSChristoph Hellwig DMA_TO_DEVICE); 2310e2bea6dfSStephen M. Cameron if (dma_mapping_error(&h->pdev->dev, temp64)) { 2311e2bea6dfSStephen M. Cameron /* prevent subsequent unmapping */ 231250a0decfSStephen M. Cameron chain_sg->Addr = cpu_to_le64(0); 2313e2bea6dfSStephen M. Cameron return -1; 2314e2bea6dfSStephen M. Cameron } 231550a0decfSStephen M. Cameron chain_sg->Addr = cpu_to_le64(temp64); 2316e2bea6dfSStephen M. Cameron return 0; 231733a2ffceSStephen M. Cameron } 231833a2ffceSStephen M. Cameron 231933a2ffceSStephen M. Cameron static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, 232033a2ffceSStephen M. Cameron struct CommandList *c) 232133a2ffceSStephen M. Cameron { 232233a2ffceSStephen M. Cameron struct SGDescriptor *chain_sg; 232333a2ffceSStephen M. Cameron 232450a0decfSStephen M. Cameron if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) 232533a2ffceSStephen M. Cameron return; 232633a2ffceSStephen M. Cameron 232733a2ffceSStephen M. Cameron chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 23288bc8f47eSChristoph Hellwig dma_unmap_single(&h->pdev->dev, le64_to_cpu(chain_sg->Addr), 23298bc8f47eSChristoph Hellwig le32_to_cpu(chain_sg->Len), DMA_TO_DEVICE); 233033a2ffceSStephen M. Cameron } 233133a2ffceSStephen M. Cameron 2332a09c1441SScott Teel 2333a09c1441SScott Teel /* Decode the various types of errors on ioaccel2 path. 2334a09c1441SScott Teel * Return 1 for any error that should generate a RAID path retry. 2335a09c1441SScott Teel * Return 0 for errors that don't require a RAID path retry. 2336a09c1441SScott Teel */ 2337a09c1441SScott Teel static int handle_ioaccel_mode2_error(struct ctlr_info *h, 2338c349775eSScott Teel struct CommandList *c, 2339c349775eSScott Teel struct scsi_cmnd *cmd, 2340ba74fdc4SDon Brace struct io_accel2_cmd *c2, 2341ba74fdc4SDon Brace struct hpsa_scsi_dev_t *dev) 2342c349775eSScott Teel { 2343c349775eSScott Teel int data_len; 2344a09c1441SScott Teel int retry = 0; 2345c40820d5SJoe Handzik u32 ioaccel2_resid = 0; 2346c349775eSScott Teel 2347c349775eSScott Teel switch (c2->error_data.serv_response) { 2348c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_COMPLETE: 2349c349775eSScott Teel switch (c2->error_data.status) { 2350c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: 2351eeebce18SDon Brace if (cmd) 2352eeebce18SDon Brace cmd->result = 0; 2353c349775eSScott Teel break; 2354c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: 2355ee6b1889SStephen M. Cameron cmd->result |= SAM_STAT_CHECK_CONDITION; 2356c349775eSScott Teel if (c2->error_data.data_present != 2357ee6b1889SStephen M. Cameron IOACCEL2_SENSE_DATA_PRESENT) { 2358ee6b1889SStephen M. Cameron memset(cmd->sense_buffer, 0, 2359ee6b1889SStephen M. Cameron SCSI_SENSE_BUFFERSIZE); 2360c349775eSScott Teel break; 2361ee6b1889SStephen M. Cameron } 2362c349775eSScott Teel /* copy the sense data */ 2363c349775eSScott Teel data_len = c2->error_data.sense_data_len; 2364c349775eSScott Teel if (data_len > SCSI_SENSE_BUFFERSIZE) 2365c349775eSScott Teel data_len = SCSI_SENSE_BUFFERSIZE; 2366c349775eSScott Teel if (data_len > sizeof(c2->error_data.sense_data_buff)) 2367c349775eSScott Teel data_len = 2368c349775eSScott Teel sizeof(c2->error_data.sense_data_buff); 2369c349775eSScott Teel memcpy(cmd->sense_buffer, 2370c349775eSScott Teel c2->error_data.sense_data_buff, data_len); 2371a09c1441SScott Teel retry = 1; 2372c349775eSScott Teel break; 2373c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: 2374a09c1441SScott Teel retry = 1; 2375c349775eSScott Teel break; 2376c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: 2377a09c1441SScott Teel retry = 1; 2378c349775eSScott Teel break; 2379c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: 23804a8da22bSStephen Cameron retry = 1; 2381c349775eSScott Teel break; 2382c349775eSScott Teel case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: 2383a09c1441SScott Teel retry = 1; 2384c349775eSScott Teel break; 2385c349775eSScott Teel default: 2386a09c1441SScott Teel retry = 1; 2387c349775eSScott Teel break; 2388c349775eSScott Teel } 2389c349775eSScott Teel break; 2390c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_FAILURE: 2391c40820d5SJoe Handzik switch (c2->error_data.status) { 2392c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_IO_ERROR: 2393c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_IO_ABORTED: 2394c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_OVERRUN: 2395c40820d5SJoe Handzik retry = 1; 2396c40820d5SJoe Handzik break; 2397c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_UNDERRUN: 2398c40820d5SJoe Handzik cmd->result = (DID_OK << 16); /* host byte */ 2399c40820d5SJoe Handzik cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2400c40820d5SJoe Handzik ioaccel2_resid = get_unaligned_le32( 2401c40820d5SJoe Handzik &c2->error_data.resid_cnt[0]); 2402c40820d5SJoe Handzik scsi_set_resid(cmd, ioaccel2_resid); 2403c40820d5SJoe Handzik break; 2404c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: 2405c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_INVALID_DEVICE: 2406c40820d5SJoe Handzik case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: 2407ba74fdc4SDon Brace /* 2408ba74fdc4SDon Brace * Did an HBA disk disappear? We will eventually 2409ba74fdc4SDon Brace * get a state change event from the controller but 2410ba74fdc4SDon Brace * in the meantime, we need to tell the OS that the 2411ba74fdc4SDon Brace * HBA disk is no longer there and stop I/O 2412ba74fdc4SDon Brace * from going down. This allows the potential re-insert 2413ba74fdc4SDon Brace * of the disk to get the same device node. 2414ba74fdc4SDon Brace */ 2415ba74fdc4SDon Brace if (dev->physical_device && dev->expose_device) { 2416ba74fdc4SDon Brace cmd->result = DID_NO_CONNECT << 16; 2417ba74fdc4SDon Brace dev->removed = 1; 2418ba74fdc4SDon Brace h->drv_req_rescan = 1; 2419ba74fdc4SDon Brace dev_warn(&h->pdev->dev, 2420ba74fdc4SDon Brace "%s: device is gone!\n", __func__); 2421ba74fdc4SDon Brace } else 2422ba74fdc4SDon Brace /* 2423ba74fdc4SDon Brace * Retry by sending down the RAID path. 2424ba74fdc4SDon Brace * We will get an event from ctlr to 2425ba74fdc4SDon Brace * trigger rescan regardless. 2426ba74fdc4SDon Brace */ 2427c40820d5SJoe Handzik retry = 1; 2428c40820d5SJoe Handzik break; 2429c40820d5SJoe Handzik default: 2430c40820d5SJoe Handzik retry = 1; 2431c40820d5SJoe Handzik } 2432c349775eSScott Teel break; 2433c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: 2434c349775eSScott Teel break; 2435c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: 2436c349775eSScott Teel break; 2437c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: 2438a09c1441SScott Teel retry = 1; 2439c349775eSScott Teel break; 2440c349775eSScott Teel case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: 2441c349775eSScott Teel break; 2442c349775eSScott Teel default: 2443a09c1441SScott Teel retry = 1; 2444c349775eSScott Teel break; 2445c349775eSScott Teel } 2446a09c1441SScott Teel 2447c5dfd106SDon Brace if (dev->in_reset) 2448c5dfd106SDon Brace retry = 0; 2449c5dfd106SDon Brace 2450a09c1441SScott Teel return retry; /* retry on raid path? */ 2451c349775eSScott Teel } 2452c349775eSScott Teel 2453a58e7e53SWebb Scales static void hpsa_cmd_resolve_events(struct ctlr_info *h, 2454a58e7e53SWebb Scales struct CommandList *c) 2455a58e7e53SWebb Scales { 2456c5dfd106SDon Brace struct hpsa_scsi_dev_t *dev = c->device; 2457d604f533SWebb Scales 2458a58e7e53SWebb Scales /* 245908ec46f6SDon Brace * Reset c->scsi_cmd here so that the reset handler will know 2460d604f533SWebb Scales * this command has completed. Then, check to see if the handler is 2461a58e7e53SWebb Scales * waiting for this command, and, if so, wake it. 2462a58e7e53SWebb Scales */ 2463a58e7e53SWebb Scales c->scsi_cmd = SCSI_CMD_IDLE; 2464d604f533SWebb Scales mb(); /* Declare command idle before checking for pending events. */ 2465c5dfd106SDon Brace if (dev) { 2466c5dfd106SDon Brace atomic_dec(&dev->commands_outstanding); 2467c5dfd106SDon Brace if (dev->in_reset && 2468c5dfd106SDon Brace atomic_read(&dev->commands_outstanding) <= 0) 2469d604f533SWebb Scales wake_up_all(&h->event_sync_wait_queue); 2470a58e7e53SWebb Scales } 2471c5dfd106SDon Brace } 2472a58e7e53SWebb Scales 247373153fe5SWebb Scales static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, 247473153fe5SWebb Scales struct CommandList *c) 247573153fe5SWebb Scales { 247673153fe5SWebb Scales hpsa_cmd_resolve_events(h, c); 247773153fe5SWebb Scales cmd_tagged_free(h, c); 247873153fe5SWebb Scales } 247973153fe5SWebb Scales 24808a0ff92cSWebb Scales static void hpsa_cmd_free_and_done(struct ctlr_info *h, 24818a0ff92cSWebb Scales struct CommandList *c, struct scsi_cmnd *cmd) 24828a0ff92cSWebb Scales { 248373153fe5SWebb Scales hpsa_cmd_resolve_and_free(h, c); 2484d49c2077SDon Brace if (cmd && cmd->scsi_done) 24858a0ff92cSWebb Scales cmd->scsi_done(cmd); 24868a0ff92cSWebb Scales } 24878a0ff92cSWebb Scales 24888a0ff92cSWebb Scales static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) 24898a0ff92cSWebb Scales { 24908a0ff92cSWebb Scales INIT_WORK(&c->work, hpsa_command_resubmit_worker); 24918a0ff92cSWebb Scales queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); 24928a0ff92cSWebb Scales } 24938a0ff92cSWebb Scales 2494c349775eSScott Teel static void process_ioaccel2_completion(struct ctlr_info *h, 2495c349775eSScott Teel struct CommandList *c, struct scsi_cmnd *cmd, 2496c349775eSScott Teel struct hpsa_scsi_dev_t *dev) 2497c349775eSScott Teel { 2498c349775eSScott Teel struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 2499c349775eSScott Teel 2500c349775eSScott Teel /* check for good status */ 2501c349775eSScott Teel if (likely(c2->error_data.serv_response == 0 && 2502eeebce18SDon Brace c2->error_data.status == 0)) { 2503eeebce18SDon Brace cmd->result = 0; 25048a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, c, cmd); 2505eeebce18SDon Brace } 2506c349775eSScott Teel 25078a0ff92cSWebb Scales /* 25088a0ff92cSWebb Scales * Any RAID offload error results in retry which will use 2509b2582a65SDon Brace * the normal I/O path so the controller can handle whatever is 2510c349775eSScott Teel * wrong. 2511c349775eSScott Teel */ 2512f3f01730SKevin Barnett if (is_logical_device(dev) && 2513c349775eSScott Teel c2->error_data.serv_response == 2514c349775eSScott Teel IOACCEL2_SERV_RESPONSE_FAILURE) { 2515080ef1ccSDon Brace if (c2->error_data.status == 2516064d1b1dSDon Brace IOACCEL2_STATUS_SR_IOACCEL_DISABLED) { 25173e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(dev); 2518064d1b1dSDon Brace } 25198a0ff92cSWebb Scales 2520c5dfd106SDon Brace if (dev->in_reset) { 2521c5dfd106SDon Brace cmd->result = DID_RESET << 16; 2522c5dfd106SDon Brace return hpsa_cmd_free_and_done(h, c, cmd); 2523c5dfd106SDon Brace } 2524c5dfd106SDon Brace 25258a0ff92cSWebb Scales return hpsa_retry_cmd(h, c); 2526080ef1ccSDon Brace } 2527080ef1ccSDon Brace 2528ba74fdc4SDon Brace if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev)) 25298a0ff92cSWebb Scales return hpsa_retry_cmd(h, c); 2530080ef1ccSDon Brace 25318a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, c, cmd); 2532c349775eSScott Teel } 2533c349775eSScott Teel 25349437ac43SStephen Cameron /* Returns 0 on success, < 0 otherwise. */ 25359437ac43SStephen Cameron static int hpsa_evaluate_tmf_status(struct ctlr_info *h, 25369437ac43SStephen Cameron struct CommandList *cp) 25379437ac43SStephen Cameron { 25389437ac43SStephen Cameron u8 tmf_status = cp->err_info->ScsiStatus; 25399437ac43SStephen Cameron 25409437ac43SStephen Cameron switch (tmf_status) { 25419437ac43SStephen Cameron case CISS_TMF_COMPLETE: 25429437ac43SStephen Cameron /* 25439437ac43SStephen Cameron * CISS_TMF_COMPLETE never happens, instead, 25449437ac43SStephen Cameron * ei->CommandStatus == 0 for this case. 25459437ac43SStephen Cameron */ 25469437ac43SStephen Cameron case CISS_TMF_SUCCESS: 25479437ac43SStephen Cameron return 0; 25489437ac43SStephen Cameron case CISS_TMF_INVALID_FRAME: 25499437ac43SStephen Cameron case CISS_TMF_NOT_SUPPORTED: 25509437ac43SStephen Cameron case CISS_TMF_FAILED: 25519437ac43SStephen Cameron case CISS_TMF_WRONG_LUN: 25529437ac43SStephen Cameron case CISS_TMF_OVERLAPPED_TAG: 25539437ac43SStephen Cameron break; 25549437ac43SStephen Cameron default: 25559437ac43SStephen Cameron dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", 25569437ac43SStephen Cameron tmf_status); 25579437ac43SStephen Cameron break; 25589437ac43SStephen Cameron } 25599437ac43SStephen Cameron return -tmf_status; 25609437ac43SStephen Cameron } 25619437ac43SStephen Cameron 25621fb011fbSStephen M. Cameron static void complete_scsi_command(struct CommandList *cp) 2563edd16368SStephen M. Cameron { 2564edd16368SStephen M. Cameron struct scsi_cmnd *cmd; 2565edd16368SStephen M. Cameron struct ctlr_info *h; 2566edd16368SStephen M. Cameron struct ErrorInfo *ei; 2567283b4a9bSStephen M. Cameron struct hpsa_scsi_dev_t *dev; 2568d9a729f3SWebb Scales struct io_accel2_cmd *c2; 2569edd16368SStephen M. Cameron 25709437ac43SStephen Cameron u8 sense_key; 25719437ac43SStephen Cameron u8 asc; /* additional sense code */ 25729437ac43SStephen Cameron u8 ascq; /* additional sense code qualifier */ 2573db111e18SStephen M. Cameron unsigned long sense_data_size; 2574edd16368SStephen M. Cameron 2575edd16368SStephen M. Cameron ei = cp->err_info; 25767fa3030cSStephen Cameron cmd = cp->scsi_cmd; 2577edd16368SStephen M. Cameron h = cp->h; 2578d49c2077SDon Brace 2579d49c2077SDon Brace if (!cmd->device) { 2580d49c2077SDon Brace cmd->result = DID_NO_CONNECT << 16; 2581d49c2077SDon Brace return hpsa_cmd_free_and_done(h, cp, cmd); 2582d49c2077SDon Brace } 2583d49c2077SDon Brace 2584283b4a9bSStephen M. Cameron dev = cmd->device->hostdata; 258545e596cdSDon Brace if (!dev) { 258645e596cdSDon Brace cmd->result = DID_NO_CONNECT << 16; 258745e596cdSDon Brace return hpsa_cmd_free_and_done(h, cp, cmd); 258845e596cdSDon Brace } 2589d9a729f3SWebb Scales c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; 2590edd16368SStephen M. Cameron 2591edd16368SStephen M. Cameron scsi_dma_unmap(cmd); /* undo the DMA mappings */ 2592e1f7de0cSMatt Gates if ((cp->cmd_type == CMD_SCSI) && 25932b08b3e9SDon Brace (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) 259433a2ffceSStephen M. Cameron hpsa_unmap_sg_chain_block(h, cp); 2595edd16368SStephen M. Cameron 2596d9a729f3SWebb Scales if ((cp->cmd_type == CMD_IOACCEL2) && 2597d9a729f3SWebb Scales (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) 2598d9a729f3SWebb Scales hpsa_unmap_ioaccel2_sg_chain_block(h, c2); 2599d9a729f3SWebb Scales 2600edd16368SStephen M. Cameron cmd->result = (DID_OK << 16); /* host byte */ 2601edd16368SStephen M. Cameron cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2602c349775eSScott Teel 26039e33f0d5SDon Brace /* SCSI command has already been cleaned up in SML */ 26049e33f0d5SDon Brace if (dev->was_removed) { 26059e33f0d5SDon Brace hpsa_cmd_resolve_and_free(h, cp); 26069e33f0d5SDon Brace return; 26079e33f0d5SDon Brace } 26089e33f0d5SDon Brace 2609d49c2077SDon Brace if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) { 2610d49c2077SDon Brace if (dev->physical_device && dev->expose_device && 2611d49c2077SDon Brace dev->removed) { 2612d49c2077SDon Brace cmd->result = DID_NO_CONNECT << 16; 2613d49c2077SDon Brace return hpsa_cmd_free_and_done(h, cp, cmd); 2614d49c2077SDon Brace } 2615d49c2077SDon Brace if (likely(cp->phys_disk != NULL)) 261603383736SDon Brace atomic_dec(&cp->phys_disk->ioaccel_cmds_out); 2617d49c2077SDon Brace } 261803383736SDon Brace 261925163bd5SWebb Scales /* 262025163bd5SWebb Scales * We check for lockup status here as it may be set for 262125163bd5SWebb Scales * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by 262225163bd5SWebb Scales * fail_all_oustanding_cmds() 262325163bd5SWebb Scales */ 262425163bd5SWebb Scales if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { 262525163bd5SWebb Scales /* DID_NO_CONNECT will prevent a retry */ 262625163bd5SWebb Scales cmd->result = DID_NO_CONNECT << 16; 26278a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, cp, cmd); 262825163bd5SWebb Scales } 262925163bd5SWebb Scales 2630c349775eSScott Teel if (cp->cmd_type == CMD_IOACCEL2) 2631c349775eSScott Teel return process_ioaccel2_completion(h, cp, cmd, dev); 2632c349775eSScott Teel 26336aa4c361SRobert Elliott scsi_set_resid(cmd, ei->ResidualCnt); 26348a0ff92cSWebb Scales if (ei->CommandStatus == 0) 26358a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, cp, cmd); 26366aa4c361SRobert Elliott 2637e1f7de0cSMatt Gates /* For I/O accelerator commands, copy over some fields to the normal 2638e1f7de0cSMatt Gates * CISS header used below for error handling. 2639e1f7de0cSMatt Gates */ 2640e1f7de0cSMatt Gates if (cp->cmd_type == CMD_IOACCEL1) { 2641e1f7de0cSMatt Gates struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; 26422b08b3e9SDon Brace cp->Header.SGList = scsi_sg_count(cmd); 26432b08b3e9SDon Brace cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); 26442b08b3e9SDon Brace cp->Request.CDBLen = le16_to_cpu(c->io_flags) & 26452b08b3e9SDon Brace IOACCEL1_IOFLAGS_CDBLEN_MASK; 264650a0decfSStephen M. Cameron cp->Header.tag = c->tag; 2647e1f7de0cSMatt Gates memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); 2648e1f7de0cSMatt Gates memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); 2649283b4a9bSStephen M. Cameron 2650283b4a9bSStephen M. Cameron /* Any RAID offload error results in retry which will use 2651283b4a9bSStephen M. Cameron * the normal I/O path so the controller can handle whatever's 2652283b4a9bSStephen M. Cameron * wrong. 2653283b4a9bSStephen M. Cameron */ 2654f3f01730SKevin Barnett if (is_logical_device(dev)) { 2655283b4a9bSStephen M. Cameron if (ei->CommandStatus == CMD_IOACCEL_DISABLED) 2656283b4a9bSStephen M. Cameron dev->offload_enabled = 0; 26578a0ff92cSWebb Scales return hpsa_retry_cmd(h, cp); 2658283b4a9bSStephen M. Cameron } 2659e1f7de0cSMatt Gates } 2660e1f7de0cSMatt Gates 2661edd16368SStephen M. Cameron /* an error has occurred */ 2662edd16368SStephen M. Cameron switch (ei->CommandStatus) { 2663edd16368SStephen M. Cameron 2664edd16368SStephen M. Cameron case CMD_TARGET_STATUS: 26659437ac43SStephen Cameron cmd->result |= ei->ScsiStatus; 26669437ac43SStephen Cameron /* copy the sense data */ 26679437ac43SStephen Cameron if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) 26689437ac43SStephen Cameron sense_data_size = SCSI_SENSE_BUFFERSIZE; 26699437ac43SStephen Cameron else 26709437ac43SStephen Cameron sense_data_size = sizeof(ei->SenseInfo); 26719437ac43SStephen Cameron if (ei->SenseLen < sense_data_size) 26729437ac43SStephen Cameron sense_data_size = ei->SenseLen; 26739437ac43SStephen Cameron memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); 26749437ac43SStephen Cameron if (ei->ScsiStatus) 26759437ac43SStephen Cameron decode_sense_data(ei->SenseInfo, sense_data_size, 26769437ac43SStephen Cameron &sense_key, &asc, &ascq); 2677edd16368SStephen M. Cameron if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { 267849ea45cbSDon Brace switch (sense_key) { 267949ea45cbSDon Brace case ABORTED_COMMAND: 26802e311fbaSStephen M. Cameron cmd->result |= DID_SOFT_ERROR << 16; 26811d3b3609SMatt Gates break; 268249ea45cbSDon Brace case UNIT_ATTENTION: 268349ea45cbSDon Brace if (asc == 0x3F && ascq == 0x0E) 268449ea45cbSDon Brace h->drv_req_rescan = 1; 268549ea45cbSDon Brace break; 268649ea45cbSDon Brace case ILLEGAL_REQUEST: 268749ea45cbSDon Brace if (asc == 0x25 && ascq == 0x00) { 268849ea45cbSDon Brace dev->removed = 1; 268949ea45cbSDon Brace cmd->result = DID_NO_CONNECT << 16; 269049ea45cbSDon Brace } 269149ea45cbSDon Brace break; 26921d3b3609SMatt Gates } 2693edd16368SStephen M. Cameron break; 2694edd16368SStephen M. Cameron } 2695edd16368SStephen M. Cameron /* Problem was not a check condition 2696edd16368SStephen M. Cameron * Pass it up to the upper layers... 2697edd16368SStephen M. Cameron */ 2698edd16368SStephen M. Cameron if (ei->ScsiStatus) { 2699edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "cp %p has status 0x%x " 2700edd16368SStephen M. Cameron "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " 2701edd16368SStephen M. Cameron "Returning result: 0x%x\n", 2702edd16368SStephen M. Cameron cp, ei->ScsiStatus, 2703edd16368SStephen M. Cameron sense_key, asc, ascq, 2704edd16368SStephen M. Cameron cmd->result); 2705edd16368SStephen M. Cameron } else { /* scsi status is zero??? How??? */ 2706edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " 2707edd16368SStephen M. Cameron "Returning no connection.\n", cp), 2708edd16368SStephen M. Cameron 2709edd16368SStephen M. Cameron /* Ordinarily, this case should never happen, 2710edd16368SStephen M. Cameron * but there is a bug in some released firmware 2711edd16368SStephen M. Cameron * revisions that allows it to happen if, for 2712edd16368SStephen M. Cameron * example, a 4100 backplane loses power and 2713edd16368SStephen M. Cameron * the tape drive is in it. We assume that 2714edd16368SStephen M. Cameron * it's a fatal error of some kind because we 2715edd16368SStephen M. Cameron * can't show that it wasn't. We will make it 2716edd16368SStephen M. Cameron * look like selection timeout since that is 2717edd16368SStephen M. Cameron * the most common reason for this to occur, 2718edd16368SStephen M. Cameron * and it's severe enough. 2719edd16368SStephen M. Cameron */ 2720edd16368SStephen M. Cameron 2721edd16368SStephen M. Cameron cmd->result = DID_NO_CONNECT << 16; 2722edd16368SStephen M. Cameron } 2723edd16368SStephen M. Cameron break; 2724edd16368SStephen M. Cameron 2725edd16368SStephen M. Cameron case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2726edd16368SStephen M. Cameron break; 2727edd16368SStephen M. Cameron case CMD_DATA_OVERRUN: 2728f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, 2729f42e81e1SStephen Cameron "CDB %16phN data overrun\n", cp->Request.CDB); 2730edd16368SStephen M. Cameron break; 2731edd16368SStephen M. Cameron case CMD_INVALID: { 2732edd16368SStephen M. Cameron /* print_bytes(cp, sizeof(*cp), 1, 0); 2733edd16368SStephen M. Cameron print_cmd(cp); */ 2734edd16368SStephen M. Cameron /* We get CMD_INVALID if you address a non-existent device 2735edd16368SStephen M. Cameron * instead of a selection timeout (no response). You will 2736edd16368SStephen M. Cameron * see this if you yank out a drive, then try to access it. 2737edd16368SStephen M. Cameron * This is kind of a shame because it means that any other 2738edd16368SStephen M. Cameron * CMD_INVALID (e.g. driver bug) will get interpreted as a 2739edd16368SStephen M. Cameron * missing target. */ 2740edd16368SStephen M. Cameron cmd->result = DID_NO_CONNECT << 16; 2741edd16368SStephen M. Cameron } 2742edd16368SStephen M. Cameron break; 2743edd16368SStephen M. Cameron case CMD_PROTOCOL_ERR: 2744256d0eaaSStephen M. Cameron cmd->result = DID_ERROR << 16; 2745f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", 2746f42e81e1SStephen Cameron cp->Request.CDB); 2747edd16368SStephen M. Cameron break; 2748edd16368SStephen M. Cameron case CMD_HARDWARE_ERR: 2749edd16368SStephen M. Cameron cmd->result = DID_ERROR << 16; 2750f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", 2751f42e81e1SStephen Cameron cp->Request.CDB); 2752edd16368SStephen M. Cameron break; 2753edd16368SStephen M. Cameron case CMD_CONNECTION_LOST: 2754edd16368SStephen M. Cameron cmd->result = DID_ERROR << 16; 2755f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", 2756f42e81e1SStephen Cameron cp->Request.CDB); 2757edd16368SStephen M. Cameron break; 2758edd16368SStephen M. Cameron case CMD_ABORTED: 275908ec46f6SDon Brace cmd->result = DID_ABORT << 16; 276008ec46f6SDon Brace break; 2761edd16368SStephen M. Cameron case CMD_ABORT_FAILED: 2762edd16368SStephen M. Cameron cmd->result = DID_ERROR << 16; 2763f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", 2764f42e81e1SStephen Cameron cp->Request.CDB); 2765edd16368SStephen M. Cameron break; 2766edd16368SStephen M. Cameron case CMD_UNSOLICITED_ABORT: 2767f6e76055SStephen M. Cameron cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ 2768f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", 2769f42e81e1SStephen Cameron cp->Request.CDB); 2770edd16368SStephen M. Cameron break; 2771edd16368SStephen M. Cameron case CMD_TIMEOUT: 2772edd16368SStephen M. Cameron cmd->result = DID_TIME_OUT << 16; 2773f42e81e1SStephen Cameron dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", 2774f42e81e1SStephen Cameron cp->Request.CDB); 2775edd16368SStephen M. Cameron break; 27761d5e2ed0SStephen M. Cameron case CMD_UNABORTABLE: 27771d5e2ed0SStephen M. Cameron cmd->result = DID_ERROR << 16; 27781d5e2ed0SStephen M. Cameron dev_warn(&h->pdev->dev, "Command unabortable\n"); 27791d5e2ed0SStephen M. Cameron break; 27809437ac43SStephen Cameron case CMD_TMF_STATUS: 27819437ac43SStephen Cameron if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ 27829437ac43SStephen Cameron cmd->result = DID_ERROR << 16; 27839437ac43SStephen Cameron break; 2784283b4a9bSStephen M. Cameron case CMD_IOACCEL_DISABLED: 2785283b4a9bSStephen M. Cameron /* This only handles the direct pass-through case since RAID 2786283b4a9bSStephen M. Cameron * offload is handled above. Just attempt a retry. 2787283b4a9bSStephen M. Cameron */ 2788283b4a9bSStephen M. Cameron cmd->result = DID_SOFT_ERROR << 16; 2789283b4a9bSStephen M. Cameron dev_warn(&h->pdev->dev, 2790283b4a9bSStephen M. Cameron "cp %p had HP SSD Smart Path error\n", cp); 2791283b4a9bSStephen M. Cameron break; 2792edd16368SStephen M. Cameron default: 2793edd16368SStephen M. Cameron cmd->result = DID_ERROR << 16; 2794edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", 2795edd16368SStephen M. Cameron cp, ei->CommandStatus); 2796edd16368SStephen M. Cameron } 27978a0ff92cSWebb Scales 27988a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, cp, cmd); 2799edd16368SStephen M. Cameron } 2800edd16368SStephen M. Cameron 28018bc8f47eSChristoph Hellwig static void hpsa_pci_unmap(struct pci_dev *pdev, struct CommandList *c, 28028bc8f47eSChristoph Hellwig int sg_used, enum dma_data_direction data_direction) 2803edd16368SStephen M. Cameron { 2804edd16368SStephen M. Cameron int i; 2805edd16368SStephen M. Cameron 280650a0decfSStephen M. Cameron for (i = 0; i < sg_used; i++) 28078bc8f47eSChristoph Hellwig dma_unmap_single(&pdev->dev, le64_to_cpu(c->SG[i].Addr), 280850a0decfSStephen M. Cameron le32_to_cpu(c->SG[i].Len), 2809edd16368SStephen M. Cameron data_direction); 2810edd16368SStephen M. Cameron } 2811edd16368SStephen M. Cameron 2812a2dac136SStephen M. Cameron static int hpsa_map_one(struct pci_dev *pdev, 2813edd16368SStephen M. Cameron struct CommandList *cp, 2814edd16368SStephen M. Cameron unsigned char *buf, 2815edd16368SStephen M. Cameron size_t buflen, 28168bc8f47eSChristoph Hellwig enum dma_data_direction data_direction) 2817edd16368SStephen M. Cameron { 281801a02ffcSStephen M. Cameron u64 addr64; 2819edd16368SStephen M. Cameron 28208bc8f47eSChristoph Hellwig if (buflen == 0 || data_direction == DMA_NONE) { 2821edd16368SStephen M. Cameron cp->Header.SGList = 0; 282250a0decfSStephen M. Cameron cp->Header.SGTotal = cpu_to_le16(0); 2823a2dac136SStephen M. Cameron return 0; 2824edd16368SStephen M. Cameron } 2825edd16368SStephen M. Cameron 28268bc8f47eSChristoph Hellwig addr64 = dma_map_single(&pdev->dev, buf, buflen, data_direction); 2827eceaae18SShuah Khan if (dma_mapping_error(&pdev->dev, addr64)) { 2828a2dac136SStephen M. Cameron /* Prevent subsequent unmap of something never mapped */ 2829eceaae18SShuah Khan cp->Header.SGList = 0; 283050a0decfSStephen M. Cameron cp->Header.SGTotal = cpu_to_le16(0); 2831a2dac136SStephen M. Cameron return -1; 2832eceaae18SShuah Khan } 283350a0decfSStephen M. Cameron cp->SG[0].Addr = cpu_to_le64(addr64); 283450a0decfSStephen M. Cameron cp->SG[0].Len = cpu_to_le32(buflen); 283550a0decfSStephen M. Cameron cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ 283650a0decfSStephen M. Cameron cp->Header.SGList = 1; /* no. SGs contig in this cmd */ 283750a0decfSStephen M. Cameron cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ 2838a2dac136SStephen M. Cameron return 0; 2839edd16368SStephen M. Cameron } 2840edd16368SStephen M. Cameron 284125163bd5SWebb Scales #define NO_TIMEOUT ((unsigned long) -1) 284225163bd5SWebb Scales #define DEFAULT_TIMEOUT 30000 /* milliseconds */ 284325163bd5SWebb Scales static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, 284425163bd5SWebb Scales struct CommandList *c, int reply_queue, unsigned long timeout_msecs) 2845edd16368SStephen M. Cameron { 2846edd16368SStephen M. Cameron DECLARE_COMPLETION_ONSTACK(wait); 2847edd16368SStephen M. Cameron 2848edd16368SStephen M. Cameron c->waiting = &wait; 284925163bd5SWebb Scales __enqueue_cmd_and_start_io(h, c, reply_queue); 285025163bd5SWebb Scales if (timeout_msecs == NO_TIMEOUT) { 285125163bd5SWebb Scales /* TODO: get rid of this no-timeout thing */ 285225163bd5SWebb Scales wait_for_completion_io(&wait); 285325163bd5SWebb Scales return IO_OK; 285425163bd5SWebb Scales } 285525163bd5SWebb Scales if (!wait_for_completion_io_timeout(&wait, 285625163bd5SWebb Scales msecs_to_jiffies(timeout_msecs))) { 285725163bd5SWebb Scales dev_warn(&h->pdev->dev, "Command timed out.\n"); 285825163bd5SWebb Scales return -ETIMEDOUT; 285925163bd5SWebb Scales } 286025163bd5SWebb Scales return IO_OK; 286125163bd5SWebb Scales } 286225163bd5SWebb Scales 286325163bd5SWebb Scales static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, 286425163bd5SWebb Scales int reply_queue, unsigned long timeout_msecs) 286525163bd5SWebb Scales { 286625163bd5SWebb Scales if (unlikely(lockup_detected(h))) { 286725163bd5SWebb Scales c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 286825163bd5SWebb Scales return IO_OK; 286925163bd5SWebb Scales } 287025163bd5SWebb Scales return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); 2871edd16368SStephen M. Cameron } 2872edd16368SStephen M. Cameron 2873094963daSStephen M. Cameron static u32 lockup_detected(struct ctlr_info *h) 2874094963daSStephen M. Cameron { 2875094963daSStephen M. Cameron int cpu; 2876094963daSStephen M. Cameron u32 rc, *lockup_detected; 2877094963daSStephen M. Cameron 2878094963daSStephen M. Cameron cpu = get_cpu(); 2879094963daSStephen M. Cameron lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 2880094963daSStephen M. Cameron rc = *lockup_detected; 2881094963daSStephen M. Cameron put_cpu(); 2882094963daSStephen M. Cameron return rc; 2883094963daSStephen M. Cameron } 2884094963daSStephen M. Cameron 28859c2fc160SStephen M. Cameron #define MAX_DRIVER_CMD_RETRIES 25 288625163bd5SWebb Scales static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, 28878bc8f47eSChristoph Hellwig struct CommandList *c, enum dma_data_direction data_direction, 28888bc8f47eSChristoph Hellwig unsigned long timeout_msecs) 2889edd16368SStephen M. Cameron { 28909c2fc160SStephen M. Cameron int backoff_time = 10, retry_count = 0; 289125163bd5SWebb Scales int rc; 2892edd16368SStephen M. Cameron 2893edd16368SStephen M. Cameron do { 28947630abd0SJoe Perches memset(c->err_info, 0, sizeof(*c->err_info)); 289525163bd5SWebb Scales rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 289625163bd5SWebb Scales timeout_msecs); 289725163bd5SWebb Scales if (rc) 289825163bd5SWebb Scales break; 2899edd16368SStephen M. Cameron retry_count++; 29009c2fc160SStephen M. Cameron if (retry_count > 3) { 29019c2fc160SStephen M. Cameron msleep(backoff_time); 29029c2fc160SStephen M. Cameron if (backoff_time < 1000) 29039c2fc160SStephen M. Cameron backoff_time *= 2; 29049c2fc160SStephen M. Cameron } 2905852af20aSMatt Bondurant } while ((check_for_unit_attention(h, c) || 29069c2fc160SStephen M. Cameron check_for_busy(h, c)) && 29079c2fc160SStephen M. Cameron retry_count <= MAX_DRIVER_CMD_RETRIES); 2908edd16368SStephen M. Cameron hpsa_pci_unmap(h->pdev, c, 1, data_direction); 290925163bd5SWebb Scales if (retry_count > MAX_DRIVER_CMD_RETRIES) 291025163bd5SWebb Scales rc = -EIO; 291125163bd5SWebb Scales return rc; 2912edd16368SStephen M. Cameron } 2913edd16368SStephen M. Cameron 2914d1e8beacSStephen M. Cameron static void hpsa_print_cmd(struct ctlr_info *h, char *txt, 2915d1e8beacSStephen M. Cameron struct CommandList *c) 2916edd16368SStephen M. Cameron { 2917d1e8beacSStephen M. Cameron const u8 *cdb = c->Request.CDB; 2918d1e8beacSStephen M. Cameron const u8 *lun = c->Header.LUN.LunAddrBytes; 2919edd16368SStephen M. Cameron 2920609a70dfSRasmus Villemoes dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n", 2921609a70dfSRasmus Villemoes txt, lun, cdb); 2922d1e8beacSStephen M. Cameron } 2923d1e8beacSStephen M. Cameron 2924d1e8beacSStephen M. Cameron static void hpsa_scsi_interpret_error(struct ctlr_info *h, 2925d1e8beacSStephen M. Cameron struct CommandList *cp) 2926d1e8beacSStephen M. Cameron { 2927d1e8beacSStephen M. Cameron const struct ErrorInfo *ei = cp->err_info; 2928d1e8beacSStephen M. Cameron struct device *d = &cp->h->pdev->dev; 29299437ac43SStephen Cameron u8 sense_key, asc, ascq; 29309437ac43SStephen Cameron int sense_len; 2931d1e8beacSStephen M. Cameron 2932edd16368SStephen M. Cameron switch (ei->CommandStatus) { 2933edd16368SStephen M. Cameron case CMD_TARGET_STATUS: 29349437ac43SStephen Cameron if (ei->SenseLen > sizeof(ei->SenseInfo)) 29359437ac43SStephen Cameron sense_len = sizeof(ei->SenseInfo); 29369437ac43SStephen Cameron else 29379437ac43SStephen Cameron sense_len = ei->SenseLen; 29389437ac43SStephen Cameron decode_sense_data(ei->SenseInfo, sense_len, 29399437ac43SStephen Cameron &sense_key, &asc, &ascq); 2940d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "SCSI status", cp); 2941d1e8beacSStephen M. Cameron if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) 29429437ac43SStephen Cameron dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", 29439437ac43SStephen Cameron sense_key, asc, ascq); 2944d1e8beacSStephen M. Cameron else 29459437ac43SStephen Cameron dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); 2946edd16368SStephen M. Cameron if (ei->ScsiStatus == 0) 2947edd16368SStephen M. Cameron dev_warn(d, "SCSI status is abnormally zero. " 2948edd16368SStephen M. Cameron "(probably indicates selection timeout " 2949edd16368SStephen M. Cameron "reported incorrectly due to a known " 2950edd16368SStephen M. Cameron "firmware bug, circa July, 2001.)\n"); 2951edd16368SStephen M. Cameron break; 2952edd16368SStephen M. Cameron case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2953edd16368SStephen M. Cameron break; 2954edd16368SStephen M. Cameron case CMD_DATA_OVERRUN: 2955d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "overrun condition", cp); 2956edd16368SStephen M. Cameron break; 2957edd16368SStephen M. Cameron case CMD_INVALID: { 2958edd16368SStephen M. Cameron /* controller unfortunately reports SCSI passthru's 2959edd16368SStephen M. Cameron * to non-existent targets as invalid commands. 2960edd16368SStephen M. Cameron */ 2961d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "invalid command", cp); 2962d1e8beacSStephen M. Cameron dev_warn(d, "probably means device no longer present\n"); 2963edd16368SStephen M. Cameron } 2964edd16368SStephen M. Cameron break; 2965edd16368SStephen M. Cameron case CMD_PROTOCOL_ERR: 2966d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "protocol error", cp); 2967edd16368SStephen M. Cameron break; 2968edd16368SStephen M. Cameron case CMD_HARDWARE_ERR: 2969d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "hardware error", cp); 2970edd16368SStephen M. Cameron break; 2971edd16368SStephen M. Cameron case CMD_CONNECTION_LOST: 2972d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "connection lost", cp); 2973edd16368SStephen M. Cameron break; 2974edd16368SStephen M. Cameron case CMD_ABORTED: 2975d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "aborted", cp); 2976edd16368SStephen M. Cameron break; 2977edd16368SStephen M. Cameron case CMD_ABORT_FAILED: 2978d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "abort failed", cp); 2979edd16368SStephen M. Cameron break; 2980edd16368SStephen M. Cameron case CMD_UNSOLICITED_ABORT: 2981d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "unsolicited abort", cp); 2982edd16368SStephen M. Cameron break; 2983edd16368SStephen M. Cameron case CMD_TIMEOUT: 2984d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "timed out", cp); 2985edd16368SStephen M. Cameron break; 29861d5e2ed0SStephen M. Cameron case CMD_UNABORTABLE: 2987d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "unabortable", cp); 29881d5e2ed0SStephen M. Cameron break; 298925163bd5SWebb Scales case CMD_CTLR_LOCKUP: 299025163bd5SWebb Scales hpsa_print_cmd(h, "controller lockup detected", cp); 299125163bd5SWebb Scales break; 2992edd16368SStephen M. Cameron default: 2993d1e8beacSStephen M. Cameron hpsa_print_cmd(h, "unknown status", cp); 2994d1e8beacSStephen M. Cameron dev_warn(d, "Unknown command status %x\n", 2995edd16368SStephen M. Cameron ei->CommandStatus); 2996edd16368SStephen M. Cameron } 2997edd16368SStephen M. Cameron } 2998edd16368SStephen M. Cameron 29990a7c3bb8SDon Brace static int hpsa_do_receive_diagnostic(struct ctlr_info *h, u8 *scsi3addr, 30000a7c3bb8SDon Brace u8 page, u8 *buf, size_t bufsize) 30010a7c3bb8SDon Brace { 30020a7c3bb8SDon Brace int rc = IO_OK; 30030a7c3bb8SDon Brace struct CommandList *c; 30040a7c3bb8SDon Brace struct ErrorInfo *ei; 30050a7c3bb8SDon Brace 30060a7c3bb8SDon Brace c = cmd_alloc(h); 30070a7c3bb8SDon Brace if (fill_cmd(c, RECEIVE_DIAGNOSTIC, h, buf, bufsize, 30080a7c3bb8SDon Brace page, scsi3addr, TYPE_CMD)) { 30090a7c3bb8SDon Brace rc = -1; 30100a7c3bb8SDon Brace goto out; 30110a7c3bb8SDon Brace } 30128bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 30138bc8f47eSChristoph Hellwig NO_TIMEOUT); 30140a7c3bb8SDon Brace if (rc) 30150a7c3bb8SDon Brace goto out; 30160a7c3bb8SDon Brace ei = c->err_info; 30170a7c3bb8SDon Brace if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 30180a7c3bb8SDon Brace hpsa_scsi_interpret_error(h, c); 30190a7c3bb8SDon Brace rc = -1; 30200a7c3bb8SDon Brace } 30210a7c3bb8SDon Brace out: 30220a7c3bb8SDon Brace cmd_free(h, c); 30230a7c3bb8SDon Brace return rc; 30240a7c3bb8SDon Brace } 30250a7c3bb8SDon Brace 30260a7c3bb8SDon Brace static u64 hpsa_get_enclosure_logical_identifier(struct ctlr_info *h, 30270a7c3bb8SDon Brace u8 *scsi3addr) 30280a7c3bb8SDon Brace { 30290a7c3bb8SDon Brace u8 *buf; 30300a7c3bb8SDon Brace u64 sa = 0; 30310a7c3bb8SDon Brace int rc = 0; 30320a7c3bb8SDon Brace 30330a7c3bb8SDon Brace buf = kzalloc(1024, GFP_KERNEL); 30340a7c3bb8SDon Brace if (!buf) 30350a7c3bb8SDon Brace return 0; 30360a7c3bb8SDon Brace 30370a7c3bb8SDon Brace rc = hpsa_do_receive_diagnostic(h, scsi3addr, RECEIVE_DIAGNOSTIC, 30380a7c3bb8SDon Brace buf, 1024); 30390a7c3bb8SDon Brace 30400a7c3bb8SDon Brace if (rc) 30410a7c3bb8SDon Brace goto out; 30420a7c3bb8SDon Brace 30430a7c3bb8SDon Brace sa = get_unaligned_be64(buf+12); 30440a7c3bb8SDon Brace 30450a7c3bb8SDon Brace out: 30460a7c3bb8SDon Brace kfree(buf); 30470a7c3bb8SDon Brace return sa; 30480a7c3bb8SDon Brace } 30490a7c3bb8SDon Brace 3050edd16368SStephen M. Cameron static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, 3051b7bb24ebSStephen M. Cameron u16 page, unsigned char *buf, 3052edd16368SStephen M. Cameron unsigned char bufsize) 3053edd16368SStephen M. Cameron { 3054edd16368SStephen M. Cameron int rc = IO_OK; 3055edd16368SStephen M. Cameron struct CommandList *c; 3056edd16368SStephen M. Cameron struct ErrorInfo *ei; 3057edd16368SStephen M. Cameron 305845fcb86eSStephen Cameron c = cmd_alloc(h); 3059edd16368SStephen M. Cameron 3060a2dac136SStephen M. Cameron if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, 3061a2dac136SStephen M. Cameron page, scsi3addr, TYPE_CMD)) { 3062a2dac136SStephen M. Cameron rc = -1; 3063a2dac136SStephen M. Cameron goto out; 3064a2dac136SStephen M. Cameron } 30658bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 30668bc8f47eSChristoph Hellwig NO_TIMEOUT); 306725163bd5SWebb Scales if (rc) 306825163bd5SWebb Scales goto out; 3069edd16368SStephen M. Cameron ei = c->err_info; 3070edd16368SStephen M. Cameron if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3071d1e8beacSStephen M. Cameron hpsa_scsi_interpret_error(h, c); 3072edd16368SStephen M. Cameron rc = -1; 3073edd16368SStephen M. Cameron } 3074a2dac136SStephen M. Cameron out: 307545fcb86eSStephen Cameron cmd_free(h, c); 3076edd16368SStephen M. Cameron return rc; 3077edd16368SStephen M. Cameron } 3078edd16368SStephen M. Cameron 3079c5dfd106SDon Brace static int hpsa_send_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, 308025163bd5SWebb Scales u8 reset_type, int reply_queue) 3081edd16368SStephen M. Cameron { 3082edd16368SStephen M. Cameron int rc = IO_OK; 3083edd16368SStephen M. Cameron struct CommandList *c; 3084edd16368SStephen M. Cameron struct ErrorInfo *ei; 3085edd16368SStephen M. Cameron 308645fcb86eSStephen Cameron c = cmd_alloc(h); 3087c5dfd106SDon Brace c->device = dev; 3088edd16368SStephen M. Cameron 3089a2dac136SStephen M. Cameron /* fill_cmd can't fail here, no data buffer to map. */ 3090c5dfd106SDon Brace (void) fill_cmd(c, reset_type, h, NULL, 0, 0, dev->scsi3addr, TYPE_MSG); 30912ef28849SDon Brace rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); 309225163bd5SWebb Scales if (rc) { 309325163bd5SWebb Scales dev_warn(&h->pdev->dev, "Failed to send reset command\n"); 309425163bd5SWebb Scales goto out; 309525163bd5SWebb Scales } 3096edd16368SStephen M. Cameron /* no unmap needed here because no data xfer. */ 3097edd16368SStephen M. Cameron 3098edd16368SStephen M. Cameron ei = c->err_info; 3099edd16368SStephen M. Cameron if (ei->CommandStatus != 0) { 3100d1e8beacSStephen M. Cameron hpsa_scsi_interpret_error(h, c); 3101edd16368SStephen M. Cameron rc = -1; 3102edd16368SStephen M. Cameron } 310325163bd5SWebb Scales out: 310445fcb86eSStephen Cameron cmd_free(h, c); 3105edd16368SStephen M. Cameron return rc; 3106edd16368SStephen M. Cameron } 3107edd16368SStephen M. Cameron 3108d604f533SWebb Scales static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 3109d604f533SWebb Scales struct hpsa_scsi_dev_t *dev, 3110d604f533SWebb Scales unsigned char *scsi3addr) 3111d604f533SWebb Scales { 3112d604f533SWebb Scales int i; 3113d604f533SWebb Scales bool match = false; 3114d604f533SWebb Scales struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 3115d604f533SWebb Scales struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; 3116d604f533SWebb Scales 3117d604f533SWebb Scales if (hpsa_is_cmd_idle(c)) 3118d604f533SWebb Scales return false; 3119d604f533SWebb Scales 3120d604f533SWebb Scales switch (c->cmd_type) { 3121d604f533SWebb Scales case CMD_SCSI: 3122d604f533SWebb Scales case CMD_IOCTL_PEND: 3123d604f533SWebb Scales match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, 3124d604f533SWebb Scales sizeof(c->Header.LUN.LunAddrBytes)); 3125d604f533SWebb Scales break; 3126d604f533SWebb Scales 3127d604f533SWebb Scales case CMD_IOACCEL1: 3128d604f533SWebb Scales case CMD_IOACCEL2: 3129d604f533SWebb Scales if (c->phys_disk == dev) { 3130d604f533SWebb Scales /* HBA mode match */ 3131d604f533SWebb Scales match = true; 3132d604f533SWebb Scales } else { 3133d604f533SWebb Scales /* Possible RAID mode -- check each phys dev. */ 3134d604f533SWebb Scales /* FIXME: Do we need to take out a lock here? If 3135d604f533SWebb Scales * so, we could just call hpsa_get_pdisk_of_ioaccel2() 3136d604f533SWebb Scales * instead. */ 3137d604f533SWebb Scales for (i = 0; i < dev->nphysical_disks && !match; i++) { 3138d604f533SWebb Scales /* FIXME: an alternate test might be 3139d604f533SWebb Scales * 3140d604f533SWebb Scales * match = dev->phys_disk[i]->ioaccel_handle 3141d604f533SWebb Scales * == c2->scsi_nexus; */ 3142d604f533SWebb Scales match = dev->phys_disk[i] == c->phys_disk; 3143d604f533SWebb Scales } 3144d604f533SWebb Scales } 3145d604f533SWebb Scales break; 3146d604f533SWebb Scales 3147d604f533SWebb Scales case IOACCEL2_TMF: 3148d604f533SWebb Scales for (i = 0; i < dev->nphysical_disks && !match; i++) { 3149d604f533SWebb Scales match = dev->phys_disk[i]->ioaccel_handle == 3150d604f533SWebb Scales le32_to_cpu(ac->it_nexus); 3151d604f533SWebb Scales } 3152d604f533SWebb Scales break; 3153d604f533SWebb Scales 3154d604f533SWebb Scales case 0: /* The command is in the middle of being initialized. */ 3155d604f533SWebb Scales match = false; 3156d604f533SWebb Scales break; 3157d604f533SWebb Scales 3158d604f533SWebb Scales default: 3159d604f533SWebb Scales dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", 3160d604f533SWebb Scales c->cmd_type); 3161d604f533SWebb Scales BUG(); 3162d604f533SWebb Scales } 3163d604f533SWebb Scales 3164d604f533SWebb Scales return match; 3165d604f533SWebb Scales } 3166d604f533SWebb Scales 3167d604f533SWebb Scales static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, 3168c5dfd106SDon Brace u8 reset_type, int reply_queue) 3169d604f533SWebb Scales { 3170d604f533SWebb Scales int rc = 0; 3171d604f533SWebb Scales 3172d604f533SWebb Scales /* We can really only handle one reset at a time */ 3173d604f533SWebb Scales if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { 3174d604f533SWebb Scales dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); 3175d604f533SWebb Scales return -EINTR; 3176d604f533SWebb Scales } 3177d604f533SWebb Scales 3178c5dfd106SDon Brace rc = hpsa_send_reset(h, dev, reset_type, reply_queue); 3179c5dfd106SDon Brace if (!rc) { 3180c5dfd106SDon Brace /* incremented by sending the reset request */ 3181c5dfd106SDon Brace atomic_dec(&dev->commands_outstanding); 3182d604f533SWebb Scales wait_event(h->event_sync_wait_queue, 3183c5dfd106SDon Brace atomic_read(&dev->commands_outstanding) <= 0 || 3184d604f533SWebb Scales lockup_detected(h)); 3185c5dfd106SDon Brace } 3186d604f533SWebb Scales 3187d604f533SWebb Scales if (unlikely(lockup_detected(h))) { 3188d604f533SWebb Scales dev_warn(&h->pdev->dev, 3189d604f533SWebb Scales "Controller lockup detected during reset wait\n"); 3190d604f533SWebb Scales rc = -ENODEV; 3191d604f533SWebb Scales } 3192d604f533SWebb Scales 3193c5dfd106SDon Brace if (!rc) 3194c5dfd106SDon Brace rc = wait_for_device_to_become_ready(h, dev->scsi3addr, 0); 3195d604f533SWebb Scales 3196d604f533SWebb Scales mutex_unlock(&h->reset_mutex); 3197d604f533SWebb Scales return rc; 3198d604f533SWebb Scales } 3199d604f533SWebb Scales 3200edd16368SStephen M. Cameron static void hpsa_get_raid_level(struct ctlr_info *h, 3201edd16368SStephen M. Cameron unsigned char *scsi3addr, unsigned char *raid_level) 3202edd16368SStephen M. Cameron { 3203edd16368SStephen M. Cameron int rc; 3204edd16368SStephen M. Cameron unsigned char *buf; 3205edd16368SStephen M. Cameron 3206edd16368SStephen M. Cameron *raid_level = RAID_UNKNOWN; 3207edd16368SStephen M. Cameron buf = kzalloc(64, GFP_KERNEL); 3208edd16368SStephen M. Cameron if (!buf) 3209edd16368SStephen M. Cameron return; 32108383278dSScott Teel 32118383278dSScott Teel if (!hpsa_vpd_page_supported(h, scsi3addr, 32128383278dSScott Teel HPSA_VPD_LV_DEVICE_GEOMETRY)) 32138383278dSScott Teel goto exit; 32148383278dSScott Teel 32158383278dSScott Teel rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 32168383278dSScott Teel HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64); 32178383278dSScott Teel 3218edd16368SStephen M. Cameron if (rc == 0) 3219edd16368SStephen M. Cameron *raid_level = buf[8]; 3220edd16368SStephen M. Cameron if (*raid_level > RAID_UNKNOWN) 3221edd16368SStephen M. Cameron *raid_level = RAID_UNKNOWN; 32228383278dSScott Teel exit: 3223edd16368SStephen M. Cameron kfree(buf); 3224edd16368SStephen M. Cameron return; 3225edd16368SStephen M. Cameron } 3226edd16368SStephen M. Cameron 3227283b4a9bSStephen M. Cameron #define HPSA_MAP_DEBUG 3228283b4a9bSStephen M. Cameron #ifdef HPSA_MAP_DEBUG 3229283b4a9bSStephen M. Cameron static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, 3230283b4a9bSStephen M. Cameron struct raid_map_data *map_buff) 3231283b4a9bSStephen M. Cameron { 3232283b4a9bSStephen M. Cameron struct raid_map_disk_data *dd = &map_buff->data[0]; 3233283b4a9bSStephen M. Cameron int map, row, col; 3234283b4a9bSStephen M. Cameron u16 map_cnt, row_cnt, disks_per_row; 3235283b4a9bSStephen M. Cameron 3236283b4a9bSStephen M. Cameron if (rc != 0) 3237283b4a9bSStephen M. Cameron return; 3238283b4a9bSStephen M. Cameron 32392ba8bfc8SStephen M. Cameron /* Show details only if debugging has been activated. */ 32402ba8bfc8SStephen M. Cameron if (h->raid_offload_debug < 2) 32412ba8bfc8SStephen M. Cameron return; 32422ba8bfc8SStephen M. Cameron 3243283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "structure_size = %u\n", 3244283b4a9bSStephen M. Cameron le32_to_cpu(map_buff->structure_size)); 3245283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "volume_blk_size = %u\n", 3246283b4a9bSStephen M. Cameron le32_to_cpu(map_buff->volume_blk_size)); 3247283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", 3248283b4a9bSStephen M. Cameron le64_to_cpu(map_buff->volume_blk_cnt)); 3249283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", 3250283b4a9bSStephen M. Cameron map_buff->phys_blk_shift); 3251283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", 3252283b4a9bSStephen M. Cameron map_buff->parity_rotation_shift); 3253283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "strip_size = %u\n", 3254283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->strip_size)); 3255283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", 3256283b4a9bSStephen M. Cameron le64_to_cpu(map_buff->disk_starting_blk)); 3257283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", 3258283b4a9bSStephen M. Cameron le64_to_cpu(map_buff->disk_blk_cnt)); 3259283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", 3260283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->data_disks_per_row)); 3261283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", 3262283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->metadata_disks_per_row)); 3263283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "row_cnt = %u\n", 3264283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->row_cnt)); 3265283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "layout_map_count = %u\n", 3266283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->layout_map_count)); 32672b08b3e9SDon Brace dev_info(&h->pdev->dev, "flags = 0x%x\n", 3268dd0e19f3SScott Teel le16_to_cpu(map_buff->flags)); 3269ba82d91bSColin Ian King dev_info(&h->pdev->dev, "encryption = %s\n", 32702b08b3e9SDon Brace le16_to_cpu(map_buff->flags) & 32712b08b3e9SDon Brace RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); 3272dd0e19f3SScott Teel dev_info(&h->pdev->dev, "dekindex = %u\n", 3273dd0e19f3SScott Teel le16_to_cpu(map_buff->dekindex)); 3274283b4a9bSStephen M. Cameron map_cnt = le16_to_cpu(map_buff->layout_map_count); 3275283b4a9bSStephen M. Cameron for (map = 0; map < map_cnt; map++) { 3276283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, "Map%u:\n", map); 3277283b4a9bSStephen M. Cameron row_cnt = le16_to_cpu(map_buff->row_cnt); 3278283b4a9bSStephen M. Cameron for (row = 0; row < row_cnt; row++) { 3279283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, " Row%u:\n", row); 3280283b4a9bSStephen M. Cameron disks_per_row = 3281283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->data_disks_per_row); 3282283b4a9bSStephen M. Cameron for (col = 0; col < disks_per_row; col++, dd++) 3283283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, 3284283b4a9bSStephen M. Cameron " D%02u: h=0x%04x xor=%u,%u\n", 3285283b4a9bSStephen M. Cameron col, dd->ioaccel_handle, 3286283b4a9bSStephen M. Cameron dd->xor_mult[0], dd->xor_mult[1]); 3287283b4a9bSStephen M. Cameron disks_per_row = 3288283b4a9bSStephen M. Cameron le16_to_cpu(map_buff->metadata_disks_per_row); 3289283b4a9bSStephen M. Cameron for (col = 0; col < disks_per_row; col++, dd++) 3290283b4a9bSStephen M. Cameron dev_info(&h->pdev->dev, 3291283b4a9bSStephen M. Cameron " M%02u: h=0x%04x xor=%u,%u\n", 3292283b4a9bSStephen M. Cameron col, dd->ioaccel_handle, 3293283b4a9bSStephen M. Cameron dd->xor_mult[0], dd->xor_mult[1]); 3294283b4a9bSStephen M. Cameron } 3295283b4a9bSStephen M. Cameron } 3296283b4a9bSStephen M. Cameron } 3297283b4a9bSStephen M. Cameron #else 3298283b4a9bSStephen M. Cameron static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, 3299283b4a9bSStephen M. Cameron __attribute__((unused)) int rc, 3300283b4a9bSStephen M. Cameron __attribute__((unused)) struct raid_map_data *map_buff) 3301283b4a9bSStephen M. Cameron { 3302283b4a9bSStephen M. Cameron } 3303283b4a9bSStephen M. Cameron #endif 3304283b4a9bSStephen M. Cameron 3305283b4a9bSStephen M. Cameron static int hpsa_get_raid_map(struct ctlr_info *h, 3306283b4a9bSStephen M. Cameron unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3307283b4a9bSStephen M. Cameron { 3308283b4a9bSStephen M. Cameron int rc = 0; 3309283b4a9bSStephen M. Cameron struct CommandList *c; 3310283b4a9bSStephen M. Cameron struct ErrorInfo *ei; 3311283b4a9bSStephen M. Cameron 331245fcb86eSStephen Cameron c = cmd_alloc(h); 3313bf43caf3SRobert Elliott 3314283b4a9bSStephen M. Cameron if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, 3315283b4a9bSStephen M. Cameron sizeof(this_device->raid_map), 0, 3316283b4a9bSStephen M. Cameron scsi3addr, TYPE_CMD)) { 33172dd02d74SRobert Elliott dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); 33182dd02d74SRobert Elliott cmd_free(h, c); 33192dd02d74SRobert Elliott return -1; 3320283b4a9bSStephen M. Cameron } 33218bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 33228bc8f47eSChristoph Hellwig NO_TIMEOUT); 332325163bd5SWebb Scales if (rc) 332425163bd5SWebb Scales goto out; 3325283b4a9bSStephen M. Cameron ei = c->err_info; 3326283b4a9bSStephen M. Cameron if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3327d1e8beacSStephen M. Cameron hpsa_scsi_interpret_error(h, c); 332825163bd5SWebb Scales rc = -1; 332925163bd5SWebb Scales goto out; 3330283b4a9bSStephen M. Cameron } 333145fcb86eSStephen Cameron cmd_free(h, c); 3332283b4a9bSStephen M. Cameron 3333283b4a9bSStephen M. Cameron /* @todo in the future, dynamically allocate RAID map memory */ 3334283b4a9bSStephen M. Cameron if (le32_to_cpu(this_device->raid_map.structure_size) > 3335283b4a9bSStephen M. Cameron sizeof(this_device->raid_map)) { 3336283b4a9bSStephen M. Cameron dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); 3337283b4a9bSStephen M. Cameron rc = -1; 3338283b4a9bSStephen M. Cameron } 3339283b4a9bSStephen M. Cameron hpsa_debug_map_buff(h, rc, &this_device->raid_map); 3340283b4a9bSStephen M. Cameron return rc; 334125163bd5SWebb Scales out: 334225163bd5SWebb Scales cmd_free(h, c); 334325163bd5SWebb Scales return rc; 3344283b4a9bSStephen M. Cameron } 3345283b4a9bSStephen M. Cameron 3346d04e62b9SKevin Barnett static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, 3347d04e62b9SKevin Barnett unsigned char scsi3addr[], u16 bmic_device_index, 3348d04e62b9SKevin Barnett struct bmic_sense_subsystem_info *buf, size_t bufsize) 3349d04e62b9SKevin Barnett { 3350d04e62b9SKevin Barnett int rc = IO_OK; 3351d04e62b9SKevin Barnett struct CommandList *c; 3352d04e62b9SKevin Barnett struct ErrorInfo *ei; 3353d04e62b9SKevin Barnett 3354d04e62b9SKevin Barnett c = cmd_alloc(h); 3355d04e62b9SKevin Barnett 3356d04e62b9SKevin Barnett rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, 3357d04e62b9SKevin Barnett 0, RAID_CTLR_LUNID, TYPE_CMD); 3358d04e62b9SKevin Barnett if (rc) 3359d04e62b9SKevin Barnett goto out; 3360d04e62b9SKevin Barnett 3361d04e62b9SKevin Barnett c->Request.CDB[2] = bmic_device_index & 0xff; 3362d04e62b9SKevin Barnett c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 3363d04e62b9SKevin Barnett 33648bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 33658bc8f47eSChristoph Hellwig NO_TIMEOUT); 3366d04e62b9SKevin Barnett if (rc) 3367d04e62b9SKevin Barnett goto out; 3368d04e62b9SKevin Barnett ei = c->err_info; 3369d04e62b9SKevin Barnett if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3370d04e62b9SKevin Barnett hpsa_scsi_interpret_error(h, c); 3371d04e62b9SKevin Barnett rc = -1; 3372d04e62b9SKevin Barnett } 3373d04e62b9SKevin Barnett out: 3374d04e62b9SKevin Barnett cmd_free(h, c); 3375d04e62b9SKevin Barnett return rc; 3376d04e62b9SKevin Barnett } 3377d04e62b9SKevin Barnett 337866749d0dSScott Teel static int hpsa_bmic_id_controller(struct ctlr_info *h, 337966749d0dSScott Teel struct bmic_identify_controller *buf, size_t bufsize) 338066749d0dSScott Teel { 338166749d0dSScott Teel int rc = IO_OK; 338266749d0dSScott Teel struct CommandList *c; 338366749d0dSScott Teel struct ErrorInfo *ei; 338466749d0dSScott Teel 338566749d0dSScott Teel c = cmd_alloc(h); 338666749d0dSScott Teel 338766749d0dSScott Teel rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, 338866749d0dSScott Teel 0, RAID_CTLR_LUNID, TYPE_CMD); 338966749d0dSScott Teel if (rc) 339066749d0dSScott Teel goto out; 339166749d0dSScott Teel 33928bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 33938bc8f47eSChristoph Hellwig NO_TIMEOUT); 339466749d0dSScott Teel if (rc) 339566749d0dSScott Teel goto out; 339666749d0dSScott Teel ei = c->err_info; 339766749d0dSScott Teel if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 339866749d0dSScott Teel hpsa_scsi_interpret_error(h, c); 339966749d0dSScott Teel rc = -1; 340066749d0dSScott Teel } 340166749d0dSScott Teel out: 340266749d0dSScott Teel cmd_free(h, c); 340366749d0dSScott Teel return rc; 340466749d0dSScott Teel } 340566749d0dSScott Teel 340603383736SDon Brace static int hpsa_bmic_id_physical_device(struct ctlr_info *h, 340703383736SDon Brace unsigned char scsi3addr[], u16 bmic_device_index, 340803383736SDon Brace struct bmic_identify_physical_device *buf, size_t bufsize) 340903383736SDon Brace { 341003383736SDon Brace int rc = IO_OK; 341103383736SDon Brace struct CommandList *c; 341203383736SDon Brace struct ErrorInfo *ei; 341303383736SDon Brace 341403383736SDon Brace c = cmd_alloc(h); 341503383736SDon Brace rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, 341603383736SDon Brace 0, RAID_CTLR_LUNID, TYPE_CMD); 341703383736SDon Brace if (rc) 341803383736SDon Brace goto out; 341903383736SDon Brace 342003383736SDon Brace c->Request.CDB[2] = bmic_device_index & 0xff; 342103383736SDon Brace c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 342203383736SDon Brace 34238bc8f47eSChristoph Hellwig hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 34243026ff9bSDon Brace NO_TIMEOUT); 342503383736SDon Brace ei = c->err_info; 342603383736SDon Brace if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 342703383736SDon Brace hpsa_scsi_interpret_error(h, c); 342803383736SDon Brace rc = -1; 342903383736SDon Brace } 343003383736SDon Brace out: 343103383736SDon Brace cmd_free(h, c); 3432d04e62b9SKevin Barnett 343303383736SDon Brace return rc; 343403383736SDon Brace } 343503383736SDon Brace 3436cca8f13bSDon Brace /* 3437cca8f13bSDon Brace * get enclosure information 3438cca8f13bSDon Brace * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number 3439cca8f13bSDon Brace * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure 3440cca8f13bSDon Brace * Uses id_physical_device to determine the box_index. 3441cca8f13bSDon Brace */ 3442cca8f13bSDon Brace static void hpsa_get_enclosure_info(struct ctlr_info *h, 3443cca8f13bSDon Brace unsigned char *scsi3addr, 3444cca8f13bSDon Brace struct ReportExtendedLUNdata *rlep, int rle_index, 3445cca8f13bSDon Brace struct hpsa_scsi_dev_t *encl_dev) 3446cca8f13bSDon Brace { 3447cca8f13bSDon Brace int rc = -1; 3448cca8f13bSDon Brace struct CommandList *c = NULL; 3449cca8f13bSDon Brace struct ErrorInfo *ei = NULL; 3450cca8f13bSDon Brace struct bmic_sense_storage_box_params *bssbp = NULL; 3451cca8f13bSDon Brace struct bmic_identify_physical_device *id_phys = NULL; 345227e1b94dSDon Brace struct ext_report_lun_entry *rle; 3453cca8f13bSDon Brace u16 bmic_device_index = 0; 3454cca8f13bSDon Brace 345527e1b94dSDon Brace if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN) 345627e1b94dSDon Brace return; 345727e1b94dSDon Brace 345827e1b94dSDon Brace rle = &rlep->LUN[rle_index]; 345927e1b94dSDon Brace 346001d0e789SDon Brace encl_dev->eli = 34610a7c3bb8SDon Brace hpsa_get_enclosure_logical_identifier(h, scsi3addr); 34620a7c3bb8SDon Brace 346301d0e789SDon Brace bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]); 346401d0e789SDon Brace 34655ac517b8SDon Brace if (encl_dev->target == -1 || encl_dev->lun == -1) { 34665ac517b8SDon Brace rc = IO_OK; 34675ac517b8SDon Brace goto out; 34685ac517b8SDon Brace } 34695ac517b8SDon Brace 347017a9e54aSDon Brace if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) { 347117a9e54aSDon Brace rc = IO_OK; 3472cca8f13bSDon Brace goto out; 347317a9e54aSDon Brace } 3474cca8f13bSDon Brace 3475cca8f13bSDon Brace bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL); 3476cca8f13bSDon Brace if (!bssbp) 3477cca8f13bSDon Brace goto out; 3478cca8f13bSDon Brace 3479cca8f13bSDon Brace id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 3480cca8f13bSDon Brace if (!id_phys) 3481cca8f13bSDon Brace goto out; 3482cca8f13bSDon Brace 3483cca8f13bSDon Brace rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index, 3484cca8f13bSDon Brace id_phys, sizeof(*id_phys)); 3485cca8f13bSDon Brace if (rc) { 3486cca8f13bSDon Brace dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n", 3487cca8f13bSDon Brace __func__, encl_dev->external, bmic_device_index); 3488cca8f13bSDon Brace goto out; 3489cca8f13bSDon Brace } 3490cca8f13bSDon Brace 3491cca8f13bSDon Brace c = cmd_alloc(h); 3492cca8f13bSDon Brace 3493cca8f13bSDon Brace rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp, 3494cca8f13bSDon Brace sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD); 3495cca8f13bSDon Brace 3496cca8f13bSDon Brace if (rc) 3497cca8f13bSDon Brace goto out; 3498cca8f13bSDon Brace 3499cca8f13bSDon Brace if (id_phys->phys_connector[1] == 'E') 3500cca8f13bSDon Brace c->Request.CDB[5] = id_phys->box_index; 3501cca8f13bSDon Brace else 3502cca8f13bSDon Brace c->Request.CDB[5] = 0; 3503cca8f13bSDon Brace 35048bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 35053026ff9bSDon Brace NO_TIMEOUT); 3506cca8f13bSDon Brace if (rc) 3507cca8f13bSDon Brace goto out; 3508cca8f13bSDon Brace 3509cca8f13bSDon Brace ei = c->err_info; 3510cca8f13bSDon Brace if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3511cca8f13bSDon Brace rc = -1; 3512cca8f13bSDon Brace goto out; 3513cca8f13bSDon Brace } 3514cca8f13bSDon Brace 3515cca8f13bSDon Brace encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port; 3516cca8f13bSDon Brace memcpy(&encl_dev->phys_connector[id_phys->active_path_number], 3517cca8f13bSDon Brace bssbp->phys_connector, sizeof(bssbp->phys_connector)); 3518cca8f13bSDon Brace 3519cca8f13bSDon Brace rc = IO_OK; 3520cca8f13bSDon Brace out: 3521cca8f13bSDon Brace kfree(bssbp); 3522cca8f13bSDon Brace kfree(id_phys); 3523cca8f13bSDon Brace 3524cca8f13bSDon Brace if (c) 3525cca8f13bSDon Brace cmd_free(h, c); 3526cca8f13bSDon Brace 3527cca8f13bSDon Brace if (rc != IO_OK) 3528cca8f13bSDon Brace hpsa_show_dev_msg(KERN_INFO, h, encl_dev, 3529b4e9ce1cSJulia Lawall "Error, could not get enclosure information"); 3530cca8f13bSDon Brace } 3531cca8f13bSDon Brace 3532d04e62b9SKevin Barnett static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, 3533d04e62b9SKevin Barnett unsigned char *scsi3addr) 3534d04e62b9SKevin Barnett { 3535d04e62b9SKevin Barnett struct ReportExtendedLUNdata *physdev; 3536d04e62b9SKevin Barnett u32 nphysicals; 3537d04e62b9SKevin Barnett u64 sa = 0; 3538d04e62b9SKevin Barnett int i; 3539d04e62b9SKevin Barnett 3540d04e62b9SKevin Barnett physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); 3541d04e62b9SKevin Barnett if (!physdev) 3542d04e62b9SKevin Barnett return 0; 3543d04e62b9SKevin Barnett 3544d04e62b9SKevin Barnett if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 3545d04e62b9SKevin Barnett dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 3546d04e62b9SKevin Barnett kfree(physdev); 3547d04e62b9SKevin Barnett return 0; 3548d04e62b9SKevin Barnett } 3549d04e62b9SKevin Barnett nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; 3550d04e62b9SKevin Barnett 3551d04e62b9SKevin Barnett for (i = 0; i < nphysicals; i++) 3552d04e62b9SKevin Barnett if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { 3553d04e62b9SKevin Barnett sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); 3554d04e62b9SKevin Barnett break; 3555d04e62b9SKevin Barnett } 3556d04e62b9SKevin Barnett 3557d04e62b9SKevin Barnett kfree(physdev); 3558d04e62b9SKevin Barnett 3559d04e62b9SKevin Barnett return sa; 3560d04e62b9SKevin Barnett } 3561d04e62b9SKevin Barnett 3562d04e62b9SKevin Barnett static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, 3563d04e62b9SKevin Barnett struct hpsa_scsi_dev_t *dev) 3564d04e62b9SKevin Barnett { 3565d04e62b9SKevin Barnett int rc; 3566d04e62b9SKevin Barnett u64 sa = 0; 3567d04e62b9SKevin Barnett 3568d04e62b9SKevin Barnett if (is_hba_lunid(scsi3addr)) { 3569d04e62b9SKevin Barnett struct bmic_sense_subsystem_info *ssi; 3570d04e62b9SKevin Barnett 3571d04e62b9SKevin Barnett ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); 35727e8a9486SAmit Kushwaha if (!ssi) 3573d04e62b9SKevin Barnett return; 3574d04e62b9SKevin Barnett 3575d04e62b9SKevin Barnett rc = hpsa_bmic_sense_subsystem_information(h, 3576d04e62b9SKevin Barnett scsi3addr, 0, ssi, sizeof(*ssi)); 3577d04e62b9SKevin Barnett if (rc == 0) { 3578d04e62b9SKevin Barnett sa = get_unaligned_be64(ssi->primary_world_wide_id); 3579d04e62b9SKevin Barnett h->sas_address = sa; 3580d04e62b9SKevin Barnett } 3581d04e62b9SKevin Barnett 3582d04e62b9SKevin Barnett kfree(ssi); 3583d04e62b9SKevin Barnett } else 3584d04e62b9SKevin Barnett sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); 3585d04e62b9SKevin Barnett 3586d04e62b9SKevin Barnett dev->sas_address = sa; 3587d04e62b9SKevin Barnett } 3588d04e62b9SKevin Barnett 35894e188184SBader Ali Saleh static void hpsa_ext_ctrl_present(struct ctlr_info *h, 35904e188184SBader Ali Saleh struct ReportExtendedLUNdata *physdev) 35914e188184SBader Ali Saleh { 35924e188184SBader Ali Saleh u32 nphysicals; 35934e188184SBader Ali Saleh int i; 35944e188184SBader Ali Saleh 35954e188184SBader Ali Saleh if (h->discovery_polling) 35964e188184SBader Ali Saleh return; 35974e188184SBader Ali Saleh 35984e188184SBader Ali Saleh nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1; 35994e188184SBader Ali Saleh 36004e188184SBader Ali Saleh for (i = 0; i < nphysicals; i++) { 36014e188184SBader Ali Saleh if (physdev->LUN[i].device_type == 36024e188184SBader Ali Saleh BMIC_DEVICE_TYPE_CONTROLLER 36034e188184SBader Ali Saleh && !is_hba_lunid(physdev->LUN[i].lunid)) { 36044e188184SBader Ali Saleh dev_info(&h->pdev->dev, 36054e188184SBader Ali Saleh "External controller present, activate discovery polling and disable rld caching\n"); 36064e188184SBader Ali Saleh hpsa_disable_rld_caching(h); 36074e188184SBader Ali Saleh h->discovery_polling = 1; 36084e188184SBader Ali Saleh break; 36094e188184SBader Ali Saleh } 36104e188184SBader Ali Saleh } 36114e188184SBader Ali Saleh } 36124e188184SBader Ali Saleh 3613d04e62b9SKevin Barnett /* Get a device id from inquiry page 0x83 */ 36148383278dSScott Teel static bool hpsa_vpd_page_supported(struct ctlr_info *h, 36151b70150aSStephen M. Cameron unsigned char scsi3addr[], u8 page) 36161b70150aSStephen M. Cameron { 36171b70150aSStephen M. Cameron int rc; 36181b70150aSStephen M. Cameron int i; 36191b70150aSStephen M. Cameron int pages; 36201b70150aSStephen M. Cameron unsigned char *buf, bufsize; 36211b70150aSStephen M. Cameron 36221b70150aSStephen M. Cameron buf = kzalloc(256, GFP_KERNEL); 36231b70150aSStephen M. Cameron if (!buf) 36248383278dSScott Teel return false; 36251b70150aSStephen M. Cameron 36261b70150aSStephen M. Cameron /* Get the size of the page list first */ 36271b70150aSStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, scsi3addr, 36281b70150aSStephen M. Cameron VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 36291b70150aSStephen M. Cameron buf, HPSA_VPD_HEADER_SZ); 36301b70150aSStephen M. Cameron if (rc != 0) 36311b70150aSStephen M. Cameron goto exit_unsupported; 36321b70150aSStephen M. Cameron pages = buf[3]; 36331b70150aSStephen M. Cameron if ((pages + HPSA_VPD_HEADER_SZ) <= 255) 36341b70150aSStephen M. Cameron bufsize = pages + HPSA_VPD_HEADER_SZ; 36351b70150aSStephen M. Cameron else 36361b70150aSStephen M. Cameron bufsize = 255; 36371b70150aSStephen M. Cameron 36381b70150aSStephen M. Cameron /* Get the whole VPD page list */ 36391b70150aSStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, scsi3addr, 36401b70150aSStephen M. Cameron VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 36411b70150aSStephen M. Cameron buf, bufsize); 36421b70150aSStephen M. Cameron if (rc != 0) 36431b70150aSStephen M. Cameron goto exit_unsupported; 36441b70150aSStephen M. Cameron 36451b70150aSStephen M. Cameron pages = buf[3]; 36461b70150aSStephen M. Cameron for (i = 1; i <= pages; i++) 36471b70150aSStephen M. Cameron if (buf[3 + i] == page) 36481b70150aSStephen M. Cameron goto exit_supported; 36491b70150aSStephen M. Cameron exit_unsupported: 36501b70150aSStephen M. Cameron kfree(buf); 36518383278dSScott Teel return false; 36521b70150aSStephen M. Cameron exit_supported: 36531b70150aSStephen M. Cameron kfree(buf); 36548383278dSScott Teel return true; 36551b70150aSStephen M. Cameron } 36561b70150aSStephen M. Cameron 3657b2582a65SDon Brace /* 3658b2582a65SDon Brace * Called during a scan operation. 3659b2582a65SDon Brace * Sets ioaccel status on the new device list, not the existing device list 3660b2582a65SDon Brace * 3661b2582a65SDon Brace * The device list used during I/O will be updated later in 3662b2582a65SDon Brace * adjust_hpsa_scsi_table. 3663b2582a65SDon Brace */ 3664283b4a9bSStephen M. Cameron static void hpsa_get_ioaccel_status(struct ctlr_info *h, 3665283b4a9bSStephen M. Cameron unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3666283b4a9bSStephen M. Cameron { 3667283b4a9bSStephen M. Cameron int rc; 3668283b4a9bSStephen M. Cameron unsigned char *buf; 3669283b4a9bSStephen M. Cameron u8 ioaccel_status; 3670283b4a9bSStephen M. Cameron 3671283b4a9bSStephen M. Cameron this_device->offload_config = 0; 3672283b4a9bSStephen M. Cameron this_device->offload_enabled = 0; 367341ce4c35SStephen Cameron this_device->offload_to_be_enabled = 0; 3674283b4a9bSStephen M. Cameron 3675283b4a9bSStephen M. Cameron buf = kzalloc(64, GFP_KERNEL); 3676283b4a9bSStephen M. Cameron if (!buf) 3677283b4a9bSStephen M. Cameron return; 36781b70150aSStephen M. Cameron if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) 36791b70150aSStephen M. Cameron goto out; 3680283b4a9bSStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3681b7bb24ebSStephen M. Cameron VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); 3682283b4a9bSStephen M. Cameron if (rc != 0) 3683283b4a9bSStephen M. Cameron goto out; 3684283b4a9bSStephen M. Cameron 3685283b4a9bSStephen M. Cameron #define IOACCEL_STATUS_BYTE 4 3686283b4a9bSStephen M. Cameron #define OFFLOAD_CONFIGURED_BIT 0x01 3687283b4a9bSStephen M. Cameron #define OFFLOAD_ENABLED_BIT 0x02 3688283b4a9bSStephen M. Cameron ioaccel_status = buf[IOACCEL_STATUS_BYTE]; 3689283b4a9bSStephen M. Cameron this_device->offload_config = 3690283b4a9bSStephen M. Cameron !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); 3691283b4a9bSStephen M. Cameron if (this_device->offload_config) { 36923e16e83aSDon Brace bool offload_enabled = 3693283b4a9bSStephen M. Cameron !!(ioaccel_status & OFFLOAD_ENABLED_BIT); 36943e16e83aSDon Brace /* 36953e16e83aSDon Brace * Check to see if offload can be enabled. 36963e16e83aSDon Brace */ 36973e16e83aSDon Brace if (offload_enabled) { 36983e16e83aSDon Brace rc = hpsa_get_raid_map(h, scsi3addr, this_device); 36993e16e83aSDon Brace if (rc) /* could not load raid_map */ 37003e16e83aSDon Brace goto out; 37013e16e83aSDon Brace this_device->offload_to_be_enabled = 1; 37023e16e83aSDon Brace } 3703283b4a9bSStephen M. Cameron } 3704b2582a65SDon Brace 3705283b4a9bSStephen M. Cameron out: 3706283b4a9bSStephen M. Cameron kfree(buf); 3707283b4a9bSStephen M. Cameron return; 3708283b4a9bSStephen M. Cameron } 3709283b4a9bSStephen M. Cameron 3710edd16368SStephen M. Cameron /* Get the device id from inquiry page 0x83 */ 3711edd16368SStephen M. Cameron static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, 371275d23d89SDon Brace unsigned char *device_id, int index, int buflen) 3713edd16368SStephen M. Cameron { 3714edd16368SStephen M. Cameron int rc; 3715edd16368SStephen M. Cameron unsigned char *buf; 3716edd16368SStephen M. Cameron 37178383278dSScott Teel /* Does controller have VPD for device id? */ 37188383278dSScott Teel if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID)) 37198383278dSScott Teel return 1; /* not supported */ 37208383278dSScott Teel 3721edd16368SStephen M. Cameron buf = kzalloc(64, GFP_KERNEL); 3722edd16368SStephen M. Cameron if (!buf) 3723a84d794dSStephen M. Cameron return -ENOMEM; 37248383278dSScott Teel 37258383278dSScott Teel rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 37268383278dSScott Teel HPSA_VPD_LV_DEVICE_ID, buf, 64); 37278383278dSScott Teel if (rc == 0) { 37288383278dSScott Teel if (buflen > 16) 37298383278dSScott Teel buflen = 16; 37308383278dSScott Teel memcpy(device_id, &buf[8], buflen); 37318383278dSScott Teel } 373275d23d89SDon Brace 3733edd16368SStephen M. Cameron kfree(buf); 373475d23d89SDon Brace 37358383278dSScott Teel return rc; /*0 - got id, otherwise, didn't */ 3736edd16368SStephen M. Cameron } 3737edd16368SStephen M. Cameron 3738edd16368SStephen M. Cameron static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, 373903383736SDon Brace void *buf, int bufsize, 3740edd16368SStephen M. Cameron int extended_response) 3741edd16368SStephen M. Cameron { 3742edd16368SStephen M. Cameron int rc = IO_OK; 3743edd16368SStephen M. Cameron struct CommandList *c; 3744edd16368SStephen M. Cameron unsigned char scsi3addr[8]; 3745edd16368SStephen M. Cameron struct ErrorInfo *ei; 3746edd16368SStephen M. Cameron 374745fcb86eSStephen Cameron c = cmd_alloc(h); 3748bf43caf3SRobert Elliott 3749e89c0ae7SStephen M. Cameron /* address the controller */ 3750e89c0ae7SStephen M. Cameron memset(scsi3addr, 0, sizeof(scsi3addr)); 3751a2dac136SStephen M. Cameron if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, 3752a2dac136SStephen M. Cameron buf, bufsize, 0, scsi3addr, TYPE_CMD)) { 375345f769b2SHannes Reinecke rc = -EAGAIN; 3754a2dac136SStephen M. Cameron goto out; 3755a2dac136SStephen M. Cameron } 3756edd16368SStephen M. Cameron if (extended_response) 3757edd16368SStephen M. Cameron c->Request.CDB[1] = extended_response; 37588bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 37598bc8f47eSChristoph Hellwig NO_TIMEOUT); 376025163bd5SWebb Scales if (rc) 376125163bd5SWebb Scales goto out; 3762edd16368SStephen M. Cameron ei = c->err_info; 3763edd16368SStephen M. Cameron if (ei->CommandStatus != 0 && 3764edd16368SStephen M. Cameron ei->CommandStatus != CMD_DATA_UNDERRUN) { 3765d1e8beacSStephen M. Cameron hpsa_scsi_interpret_error(h, c); 376645f769b2SHannes Reinecke rc = -EIO; 3767283b4a9bSStephen M. Cameron } else { 376803383736SDon Brace struct ReportLUNdata *rld = buf; 376903383736SDon Brace 377003383736SDon Brace if (rld->extended_response_flag != extended_response) { 377145f769b2SHannes Reinecke if (!h->legacy_board) { 3772283b4a9bSStephen M. Cameron dev_err(&h->pdev->dev, 3773283b4a9bSStephen M. Cameron "report luns requested format %u, got %u\n", 3774283b4a9bSStephen M. Cameron extended_response, 377503383736SDon Brace rld->extended_response_flag); 377645f769b2SHannes Reinecke rc = -EINVAL; 377745f769b2SHannes Reinecke } else 377845f769b2SHannes Reinecke rc = -EOPNOTSUPP; 3779283b4a9bSStephen M. Cameron } 3780edd16368SStephen M. Cameron } 3781a2dac136SStephen M. Cameron out: 378245fcb86eSStephen Cameron cmd_free(h, c); 3783edd16368SStephen M. Cameron return rc; 3784edd16368SStephen M. Cameron } 3785edd16368SStephen M. Cameron 3786edd16368SStephen M. Cameron static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 378703383736SDon Brace struct ReportExtendedLUNdata *buf, int bufsize) 3788edd16368SStephen M. Cameron { 37892a80d545SHannes Reinecke int rc; 37902a80d545SHannes Reinecke struct ReportLUNdata *lbuf; 37912a80d545SHannes Reinecke 37922a80d545SHannes Reinecke rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize, 379303383736SDon Brace HPSA_REPORT_PHYS_EXTENDED); 379445f769b2SHannes Reinecke if (!rc || rc != -EOPNOTSUPP) 37952a80d545SHannes Reinecke return rc; 37962a80d545SHannes Reinecke 37972a80d545SHannes Reinecke /* REPORT PHYS EXTENDED is not supported */ 37982a80d545SHannes Reinecke lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL); 37992a80d545SHannes Reinecke if (!lbuf) 38002a80d545SHannes Reinecke return -ENOMEM; 38012a80d545SHannes Reinecke 38022a80d545SHannes Reinecke rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0); 38032a80d545SHannes Reinecke if (!rc) { 38042a80d545SHannes Reinecke int i; 38052a80d545SHannes Reinecke u32 nphys; 38062a80d545SHannes Reinecke 38072a80d545SHannes Reinecke /* Copy ReportLUNdata header */ 38082a80d545SHannes Reinecke memcpy(buf, lbuf, 8); 38092a80d545SHannes Reinecke nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8; 38102a80d545SHannes Reinecke for (i = 0; i < nphys; i++) 38112a80d545SHannes Reinecke memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8); 38122a80d545SHannes Reinecke } 38132a80d545SHannes Reinecke kfree(lbuf); 38142a80d545SHannes Reinecke return rc; 3815edd16368SStephen M. Cameron } 3816edd16368SStephen M. Cameron 3817edd16368SStephen M. Cameron static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, 3818edd16368SStephen M. Cameron struct ReportLUNdata *buf, int bufsize) 3819edd16368SStephen M. Cameron { 3820edd16368SStephen M. Cameron return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); 3821edd16368SStephen M. Cameron } 3822edd16368SStephen M. Cameron 3823edd16368SStephen M. Cameron static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, 3824edd16368SStephen M. Cameron int bus, int target, int lun) 3825edd16368SStephen M. Cameron { 3826edd16368SStephen M. Cameron device->bus = bus; 3827edd16368SStephen M. Cameron device->target = target; 3828edd16368SStephen M. Cameron device->lun = lun; 3829edd16368SStephen M. Cameron } 3830edd16368SStephen M. Cameron 38319846590eSStephen M. Cameron /* Use VPD inquiry to get details of volume status */ 38329846590eSStephen M. Cameron static int hpsa_get_volume_status(struct ctlr_info *h, 38339846590eSStephen M. Cameron unsigned char scsi3addr[]) 38349846590eSStephen M. Cameron { 38359846590eSStephen M. Cameron int rc; 38369846590eSStephen M. Cameron int status; 38379846590eSStephen M. Cameron int size; 38389846590eSStephen M. Cameron unsigned char *buf; 38399846590eSStephen M. Cameron 38409846590eSStephen M. Cameron buf = kzalloc(64, GFP_KERNEL); 38419846590eSStephen M. Cameron if (!buf) 38429846590eSStephen M. Cameron return HPSA_VPD_LV_STATUS_UNSUPPORTED; 38439846590eSStephen M. Cameron 38449846590eSStephen M. Cameron /* Does controller have VPD for logical volume status? */ 384524a4b078SStephen M. Cameron if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) 38469846590eSStephen M. Cameron goto exit_failed; 38479846590eSStephen M. Cameron 38489846590eSStephen M. Cameron /* Get the size of the VPD return buffer */ 38499846590eSStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 38509846590eSStephen M. Cameron buf, HPSA_VPD_HEADER_SZ); 385124a4b078SStephen M. Cameron if (rc != 0) 38529846590eSStephen M. Cameron goto exit_failed; 38539846590eSStephen M. Cameron size = buf[3]; 38549846590eSStephen M. Cameron 38559846590eSStephen M. Cameron /* Now get the whole VPD buffer */ 38569846590eSStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 38579846590eSStephen M. Cameron buf, size + HPSA_VPD_HEADER_SZ); 385824a4b078SStephen M. Cameron if (rc != 0) 38599846590eSStephen M. Cameron goto exit_failed; 38609846590eSStephen M. Cameron status = buf[4]; /* status byte */ 38619846590eSStephen M. Cameron 38629846590eSStephen M. Cameron kfree(buf); 38639846590eSStephen M. Cameron return status; 38649846590eSStephen M. Cameron exit_failed: 38659846590eSStephen M. Cameron kfree(buf); 38669846590eSStephen M. Cameron return HPSA_VPD_LV_STATUS_UNSUPPORTED; 38679846590eSStephen M. Cameron } 38689846590eSStephen M. Cameron 38699846590eSStephen M. Cameron /* Determine offline status of a volume. 38709846590eSStephen M. Cameron * Return either: 38719846590eSStephen M. Cameron * 0 (not offline) 387267955ba3SStephen M. Cameron * 0xff (offline for unknown reasons) 38739846590eSStephen M. Cameron * # (integer code indicating one of several NOT READY states 38749846590eSStephen M. Cameron * describing why a volume is to be kept offline) 38759846590eSStephen M. Cameron */ 387685b29008SDon Brace static unsigned char hpsa_volume_offline(struct ctlr_info *h, 38779846590eSStephen M. Cameron unsigned char scsi3addr[]) 38789846590eSStephen M. Cameron { 38799846590eSStephen M. Cameron struct CommandList *c; 38809437ac43SStephen Cameron unsigned char *sense; 38819437ac43SStephen Cameron u8 sense_key, asc, ascq; 38829437ac43SStephen Cameron int sense_len; 388325163bd5SWebb Scales int rc, ldstat = 0; 38849846590eSStephen M. Cameron u16 cmd_status; 38859846590eSStephen M. Cameron u8 scsi_status; 38869846590eSStephen M. Cameron #define ASC_LUN_NOT_READY 0x04 38879846590eSStephen M. Cameron #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 38889846590eSStephen M. Cameron #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 38899846590eSStephen M. Cameron 38909846590eSStephen M. Cameron c = cmd_alloc(h); 3891bf43caf3SRobert Elliott 38929846590eSStephen M. Cameron (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); 3893c448ecfaSDon Brace rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 38943026ff9bSDon Brace NO_TIMEOUT); 389525163bd5SWebb Scales if (rc) { 389625163bd5SWebb Scales cmd_free(h, c); 389785b29008SDon Brace return HPSA_VPD_LV_STATUS_UNSUPPORTED; 389825163bd5SWebb Scales } 38999846590eSStephen M. Cameron sense = c->err_info->SenseInfo; 39009437ac43SStephen Cameron if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 39019437ac43SStephen Cameron sense_len = sizeof(c->err_info->SenseInfo); 39029437ac43SStephen Cameron else 39039437ac43SStephen Cameron sense_len = c->err_info->SenseLen; 39049437ac43SStephen Cameron decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); 39059846590eSStephen M. Cameron cmd_status = c->err_info->CommandStatus; 39069846590eSStephen M. Cameron scsi_status = c->err_info->ScsiStatus; 39079846590eSStephen M. Cameron cmd_free(h, c); 39089846590eSStephen M. Cameron 39099846590eSStephen M. Cameron /* Determine the reason for not ready state */ 39109846590eSStephen M. Cameron ldstat = hpsa_get_volume_status(h, scsi3addr); 39119846590eSStephen M. Cameron 39129846590eSStephen M. Cameron /* Keep volume offline in certain cases: */ 39139846590eSStephen M. Cameron switch (ldstat) { 391485b29008SDon Brace case HPSA_LV_FAILED: 39159846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ERASE: 39165ca01204SScott Benesh case HPSA_LV_NOT_AVAILABLE: 39179846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_RPI: 39189846590eSStephen M. Cameron case HPSA_LV_PENDING_RPI: 39199846590eSStephen M. Cameron case HPSA_LV_ENCRYPTED_NO_KEY: 39209846590eSStephen M. Cameron case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 39219846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ENCRYPTION: 39229846590eSStephen M. Cameron case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 39239846590eSStephen M. Cameron case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 39249846590eSStephen M. Cameron return ldstat; 39259846590eSStephen M. Cameron case HPSA_VPD_LV_STATUS_UNSUPPORTED: 39269846590eSStephen M. Cameron /* If VPD status page isn't available, 39279846590eSStephen M. Cameron * use ASC/ASCQ to determine state 39289846590eSStephen M. Cameron */ 39299846590eSStephen M. Cameron if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || 39309846590eSStephen M. Cameron (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) 39319846590eSStephen M. Cameron return ldstat; 39329846590eSStephen M. Cameron break; 39339846590eSStephen M. Cameron default: 39349846590eSStephen M. Cameron break; 39359846590eSStephen M. Cameron } 393685b29008SDon Brace return HPSA_LV_OK; 39379846590eSStephen M. Cameron } 39389846590eSStephen M. Cameron 3939edd16368SStephen M. Cameron static int hpsa_update_device_info(struct ctlr_info *h, 39400b0e1d6cSStephen M. Cameron unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, 39410b0e1d6cSStephen M. Cameron unsigned char *is_OBDR_device) 3942edd16368SStephen M. Cameron { 39430b0e1d6cSStephen M. Cameron 39440b0e1d6cSStephen M. Cameron #define OBDR_SIG_OFFSET 43 39450b0e1d6cSStephen M. Cameron #define OBDR_TAPE_SIG "$DR-10" 39460b0e1d6cSStephen M. Cameron #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 39470b0e1d6cSStephen M. Cameron #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 39480b0e1d6cSStephen M. Cameron 3949ea6d3bc3SStephen M. Cameron unsigned char *inq_buff; 39500b0e1d6cSStephen M. Cameron unsigned char *obdr_sig; 3951683fc444SDon Brace int rc = 0; 3952edd16368SStephen M. Cameron 3953ea6d3bc3SStephen M. Cameron inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); 3954683fc444SDon Brace if (!inq_buff) { 3955683fc444SDon Brace rc = -ENOMEM; 3956edd16368SStephen M. Cameron goto bail_out; 3957683fc444SDon Brace } 3958edd16368SStephen M. Cameron 3959edd16368SStephen M. Cameron /* Do an inquiry to the device to see what it is. */ 3960edd16368SStephen M. Cameron if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, 3961edd16368SStephen M. Cameron (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { 3962edd16368SStephen M. Cameron dev_err(&h->pdev->dev, 396385b29008SDon Brace "%s: inquiry failed, device will be skipped.\n", 396485b29008SDon Brace __func__); 396585b29008SDon Brace rc = HPSA_INQUIRY_FAILED; 3966edd16368SStephen M. Cameron goto bail_out; 3967edd16368SStephen M. Cameron } 3968edd16368SStephen M. Cameron 39694af61e4fSDon Brace scsi_sanitize_inquiry_string(&inq_buff[8], 8); 39704af61e4fSDon Brace scsi_sanitize_inquiry_string(&inq_buff[16], 16); 397175d23d89SDon Brace 3972edd16368SStephen M. Cameron this_device->devtype = (inq_buff[0] & 0x1f); 3973edd16368SStephen M. Cameron memcpy(this_device->scsi3addr, scsi3addr, 8); 3974edd16368SStephen M. Cameron memcpy(this_device->vendor, &inq_buff[8], 3975edd16368SStephen M. Cameron sizeof(this_device->vendor)); 3976edd16368SStephen M. Cameron memcpy(this_device->model, &inq_buff[16], 3977edd16368SStephen M. Cameron sizeof(this_device->model)); 39787630b3a5SHannes Reinecke this_device->rev = inq_buff[2]; 3979edd16368SStephen M. Cameron memset(this_device->device_id, 0, 3980edd16368SStephen M. Cameron sizeof(this_device->device_id)); 39818383278dSScott Teel if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, 3982a45bcc4eSDon Brace sizeof(this_device->device_id)) < 0) { 39838383278dSScott Teel dev_err(&h->pdev->dev, 3984a45bcc4eSDon Brace "hpsa%d: %s: can't get device id for [%d:%d:%d:%d]\t%s\t%.16s\n", 39858383278dSScott Teel h->ctlr, __func__, 39868383278dSScott Teel h->scsi_host->host_no, 3987a45bcc4eSDon Brace this_device->bus, this_device->target, 3988a45bcc4eSDon Brace this_device->lun, 39898383278dSScott Teel scsi_device_type(this_device->devtype), 39908383278dSScott Teel this_device->model); 3991a45bcc4eSDon Brace rc = HPSA_LV_FAILED; 3992a45bcc4eSDon Brace goto bail_out; 3993a45bcc4eSDon Brace } 3994edd16368SStephen M. Cameron 3995af15ed36SDon Brace if ((this_device->devtype == TYPE_DISK || 3996af15ed36SDon Brace this_device->devtype == TYPE_ZBC) && 3997283b4a9bSStephen M. Cameron is_logical_dev_addr_mode(scsi3addr)) { 399885b29008SDon Brace unsigned char volume_offline; 399967955ba3SStephen M. Cameron 4000edd16368SStephen M. Cameron hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); 4001283b4a9bSStephen M. Cameron if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) 4002283b4a9bSStephen M. Cameron hpsa_get_ioaccel_status(h, scsi3addr, this_device); 400367955ba3SStephen M. Cameron volume_offline = hpsa_volume_offline(h, scsi3addr); 40044d17944aSHannes Reinecke if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED && 40054d17944aSHannes Reinecke h->legacy_board) { 40064d17944aSHannes Reinecke /* 40074d17944aSHannes Reinecke * Legacy boards might not support volume status 40084d17944aSHannes Reinecke */ 40094d17944aSHannes Reinecke dev_info(&h->pdev->dev, 40104d17944aSHannes Reinecke "C0:T%d:L%d Volume status not available, assuming online.\n", 40114d17944aSHannes Reinecke this_device->target, this_device->lun); 40124d17944aSHannes Reinecke volume_offline = 0; 40134d17944aSHannes Reinecke } 4014eb94588dSTomas Henzl this_device->volume_offline = volume_offline; 401585b29008SDon Brace if (volume_offline == HPSA_LV_FAILED) { 401685b29008SDon Brace rc = HPSA_LV_FAILED; 401785b29008SDon Brace dev_err(&h->pdev->dev, 401885b29008SDon Brace "%s: LV failed, device will be skipped.\n", 401985b29008SDon Brace __func__); 402085b29008SDon Brace goto bail_out; 402185b29008SDon Brace } 4022283b4a9bSStephen M. Cameron } else { 4023edd16368SStephen M. Cameron this_device->raid_level = RAID_UNKNOWN; 4024283b4a9bSStephen M. Cameron this_device->offload_config = 0; 40253e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(this_device); 4026a3144e0bSJoe Handzik this_device->hba_ioaccel_enabled = 0; 40279846590eSStephen M. Cameron this_device->volume_offline = 0; 402803383736SDon Brace this_device->queue_depth = h->nr_cmds; 4029283b4a9bSStephen M. Cameron } 4030edd16368SStephen M. Cameron 40315086435eSDon Brace if (this_device->external) 40325086435eSDon Brace this_device->queue_depth = EXTERNAL_QD; 40335086435eSDon Brace 40340b0e1d6cSStephen M. Cameron if (is_OBDR_device) { 40350b0e1d6cSStephen M. Cameron /* See if this is a One-Button-Disaster-Recovery device 40360b0e1d6cSStephen M. Cameron * by looking for "$DR-10" at offset 43 in inquiry data. 40370b0e1d6cSStephen M. Cameron */ 40380b0e1d6cSStephen M. Cameron obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; 40390b0e1d6cSStephen M. Cameron *is_OBDR_device = (this_device->devtype == TYPE_ROM && 40400b0e1d6cSStephen M. Cameron strncmp(obdr_sig, OBDR_TAPE_SIG, 40410b0e1d6cSStephen M. Cameron OBDR_SIG_LEN) == 0); 40420b0e1d6cSStephen M. Cameron } 4043edd16368SStephen M. Cameron kfree(inq_buff); 4044edd16368SStephen M. Cameron return 0; 4045edd16368SStephen M. Cameron 4046edd16368SStephen M. Cameron bail_out: 4047edd16368SStephen M. Cameron kfree(inq_buff); 4048683fc444SDon Brace return rc; 4049edd16368SStephen M. Cameron } 4050edd16368SStephen M. Cameron 4051c795505aSKevin Barnett /* 4052c795505aSKevin Barnett * Helper function to assign bus, target, lun mapping of devices. 4053edd16368SStephen M. Cameron * Logical drive target and lun are assigned at this time, but 4054edd16368SStephen M. Cameron * physical device lun and target assignment are deferred (assigned 4055edd16368SStephen M. Cameron * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) 4056edd16368SStephen M. Cameron */ 4057edd16368SStephen M. Cameron static void figure_bus_target_lun(struct ctlr_info *h, 40581f310bdeSStephen M. Cameron u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) 4059edd16368SStephen M. Cameron { 4060c795505aSKevin Barnett u32 lunid = get_unaligned_le32(lunaddrbytes); 4061edd16368SStephen M. Cameron 40621f310bdeSStephen M. Cameron if (!is_logical_dev_addr_mode(lunaddrbytes)) { 40631f310bdeSStephen M. Cameron /* physical device, target and lun filled in later */ 40647630b3a5SHannes Reinecke if (is_hba_lunid(lunaddrbytes)) { 40657630b3a5SHannes Reinecke int bus = HPSA_HBA_BUS; 40667630b3a5SHannes Reinecke 40677630b3a5SHannes Reinecke if (!device->rev) 40687630b3a5SHannes Reinecke bus = HPSA_LEGACY_HBA_BUS; 4069c795505aSKevin Barnett hpsa_set_bus_target_lun(device, 40707630b3a5SHannes Reinecke bus, 0, lunid & 0x3fff); 40717630b3a5SHannes Reinecke } else 40721f310bdeSStephen M. Cameron /* defer target, lun assignment for physical devices */ 4073c795505aSKevin Barnett hpsa_set_bus_target_lun(device, 4074c795505aSKevin Barnett HPSA_PHYSICAL_DEVICE_BUS, -1, -1); 40751f310bdeSStephen M. Cameron return; 40761f310bdeSStephen M. Cameron } 40771f310bdeSStephen M. Cameron /* It's a logical device */ 407866749d0dSScott Teel if (device->external) { 40791f310bdeSStephen M. Cameron hpsa_set_bus_target_lun(device, 4080c795505aSKevin Barnett HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, 4081c795505aSKevin Barnett lunid & 0x00ff); 40821f310bdeSStephen M. Cameron return; 4083339b2b14SStephen M. Cameron } 4084c795505aSKevin Barnett hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, 4085c795505aSKevin Barnett 0, lunid & 0x3fff); 4086edd16368SStephen M. Cameron } 4087edd16368SStephen M. Cameron 408866749d0dSScott Teel static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, 408966749d0dSScott Teel int i, int nphysicals, int nlocal_logicals) 409066749d0dSScott Teel { 409166749d0dSScott Teel /* In report logicals, local logicals are listed first, 409266749d0dSScott Teel * then any externals. 409366749d0dSScott Teel */ 409466749d0dSScott Teel int logicals_start = nphysicals + (raid_ctlr_position == 0); 409566749d0dSScott Teel 409666749d0dSScott Teel if (i == raid_ctlr_position) 409766749d0dSScott Teel return 0; 409866749d0dSScott Teel 409966749d0dSScott Teel if (i < logicals_start) 410066749d0dSScott Teel return 0; 410166749d0dSScott Teel 410266749d0dSScott Teel /* i is in logicals range, but still within local logicals */ 410366749d0dSScott Teel if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) 410466749d0dSScott Teel return 0; 410566749d0dSScott Teel 410666749d0dSScott Teel return 1; /* it's an external lun */ 410766749d0dSScott Teel } 410866749d0dSScott Teel 410954b6e9e9SScott Teel /* 4110edd16368SStephen M. Cameron * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, 4111edd16368SStephen M. Cameron * logdev. The number of luns in physdev and logdev are returned in 4112edd16368SStephen M. Cameron * *nphysicals and *nlogicals, respectively. 4113edd16368SStephen M. Cameron * Returns 0 on success, -1 otherwise. 4114edd16368SStephen M. Cameron */ 4115edd16368SStephen M. Cameron static int hpsa_gather_lun_info(struct ctlr_info *h, 411603383736SDon Brace struct ReportExtendedLUNdata *physdev, u32 *nphysicals, 411701a02ffcSStephen M. Cameron struct ReportLUNdata *logdev, u32 *nlogicals) 4118edd16368SStephen M. Cameron { 411903383736SDon Brace if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 4120edd16368SStephen M. Cameron dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 4121edd16368SStephen M. Cameron return -1; 4122edd16368SStephen M. Cameron } 412303383736SDon Brace *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; 4124edd16368SStephen M. Cameron if (*nphysicals > HPSA_MAX_PHYS_LUN) { 412503383736SDon Brace dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", 412603383736SDon Brace HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); 4127edd16368SStephen M. Cameron *nphysicals = HPSA_MAX_PHYS_LUN; 4128edd16368SStephen M. Cameron } 412903383736SDon Brace if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { 4130edd16368SStephen M. Cameron dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); 4131edd16368SStephen M. Cameron return -1; 4132edd16368SStephen M. Cameron } 41336df1e954SStephen M. Cameron *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; 4134edd16368SStephen M. Cameron /* Reject Logicals in excess of our max capability. */ 4135edd16368SStephen M. Cameron if (*nlogicals > HPSA_MAX_LUN) { 4136edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, 4137edd16368SStephen M. Cameron "maximum logical LUNs (%d) exceeded. " 4138edd16368SStephen M. Cameron "%d LUNs ignored.\n", HPSA_MAX_LUN, 4139edd16368SStephen M. Cameron *nlogicals - HPSA_MAX_LUN); 4140edd16368SStephen M. Cameron *nlogicals = HPSA_MAX_LUN; 4141edd16368SStephen M. Cameron } 4142edd16368SStephen M. Cameron if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { 4143edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, 4144edd16368SStephen M. Cameron "maximum logical + physical LUNs (%d) exceeded. " 4145edd16368SStephen M. Cameron "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, 4146edd16368SStephen M. Cameron *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); 4147edd16368SStephen M. Cameron *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; 4148edd16368SStephen M. Cameron } 4149edd16368SStephen M. Cameron return 0; 4150edd16368SStephen M. Cameron } 4151edd16368SStephen M. Cameron 415242a91641SDon Brace static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, 415342a91641SDon Brace int i, int nphysicals, int nlogicals, 4154a93aa1feSMatt Gates struct ReportExtendedLUNdata *physdev_list, 4155339b2b14SStephen M. Cameron struct ReportLUNdata *logdev_list) 4156339b2b14SStephen M. Cameron { 4157339b2b14SStephen M. Cameron /* Helper function, figure out where the LUN ID info is coming from 4158339b2b14SStephen M. Cameron * given index i, lists of physical and logical devices, where in 4159339b2b14SStephen M. Cameron * the list the raid controller is supposed to appear (first or last) 4160339b2b14SStephen M. Cameron */ 4161339b2b14SStephen M. Cameron 4162339b2b14SStephen M. Cameron int logicals_start = nphysicals + (raid_ctlr_position == 0); 4163339b2b14SStephen M. Cameron int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); 4164339b2b14SStephen M. Cameron 4165339b2b14SStephen M. Cameron if (i == raid_ctlr_position) 4166339b2b14SStephen M. Cameron return RAID_CTLR_LUNID; 4167339b2b14SStephen M. Cameron 4168339b2b14SStephen M. Cameron if (i < logicals_start) 4169d5b5d964SStephen M. Cameron return &physdev_list->LUN[i - 4170d5b5d964SStephen M. Cameron (raid_ctlr_position == 0)].lunid[0]; 4171339b2b14SStephen M. Cameron 4172339b2b14SStephen M. Cameron if (i < last_device) 4173339b2b14SStephen M. Cameron return &logdev_list->LUN[i - nphysicals - 4174339b2b14SStephen M. Cameron (raid_ctlr_position == 0)][0]; 4175339b2b14SStephen M. Cameron BUG(); 4176339b2b14SStephen M. Cameron return NULL; 4177339b2b14SStephen M. Cameron } 4178339b2b14SStephen M. Cameron 417903383736SDon Brace /* get physical drive ioaccel handle and queue depth */ 418003383736SDon Brace static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, 418103383736SDon Brace struct hpsa_scsi_dev_t *dev, 4182f2039b03SDon Brace struct ReportExtendedLUNdata *rlep, int rle_index, 418303383736SDon Brace struct bmic_identify_physical_device *id_phys) 418403383736SDon Brace { 418503383736SDon Brace int rc; 41864b6e5597SScott Teel struct ext_report_lun_entry *rle; 41874b6e5597SScott Teel 418827e1b94dSDon Brace if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN) 418927e1b94dSDon Brace return; 419027e1b94dSDon Brace 41914b6e5597SScott Teel rle = &rlep->LUN[rle_index]; 419203383736SDon Brace 419303383736SDon Brace dev->ioaccel_handle = rle->ioaccel_handle; 4194f2039b03SDon Brace if ((rle->device_flags & 0x08) && dev->ioaccel_handle) 4195a3144e0bSJoe Handzik dev->hba_ioaccel_enabled = 1; 419603383736SDon Brace memset(id_phys, 0, sizeof(*id_phys)); 4197f2039b03SDon Brace rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], 4198f2039b03SDon Brace GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, 419903383736SDon Brace sizeof(*id_phys)); 420003383736SDon Brace if (!rc) 420103383736SDon Brace /* Reserve space for FW operations */ 420203383736SDon Brace #define DRIVE_CMDS_RESERVED_FOR_FW 2 420303383736SDon Brace #define DRIVE_QUEUE_DEPTH 7 420403383736SDon Brace dev->queue_depth = 420503383736SDon Brace le16_to_cpu(id_phys->current_queue_depth_limit) - 420603383736SDon Brace DRIVE_CMDS_RESERVED_FOR_FW; 420703383736SDon Brace else 420803383736SDon Brace dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ 420903383736SDon Brace } 421003383736SDon Brace 42118270b862SJoe Handzik static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, 4212f2039b03SDon Brace struct ReportExtendedLUNdata *rlep, int rle_index, 42138270b862SJoe Handzik struct bmic_identify_physical_device *id_phys) 42148270b862SJoe Handzik { 421527e1b94dSDon Brace struct ext_report_lun_entry *rle; 421627e1b94dSDon Brace 421727e1b94dSDon Brace if (rle_index < 0 || rle_index >= HPSA_MAX_PHYS_LUN) 421827e1b94dSDon Brace return; 421927e1b94dSDon Brace 422027e1b94dSDon Brace rle = &rlep->LUN[rle_index]; 4221f2039b03SDon Brace 4222f2039b03SDon Brace if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) 42238270b862SJoe Handzik this_device->hba_ioaccel_enabled = 1; 42248270b862SJoe Handzik 42258270b862SJoe Handzik memcpy(&this_device->active_path_index, 42268270b862SJoe Handzik &id_phys->active_path_number, 42278270b862SJoe Handzik sizeof(this_device->active_path_index)); 42288270b862SJoe Handzik memcpy(&this_device->path_map, 42298270b862SJoe Handzik &id_phys->redundant_path_present_map, 42308270b862SJoe Handzik sizeof(this_device->path_map)); 42318270b862SJoe Handzik memcpy(&this_device->box, 42328270b862SJoe Handzik &id_phys->alternate_paths_phys_box_on_port, 42338270b862SJoe Handzik sizeof(this_device->box)); 42348270b862SJoe Handzik memcpy(&this_device->phys_connector, 42358270b862SJoe Handzik &id_phys->alternate_paths_phys_connector, 42368270b862SJoe Handzik sizeof(this_device->phys_connector)); 42378270b862SJoe Handzik memcpy(&this_device->bay, 42388270b862SJoe Handzik &id_phys->phys_bay_in_box, 42398270b862SJoe Handzik sizeof(this_device->bay)); 42408270b862SJoe Handzik } 42418270b862SJoe Handzik 424266749d0dSScott Teel /* get number of local logical disks. */ 424366749d0dSScott Teel static int hpsa_set_local_logical_count(struct ctlr_info *h, 424466749d0dSScott Teel struct bmic_identify_controller *id_ctlr, 424566749d0dSScott Teel u32 *nlocals) 424666749d0dSScott Teel { 424766749d0dSScott Teel int rc; 424866749d0dSScott Teel 424966749d0dSScott Teel if (!id_ctlr) { 425066749d0dSScott Teel dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", 425166749d0dSScott Teel __func__); 425266749d0dSScott Teel return -ENOMEM; 425366749d0dSScott Teel } 425466749d0dSScott Teel memset(id_ctlr, 0, sizeof(*id_ctlr)); 425566749d0dSScott Teel rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); 425666749d0dSScott Teel if (!rc) 4257c99dfd20SChristos Gkekas if (id_ctlr->configured_logical_drive_count < 255) 425866749d0dSScott Teel *nlocals = id_ctlr->configured_logical_drive_count; 425966749d0dSScott Teel else 426066749d0dSScott Teel *nlocals = le16_to_cpu( 426166749d0dSScott Teel id_ctlr->extended_logical_unit_count); 426266749d0dSScott Teel else 426366749d0dSScott Teel *nlocals = -1; 426466749d0dSScott Teel return rc; 426566749d0dSScott Teel } 426666749d0dSScott Teel 426764ce60caSDon Brace static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes) 426864ce60caSDon Brace { 426964ce60caSDon Brace struct bmic_identify_physical_device *id_phys; 427064ce60caSDon Brace bool is_spare = false; 427164ce60caSDon Brace int rc; 427264ce60caSDon Brace 427364ce60caSDon Brace id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 427464ce60caSDon Brace if (!id_phys) 427564ce60caSDon Brace return false; 427664ce60caSDon Brace 427764ce60caSDon Brace rc = hpsa_bmic_id_physical_device(h, 427864ce60caSDon Brace lunaddrbytes, 427964ce60caSDon Brace GET_BMIC_DRIVE_NUMBER(lunaddrbytes), 428064ce60caSDon Brace id_phys, sizeof(*id_phys)); 428164ce60caSDon Brace if (rc == 0) 428264ce60caSDon Brace is_spare = (id_phys->more_flags >> 6) & 0x01; 428364ce60caSDon Brace 428464ce60caSDon Brace kfree(id_phys); 428564ce60caSDon Brace return is_spare; 428664ce60caSDon Brace } 428764ce60caSDon Brace 428864ce60caSDon Brace #define RPL_DEV_FLAG_NON_DISK 0x1 428964ce60caSDon Brace #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2 429064ce60caSDon Brace #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4 429164ce60caSDon Brace 429264ce60caSDon Brace #define BMIC_DEVICE_TYPE_ENCLOSURE 6 429364ce60caSDon Brace 429464ce60caSDon Brace static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes, 429564ce60caSDon Brace struct ext_report_lun_entry *rle) 429664ce60caSDon Brace { 429764ce60caSDon Brace u8 device_flags; 429864ce60caSDon Brace u8 device_type; 429964ce60caSDon Brace 430064ce60caSDon Brace if (!MASKED_DEVICE(lunaddrbytes)) 430164ce60caSDon Brace return false; 430264ce60caSDon Brace 430364ce60caSDon Brace device_flags = rle->device_flags; 430464ce60caSDon Brace device_type = rle->device_type; 430564ce60caSDon Brace 430664ce60caSDon Brace if (device_flags & RPL_DEV_FLAG_NON_DISK) { 430764ce60caSDon Brace if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE) 430864ce60caSDon Brace return false; 430964ce60caSDon Brace return true; 431064ce60caSDon Brace } 431164ce60caSDon Brace 431264ce60caSDon Brace if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED)) 431364ce60caSDon Brace return false; 431464ce60caSDon Brace 431564ce60caSDon Brace if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK) 431664ce60caSDon Brace return false; 431764ce60caSDon Brace 431864ce60caSDon Brace /* 431964ce60caSDon Brace * Spares may be spun down, we do not want to 432064ce60caSDon Brace * do an Inquiry to a RAID set spare drive as 432164ce60caSDon Brace * that would have them spun up, that is a 432264ce60caSDon Brace * performance hit because I/O to the RAID device 432364ce60caSDon Brace * stops while the spin up occurs which can take 432464ce60caSDon Brace * over 50 seconds. 432564ce60caSDon Brace */ 432664ce60caSDon Brace if (hpsa_is_disk_spare(h, lunaddrbytes)) 432764ce60caSDon Brace return true; 432864ce60caSDon Brace 432964ce60caSDon Brace return false; 433064ce60caSDon Brace } 433166749d0dSScott Teel 43328aa60681SDon Brace static void hpsa_update_scsi_devices(struct ctlr_info *h) 4333edd16368SStephen M. Cameron { 4334edd16368SStephen M. Cameron /* the idea here is we could get notified 4335edd16368SStephen M. Cameron * that some devices have changed, so we do a report 4336edd16368SStephen M. Cameron * physical luns and report logical luns cmd, and adjust 4337edd16368SStephen M. Cameron * our list of devices accordingly. 4338edd16368SStephen M. Cameron * 4339edd16368SStephen M. Cameron * The scsi3addr's of devices won't change so long as the 4340edd16368SStephen M. Cameron * adapter is not reset. That means we can rescan and 4341edd16368SStephen M. Cameron * tell which devices we already know about, vs. new 4342edd16368SStephen M. Cameron * devices, vs. disappearing devices. 4343edd16368SStephen M. Cameron */ 4344a93aa1feSMatt Gates struct ReportExtendedLUNdata *physdev_list = NULL; 4345edd16368SStephen M. Cameron struct ReportLUNdata *logdev_list = NULL; 434603383736SDon Brace struct bmic_identify_physical_device *id_phys = NULL; 434766749d0dSScott Teel struct bmic_identify_controller *id_ctlr = NULL; 434801a02ffcSStephen M. Cameron u32 nphysicals = 0; 434901a02ffcSStephen M. Cameron u32 nlogicals = 0; 435066749d0dSScott Teel u32 nlocal_logicals = 0; 435101a02ffcSStephen M. Cameron u32 ndev_allocated = 0; 4352edd16368SStephen M. Cameron struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; 4353edd16368SStephen M. Cameron int ncurrent = 0; 43544f4eb9f1SScott Teel int i, n_ext_target_devs, ndevs_to_allocate; 4355339b2b14SStephen M. Cameron int raid_ctlr_position; 435604fa2f44SKevin Barnett bool physical_device; 4357aca4a520SScott Teel DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); 4358edd16368SStephen M. Cameron 43596396bb22SKees Cook currentsd = kcalloc(HPSA_MAX_DEVICES, sizeof(*currentsd), GFP_KERNEL); 436092084715SStephen M. Cameron physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); 436192084715SStephen M. Cameron logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); 4362edd16368SStephen M. Cameron tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); 436303383736SDon Brace id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 436466749d0dSScott Teel id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); 4365edd16368SStephen M. Cameron 436603383736SDon Brace if (!currentsd || !physdev_list || !logdev_list || 436766749d0dSScott Teel !tmpdevice || !id_phys || !id_ctlr) { 4368edd16368SStephen M. Cameron dev_err(&h->pdev->dev, "out of memory\n"); 4369edd16368SStephen M. Cameron goto out; 4370edd16368SStephen M. Cameron } 4371edd16368SStephen M. Cameron memset(lunzerobits, 0, sizeof(lunzerobits)); 4372edd16368SStephen M. Cameron 4373853633e8SDon Brace h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ 4374853633e8SDon Brace 437503383736SDon Brace if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, 4376853633e8SDon Brace logdev_list, &nlogicals)) { 4377853633e8SDon Brace h->drv_req_rescan = 1; 4378edd16368SStephen M. Cameron goto out; 4379853633e8SDon Brace } 4380edd16368SStephen M. Cameron 438166749d0dSScott Teel /* Set number of local logicals (non PTRAID) */ 438266749d0dSScott Teel if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { 438366749d0dSScott Teel dev_warn(&h->pdev->dev, 438466749d0dSScott Teel "%s: Can't determine number of local logical devices.\n", 438566749d0dSScott Teel __func__); 438666749d0dSScott Teel } 4387edd16368SStephen M. Cameron 4388aca4a520SScott Teel /* We might see up to the maximum number of logical and physical disks 4389aca4a520SScott Teel * plus external target devices, and a device for the local RAID 4390aca4a520SScott Teel * controller. 4391edd16368SStephen M. Cameron */ 4392aca4a520SScott Teel ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; 4393edd16368SStephen M. Cameron 43944e188184SBader Ali Saleh hpsa_ext_ctrl_present(h, physdev_list); 43954e188184SBader Ali Saleh 4396edd16368SStephen M. Cameron /* Allocate the per device structures */ 4397edd16368SStephen M. Cameron for (i = 0; i < ndevs_to_allocate; i++) { 4398b7ec021fSScott Teel if (i >= HPSA_MAX_DEVICES) { 4399b7ec021fSScott Teel dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." 4400b7ec021fSScott Teel " %d devices ignored.\n", HPSA_MAX_DEVICES, 4401b7ec021fSScott Teel ndevs_to_allocate - HPSA_MAX_DEVICES); 4402b7ec021fSScott Teel break; 4403b7ec021fSScott Teel } 4404b7ec021fSScott Teel 4405edd16368SStephen M. Cameron currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); 4406edd16368SStephen M. Cameron if (!currentsd[i]) { 4407853633e8SDon Brace h->drv_req_rescan = 1; 4408edd16368SStephen M. Cameron goto out; 4409edd16368SStephen M. Cameron } 4410edd16368SStephen M. Cameron ndev_allocated++; 4411edd16368SStephen M. Cameron } 4412edd16368SStephen M. Cameron 44138645291bSStephen M. Cameron if (is_scsi_rev_5(h)) 4414339b2b14SStephen M. Cameron raid_ctlr_position = 0; 4415339b2b14SStephen M. Cameron else 4416339b2b14SStephen M. Cameron raid_ctlr_position = nphysicals + nlogicals; 4417339b2b14SStephen M. Cameron 4418edd16368SStephen M. Cameron /* adjust our table of devices */ 44194f4eb9f1SScott Teel n_ext_target_devs = 0; 4420edd16368SStephen M. Cameron for (i = 0; i < nphysicals + nlogicals + 1; i++) { 44210b0e1d6cSStephen M. Cameron u8 *lunaddrbytes, is_OBDR = 0; 4422683fc444SDon Brace int rc = 0; 4423f2039b03SDon Brace int phys_dev_index = i - (raid_ctlr_position == 0); 442464ce60caSDon Brace bool skip_device = false; 4425edd16368SStephen M. Cameron 4426421bf80cSScott Teel memset(tmpdevice, 0, sizeof(*tmpdevice)); 4427421bf80cSScott Teel 442804fa2f44SKevin Barnett physical_device = i < nphysicals + (raid_ctlr_position == 0); 4429edd16368SStephen M. Cameron 4430edd16368SStephen M. Cameron /* Figure out where the LUN ID info is coming from */ 4431339b2b14SStephen M. Cameron lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, 4432339b2b14SStephen M. Cameron i, nphysicals, nlogicals, physdev_list, logdev_list); 443341ce4c35SStephen Cameron 443486cf7130SDon Brace /* Determine if this is a lun from an external target array */ 443586cf7130SDon Brace tmpdevice->external = 443686cf7130SDon Brace figure_external_status(h, raid_ctlr_position, i, 443786cf7130SDon Brace nphysicals, nlocal_logicals); 443886cf7130SDon Brace 443964ce60caSDon Brace /* 444064ce60caSDon Brace * Skip over some devices such as a spare. 444164ce60caSDon Brace */ 444227e1b94dSDon Brace if (phys_dev_index >= 0 && !tmpdevice->external && 444327e1b94dSDon Brace physical_device) { 444464ce60caSDon Brace skip_device = hpsa_skip_device(h, lunaddrbytes, 444564ce60caSDon Brace &physdev_list->LUN[phys_dev_index]); 444664ce60caSDon Brace if (skip_device) 4447edd16368SStephen M. Cameron continue; 444864ce60caSDon Brace } 4449edd16368SStephen M. Cameron 4450b2582a65SDon Brace /* Get device type, vendor, model, device id, raid_map */ 4451683fc444SDon Brace rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, 4452683fc444SDon Brace &is_OBDR); 4453683fc444SDon Brace if (rc == -ENOMEM) { 4454683fc444SDon Brace dev_warn(&h->pdev->dev, 4455683fc444SDon Brace "Out of memory, rescan deferred.\n"); 4456853633e8SDon Brace h->drv_req_rescan = 1; 4457683fc444SDon Brace goto out; 4458853633e8SDon Brace } 4459683fc444SDon Brace if (rc) { 446085b29008SDon Brace h->drv_req_rescan = 1; 4461683fc444SDon Brace continue; 4462683fc444SDon Brace } 4463683fc444SDon Brace 44641f310bdeSStephen M. Cameron figure_bus_target_lun(h, lunaddrbytes, tmpdevice); 4465edd16368SStephen M. Cameron this_device = currentsd[ncurrent]; 4466edd16368SStephen M. Cameron 4467edd16368SStephen M. Cameron *this_device = *tmpdevice; 446804fa2f44SKevin Barnett this_device->physical_device = physical_device; 4469edd16368SStephen M. Cameron 447004fa2f44SKevin Barnett /* 447104fa2f44SKevin Barnett * Expose all devices except for physical devices that 447204fa2f44SKevin Barnett * are masked. 447304fa2f44SKevin Barnett */ 447404fa2f44SKevin Barnett if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) 44752a168208SKevin Barnett this_device->expose_device = 0; 44762a168208SKevin Barnett else 44772a168208SKevin Barnett this_device->expose_device = 1; 447841ce4c35SStephen Cameron 4479d04e62b9SKevin Barnett 4480d04e62b9SKevin Barnett /* 4481d04e62b9SKevin Barnett * Get the SAS address for physical devices that are exposed. 4482d04e62b9SKevin Barnett */ 4483d04e62b9SKevin Barnett if (this_device->physical_device && this_device->expose_device) 4484d04e62b9SKevin Barnett hpsa_get_sas_address(h, lunaddrbytes, this_device); 4485edd16368SStephen M. Cameron 4486edd16368SStephen M. Cameron switch (this_device->devtype) { 44870b0e1d6cSStephen M. Cameron case TYPE_ROM: 4488edd16368SStephen M. Cameron /* We don't *really* support actual CD-ROM devices, 4489edd16368SStephen M. Cameron * just "One Button Disaster Recovery" tape drive 4490edd16368SStephen M. Cameron * which temporarily pretends to be a CD-ROM drive. 4491edd16368SStephen M. Cameron * So we check that the device is really an OBDR tape 4492edd16368SStephen M. Cameron * device by checking for "$DR-10" in bytes 43-48 of 4493edd16368SStephen M. Cameron * the inquiry data. 4494edd16368SStephen M. Cameron */ 44950b0e1d6cSStephen M. Cameron if (is_OBDR) 4496edd16368SStephen M. Cameron ncurrent++; 4497edd16368SStephen M. Cameron break; 4498edd16368SStephen M. Cameron case TYPE_DISK: 4499af15ed36SDon Brace case TYPE_ZBC: 450004fa2f44SKevin Barnett if (this_device->physical_device) { 4501b9092b79SKevin Barnett /* The disk is in HBA mode. */ 4502b9092b79SKevin Barnett /* Never use RAID mapper in HBA mode. */ 4503ecf418d1SJoe Handzik this_device->offload_enabled = 0; 450403383736SDon Brace hpsa_get_ioaccel_drive_info(h, this_device, 4505f2039b03SDon Brace physdev_list, phys_dev_index, id_phys); 4506f2039b03SDon Brace hpsa_get_path_info(this_device, 4507f2039b03SDon Brace physdev_list, phys_dev_index, id_phys); 4508b9092b79SKevin Barnett } 4509edd16368SStephen M. Cameron ncurrent++; 4510edd16368SStephen M. Cameron break; 4511edd16368SStephen M. Cameron case TYPE_TAPE: 4512edd16368SStephen M. Cameron case TYPE_MEDIUM_CHANGER: 4513cca8f13bSDon Brace ncurrent++; 4514cca8f13bSDon Brace break; 451541ce4c35SStephen Cameron case TYPE_ENCLOSURE: 451617a9e54aSDon Brace if (!this_device->external) 4517cca8f13bSDon Brace hpsa_get_enclosure_info(h, lunaddrbytes, 4518cca8f13bSDon Brace physdev_list, phys_dev_index, 4519cca8f13bSDon Brace this_device); 452041ce4c35SStephen Cameron ncurrent++; 452141ce4c35SStephen Cameron break; 4522edd16368SStephen M. Cameron case TYPE_RAID: 4523edd16368SStephen M. Cameron /* Only present the Smartarray HBA as a RAID controller. 4524edd16368SStephen M. Cameron * If it's a RAID controller other than the HBA itself 4525edd16368SStephen M. Cameron * (an external RAID controller, MSA500 or similar) 4526edd16368SStephen M. Cameron * don't present it. 4527edd16368SStephen M. Cameron */ 4528edd16368SStephen M. Cameron if (!is_hba_lunid(lunaddrbytes)) 4529edd16368SStephen M. Cameron break; 4530edd16368SStephen M. Cameron ncurrent++; 4531edd16368SStephen M. Cameron break; 4532edd16368SStephen M. Cameron default: 4533edd16368SStephen M. Cameron break; 4534edd16368SStephen M. Cameron } 4535cfe5badcSScott Teel if (ncurrent >= HPSA_MAX_DEVICES) 4536edd16368SStephen M. Cameron break; 4537edd16368SStephen M. Cameron } 4538d04e62b9SKevin Barnett 4539d04e62b9SKevin Barnett if (h->sas_host == NULL) { 4540d04e62b9SKevin Barnett int rc = 0; 4541d04e62b9SKevin Barnett 4542d04e62b9SKevin Barnett rc = hpsa_add_sas_host(h); 4543d04e62b9SKevin Barnett if (rc) { 4544d04e62b9SKevin Barnett dev_warn(&h->pdev->dev, 4545d04e62b9SKevin Barnett "Could not add sas host %d\n", rc); 4546d04e62b9SKevin Barnett goto out; 4547d04e62b9SKevin Barnett } 4548d04e62b9SKevin Barnett } 4549d04e62b9SKevin Barnett 45508aa60681SDon Brace adjust_hpsa_scsi_table(h, currentsd, ncurrent); 4551edd16368SStephen M. Cameron out: 4552edd16368SStephen M. Cameron kfree(tmpdevice); 4553edd16368SStephen M. Cameron for (i = 0; i < ndev_allocated; i++) 4554edd16368SStephen M. Cameron kfree(currentsd[i]); 4555edd16368SStephen M. Cameron kfree(currentsd); 4556edd16368SStephen M. Cameron kfree(physdev_list); 4557edd16368SStephen M. Cameron kfree(logdev_list); 455866749d0dSScott Teel kfree(id_ctlr); 455903383736SDon Brace kfree(id_phys); 4560edd16368SStephen M. Cameron } 4561edd16368SStephen M. Cameron 4562ec5cbf04SWebb Scales static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, 4563ec5cbf04SWebb Scales struct scatterlist *sg) 4564ec5cbf04SWebb Scales { 4565ec5cbf04SWebb Scales u64 addr64 = (u64) sg_dma_address(sg); 4566ec5cbf04SWebb Scales unsigned int len = sg_dma_len(sg); 4567ec5cbf04SWebb Scales 4568ec5cbf04SWebb Scales desc->Addr = cpu_to_le64(addr64); 4569ec5cbf04SWebb Scales desc->Len = cpu_to_le32(len); 4570ec5cbf04SWebb Scales desc->Ext = 0; 4571ec5cbf04SWebb Scales } 4572ec5cbf04SWebb Scales 4573c7ee65b3SWebb Scales /* 4574c7ee65b3SWebb Scales * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci 4575edd16368SStephen M. Cameron * dma mapping and fills in the scatter gather entries of the 4576edd16368SStephen M. Cameron * hpsa command, cp. 4577edd16368SStephen M. Cameron */ 457833a2ffceSStephen M. Cameron static int hpsa_scatter_gather(struct ctlr_info *h, 4579edd16368SStephen M. Cameron struct CommandList *cp, 4580edd16368SStephen M. Cameron struct scsi_cmnd *cmd) 4581edd16368SStephen M. Cameron { 4582edd16368SStephen M. Cameron struct scatterlist *sg; 4583b3a7ba7cSWebb Scales int use_sg, i, sg_limit, chained, last_sg; 458433a2ffceSStephen M. Cameron struct SGDescriptor *curr_sg; 4585edd16368SStephen M. Cameron 458633a2ffceSStephen M. Cameron BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4587edd16368SStephen M. Cameron 4588edd16368SStephen M. Cameron use_sg = scsi_dma_map(cmd); 4589edd16368SStephen M. Cameron if (use_sg < 0) 4590edd16368SStephen M. Cameron return use_sg; 4591edd16368SStephen M. Cameron 4592edd16368SStephen M. Cameron if (!use_sg) 4593edd16368SStephen M. Cameron goto sglist_finished; 4594edd16368SStephen M. Cameron 4595b3a7ba7cSWebb Scales /* 4596b3a7ba7cSWebb Scales * If the number of entries is greater than the max for a single list, 4597b3a7ba7cSWebb Scales * then we have a chained list; we will set up all but one entry in the 4598b3a7ba7cSWebb Scales * first list (the last entry is saved for link information); 4599b3a7ba7cSWebb Scales * otherwise, we don't have a chained list and we'll set up at each of 4600b3a7ba7cSWebb Scales * the entries in the one list. 4601b3a7ba7cSWebb Scales */ 460233a2ffceSStephen M. Cameron curr_sg = cp->SG; 4603b3a7ba7cSWebb Scales chained = use_sg > h->max_cmd_sg_entries; 4604b3a7ba7cSWebb Scales sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; 4605b3a7ba7cSWebb Scales last_sg = scsi_sg_count(cmd) - 1; 4606b3a7ba7cSWebb Scales scsi_for_each_sg(cmd, sg, sg_limit, i) { 4607ec5cbf04SWebb Scales hpsa_set_sg_descriptor(curr_sg, sg); 460833a2ffceSStephen M. Cameron curr_sg++; 460933a2ffceSStephen M. Cameron } 4610ec5cbf04SWebb Scales 4611b3a7ba7cSWebb Scales if (chained) { 4612b3a7ba7cSWebb Scales /* 4613b3a7ba7cSWebb Scales * Continue with the chained list. Set curr_sg to the chained 4614b3a7ba7cSWebb Scales * list. Modify the limit to the total count less the entries 4615b3a7ba7cSWebb Scales * we've already set up. Resume the scan at the list entry 4616b3a7ba7cSWebb Scales * where the previous loop left off. 4617b3a7ba7cSWebb Scales */ 4618b3a7ba7cSWebb Scales curr_sg = h->cmd_sg_list[cp->cmdindex]; 4619b3a7ba7cSWebb Scales sg_limit = use_sg - sg_limit; 4620b3a7ba7cSWebb Scales for_each_sg(sg, sg, sg_limit, i) { 4621b3a7ba7cSWebb Scales hpsa_set_sg_descriptor(curr_sg, sg); 4622b3a7ba7cSWebb Scales curr_sg++; 4623b3a7ba7cSWebb Scales } 4624b3a7ba7cSWebb Scales } 4625b3a7ba7cSWebb Scales 4626ec5cbf04SWebb Scales /* Back the pointer up to the last entry and mark it as "last". */ 4627b3a7ba7cSWebb Scales (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); 462833a2ffceSStephen M. Cameron 462933a2ffceSStephen M. Cameron if (use_sg + chained > h->maxSG) 463033a2ffceSStephen M. Cameron h->maxSG = use_sg + chained; 463133a2ffceSStephen M. Cameron 463233a2ffceSStephen M. Cameron if (chained) { 463333a2ffceSStephen M. Cameron cp->Header.SGList = h->max_cmd_sg_entries; 463450a0decfSStephen M. Cameron cp->Header.SGTotal = cpu_to_le16(use_sg + 1); 4635e2bea6dfSStephen M. Cameron if (hpsa_map_sg_chain_block(h, cp)) { 4636e2bea6dfSStephen M. Cameron scsi_dma_unmap(cmd); 4637e2bea6dfSStephen M. Cameron return -1; 4638e2bea6dfSStephen M. Cameron } 463933a2ffceSStephen M. Cameron return 0; 4640edd16368SStephen M. Cameron } 4641edd16368SStephen M. Cameron 4642edd16368SStephen M. Cameron sglist_finished: 4643edd16368SStephen M. Cameron 464401a02ffcSStephen M. Cameron cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ 4645c7ee65b3SWebb Scales cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ 4646edd16368SStephen M. Cameron return 0; 4647edd16368SStephen M. Cameron } 4648edd16368SStephen M. Cameron 4649b63c64acSDon Brace static inline void warn_zero_length_transfer(struct ctlr_info *h, 4650b63c64acSDon Brace u8 *cdb, int cdb_len, 4651b63c64acSDon Brace const char *func) 4652b63c64acSDon Brace { 4653f4d0ad1fSAndy Shevchenko dev_warn(&h->pdev->dev, 4654f4d0ad1fSAndy Shevchenko "%s: Blocking zero-length request: CDB:%*phN\n", 4655f4d0ad1fSAndy Shevchenko func, cdb_len, cdb); 4656b63c64acSDon Brace } 4657b63c64acSDon Brace 4658b63c64acSDon Brace #define IO_ACCEL_INELIGIBLE 1 4659b63c64acSDon Brace /* zero-length transfers trigger hardware errors. */ 4660b63c64acSDon Brace static bool is_zero_length_transfer(u8 *cdb) 4661b63c64acSDon Brace { 4662b63c64acSDon Brace u32 block_cnt; 4663b63c64acSDon Brace 4664b63c64acSDon Brace /* Block zero-length transfer sizes on certain commands. */ 4665b63c64acSDon Brace switch (cdb[0]) { 4666b63c64acSDon Brace case READ_10: 4667b63c64acSDon Brace case WRITE_10: 4668b63c64acSDon Brace case VERIFY: /* 0x2F */ 4669b63c64acSDon Brace case WRITE_VERIFY: /* 0x2E */ 4670b63c64acSDon Brace block_cnt = get_unaligned_be16(&cdb[7]); 4671b63c64acSDon Brace break; 4672b63c64acSDon Brace case READ_12: 4673b63c64acSDon Brace case WRITE_12: 4674b63c64acSDon Brace case VERIFY_12: /* 0xAF */ 4675b63c64acSDon Brace case WRITE_VERIFY_12: /* 0xAE */ 4676b63c64acSDon Brace block_cnt = get_unaligned_be32(&cdb[6]); 4677b63c64acSDon Brace break; 4678b63c64acSDon Brace case READ_16: 4679b63c64acSDon Brace case WRITE_16: 4680b63c64acSDon Brace case VERIFY_16: /* 0x8F */ 4681b63c64acSDon Brace block_cnt = get_unaligned_be32(&cdb[10]); 4682b63c64acSDon Brace break; 4683b63c64acSDon Brace default: 4684b63c64acSDon Brace return false; 4685b63c64acSDon Brace } 4686b63c64acSDon Brace 4687b63c64acSDon Brace return block_cnt == 0; 4688b63c64acSDon Brace } 4689b63c64acSDon Brace 4690283b4a9bSStephen M. Cameron static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) 4691283b4a9bSStephen M. Cameron { 4692283b4a9bSStephen M. Cameron int is_write = 0; 4693283b4a9bSStephen M. Cameron u32 block; 4694283b4a9bSStephen M. Cameron u32 block_cnt; 4695283b4a9bSStephen M. Cameron 4696283b4a9bSStephen M. Cameron /* Perform some CDB fixups if needed using 10 byte reads/writes only */ 4697283b4a9bSStephen M. Cameron switch (cdb[0]) { 4698283b4a9bSStephen M. Cameron case WRITE_6: 4699283b4a9bSStephen M. Cameron case WRITE_12: 4700283b4a9bSStephen M. Cameron is_write = 1; 4701df561f66SGustavo A. R. Silva fallthrough; 4702283b4a9bSStephen M. Cameron case READ_6: 4703283b4a9bSStephen M. Cameron case READ_12: 4704283b4a9bSStephen M. Cameron if (*cdb_len == 6) { 4705abbada71SMahesh Rajashekhara block = (((cdb[1] & 0x1F) << 16) | 4706abbada71SMahesh Rajashekhara (cdb[2] << 8) | 4707abbada71SMahesh Rajashekhara cdb[3]); 4708283b4a9bSStephen M. Cameron block_cnt = cdb[4]; 4709c8a6c9a6SDon Brace if (block_cnt == 0) 4710c8a6c9a6SDon Brace block_cnt = 256; 4711283b4a9bSStephen M. Cameron } else { 4712283b4a9bSStephen M. Cameron BUG_ON(*cdb_len != 12); 4713c8a6c9a6SDon Brace block = get_unaligned_be32(&cdb[2]); 4714c8a6c9a6SDon Brace block_cnt = get_unaligned_be32(&cdb[6]); 4715283b4a9bSStephen M. Cameron } 4716283b4a9bSStephen M. Cameron if (block_cnt > 0xffff) 4717283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 4718283b4a9bSStephen M. Cameron 4719283b4a9bSStephen M. Cameron cdb[0] = is_write ? WRITE_10 : READ_10; 4720283b4a9bSStephen M. Cameron cdb[1] = 0; 4721283b4a9bSStephen M. Cameron cdb[2] = (u8) (block >> 24); 4722283b4a9bSStephen M. Cameron cdb[3] = (u8) (block >> 16); 4723283b4a9bSStephen M. Cameron cdb[4] = (u8) (block >> 8); 4724283b4a9bSStephen M. Cameron cdb[5] = (u8) (block); 4725283b4a9bSStephen M. Cameron cdb[6] = 0; 4726283b4a9bSStephen M. Cameron cdb[7] = (u8) (block_cnt >> 8); 4727283b4a9bSStephen M. Cameron cdb[8] = (u8) (block_cnt); 4728283b4a9bSStephen M. Cameron cdb[9] = 0; 4729283b4a9bSStephen M. Cameron *cdb_len = 10; 4730283b4a9bSStephen M. Cameron break; 4731283b4a9bSStephen M. Cameron } 4732283b4a9bSStephen M. Cameron return 0; 4733283b4a9bSStephen M. Cameron } 4734283b4a9bSStephen M. Cameron 4735c349775eSScott Teel static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, 4736283b4a9bSStephen M. Cameron struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 473703383736SDon Brace u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4738e1f7de0cSMatt Gates { 4739e1f7de0cSMatt Gates struct scsi_cmnd *cmd = c->scsi_cmd; 4740e1f7de0cSMatt Gates struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 4741e1f7de0cSMatt Gates unsigned int len; 4742e1f7de0cSMatt Gates unsigned int total_len = 0; 4743e1f7de0cSMatt Gates struct scatterlist *sg; 4744e1f7de0cSMatt Gates u64 addr64; 4745e1f7de0cSMatt Gates int use_sg, i; 4746e1f7de0cSMatt Gates struct SGDescriptor *curr_sg; 4747e1f7de0cSMatt Gates u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; 4748e1f7de0cSMatt Gates 4749283b4a9bSStephen M. Cameron /* TODO: implement chaining support */ 475003383736SDon Brace if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { 475103383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4752283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 475303383736SDon Brace } 4754283b4a9bSStephen M. Cameron 4755e1f7de0cSMatt Gates BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); 4756e1f7de0cSMatt Gates 4757b63c64acSDon Brace if (is_zero_length_transfer(cdb)) { 4758b63c64acSDon Brace warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4759b63c64acSDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4760b63c64acSDon Brace return IO_ACCEL_INELIGIBLE; 4761b63c64acSDon Brace } 4762b63c64acSDon Brace 476303383736SDon Brace if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 476403383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4765283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 476603383736SDon Brace } 4767283b4a9bSStephen M. Cameron 4768e1f7de0cSMatt Gates c->cmd_type = CMD_IOACCEL1; 4769e1f7de0cSMatt Gates 4770e1f7de0cSMatt Gates /* Adjust the DMA address to point to the accelerated command buffer */ 4771e1f7de0cSMatt Gates c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + 4772e1f7de0cSMatt Gates (c->cmdindex * sizeof(*cp)); 4773e1f7de0cSMatt Gates BUG_ON(c->busaddr & 0x0000007F); 4774e1f7de0cSMatt Gates 4775e1f7de0cSMatt Gates use_sg = scsi_dma_map(cmd); 477603383736SDon Brace if (use_sg < 0) { 477703383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4778e1f7de0cSMatt Gates return use_sg; 477903383736SDon Brace } 4780e1f7de0cSMatt Gates 4781e1f7de0cSMatt Gates if (use_sg) { 4782e1f7de0cSMatt Gates curr_sg = cp->SG; 4783e1f7de0cSMatt Gates scsi_for_each_sg(cmd, sg, use_sg, i) { 4784e1f7de0cSMatt Gates addr64 = (u64) sg_dma_address(sg); 4785e1f7de0cSMatt Gates len = sg_dma_len(sg); 4786e1f7de0cSMatt Gates total_len += len; 478750a0decfSStephen M. Cameron curr_sg->Addr = cpu_to_le64(addr64); 478850a0decfSStephen M. Cameron curr_sg->Len = cpu_to_le32(len); 478950a0decfSStephen M. Cameron curr_sg->Ext = cpu_to_le32(0); 4790e1f7de0cSMatt Gates curr_sg++; 4791e1f7de0cSMatt Gates } 479250a0decfSStephen M. Cameron (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); 4793e1f7de0cSMatt Gates 4794e1f7de0cSMatt Gates switch (cmd->sc_data_direction) { 4795e1f7de0cSMatt Gates case DMA_TO_DEVICE: 4796e1f7de0cSMatt Gates control |= IOACCEL1_CONTROL_DATA_OUT; 4797e1f7de0cSMatt Gates break; 4798e1f7de0cSMatt Gates case DMA_FROM_DEVICE: 4799e1f7de0cSMatt Gates control |= IOACCEL1_CONTROL_DATA_IN; 4800e1f7de0cSMatt Gates break; 4801e1f7de0cSMatt Gates case DMA_NONE: 4802e1f7de0cSMatt Gates control |= IOACCEL1_CONTROL_NODATAXFER; 4803e1f7de0cSMatt Gates break; 4804e1f7de0cSMatt Gates default: 4805e1f7de0cSMatt Gates dev_err(&h->pdev->dev, "unknown data direction: %d\n", 4806e1f7de0cSMatt Gates cmd->sc_data_direction); 4807e1f7de0cSMatt Gates BUG(); 4808e1f7de0cSMatt Gates break; 4809e1f7de0cSMatt Gates } 4810e1f7de0cSMatt Gates } else { 4811e1f7de0cSMatt Gates control |= IOACCEL1_CONTROL_NODATAXFER; 4812e1f7de0cSMatt Gates } 4813e1f7de0cSMatt Gates 4814c349775eSScott Teel c->Header.SGList = use_sg; 4815e1f7de0cSMatt Gates /* Fill out the command structure to submit */ 48162b08b3e9SDon Brace cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); 48172b08b3e9SDon Brace cp->transfer_len = cpu_to_le32(total_len); 48182b08b3e9SDon Brace cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | 48192b08b3e9SDon Brace (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); 48202b08b3e9SDon Brace cp->control = cpu_to_le32(control); 4821283b4a9bSStephen M. Cameron memcpy(cp->CDB, cdb, cdb_len); 4822283b4a9bSStephen M. Cameron memcpy(cp->CISS_LUN, scsi3addr, 8); 4823c349775eSScott Teel /* Tag was already set at init time. */ 4824e1f7de0cSMatt Gates enqueue_cmd_and_start_io(h, c); 4825e1f7de0cSMatt Gates return 0; 4826e1f7de0cSMatt Gates } 4827edd16368SStephen M. Cameron 4828283b4a9bSStephen M. Cameron /* 4829283b4a9bSStephen M. Cameron * Queue a command directly to a device behind the controller using the 4830283b4a9bSStephen M. Cameron * I/O accelerator path. 4831283b4a9bSStephen M. Cameron */ 4832283b4a9bSStephen M. Cameron static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, 4833283b4a9bSStephen M. Cameron struct CommandList *c) 4834283b4a9bSStephen M. Cameron { 4835283b4a9bSStephen M. Cameron struct scsi_cmnd *cmd = c->scsi_cmd; 4836283b4a9bSStephen M. Cameron struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4837283b4a9bSStephen M. Cameron 483845e596cdSDon Brace if (!dev) 483945e596cdSDon Brace return -1; 484045e596cdSDon Brace 484103383736SDon Brace c->phys_disk = dev; 484203383736SDon Brace 4843c5dfd106SDon Brace if (dev->in_reset) 4844c5dfd106SDon Brace return -1; 4845c5dfd106SDon Brace 4846283b4a9bSStephen M. Cameron return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, 484703383736SDon Brace cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); 4848283b4a9bSStephen M. Cameron } 4849283b4a9bSStephen M. Cameron 4850dd0e19f3SScott Teel /* 4851dd0e19f3SScott Teel * Set encryption parameters for the ioaccel2 request 4852dd0e19f3SScott Teel */ 4853dd0e19f3SScott Teel static void set_encrypt_ioaccel2(struct ctlr_info *h, 4854dd0e19f3SScott Teel struct CommandList *c, struct io_accel2_cmd *cp) 4855dd0e19f3SScott Teel { 4856dd0e19f3SScott Teel struct scsi_cmnd *cmd = c->scsi_cmd; 4857dd0e19f3SScott Teel struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4858dd0e19f3SScott Teel struct raid_map_data *map = &dev->raid_map; 4859dd0e19f3SScott Teel u64 first_block; 4860dd0e19f3SScott Teel 4861dd0e19f3SScott Teel /* Are we doing encryption on this device */ 48622b08b3e9SDon Brace if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) 4863dd0e19f3SScott Teel return; 4864dd0e19f3SScott Teel /* Set the data encryption key index. */ 4865dd0e19f3SScott Teel cp->dekindex = map->dekindex; 4866dd0e19f3SScott Teel 4867dd0e19f3SScott Teel /* Set the encryption enable flag, encoded into direction field. */ 4868dd0e19f3SScott Teel cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; 4869dd0e19f3SScott Teel 4870dd0e19f3SScott Teel /* Set encryption tweak values based on logical block address 4871dd0e19f3SScott Teel * If block size is 512, tweak value is LBA. 4872dd0e19f3SScott Teel * For other block sizes, tweak is (LBA * block size)/ 512) 4873dd0e19f3SScott Teel */ 4874dd0e19f3SScott Teel switch (cmd->cmnd[0]) { 4875dd0e19f3SScott Teel /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ 4876dd0e19f3SScott Teel case READ_6: 4877abbada71SMahesh Rajashekhara case WRITE_6: 4878abbada71SMahesh Rajashekhara first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 4879abbada71SMahesh Rajashekhara (cmd->cmnd[2] << 8) | 4880abbada71SMahesh Rajashekhara cmd->cmnd[3]); 4881dd0e19f3SScott Teel break; 4882dd0e19f3SScott Teel case WRITE_10: 4883dd0e19f3SScott Teel case READ_10: 4884dd0e19f3SScott Teel /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ 4885dd0e19f3SScott Teel case WRITE_12: 4886dd0e19f3SScott Teel case READ_12: 48872b08b3e9SDon Brace first_block = get_unaligned_be32(&cmd->cmnd[2]); 4888dd0e19f3SScott Teel break; 4889dd0e19f3SScott Teel case WRITE_16: 4890dd0e19f3SScott Teel case READ_16: 48912b08b3e9SDon Brace first_block = get_unaligned_be64(&cmd->cmnd[2]); 4892dd0e19f3SScott Teel break; 4893dd0e19f3SScott Teel default: 4894dd0e19f3SScott Teel dev_err(&h->pdev->dev, 48952b08b3e9SDon Brace "ERROR: %s: size (0x%x) not supported for encryption\n", 48962b08b3e9SDon Brace __func__, cmd->cmnd[0]); 4897dd0e19f3SScott Teel BUG(); 4898dd0e19f3SScott Teel break; 4899dd0e19f3SScott Teel } 49002b08b3e9SDon Brace 49012b08b3e9SDon Brace if (le32_to_cpu(map->volume_blk_size) != 512) 49022b08b3e9SDon Brace first_block = first_block * 49032b08b3e9SDon Brace le32_to_cpu(map->volume_blk_size)/512; 49042b08b3e9SDon Brace 49052b08b3e9SDon Brace cp->tweak_lower = cpu_to_le32(first_block); 49062b08b3e9SDon Brace cp->tweak_upper = cpu_to_le32(first_block >> 32); 4907dd0e19f3SScott Teel } 4908dd0e19f3SScott Teel 4909c349775eSScott Teel static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, 4910c349775eSScott Teel struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 491103383736SDon Brace u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4912c349775eSScott Teel { 4913c349775eSScott Teel struct scsi_cmnd *cmd = c->scsi_cmd; 4914c349775eSScott Teel struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 4915c349775eSScott Teel struct ioaccel2_sg_element *curr_sg; 4916c349775eSScott Teel int use_sg, i; 4917c349775eSScott Teel struct scatterlist *sg; 4918c349775eSScott Teel u64 addr64; 4919c349775eSScott Teel u32 len; 4920c349775eSScott Teel u32 total_len = 0; 4921c349775eSScott Teel 492245e596cdSDon Brace if (!cmd->device) 492345e596cdSDon Brace return -1; 492445e596cdSDon Brace 492545e596cdSDon Brace if (!cmd->device->hostdata) 492645e596cdSDon Brace return -1; 492745e596cdSDon Brace 4928d9a729f3SWebb Scales BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4929c349775eSScott Teel 4930b63c64acSDon Brace if (is_zero_length_transfer(cdb)) { 4931b63c64acSDon Brace warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4932b63c64acSDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4933b63c64acSDon Brace return IO_ACCEL_INELIGIBLE; 4934b63c64acSDon Brace } 4935b63c64acSDon Brace 493603383736SDon Brace if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 493703383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4938c349775eSScott Teel return IO_ACCEL_INELIGIBLE; 493903383736SDon Brace } 494003383736SDon Brace 4941c349775eSScott Teel c->cmd_type = CMD_IOACCEL2; 4942c349775eSScott Teel /* Adjust the DMA address to point to the accelerated command buffer */ 4943c349775eSScott Teel c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + 4944c349775eSScott Teel (c->cmdindex * sizeof(*cp)); 4945c349775eSScott Teel BUG_ON(c->busaddr & 0x0000007F); 4946c349775eSScott Teel 4947c349775eSScott Teel memset(cp, 0, sizeof(*cp)); 4948c349775eSScott Teel cp->IU_type = IOACCEL2_IU_TYPE; 4949c349775eSScott Teel 4950c349775eSScott Teel use_sg = scsi_dma_map(cmd); 495103383736SDon Brace if (use_sg < 0) { 495203383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 4953c349775eSScott Teel return use_sg; 495403383736SDon Brace } 4955c349775eSScott Teel 4956c349775eSScott Teel if (use_sg) { 4957c349775eSScott Teel curr_sg = cp->sg; 4958d9a729f3SWebb Scales if (use_sg > h->ioaccel_maxsg) { 4959d9a729f3SWebb Scales addr64 = le64_to_cpu( 4960d9a729f3SWebb Scales h->ioaccel2_cmd_sg_list[c->cmdindex]->address); 4961d9a729f3SWebb Scales curr_sg->address = cpu_to_le64(addr64); 4962d9a729f3SWebb Scales curr_sg->length = 0; 4963d9a729f3SWebb Scales curr_sg->reserved[0] = 0; 4964d9a729f3SWebb Scales curr_sg->reserved[1] = 0; 4965d9a729f3SWebb Scales curr_sg->reserved[2] = 0; 4966625d7d35SDon Brace curr_sg->chain_indicator = IOACCEL2_CHAIN; 4967d9a729f3SWebb Scales 4968d9a729f3SWebb Scales curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; 4969d9a729f3SWebb Scales } 4970c349775eSScott Teel scsi_for_each_sg(cmd, sg, use_sg, i) { 4971c349775eSScott Teel addr64 = (u64) sg_dma_address(sg); 4972c349775eSScott Teel len = sg_dma_len(sg); 4973c349775eSScott Teel total_len += len; 4974c349775eSScott Teel curr_sg->address = cpu_to_le64(addr64); 4975c349775eSScott Teel curr_sg->length = cpu_to_le32(len); 4976c349775eSScott Teel curr_sg->reserved[0] = 0; 4977c349775eSScott Teel curr_sg->reserved[1] = 0; 4978c349775eSScott Teel curr_sg->reserved[2] = 0; 4979c349775eSScott Teel curr_sg->chain_indicator = 0; 4980c349775eSScott Teel curr_sg++; 4981c349775eSScott Teel } 4982c349775eSScott Teel 4983625d7d35SDon Brace /* 4984625d7d35SDon Brace * Set the last s/g element bit 4985625d7d35SDon Brace */ 4986625d7d35SDon Brace (curr_sg - 1)->chain_indicator = IOACCEL2_LAST_SG; 4987625d7d35SDon Brace 4988c349775eSScott Teel switch (cmd->sc_data_direction) { 4989c349775eSScott Teel case DMA_TO_DEVICE: 4990dd0e19f3SScott Teel cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4991dd0e19f3SScott Teel cp->direction |= IOACCEL2_DIR_DATA_OUT; 4992c349775eSScott Teel break; 4993c349775eSScott Teel case DMA_FROM_DEVICE: 4994dd0e19f3SScott Teel cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4995dd0e19f3SScott Teel cp->direction |= IOACCEL2_DIR_DATA_IN; 4996c349775eSScott Teel break; 4997c349775eSScott Teel case DMA_NONE: 4998dd0e19f3SScott Teel cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4999dd0e19f3SScott Teel cp->direction |= IOACCEL2_DIR_NO_DATA; 5000c349775eSScott Teel break; 5001c349775eSScott Teel default: 5002c349775eSScott Teel dev_err(&h->pdev->dev, "unknown data direction: %d\n", 5003c349775eSScott Teel cmd->sc_data_direction); 5004c349775eSScott Teel BUG(); 5005c349775eSScott Teel break; 5006c349775eSScott Teel } 5007c349775eSScott Teel } else { 5008dd0e19f3SScott Teel cp->direction &= ~IOACCEL2_DIRECTION_MASK; 5009dd0e19f3SScott Teel cp->direction |= IOACCEL2_DIR_NO_DATA; 5010c349775eSScott Teel } 5011dd0e19f3SScott Teel 5012dd0e19f3SScott Teel /* Set encryption parameters, if necessary */ 5013dd0e19f3SScott Teel set_encrypt_ioaccel2(h, c, cp); 5014dd0e19f3SScott Teel 50152b08b3e9SDon Brace cp->scsi_nexus = cpu_to_le32(ioaccel_handle); 5016f2405db8SDon Brace cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); 5017c349775eSScott Teel memcpy(cp->cdb, cdb, sizeof(cp->cdb)); 5018c349775eSScott Teel 5019c349775eSScott Teel cp->data_len = cpu_to_le32(total_len); 5020c349775eSScott Teel cp->err_ptr = cpu_to_le64(c->busaddr + 5021c349775eSScott Teel offsetof(struct io_accel2_cmd, error_data)); 502250a0decfSStephen M. Cameron cp->err_len = cpu_to_le32(sizeof(cp->error_data)); 5023c349775eSScott Teel 5024d9a729f3SWebb Scales /* fill in sg elements */ 5025d9a729f3SWebb Scales if (use_sg > h->ioaccel_maxsg) { 5026d9a729f3SWebb Scales cp->sg_count = 1; 5027a736e9b6SDon Brace cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); 5028d9a729f3SWebb Scales if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { 5029d9a729f3SWebb Scales atomic_dec(&phys_disk->ioaccel_cmds_out); 5030d9a729f3SWebb Scales scsi_dma_unmap(cmd); 5031d9a729f3SWebb Scales return -1; 5032d9a729f3SWebb Scales } 5033d9a729f3SWebb Scales } else 5034d9a729f3SWebb Scales cp->sg_count = (u8) use_sg; 5035d9a729f3SWebb Scales 5036c5dfd106SDon Brace if (phys_disk->in_reset) { 5037c5dfd106SDon Brace cmd->result = DID_RESET << 16; 5038c5dfd106SDon Brace return -1; 5039c5dfd106SDon Brace } 5040c5dfd106SDon Brace 5041c349775eSScott Teel enqueue_cmd_and_start_io(h, c); 5042c349775eSScott Teel return 0; 5043c349775eSScott Teel } 5044c349775eSScott Teel 5045c349775eSScott Teel /* 5046c349775eSScott Teel * Queue a command to the correct I/O accelerator path. 5047c349775eSScott Teel */ 5048c349775eSScott Teel static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 5049c349775eSScott Teel struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 505003383736SDon Brace u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 5051c349775eSScott Teel { 505245e596cdSDon Brace if (!c->scsi_cmd->device) 505345e596cdSDon Brace return -1; 505445e596cdSDon Brace 505545e596cdSDon Brace if (!c->scsi_cmd->device->hostdata) 505645e596cdSDon Brace return -1; 505745e596cdSDon Brace 5058c5dfd106SDon Brace if (phys_disk->in_reset) 5059c5dfd106SDon Brace return -1; 5060c5dfd106SDon Brace 506103383736SDon Brace /* Try to honor the device's queue depth */ 506203383736SDon Brace if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > 506303383736SDon Brace phys_disk->queue_depth) { 506403383736SDon Brace atomic_dec(&phys_disk->ioaccel_cmds_out); 506503383736SDon Brace return IO_ACCEL_INELIGIBLE; 506603383736SDon Brace } 5067c349775eSScott Teel if (h->transMethod & CFGTBL_Trans_io_accel1) 5068c349775eSScott Teel return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, 506903383736SDon Brace cdb, cdb_len, scsi3addr, 507003383736SDon Brace phys_disk); 5071c349775eSScott Teel else 5072c349775eSScott Teel return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, 507303383736SDon Brace cdb, cdb_len, scsi3addr, 507403383736SDon Brace phys_disk); 5075c349775eSScott Teel } 5076c349775eSScott Teel 50776b80b18fSScott Teel static void raid_map_helper(struct raid_map_data *map, 50786b80b18fSScott Teel int offload_to_mirror, u32 *map_index, u32 *current_group) 50796b80b18fSScott Teel { 50806b80b18fSScott Teel if (offload_to_mirror == 0) { 50816b80b18fSScott Teel /* use physical disk in the first mirrored group. */ 50822b08b3e9SDon Brace *map_index %= le16_to_cpu(map->data_disks_per_row); 50836b80b18fSScott Teel return; 50846b80b18fSScott Teel } 50856b80b18fSScott Teel do { 50866b80b18fSScott Teel /* determine mirror group that *map_index indicates */ 50872b08b3e9SDon Brace *current_group = *map_index / 50882b08b3e9SDon Brace le16_to_cpu(map->data_disks_per_row); 50896b80b18fSScott Teel if (offload_to_mirror == *current_group) 50906b80b18fSScott Teel continue; 50912b08b3e9SDon Brace if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { 50926b80b18fSScott Teel /* select map index from next group */ 50932b08b3e9SDon Brace *map_index += le16_to_cpu(map->data_disks_per_row); 50946b80b18fSScott Teel (*current_group)++; 50956b80b18fSScott Teel } else { 50966b80b18fSScott Teel /* select map index from first group */ 50972b08b3e9SDon Brace *map_index %= le16_to_cpu(map->data_disks_per_row); 50986b80b18fSScott Teel *current_group = 0; 50996b80b18fSScott Teel } 51006b80b18fSScott Teel } while (offload_to_mirror != *current_group); 51016b80b18fSScott Teel } 51026b80b18fSScott Teel 5103283b4a9bSStephen M. Cameron /* 5104283b4a9bSStephen M. Cameron * Attempt to perform offload RAID mapping for a logical volume I/O. 5105283b4a9bSStephen M. Cameron */ 5106283b4a9bSStephen M. Cameron static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, 5107283b4a9bSStephen M. Cameron struct CommandList *c) 5108283b4a9bSStephen M. Cameron { 5109283b4a9bSStephen M. Cameron struct scsi_cmnd *cmd = c->scsi_cmd; 5110283b4a9bSStephen M. Cameron struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 5111283b4a9bSStephen M. Cameron struct raid_map_data *map = &dev->raid_map; 5112283b4a9bSStephen M. Cameron struct raid_map_disk_data *dd = &map->data[0]; 5113283b4a9bSStephen M. Cameron int is_write = 0; 5114283b4a9bSStephen M. Cameron u32 map_index; 5115283b4a9bSStephen M. Cameron u64 first_block, last_block; 5116283b4a9bSStephen M. Cameron u32 block_cnt; 5117283b4a9bSStephen M. Cameron u32 blocks_per_row; 5118283b4a9bSStephen M. Cameron u64 first_row, last_row; 5119283b4a9bSStephen M. Cameron u32 first_row_offset, last_row_offset; 5120283b4a9bSStephen M. Cameron u32 first_column, last_column; 51216b80b18fSScott Teel u64 r0_first_row, r0_last_row; 51226b80b18fSScott Teel u32 r5or6_blocks_per_row; 51236b80b18fSScott Teel u64 r5or6_first_row, r5or6_last_row; 51246b80b18fSScott Teel u32 r5or6_first_row_offset, r5or6_last_row_offset; 51256b80b18fSScott Teel u32 r5or6_first_column, r5or6_last_column; 51266b80b18fSScott Teel u32 total_disks_per_row; 51276b80b18fSScott Teel u32 stripesize; 51286b80b18fSScott Teel u32 first_group, last_group, current_group; 5129283b4a9bSStephen M. Cameron u32 map_row; 5130283b4a9bSStephen M. Cameron u32 disk_handle; 5131283b4a9bSStephen M. Cameron u64 disk_block; 5132283b4a9bSStephen M. Cameron u32 disk_block_cnt; 5133283b4a9bSStephen M. Cameron u8 cdb[16]; 5134283b4a9bSStephen M. Cameron u8 cdb_len; 51352b08b3e9SDon Brace u16 strip_size; 5136283b4a9bSStephen M. Cameron #if BITS_PER_LONG == 32 5137283b4a9bSStephen M. Cameron u64 tmpdiv; 5138283b4a9bSStephen M. Cameron #endif 51396b80b18fSScott Teel int offload_to_mirror; 5140283b4a9bSStephen M. Cameron 514145e596cdSDon Brace if (!dev) 514245e596cdSDon Brace return -1; 514345e596cdSDon Brace 5144c5dfd106SDon Brace if (dev->in_reset) 5145c5dfd106SDon Brace return -1; 5146c5dfd106SDon Brace 5147283b4a9bSStephen M. Cameron /* check for valid opcode, get LBA and block count */ 5148283b4a9bSStephen M. Cameron switch (cmd->cmnd[0]) { 5149283b4a9bSStephen M. Cameron case WRITE_6: 5150283b4a9bSStephen M. Cameron is_write = 1; 5151df561f66SGustavo A. R. Silva fallthrough; 5152283b4a9bSStephen M. Cameron case READ_6: 5153abbada71SMahesh Rajashekhara first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 5154abbada71SMahesh Rajashekhara (cmd->cmnd[2] << 8) | 5155abbada71SMahesh Rajashekhara cmd->cmnd[3]); 5156283b4a9bSStephen M. Cameron block_cnt = cmd->cmnd[4]; 51573fa89a04SStephen M. Cameron if (block_cnt == 0) 51583fa89a04SStephen M. Cameron block_cnt = 256; 5159283b4a9bSStephen M. Cameron break; 5160283b4a9bSStephen M. Cameron case WRITE_10: 5161283b4a9bSStephen M. Cameron is_write = 1; 5162df561f66SGustavo A. R. Silva fallthrough; 5163283b4a9bSStephen M. Cameron case READ_10: 5164283b4a9bSStephen M. Cameron first_block = 5165283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[2]) << 24) | 5166283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[3]) << 16) | 5167283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[4]) << 8) | 5168283b4a9bSStephen M. Cameron cmd->cmnd[5]; 5169283b4a9bSStephen M. Cameron block_cnt = 5170283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[7]) << 8) | 5171283b4a9bSStephen M. Cameron cmd->cmnd[8]; 5172283b4a9bSStephen M. Cameron break; 5173283b4a9bSStephen M. Cameron case WRITE_12: 5174283b4a9bSStephen M. Cameron is_write = 1; 5175df561f66SGustavo A. R. Silva fallthrough; 5176283b4a9bSStephen M. Cameron case READ_12: 5177283b4a9bSStephen M. Cameron first_block = 5178283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[2]) << 24) | 5179283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[3]) << 16) | 5180283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[4]) << 8) | 5181283b4a9bSStephen M. Cameron cmd->cmnd[5]; 5182283b4a9bSStephen M. Cameron block_cnt = 5183283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[6]) << 24) | 5184283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[7]) << 16) | 5185283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[8]) << 8) | 5186283b4a9bSStephen M. Cameron cmd->cmnd[9]; 5187283b4a9bSStephen M. Cameron break; 5188283b4a9bSStephen M. Cameron case WRITE_16: 5189283b4a9bSStephen M. Cameron is_write = 1; 5190df561f66SGustavo A. R. Silva fallthrough; 5191283b4a9bSStephen M. Cameron case READ_16: 5192283b4a9bSStephen M. Cameron first_block = 5193283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[2]) << 56) | 5194283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[3]) << 48) | 5195283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[4]) << 40) | 5196283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[5]) << 32) | 5197283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[6]) << 24) | 5198283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[7]) << 16) | 5199283b4a9bSStephen M. Cameron (((u64) cmd->cmnd[8]) << 8) | 5200283b4a9bSStephen M. Cameron cmd->cmnd[9]; 5201283b4a9bSStephen M. Cameron block_cnt = 5202283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[10]) << 24) | 5203283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[11]) << 16) | 5204283b4a9bSStephen M. Cameron (((u32) cmd->cmnd[12]) << 8) | 5205283b4a9bSStephen M. Cameron cmd->cmnd[13]; 5206283b4a9bSStephen M. Cameron break; 5207283b4a9bSStephen M. Cameron default: 5208283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ 5209283b4a9bSStephen M. Cameron } 5210283b4a9bSStephen M. Cameron last_block = first_block + block_cnt - 1; 5211283b4a9bSStephen M. Cameron 5212283b4a9bSStephen M. Cameron /* check for write to non-RAID-0 */ 5213283b4a9bSStephen M. Cameron if (is_write && dev->raid_level != 0) 5214283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 5215283b4a9bSStephen M. Cameron 5216283b4a9bSStephen M. Cameron /* check for invalid block or wraparound */ 52172b08b3e9SDon Brace if (last_block >= le64_to_cpu(map->volume_blk_cnt) || 52182b08b3e9SDon Brace last_block < first_block) 5219283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 5220283b4a9bSStephen M. Cameron 5221283b4a9bSStephen M. Cameron /* calculate stripe information for the request */ 52222b08b3e9SDon Brace blocks_per_row = le16_to_cpu(map->data_disks_per_row) * 52232b08b3e9SDon Brace le16_to_cpu(map->strip_size); 52242b08b3e9SDon Brace strip_size = le16_to_cpu(map->strip_size); 5225283b4a9bSStephen M. Cameron #if BITS_PER_LONG == 32 5226283b4a9bSStephen M. Cameron tmpdiv = first_block; 5227283b4a9bSStephen M. Cameron (void) do_div(tmpdiv, blocks_per_row); 5228283b4a9bSStephen M. Cameron first_row = tmpdiv; 5229283b4a9bSStephen M. Cameron tmpdiv = last_block; 5230283b4a9bSStephen M. Cameron (void) do_div(tmpdiv, blocks_per_row); 5231283b4a9bSStephen M. Cameron last_row = tmpdiv; 5232283b4a9bSStephen M. Cameron first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5233283b4a9bSStephen M. Cameron last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 5234283b4a9bSStephen M. Cameron tmpdiv = first_row_offset; 52352b08b3e9SDon Brace (void) do_div(tmpdiv, strip_size); 5236283b4a9bSStephen M. Cameron first_column = tmpdiv; 5237283b4a9bSStephen M. Cameron tmpdiv = last_row_offset; 52382b08b3e9SDon Brace (void) do_div(tmpdiv, strip_size); 5239283b4a9bSStephen M. Cameron last_column = tmpdiv; 5240283b4a9bSStephen M. Cameron #else 5241283b4a9bSStephen M. Cameron first_row = first_block / blocks_per_row; 5242283b4a9bSStephen M. Cameron last_row = last_block / blocks_per_row; 5243283b4a9bSStephen M. Cameron first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5244283b4a9bSStephen M. Cameron last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 52452b08b3e9SDon Brace first_column = first_row_offset / strip_size; 52462b08b3e9SDon Brace last_column = last_row_offset / strip_size; 5247283b4a9bSStephen M. Cameron #endif 5248283b4a9bSStephen M. Cameron 5249283b4a9bSStephen M. Cameron /* if this isn't a single row/column then give to the controller */ 5250283b4a9bSStephen M. Cameron if ((first_row != last_row) || (first_column != last_column)) 5251283b4a9bSStephen M. Cameron return IO_ACCEL_INELIGIBLE; 5252283b4a9bSStephen M. Cameron 5253283b4a9bSStephen M. Cameron /* proceeding with driver mapping */ 52542b08b3e9SDon Brace total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 52552b08b3e9SDon Brace le16_to_cpu(map->metadata_disks_per_row); 5256283b4a9bSStephen M. Cameron map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 52572b08b3e9SDon Brace le16_to_cpu(map->row_cnt); 52586b80b18fSScott Teel map_index = (map_row * total_disks_per_row) + first_column; 52596b80b18fSScott Teel 52606b80b18fSScott Teel switch (dev->raid_level) { 52616b80b18fSScott Teel case HPSA_RAID_0: 52626b80b18fSScott Teel break; /* nothing special to do */ 52636b80b18fSScott Teel case HPSA_RAID_1: 52646b80b18fSScott Teel /* Handles load balance across RAID 1 members. 52656b80b18fSScott Teel * (2-drive R1 and R10 with even # of drives.) 52666b80b18fSScott Teel * Appropriate for SSDs, not optimal for HDDs 52673e16e83aSDon Brace * Ensure we have the correct raid_map. 5268283b4a9bSStephen M. Cameron */ 52693e16e83aSDon Brace if (le16_to_cpu(map->layout_map_count) != 2) { 52703e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(dev); 52713e16e83aSDon Brace return IO_ACCEL_INELIGIBLE; 52723e16e83aSDon Brace } 5273283b4a9bSStephen M. Cameron if (dev->offload_to_mirror) 52742b08b3e9SDon Brace map_index += le16_to_cpu(map->data_disks_per_row); 5275283b4a9bSStephen M. Cameron dev->offload_to_mirror = !dev->offload_to_mirror; 52766b80b18fSScott Teel break; 52776b80b18fSScott Teel case HPSA_RAID_ADM: 52786b80b18fSScott Teel /* Handles N-way mirrors (R1-ADM) 52796b80b18fSScott Teel * and R10 with # of drives divisible by 3.) 52803e16e83aSDon Brace * Ensure we have the correct raid_map. 52816b80b18fSScott Teel */ 52823e16e83aSDon Brace if (le16_to_cpu(map->layout_map_count) != 3) { 52833e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(dev); 52843e16e83aSDon Brace return IO_ACCEL_INELIGIBLE; 52853e16e83aSDon Brace } 52866b80b18fSScott Teel 52876b80b18fSScott Teel offload_to_mirror = dev->offload_to_mirror; 52886b80b18fSScott Teel raid_map_helper(map, offload_to_mirror, 52896b80b18fSScott Teel &map_index, ¤t_group); 52906b80b18fSScott Teel /* set mirror group to use next time */ 52916b80b18fSScott Teel offload_to_mirror = 52922b08b3e9SDon Brace (offload_to_mirror >= 52932b08b3e9SDon Brace le16_to_cpu(map->layout_map_count) - 1) 52946b80b18fSScott Teel ? 0 : offload_to_mirror + 1; 52956b80b18fSScott Teel dev->offload_to_mirror = offload_to_mirror; 52966b80b18fSScott Teel /* Avoid direct use of dev->offload_to_mirror within this 52976b80b18fSScott Teel * function since multiple threads might simultaneously 52986b80b18fSScott Teel * increment it beyond the range of dev->layout_map_count -1. 52996b80b18fSScott Teel */ 53006b80b18fSScott Teel break; 53016b80b18fSScott Teel case HPSA_RAID_5: 53026b80b18fSScott Teel case HPSA_RAID_6: 53032b08b3e9SDon Brace if (le16_to_cpu(map->layout_map_count) <= 1) 53046b80b18fSScott Teel break; 53056b80b18fSScott Teel 53066b80b18fSScott Teel /* Verify first and last block are in same RAID group */ 53076b80b18fSScott Teel r5or6_blocks_per_row = 53082b08b3e9SDon Brace le16_to_cpu(map->strip_size) * 53092b08b3e9SDon Brace le16_to_cpu(map->data_disks_per_row); 53103e16e83aSDon Brace if (r5or6_blocks_per_row == 0) { 53113e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(dev); 53123e16e83aSDon Brace return IO_ACCEL_INELIGIBLE; 53133e16e83aSDon Brace } 53142b08b3e9SDon Brace stripesize = r5or6_blocks_per_row * 53152b08b3e9SDon Brace le16_to_cpu(map->layout_map_count); 53166b80b18fSScott Teel #if BITS_PER_LONG == 32 53176b80b18fSScott Teel tmpdiv = first_block; 53186b80b18fSScott Teel first_group = do_div(tmpdiv, stripesize); 53196b80b18fSScott Teel tmpdiv = first_group; 53206b80b18fSScott Teel (void) do_div(tmpdiv, r5or6_blocks_per_row); 53216b80b18fSScott Teel first_group = tmpdiv; 53226b80b18fSScott Teel tmpdiv = last_block; 53236b80b18fSScott Teel last_group = do_div(tmpdiv, stripesize); 53246b80b18fSScott Teel tmpdiv = last_group; 53256b80b18fSScott Teel (void) do_div(tmpdiv, r5or6_blocks_per_row); 53266b80b18fSScott Teel last_group = tmpdiv; 53276b80b18fSScott Teel #else 53286b80b18fSScott Teel first_group = (first_block % stripesize) / r5or6_blocks_per_row; 53296b80b18fSScott Teel last_group = (last_block % stripesize) / r5or6_blocks_per_row; 53306b80b18fSScott Teel #endif 5331000ff7c2SStephen M. Cameron if (first_group != last_group) 53326b80b18fSScott Teel return IO_ACCEL_INELIGIBLE; 53336b80b18fSScott Teel 53346b80b18fSScott Teel /* Verify request is in a single row of RAID 5/6 */ 53356b80b18fSScott Teel #if BITS_PER_LONG == 32 53366b80b18fSScott Teel tmpdiv = first_block; 53376b80b18fSScott Teel (void) do_div(tmpdiv, stripesize); 53386b80b18fSScott Teel first_row = r5or6_first_row = r0_first_row = tmpdiv; 53396b80b18fSScott Teel tmpdiv = last_block; 53406b80b18fSScott Teel (void) do_div(tmpdiv, stripesize); 53416b80b18fSScott Teel r5or6_last_row = r0_last_row = tmpdiv; 53426b80b18fSScott Teel #else 53436b80b18fSScott Teel first_row = r5or6_first_row = r0_first_row = 53446b80b18fSScott Teel first_block / stripesize; 53456b80b18fSScott Teel r5or6_last_row = r0_last_row = last_block / stripesize; 53466b80b18fSScott Teel #endif 53476b80b18fSScott Teel if (r5or6_first_row != r5or6_last_row) 53486b80b18fSScott Teel return IO_ACCEL_INELIGIBLE; 53496b80b18fSScott Teel 53506b80b18fSScott Teel 53516b80b18fSScott Teel /* Verify request is in a single column */ 53526b80b18fSScott Teel #if BITS_PER_LONG == 32 53536b80b18fSScott Teel tmpdiv = first_block; 53546b80b18fSScott Teel first_row_offset = do_div(tmpdiv, stripesize); 53556b80b18fSScott Teel tmpdiv = first_row_offset; 53566b80b18fSScott Teel first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); 53576b80b18fSScott Teel r5or6_first_row_offset = first_row_offset; 53586b80b18fSScott Teel tmpdiv = last_block; 53596b80b18fSScott Teel r5or6_last_row_offset = do_div(tmpdiv, stripesize); 53606b80b18fSScott Teel tmpdiv = r5or6_last_row_offset; 53616b80b18fSScott Teel r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); 53626b80b18fSScott Teel tmpdiv = r5or6_first_row_offset; 53636b80b18fSScott Teel (void) do_div(tmpdiv, map->strip_size); 53646b80b18fSScott Teel first_column = r5or6_first_column = tmpdiv; 53656b80b18fSScott Teel tmpdiv = r5or6_last_row_offset; 53666b80b18fSScott Teel (void) do_div(tmpdiv, map->strip_size); 53676b80b18fSScott Teel r5or6_last_column = tmpdiv; 53686b80b18fSScott Teel #else 53696b80b18fSScott Teel first_row_offset = r5or6_first_row_offset = 53706b80b18fSScott Teel (u32)((first_block % stripesize) % 53716b80b18fSScott Teel r5or6_blocks_per_row); 53726b80b18fSScott Teel 53736b80b18fSScott Teel r5or6_last_row_offset = 53746b80b18fSScott Teel (u32)((last_block % stripesize) % 53756b80b18fSScott Teel r5or6_blocks_per_row); 53766b80b18fSScott Teel 53776b80b18fSScott Teel first_column = r5or6_first_column = 53782b08b3e9SDon Brace r5or6_first_row_offset / le16_to_cpu(map->strip_size); 53796b80b18fSScott Teel r5or6_last_column = 53802b08b3e9SDon Brace r5or6_last_row_offset / le16_to_cpu(map->strip_size); 53816b80b18fSScott Teel #endif 53826b80b18fSScott Teel if (r5or6_first_column != r5or6_last_column) 53836b80b18fSScott Teel return IO_ACCEL_INELIGIBLE; 53846b80b18fSScott Teel 53856b80b18fSScott Teel /* Request is eligible */ 53866b80b18fSScott Teel map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 53872b08b3e9SDon Brace le16_to_cpu(map->row_cnt); 53886b80b18fSScott Teel 53896b80b18fSScott Teel map_index = (first_group * 53902b08b3e9SDon Brace (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + 53916b80b18fSScott Teel (map_row * total_disks_per_row) + first_column; 53926b80b18fSScott Teel break; 53936b80b18fSScott Teel default: 53946b80b18fSScott Teel return IO_ACCEL_INELIGIBLE; 5395283b4a9bSStephen M. Cameron } 53966b80b18fSScott Teel 539707543e0cSStephen Cameron if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) 539807543e0cSStephen Cameron return IO_ACCEL_INELIGIBLE; 539907543e0cSStephen Cameron 540003383736SDon Brace c->phys_disk = dev->phys_disk[map_index]; 5401c3390df4SDon Brace if (!c->phys_disk) 5402c3390df4SDon Brace return IO_ACCEL_INELIGIBLE; 540303383736SDon Brace 5404283b4a9bSStephen M. Cameron disk_handle = dd[map_index].ioaccel_handle; 54052b08b3e9SDon Brace disk_block = le64_to_cpu(map->disk_starting_blk) + 54062b08b3e9SDon Brace first_row * le16_to_cpu(map->strip_size) + 54072b08b3e9SDon Brace (first_row_offset - first_column * 54082b08b3e9SDon Brace le16_to_cpu(map->strip_size)); 5409283b4a9bSStephen M. Cameron disk_block_cnt = block_cnt; 5410283b4a9bSStephen M. Cameron 5411283b4a9bSStephen M. Cameron /* handle differing logical/physical block sizes */ 5412283b4a9bSStephen M. Cameron if (map->phys_blk_shift) { 5413283b4a9bSStephen M. Cameron disk_block <<= map->phys_blk_shift; 5414283b4a9bSStephen M. Cameron disk_block_cnt <<= map->phys_blk_shift; 5415283b4a9bSStephen M. Cameron } 5416283b4a9bSStephen M. Cameron BUG_ON(disk_block_cnt > 0xffff); 5417283b4a9bSStephen M. Cameron 5418283b4a9bSStephen M. Cameron /* build the new CDB for the physical disk I/O */ 5419283b4a9bSStephen M. Cameron if (disk_block > 0xffffffff) { 5420283b4a9bSStephen M. Cameron cdb[0] = is_write ? WRITE_16 : READ_16; 5421283b4a9bSStephen M. Cameron cdb[1] = 0; 5422283b4a9bSStephen M. Cameron cdb[2] = (u8) (disk_block >> 56); 5423283b4a9bSStephen M. Cameron cdb[3] = (u8) (disk_block >> 48); 5424283b4a9bSStephen M. Cameron cdb[4] = (u8) (disk_block >> 40); 5425283b4a9bSStephen M. Cameron cdb[5] = (u8) (disk_block >> 32); 5426283b4a9bSStephen M. Cameron cdb[6] = (u8) (disk_block >> 24); 5427283b4a9bSStephen M. Cameron cdb[7] = (u8) (disk_block >> 16); 5428283b4a9bSStephen M. Cameron cdb[8] = (u8) (disk_block >> 8); 5429283b4a9bSStephen M. Cameron cdb[9] = (u8) (disk_block); 5430283b4a9bSStephen M. Cameron cdb[10] = (u8) (disk_block_cnt >> 24); 5431283b4a9bSStephen M. Cameron cdb[11] = (u8) (disk_block_cnt >> 16); 5432283b4a9bSStephen M. Cameron cdb[12] = (u8) (disk_block_cnt >> 8); 5433283b4a9bSStephen M. Cameron cdb[13] = (u8) (disk_block_cnt); 5434283b4a9bSStephen M. Cameron cdb[14] = 0; 5435283b4a9bSStephen M. Cameron cdb[15] = 0; 5436283b4a9bSStephen M. Cameron cdb_len = 16; 5437283b4a9bSStephen M. Cameron } else { 5438283b4a9bSStephen M. Cameron cdb[0] = is_write ? WRITE_10 : READ_10; 5439283b4a9bSStephen M. Cameron cdb[1] = 0; 5440283b4a9bSStephen M. Cameron cdb[2] = (u8) (disk_block >> 24); 5441283b4a9bSStephen M. Cameron cdb[3] = (u8) (disk_block >> 16); 5442283b4a9bSStephen M. Cameron cdb[4] = (u8) (disk_block >> 8); 5443283b4a9bSStephen M. Cameron cdb[5] = (u8) (disk_block); 5444283b4a9bSStephen M. Cameron cdb[6] = 0; 5445283b4a9bSStephen M. Cameron cdb[7] = (u8) (disk_block_cnt >> 8); 5446283b4a9bSStephen M. Cameron cdb[8] = (u8) (disk_block_cnt); 5447283b4a9bSStephen M. Cameron cdb[9] = 0; 5448283b4a9bSStephen M. Cameron cdb_len = 10; 5449283b4a9bSStephen M. Cameron } 5450283b4a9bSStephen M. Cameron return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, 545103383736SDon Brace dev->scsi3addr, 545203383736SDon Brace dev->phys_disk[map_index]); 5453283b4a9bSStephen M. Cameron } 5454283b4a9bSStephen M. Cameron 545525163bd5SWebb Scales /* 545625163bd5SWebb Scales * Submit commands down the "normal" RAID stack path 545725163bd5SWebb Scales * All callers to hpsa_ciss_submit must check lockup_detected 545825163bd5SWebb Scales * beforehand, before (opt.) and after calling cmd_alloc 545925163bd5SWebb Scales */ 5460574f05d3SStephen Cameron static int hpsa_ciss_submit(struct ctlr_info *h, 5461574f05d3SStephen Cameron struct CommandList *c, struct scsi_cmnd *cmd, 5462c5dfd106SDon Brace struct hpsa_scsi_dev_t *dev) 5463edd16368SStephen M. Cameron { 5464edd16368SStephen M. Cameron cmd->host_scribble = (unsigned char *) c; 5465edd16368SStephen M. Cameron c->cmd_type = CMD_SCSI; 5466edd16368SStephen M. Cameron c->scsi_cmd = cmd; 5467edd16368SStephen M. Cameron c->Header.ReplyQueue = 0; /* unused in simple mode */ 5468c5dfd106SDon Brace memcpy(&c->Header.LUN.LunAddrBytes[0], &dev->scsi3addr[0], 8); 5469f2405db8SDon Brace c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); 5470edd16368SStephen M. Cameron 5471edd16368SStephen M. Cameron /* Fill in the request block... */ 5472edd16368SStephen M. Cameron 5473edd16368SStephen M. Cameron c->Request.Timeout = 0; 5474edd16368SStephen M. Cameron BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); 5475edd16368SStephen M. Cameron c->Request.CDBLen = cmd->cmd_len; 5476edd16368SStephen M. Cameron memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); 5477edd16368SStephen M. Cameron switch (cmd->sc_data_direction) { 5478edd16368SStephen M. Cameron case DMA_TO_DEVICE: 5479a505b86fSStephen M. Cameron c->Request.type_attr_dir = 5480a505b86fSStephen M. Cameron TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); 5481edd16368SStephen M. Cameron break; 5482edd16368SStephen M. Cameron case DMA_FROM_DEVICE: 5483a505b86fSStephen M. Cameron c->Request.type_attr_dir = 5484a505b86fSStephen M. Cameron TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); 5485edd16368SStephen M. Cameron break; 5486edd16368SStephen M. Cameron case DMA_NONE: 5487a505b86fSStephen M. Cameron c->Request.type_attr_dir = 5488a505b86fSStephen M. Cameron TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); 5489edd16368SStephen M. Cameron break; 5490edd16368SStephen M. Cameron case DMA_BIDIRECTIONAL: 5491edd16368SStephen M. Cameron /* This can happen if a buggy application does a scsi passthru 5492edd16368SStephen M. Cameron * and sets both inlen and outlen to non-zero. ( see 5493edd16368SStephen M. Cameron * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) 5494edd16368SStephen M. Cameron */ 5495edd16368SStephen M. Cameron 5496a505b86fSStephen M. Cameron c->Request.type_attr_dir = 5497a505b86fSStephen M. Cameron TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); 5498edd16368SStephen M. Cameron /* This is technically wrong, and hpsa controllers should 5499edd16368SStephen M. Cameron * reject it with CMD_INVALID, which is the most correct 5500edd16368SStephen M. Cameron * response, but non-fibre backends appear to let it 5501edd16368SStephen M. Cameron * slide by, and give the same results as if this field 5502edd16368SStephen M. Cameron * were set correctly. Either way is acceptable for 5503edd16368SStephen M. Cameron * our purposes here. 5504edd16368SStephen M. Cameron */ 5505edd16368SStephen M. Cameron 5506edd16368SStephen M. Cameron break; 5507edd16368SStephen M. Cameron 5508edd16368SStephen M. Cameron default: 5509edd16368SStephen M. Cameron dev_err(&h->pdev->dev, "unknown data direction: %d\n", 5510edd16368SStephen M. Cameron cmd->sc_data_direction); 5511edd16368SStephen M. Cameron BUG(); 5512edd16368SStephen M. Cameron break; 5513edd16368SStephen M. Cameron } 5514edd16368SStephen M. Cameron 551533a2ffceSStephen M. Cameron if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ 551673153fe5SWebb Scales hpsa_cmd_resolve_and_free(h, c); 5517edd16368SStephen M. Cameron return SCSI_MLQUEUE_HOST_BUSY; 5518edd16368SStephen M. Cameron } 5519c5dfd106SDon Brace 5520c5dfd106SDon Brace if (dev->in_reset) { 5521c5dfd106SDon Brace hpsa_cmd_resolve_and_free(h, c); 5522c5dfd106SDon Brace return SCSI_MLQUEUE_HOST_BUSY; 5523c5dfd106SDon Brace } 5524c5dfd106SDon Brace 552513499345SDon Brace c->device = dev; 552613499345SDon Brace 5527edd16368SStephen M. Cameron enqueue_cmd_and_start_io(h, c); 5528edd16368SStephen M. Cameron /* the cmd'll come back via intr handler in complete_scsi_command() */ 5529edd16368SStephen M. Cameron return 0; 5530edd16368SStephen M. Cameron } 5531edd16368SStephen M. Cameron 5532360c73bdSStephen Cameron static void hpsa_cmd_init(struct ctlr_info *h, int index, 5533360c73bdSStephen Cameron struct CommandList *c) 5534360c73bdSStephen Cameron { 5535360c73bdSStephen Cameron dma_addr_t cmd_dma_handle, err_dma_handle; 5536360c73bdSStephen Cameron 5537360c73bdSStephen Cameron /* Zero out all of commandlist except the last field, refcount */ 5538360c73bdSStephen Cameron memset(c, 0, offsetof(struct CommandList, refcount)); 5539360c73bdSStephen Cameron c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); 5540360c73bdSStephen Cameron cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5541360c73bdSStephen Cameron c->err_info = h->errinfo_pool + index; 5542360c73bdSStephen Cameron memset(c->err_info, 0, sizeof(*c->err_info)); 5543360c73bdSStephen Cameron err_dma_handle = h->errinfo_pool_dhandle 5544360c73bdSStephen Cameron + index * sizeof(*c->err_info); 5545360c73bdSStephen Cameron c->cmdindex = index; 5546360c73bdSStephen Cameron c->busaddr = (u32) cmd_dma_handle; 5547360c73bdSStephen Cameron c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); 5548360c73bdSStephen Cameron c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); 5549360c73bdSStephen Cameron c->h = h; 5550a58e7e53SWebb Scales c->scsi_cmd = SCSI_CMD_IDLE; 5551360c73bdSStephen Cameron } 5552360c73bdSStephen Cameron 5553360c73bdSStephen Cameron static void hpsa_preinitialize_commands(struct ctlr_info *h) 5554360c73bdSStephen Cameron { 5555360c73bdSStephen Cameron int i; 5556360c73bdSStephen Cameron 5557360c73bdSStephen Cameron for (i = 0; i < h->nr_cmds; i++) { 5558360c73bdSStephen Cameron struct CommandList *c = h->cmd_pool + i; 5559360c73bdSStephen Cameron 5560360c73bdSStephen Cameron hpsa_cmd_init(h, i, c); 5561360c73bdSStephen Cameron atomic_set(&c->refcount, 0); 5562360c73bdSStephen Cameron } 5563360c73bdSStephen Cameron } 5564360c73bdSStephen Cameron 5565360c73bdSStephen Cameron static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, 5566360c73bdSStephen Cameron struct CommandList *c) 5567360c73bdSStephen Cameron { 5568360c73bdSStephen Cameron dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5569360c73bdSStephen Cameron 557073153fe5SWebb Scales BUG_ON(c->cmdindex != index); 557173153fe5SWebb Scales 5572360c73bdSStephen Cameron memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); 5573360c73bdSStephen Cameron memset(c->err_info, 0, sizeof(*c->err_info)); 5574360c73bdSStephen Cameron c->busaddr = (u32) cmd_dma_handle; 5575360c73bdSStephen Cameron } 5576360c73bdSStephen Cameron 5577592a0ad5SWebb Scales static int hpsa_ioaccel_submit(struct ctlr_info *h, 5578c5dfd106SDon Brace struct CommandList *c, struct scsi_cmnd *cmd) 5579592a0ad5SWebb Scales { 5580592a0ad5SWebb Scales struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 5581592a0ad5SWebb Scales int rc = IO_ACCEL_INELIGIBLE; 5582592a0ad5SWebb Scales 558345e596cdSDon Brace if (!dev) 558445e596cdSDon Brace return SCSI_MLQUEUE_HOST_BUSY; 558545e596cdSDon Brace 5586c5dfd106SDon Brace if (dev->in_reset) 5587c5dfd106SDon Brace return SCSI_MLQUEUE_HOST_BUSY; 5588c5dfd106SDon Brace 5589a68fdb3aSDon Brace if (hpsa_simple_mode) 5590a68fdb3aSDon Brace return IO_ACCEL_INELIGIBLE; 5591a68fdb3aSDon Brace 5592592a0ad5SWebb Scales cmd->host_scribble = (unsigned char *) c; 5593592a0ad5SWebb Scales 5594592a0ad5SWebb Scales if (dev->offload_enabled) { 5595592a0ad5SWebb Scales hpsa_cmd_init(h, c->cmdindex, c); 5596592a0ad5SWebb Scales c->cmd_type = CMD_SCSI; 5597592a0ad5SWebb Scales c->scsi_cmd = cmd; 559813499345SDon Brace c->device = dev; 5599592a0ad5SWebb Scales rc = hpsa_scsi_ioaccel_raid_map(h, c); 5600592a0ad5SWebb Scales if (rc < 0) /* scsi_dma_map failed. */ 5601592a0ad5SWebb Scales rc = SCSI_MLQUEUE_HOST_BUSY; 5602a3144e0bSJoe Handzik } else if (dev->hba_ioaccel_enabled) { 5603592a0ad5SWebb Scales hpsa_cmd_init(h, c->cmdindex, c); 5604592a0ad5SWebb Scales c->cmd_type = CMD_SCSI; 5605592a0ad5SWebb Scales c->scsi_cmd = cmd; 560613499345SDon Brace c->device = dev; 5607592a0ad5SWebb Scales rc = hpsa_scsi_ioaccel_direct_map(h, c); 5608592a0ad5SWebb Scales if (rc < 0) /* scsi_dma_map failed. */ 5609592a0ad5SWebb Scales rc = SCSI_MLQUEUE_HOST_BUSY; 5610592a0ad5SWebb Scales } 5611592a0ad5SWebb Scales return rc; 5612592a0ad5SWebb Scales } 5613592a0ad5SWebb Scales 5614080ef1ccSDon Brace static void hpsa_command_resubmit_worker(struct work_struct *work) 5615080ef1ccSDon Brace { 5616080ef1ccSDon Brace struct scsi_cmnd *cmd; 5617080ef1ccSDon Brace struct hpsa_scsi_dev_t *dev; 56188a0ff92cSWebb Scales struct CommandList *c = container_of(work, struct CommandList, work); 5619080ef1ccSDon Brace 5620080ef1ccSDon Brace cmd = c->scsi_cmd; 5621080ef1ccSDon Brace dev = cmd->device->hostdata; 5622080ef1ccSDon Brace if (!dev) { 5623080ef1ccSDon Brace cmd->result = DID_NO_CONNECT << 16; 56248a0ff92cSWebb Scales return hpsa_cmd_free_and_done(c->h, c, cmd); 5625080ef1ccSDon Brace } 5626c5dfd106SDon Brace 5627c5dfd106SDon Brace if (dev->in_reset) { 5628c5dfd106SDon Brace cmd->result = DID_RESET << 16; 5629d2315ce6SDon Brace return hpsa_cmd_free_and_done(c->h, c, cmd); 5630c5dfd106SDon Brace } 5631c5dfd106SDon Brace 5632592a0ad5SWebb Scales if (c->cmd_type == CMD_IOACCEL2) { 5633592a0ad5SWebb Scales struct ctlr_info *h = c->h; 5634592a0ad5SWebb Scales struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 5635592a0ad5SWebb Scales int rc; 5636592a0ad5SWebb Scales 5637592a0ad5SWebb Scales if (c2->error_data.serv_response == 5638592a0ad5SWebb Scales IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { 5639c5dfd106SDon Brace rc = hpsa_ioaccel_submit(h, c, cmd); 5640592a0ad5SWebb Scales if (rc == 0) 5641592a0ad5SWebb Scales return; 5642592a0ad5SWebb Scales if (rc == SCSI_MLQUEUE_HOST_BUSY) { 5643592a0ad5SWebb Scales /* 5644592a0ad5SWebb Scales * If we get here, it means dma mapping failed. 5645592a0ad5SWebb Scales * Try again via scsi mid layer, which will 5646592a0ad5SWebb Scales * then get SCSI_MLQUEUE_HOST_BUSY. 5647592a0ad5SWebb Scales */ 5648592a0ad5SWebb Scales cmd->result = DID_IMM_RETRY << 16; 56498a0ff92cSWebb Scales return hpsa_cmd_free_and_done(h, c, cmd); 5650592a0ad5SWebb Scales } 5651592a0ad5SWebb Scales /* else, fall thru and resubmit down CISS path */ 5652592a0ad5SWebb Scales } 5653592a0ad5SWebb Scales } 5654360c73bdSStephen Cameron hpsa_cmd_partial_init(c->h, c->cmdindex, c); 5655c5dfd106SDon Brace if (hpsa_ciss_submit(c->h, c, cmd, dev)) { 5656080ef1ccSDon Brace /* 5657080ef1ccSDon Brace * If we get here, it means dma mapping failed. Try 5658080ef1ccSDon Brace * again via scsi mid layer, which will then get 5659080ef1ccSDon Brace * SCSI_MLQUEUE_HOST_BUSY. 5660592a0ad5SWebb Scales * 5661592a0ad5SWebb Scales * hpsa_ciss_submit will have already freed c 5662592a0ad5SWebb Scales * if it encountered a dma mapping failure. 5663080ef1ccSDon Brace */ 5664080ef1ccSDon Brace cmd->result = DID_IMM_RETRY << 16; 5665080ef1ccSDon Brace cmd->scsi_done(cmd); 5666080ef1ccSDon Brace } 5667080ef1ccSDon Brace } 5668080ef1ccSDon Brace 5669574f05d3SStephen Cameron /* Running in struct Scsi_Host->host_lock less mode */ 5670574f05d3SStephen Cameron static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) 5671574f05d3SStephen Cameron { 5672574f05d3SStephen Cameron struct ctlr_info *h; 5673574f05d3SStephen Cameron struct hpsa_scsi_dev_t *dev; 5674574f05d3SStephen Cameron struct CommandList *c; 5675574f05d3SStephen Cameron int rc = 0; 5676574f05d3SStephen Cameron 5677574f05d3SStephen Cameron /* Get the ptr to our adapter structure out of cmd->host. */ 5678574f05d3SStephen Cameron h = sdev_to_hba(cmd->device); 567973153fe5SWebb Scales 568073153fe5SWebb Scales BUG_ON(cmd->request->tag < 0); 568173153fe5SWebb Scales 5682574f05d3SStephen Cameron dev = cmd->device->hostdata; 5683574f05d3SStephen Cameron if (!dev) { 56841ccde700SHannes Reinecke cmd->result = DID_NO_CONNECT << 16; 5685ba74fdc4SDon Brace cmd->scsi_done(cmd); 5686ba74fdc4SDon Brace return 0; 5687ba74fdc4SDon Brace } 5688ba74fdc4SDon Brace 5689ba74fdc4SDon Brace if (dev->removed) { 5690574f05d3SStephen Cameron cmd->result = DID_NO_CONNECT << 16; 5691574f05d3SStephen Cameron cmd->scsi_done(cmd); 5692574f05d3SStephen Cameron return 0; 5693574f05d3SStephen Cameron } 569473153fe5SWebb Scales 5695574f05d3SStephen Cameron if (unlikely(lockup_detected(h))) { 569625163bd5SWebb Scales cmd->result = DID_NO_CONNECT << 16; 5697574f05d3SStephen Cameron cmd->scsi_done(cmd); 5698574f05d3SStephen Cameron return 0; 5699574f05d3SStephen Cameron } 5700c5dfd106SDon Brace 5701c5dfd106SDon Brace if (dev->in_reset) 5702c5dfd106SDon Brace return SCSI_MLQUEUE_DEVICE_BUSY; 5703c5dfd106SDon Brace 570473153fe5SWebb Scales c = cmd_tagged_alloc(h, cmd); 57054770e68dSDon Brace if (c == NULL) 57064770e68dSDon Brace return SCSI_MLQUEUE_DEVICE_BUSY; 5707574f05d3SStephen Cameron 5708407863cbSStephen Cameron /* 5709eeebce18SDon Brace * This is necessary because the SML doesn't zero out this field during 5710eeebce18SDon Brace * error recovery. 5711eeebce18SDon Brace */ 5712eeebce18SDon Brace cmd->result = 0; 5713eeebce18SDon Brace 5714eeebce18SDon Brace /* 5715407863cbSStephen Cameron * Call alternate submit routine for I/O accelerated commands. 5716574f05d3SStephen Cameron * Retries always go down the normal I/O path. 5717574f05d3SStephen Cameron */ 5718574f05d3SStephen Cameron if (likely(cmd->retries == 0 && 571957292b58SChristoph Hellwig !blk_rq_is_passthrough(cmd->request) && 5720574f05d3SStephen Cameron h->acciopath_status)) { 5721c5dfd106SDon Brace rc = hpsa_ioaccel_submit(h, c, cmd); 5722574f05d3SStephen Cameron if (rc == 0) 5723592a0ad5SWebb Scales return 0; 5724592a0ad5SWebb Scales if (rc == SCSI_MLQUEUE_HOST_BUSY) { 572573153fe5SWebb Scales hpsa_cmd_resolve_and_free(h, c); 5726574f05d3SStephen Cameron return SCSI_MLQUEUE_HOST_BUSY; 5727574f05d3SStephen Cameron } 5728574f05d3SStephen Cameron } 5729c5dfd106SDon Brace return hpsa_ciss_submit(h, c, cmd, dev); 5730574f05d3SStephen Cameron } 5731574f05d3SStephen Cameron 57328ebc9248SWebb Scales static void hpsa_scan_complete(struct ctlr_info *h) 57335f389360SStephen M. Cameron { 57345f389360SStephen M. Cameron unsigned long flags; 57355f389360SStephen M. Cameron 57365f389360SStephen M. Cameron spin_lock_irqsave(&h->scan_lock, flags); 57375f389360SStephen M. Cameron h->scan_finished = 1; 573887b9e6aaSDon Brace wake_up(&h->scan_wait_queue); 57395f389360SStephen M. Cameron spin_unlock_irqrestore(&h->scan_lock, flags); 57405f389360SStephen M. Cameron } 57415f389360SStephen M. Cameron 5742a08a8471SStephen M. Cameron static void hpsa_scan_start(struct Scsi_Host *sh) 5743a08a8471SStephen M. Cameron { 5744a08a8471SStephen M. Cameron struct ctlr_info *h = shost_to_hba(sh); 5745a08a8471SStephen M. Cameron unsigned long flags; 5746a08a8471SStephen M. Cameron 57478ebc9248SWebb Scales /* 57488ebc9248SWebb Scales * Don't let rescans be initiated on a controller known to be locked 57498ebc9248SWebb Scales * up. If the controller locks up *during* a rescan, that thread is 57508ebc9248SWebb Scales * probably hosed, but at least we can prevent new rescan threads from 57518ebc9248SWebb Scales * piling up on a locked up controller. 57528ebc9248SWebb Scales */ 57538ebc9248SWebb Scales if (unlikely(lockup_detected(h))) 57548ebc9248SWebb Scales return hpsa_scan_complete(h); 57555f389360SStephen M. Cameron 575687b9e6aaSDon Brace /* 575787b9e6aaSDon Brace * If a scan is already waiting to run, no need to add another 575887b9e6aaSDon Brace */ 575987b9e6aaSDon Brace spin_lock_irqsave(&h->scan_lock, flags); 576087b9e6aaSDon Brace if (h->scan_waiting) { 576187b9e6aaSDon Brace spin_unlock_irqrestore(&h->scan_lock, flags); 576287b9e6aaSDon Brace return; 576387b9e6aaSDon Brace } 576487b9e6aaSDon Brace 576587b9e6aaSDon Brace spin_unlock_irqrestore(&h->scan_lock, flags); 576687b9e6aaSDon Brace 5767a08a8471SStephen M. Cameron /* wait until any scan already in progress is finished. */ 5768a08a8471SStephen M. Cameron while (1) { 5769a08a8471SStephen M. Cameron spin_lock_irqsave(&h->scan_lock, flags); 5770a08a8471SStephen M. Cameron if (h->scan_finished) 5771a08a8471SStephen M. Cameron break; 577287b9e6aaSDon Brace h->scan_waiting = 1; 5773a08a8471SStephen M. Cameron spin_unlock_irqrestore(&h->scan_lock, flags); 5774a08a8471SStephen M. Cameron wait_event(h->scan_wait_queue, h->scan_finished); 5775a08a8471SStephen M. Cameron /* Note: We don't need to worry about a race between this 5776a08a8471SStephen M. Cameron * thread and driver unload because the midlayer will 5777a08a8471SStephen M. Cameron * have incremented the reference count, so unload won't 5778a08a8471SStephen M. Cameron * happen if we're in here. 5779a08a8471SStephen M. Cameron */ 5780a08a8471SStephen M. Cameron } 5781a08a8471SStephen M. Cameron h->scan_finished = 0; /* mark scan as in progress */ 578287b9e6aaSDon Brace h->scan_waiting = 0; 5783a08a8471SStephen M. Cameron spin_unlock_irqrestore(&h->scan_lock, flags); 5784a08a8471SStephen M. Cameron 57858ebc9248SWebb Scales if (unlikely(lockup_detected(h))) 57868ebc9248SWebb Scales return hpsa_scan_complete(h); 57875f389360SStephen M. Cameron 5788bfd7546cSDon Brace /* 5789bfd7546cSDon Brace * Do the scan after a reset completion 5790bfd7546cSDon Brace */ 5791c59d04f3SDon Brace spin_lock_irqsave(&h->reset_lock, flags); 5792bfd7546cSDon Brace if (h->reset_in_progress) { 5793bfd7546cSDon Brace h->drv_req_rescan = 1; 5794c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 57953b476aa2SDon Brace hpsa_scan_complete(h); 5796bfd7546cSDon Brace return; 5797bfd7546cSDon Brace } 5798c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 5799bfd7546cSDon Brace 58008aa60681SDon Brace hpsa_update_scsi_devices(h); 5801a08a8471SStephen M. Cameron 58028ebc9248SWebb Scales hpsa_scan_complete(h); 5803a08a8471SStephen M. Cameron } 5804a08a8471SStephen M. Cameron 58057c0a0229SDon Brace static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) 58067c0a0229SDon Brace { 580703383736SDon Brace struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; 580803383736SDon Brace 580903383736SDon Brace if (!logical_drive) 581003383736SDon Brace return -ENODEV; 58117c0a0229SDon Brace 58127c0a0229SDon Brace if (qdepth < 1) 58137c0a0229SDon Brace qdepth = 1; 581403383736SDon Brace else if (qdepth > logical_drive->queue_depth) 581503383736SDon Brace qdepth = logical_drive->queue_depth; 581603383736SDon Brace 581703383736SDon Brace return scsi_change_queue_depth(sdev, qdepth); 58187c0a0229SDon Brace } 58197c0a0229SDon Brace 5820a08a8471SStephen M. Cameron static int hpsa_scan_finished(struct Scsi_Host *sh, 5821a08a8471SStephen M. Cameron unsigned long elapsed_time) 5822a08a8471SStephen M. Cameron { 5823a08a8471SStephen M. Cameron struct ctlr_info *h = shost_to_hba(sh); 5824a08a8471SStephen M. Cameron unsigned long flags; 5825a08a8471SStephen M. Cameron int finished; 5826a08a8471SStephen M. Cameron 5827a08a8471SStephen M. Cameron spin_lock_irqsave(&h->scan_lock, flags); 5828a08a8471SStephen M. Cameron finished = h->scan_finished; 5829a08a8471SStephen M. Cameron spin_unlock_irqrestore(&h->scan_lock, flags); 5830a08a8471SStephen M. Cameron return finished; 5831a08a8471SStephen M. Cameron } 5832a08a8471SStephen M. Cameron 58332946e82bSRobert Elliott static int hpsa_scsi_host_alloc(struct ctlr_info *h) 5834edd16368SStephen M. Cameron { 5835b705690dSStephen M. Cameron struct Scsi_Host *sh; 5836edd16368SStephen M. Cameron 5837b705690dSStephen M. Cameron sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); 58382946e82bSRobert Elliott if (sh == NULL) { 58392946e82bSRobert Elliott dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); 58402946e82bSRobert Elliott return -ENOMEM; 58412946e82bSRobert Elliott } 5842b705690dSStephen M. Cameron 5843b705690dSStephen M. Cameron sh->io_port = 0; 5844b705690dSStephen M. Cameron sh->n_io_port = 0; 5845b705690dSStephen M. Cameron sh->this_id = -1; 5846b705690dSStephen M. Cameron sh->max_channel = 3; 5847b705690dSStephen M. Cameron sh->max_cmd_len = MAX_COMMAND_SIZE; 5848b705690dSStephen M. Cameron sh->max_lun = HPSA_MAX_LUN; 5849b705690dSStephen M. Cameron sh->max_id = HPSA_MAX_LUN; 585041ce4c35SStephen Cameron sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; 5851d54c5c24SStephen Cameron sh->cmd_per_lun = sh->can_queue; 5852b705690dSStephen M. Cameron sh->sg_tablesize = h->maxsgentries; 5853d04e62b9SKevin Barnett sh->transportt = hpsa_sas_transport_template; 5854b705690dSStephen M. Cameron sh->hostdata[0] = (unsigned long) h; 5855bc2bb154SChristoph Hellwig sh->irq = pci_irq_vector(h->pdev, 0); 5856b705690dSStephen M. Cameron sh->unique_id = sh->irq; 585764d513acSChristoph Hellwig 58582946e82bSRobert Elliott h->scsi_host = sh; 58592946e82bSRobert Elliott return 0; 58602946e82bSRobert Elliott } 58612946e82bSRobert Elliott 58622946e82bSRobert Elliott static int hpsa_scsi_add_host(struct ctlr_info *h) 58632946e82bSRobert Elliott { 58642946e82bSRobert Elliott int rv; 58652946e82bSRobert Elliott 58662946e82bSRobert Elliott rv = scsi_add_host(h->scsi_host, &h->pdev->dev); 58672946e82bSRobert Elliott if (rv) { 58682946e82bSRobert Elliott dev_err(&h->pdev->dev, "scsi_add_host failed\n"); 58692946e82bSRobert Elliott return rv; 58702946e82bSRobert Elliott } 58712946e82bSRobert Elliott scsi_scan_host(h->scsi_host); 58722946e82bSRobert Elliott return 0; 5873edd16368SStephen M. Cameron } 5874edd16368SStephen M. Cameron 5875b69324ffSWebb Scales /* 587673153fe5SWebb Scales * The block layer has already gone to the trouble of picking out a unique, 587773153fe5SWebb Scales * small-integer tag for this request. We use an offset from that value as 587873153fe5SWebb Scales * an index to select our command block. (The offset allows us to reserve the 587973153fe5SWebb Scales * low-numbered entries for our own uses.) 588073153fe5SWebb Scales */ 588173153fe5SWebb Scales static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) 588273153fe5SWebb Scales { 588373153fe5SWebb Scales int idx = scmd->request->tag; 588473153fe5SWebb Scales 588573153fe5SWebb Scales if (idx < 0) 588673153fe5SWebb Scales return idx; 588773153fe5SWebb Scales 588873153fe5SWebb Scales /* Offset to leave space for internal cmds. */ 588973153fe5SWebb Scales return idx += HPSA_NRESERVED_CMDS; 589073153fe5SWebb Scales } 589173153fe5SWebb Scales 589273153fe5SWebb Scales /* 5893b69324ffSWebb Scales * Send a TEST_UNIT_READY command to the specified LUN using the specified 5894b69324ffSWebb Scales * reply queue; returns zero if the unit is ready, and non-zero otherwise. 5895b69324ffSWebb Scales */ 5896b69324ffSWebb Scales static int hpsa_send_test_unit_ready(struct ctlr_info *h, 5897b69324ffSWebb Scales struct CommandList *c, unsigned char lunaddr[], 5898b69324ffSWebb Scales int reply_queue) 5899edd16368SStephen M. Cameron { 59008919358eSTomas Henzl int rc; 5901edd16368SStephen M. Cameron 5902a2dac136SStephen M. Cameron /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ 5903a2dac136SStephen M. Cameron (void) fill_cmd(c, TEST_UNIT_READY, h, 5904a2dac136SStephen M. Cameron NULL, 0, 0, lunaddr, TYPE_CMD); 59051edb6934SDon Brace rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); 590625163bd5SWebb Scales if (rc) 5907b69324ffSWebb Scales return rc; 5908edd16368SStephen M. Cameron /* no unmap needed here because no data xfer. */ 5909edd16368SStephen M. Cameron 5910b69324ffSWebb Scales /* Check if the unit is already ready. */ 5911edd16368SStephen M. Cameron if (c->err_info->CommandStatus == CMD_SUCCESS) 5912b69324ffSWebb Scales return 0; 5913edd16368SStephen M. Cameron 5914b69324ffSWebb Scales /* 5915b69324ffSWebb Scales * The first command sent after reset will receive "unit attention" to 5916b69324ffSWebb Scales * indicate that the LUN has been reset...this is actually what we're 5917b69324ffSWebb Scales * looking for (but, success is good too). 5918b69324ffSWebb Scales */ 5919edd16368SStephen M. Cameron if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 5920edd16368SStephen M. Cameron c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && 5921edd16368SStephen M. Cameron (c->err_info->SenseInfo[2] == NO_SENSE || 5922edd16368SStephen M. Cameron c->err_info->SenseInfo[2] == UNIT_ATTENTION)) 5923b69324ffSWebb Scales return 0; 5924b69324ffSWebb Scales 5925b69324ffSWebb Scales return 1; 5926b69324ffSWebb Scales } 5927b69324ffSWebb Scales 5928b69324ffSWebb Scales /* 5929b69324ffSWebb Scales * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; 5930b69324ffSWebb Scales * returns zero when the unit is ready, and non-zero when giving up. 5931b69324ffSWebb Scales */ 5932b69324ffSWebb Scales static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, 5933b69324ffSWebb Scales struct CommandList *c, 5934b69324ffSWebb Scales unsigned char lunaddr[], int reply_queue) 5935b69324ffSWebb Scales { 5936b69324ffSWebb Scales int rc; 5937b69324ffSWebb Scales int count = 0; 5938b69324ffSWebb Scales int waittime = 1; /* seconds */ 5939b69324ffSWebb Scales 5940b69324ffSWebb Scales /* Send test unit ready until device ready, or give up. */ 5941b69324ffSWebb Scales for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { 5942b69324ffSWebb Scales 5943b69324ffSWebb Scales /* 5944b69324ffSWebb Scales * Wait for a bit. do this first, because if we send 5945b69324ffSWebb Scales * the TUR right away, the reset will just abort it. 5946b69324ffSWebb Scales */ 5947b69324ffSWebb Scales msleep(1000 * waittime); 5948b69324ffSWebb Scales 5949b69324ffSWebb Scales rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); 5950b69324ffSWebb Scales if (!rc) 5951edd16368SStephen M. Cameron break; 5952b69324ffSWebb Scales 5953b69324ffSWebb Scales /* Increase wait time with each try, up to a point. */ 5954b69324ffSWebb Scales if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) 5955b69324ffSWebb Scales waittime *= 2; 5956b69324ffSWebb Scales 5957b69324ffSWebb Scales dev_warn(&h->pdev->dev, 5958b69324ffSWebb Scales "waiting %d secs for device to become ready.\n", 5959b69324ffSWebb Scales waittime); 5960b69324ffSWebb Scales } 5961b69324ffSWebb Scales 5962b69324ffSWebb Scales return rc; 5963b69324ffSWebb Scales } 5964b69324ffSWebb Scales 5965b69324ffSWebb Scales static int wait_for_device_to_become_ready(struct ctlr_info *h, 5966b69324ffSWebb Scales unsigned char lunaddr[], 5967b69324ffSWebb Scales int reply_queue) 5968b69324ffSWebb Scales { 5969b69324ffSWebb Scales int first_queue; 5970b69324ffSWebb Scales int last_queue; 5971b69324ffSWebb Scales int rq; 5972b69324ffSWebb Scales int rc = 0; 5973b69324ffSWebb Scales struct CommandList *c; 5974b69324ffSWebb Scales 5975b69324ffSWebb Scales c = cmd_alloc(h); 5976b69324ffSWebb Scales 5977b69324ffSWebb Scales /* 5978b69324ffSWebb Scales * If no specific reply queue was requested, then send the TUR 5979b69324ffSWebb Scales * repeatedly, requesting a reply on each reply queue; otherwise execute 5980b69324ffSWebb Scales * the loop exactly once using only the specified queue. 5981b69324ffSWebb Scales */ 5982b69324ffSWebb Scales if (reply_queue == DEFAULT_REPLY_QUEUE) { 5983b69324ffSWebb Scales first_queue = 0; 5984b69324ffSWebb Scales last_queue = h->nreply_queues - 1; 5985b69324ffSWebb Scales } else { 5986b69324ffSWebb Scales first_queue = reply_queue; 5987b69324ffSWebb Scales last_queue = reply_queue; 5988b69324ffSWebb Scales } 5989b69324ffSWebb Scales 5990b69324ffSWebb Scales for (rq = first_queue; rq <= last_queue; rq++) { 5991b69324ffSWebb Scales rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); 5992b69324ffSWebb Scales if (rc) 5993b69324ffSWebb Scales break; 5994edd16368SStephen M. Cameron } 5995edd16368SStephen M. Cameron 5996edd16368SStephen M. Cameron if (rc) 5997edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "giving up on device.\n"); 5998edd16368SStephen M. Cameron else 5999edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "device is ready.\n"); 6000edd16368SStephen M. Cameron 600145fcb86eSStephen Cameron cmd_free(h, c); 6002edd16368SStephen M. Cameron return rc; 6003edd16368SStephen M. Cameron } 6004edd16368SStephen M. Cameron 6005edd16368SStephen M. Cameron /* Need at least one of these error handlers to keep ../scsi/hosts.c from 6006edd16368SStephen M. Cameron * complaining. Doing a host- or bus-reset can't do anything good here. 6007edd16368SStephen M. Cameron */ 6008edd16368SStephen M. Cameron static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) 6009edd16368SStephen M. Cameron { 6010c59d04f3SDon Brace int rc = SUCCESS; 6011c5dfd106SDon Brace int i; 6012edd16368SStephen M. Cameron struct ctlr_info *h; 601336631157SColin Ian King struct hpsa_scsi_dev_t *dev = NULL; 60140b9b7b6eSScott Teel u8 reset_type; 60152dc127bbSDan Carpenter char msg[48]; 6016c59d04f3SDon Brace unsigned long flags; 6017edd16368SStephen M. Cameron 6018edd16368SStephen M. Cameron /* find the controller to which the command to be aborted was sent */ 6019edd16368SStephen M. Cameron h = sdev_to_hba(scsicmd->device); 6020edd16368SStephen M. Cameron if (h == NULL) /* paranoia */ 6021edd16368SStephen M. Cameron return FAILED; 6022e345893bSDon Brace 6023c59d04f3SDon Brace spin_lock_irqsave(&h->reset_lock, flags); 6024c59d04f3SDon Brace h->reset_in_progress = 1; 6025c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 6026c59d04f3SDon Brace 6027c59d04f3SDon Brace if (lockup_detected(h)) { 6028c59d04f3SDon Brace rc = FAILED; 6029c59d04f3SDon Brace goto return_reset_status; 6030c59d04f3SDon Brace } 6031e345893bSDon Brace 6032edd16368SStephen M. Cameron dev = scsicmd->device->hostdata; 6033edd16368SStephen M. Cameron if (!dev) { 6034d604f533SWebb Scales dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); 6035c59d04f3SDon Brace rc = FAILED; 6036c59d04f3SDon Brace goto return_reset_status; 6037edd16368SStephen M. Cameron } 603825163bd5SWebb Scales 6039c59d04f3SDon Brace if (dev->devtype == TYPE_ENCLOSURE) { 6040c59d04f3SDon Brace rc = SUCCESS; 6041c59d04f3SDon Brace goto return_reset_status; 6042c59d04f3SDon Brace } 6043ef8a5203SDon Brace 604425163bd5SWebb Scales /* if controller locked up, we can guarantee command won't complete */ 604525163bd5SWebb Scales if (lockup_detected(h)) { 60462dc127bbSDan Carpenter snprintf(msg, sizeof(msg), 60472dc127bbSDan Carpenter "cmd %d RESET FAILED, lockup detected", 604873153fe5SWebb Scales hpsa_get_cmd_index(scsicmd)); 604973153fe5SWebb Scales hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 6050c59d04f3SDon Brace rc = FAILED; 6051c59d04f3SDon Brace goto return_reset_status; 605225163bd5SWebb Scales } 605325163bd5SWebb Scales 605425163bd5SWebb Scales /* this reset request might be the result of a lockup; check */ 605525163bd5SWebb Scales if (detect_controller_lockup(h)) { 60562dc127bbSDan Carpenter snprintf(msg, sizeof(msg), 60572dc127bbSDan Carpenter "cmd %d RESET FAILED, new lockup detected", 605873153fe5SWebb Scales hpsa_get_cmd_index(scsicmd)); 605973153fe5SWebb Scales hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 6060c59d04f3SDon Brace rc = FAILED; 6061c59d04f3SDon Brace goto return_reset_status; 606225163bd5SWebb Scales } 606325163bd5SWebb Scales 6064d604f533SWebb Scales /* Do not attempt on controller */ 6065c59d04f3SDon Brace if (is_hba_lunid(dev->scsi3addr)) { 6066c59d04f3SDon Brace rc = SUCCESS; 6067c59d04f3SDon Brace goto return_reset_status; 6068c59d04f3SDon Brace } 6069d604f533SWebb Scales 60700b9b7b6eSScott Teel if (is_logical_dev_addr_mode(dev->scsi3addr)) 60710b9b7b6eSScott Teel reset_type = HPSA_DEVICE_RESET_MSG; 60720b9b7b6eSScott Teel else 60730b9b7b6eSScott Teel reset_type = HPSA_PHYS_TARGET_RESET; 60740b9b7b6eSScott Teel 60750b9b7b6eSScott Teel sprintf(msg, "resetting %s", 60760b9b7b6eSScott Teel reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); 60770b9b7b6eSScott Teel hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 607825163bd5SWebb Scales 6079c5dfd106SDon Brace /* 6080c5dfd106SDon Brace * wait to see if any commands will complete before sending reset 6081c5dfd106SDon Brace */ 6082c5dfd106SDon Brace dev->in_reset = true; /* block any new cmds from OS for this device */ 6083c5dfd106SDon Brace for (i = 0; i < 10; i++) { 6084c5dfd106SDon Brace if (atomic_read(&dev->commands_outstanding) > 0) 6085c5dfd106SDon Brace msleep(1000); 6086c5dfd106SDon Brace else 6087c5dfd106SDon Brace break; 6088c5dfd106SDon Brace } 6089c5dfd106SDon Brace 6090edd16368SStephen M. Cameron /* send a reset to the SCSI LUN which the command was sent to */ 6091c5dfd106SDon Brace rc = hpsa_do_reset(h, dev, reset_type, DEFAULT_REPLY_QUEUE); 6092c59d04f3SDon Brace if (rc == 0) 6093c59d04f3SDon Brace rc = SUCCESS; 6094c59d04f3SDon Brace else 6095c59d04f3SDon Brace rc = FAILED; 6096c59d04f3SDon Brace 60970b9b7b6eSScott Teel sprintf(msg, "reset %s %s", 60980b9b7b6eSScott Teel reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", 6099c59d04f3SDon Brace rc == SUCCESS ? "completed successfully" : "failed"); 6100d604f533SWebb Scales hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 6101c59d04f3SDon Brace 6102c59d04f3SDon Brace return_reset_status: 6103c59d04f3SDon Brace spin_lock_irqsave(&h->reset_lock, flags); 6104da03ded0SDon Brace h->reset_in_progress = 0; 6105c5dfd106SDon Brace if (dev) 6106c5dfd106SDon Brace dev->in_reset = false; 6107c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 6108c59d04f3SDon Brace return rc; 6109edd16368SStephen M. Cameron } 6110edd16368SStephen M. Cameron 6111edd16368SStephen M. Cameron /* 611273153fe5SWebb Scales * For operations with an associated SCSI command, a command block is allocated 611373153fe5SWebb Scales * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the 611473153fe5SWebb Scales * block request tag as an index into a table of entries. cmd_tagged_free() is 611573153fe5SWebb Scales * the complement, although cmd_free() may be called instead. 611673153fe5SWebb Scales */ 611773153fe5SWebb Scales static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 611873153fe5SWebb Scales struct scsi_cmnd *scmd) 611973153fe5SWebb Scales { 612073153fe5SWebb Scales int idx = hpsa_get_cmd_index(scmd); 612173153fe5SWebb Scales struct CommandList *c = h->cmd_pool + idx; 612273153fe5SWebb Scales 612373153fe5SWebb Scales if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { 612473153fe5SWebb Scales dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", 612573153fe5SWebb Scales idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); 612673153fe5SWebb Scales /* The index value comes from the block layer, so if it's out of 612773153fe5SWebb Scales * bounds, it's probably not our bug. 612873153fe5SWebb Scales */ 612973153fe5SWebb Scales BUG(); 613073153fe5SWebb Scales } 613173153fe5SWebb Scales 613273153fe5SWebb Scales if (unlikely(!hpsa_is_cmd_idle(c))) { 613373153fe5SWebb Scales /* 613473153fe5SWebb Scales * We expect that the SCSI layer will hand us a unique tag 613573153fe5SWebb Scales * value. Thus, there should never be a collision here between 613673153fe5SWebb Scales * two requests...because if the selected command isn't idle 613773153fe5SWebb Scales * then someone is going to be very disappointed. 613873153fe5SWebb Scales */ 61394770e68dSDon Brace if (idx != h->last_collision_tag) { /* Print once per tag */ 61404770e68dSDon Brace dev_warn(&h->pdev->dev, 61414770e68dSDon Brace "%s: tag collision (tag=%d)\n", __func__, idx); 61424770e68dSDon Brace if (scmd) 614373153fe5SWebb Scales scsi_print_command(scmd); 61444770e68dSDon Brace h->last_collision_tag = idx; 614573153fe5SWebb Scales } 61464770e68dSDon Brace return NULL; 61474770e68dSDon Brace } 61484770e68dSDon Brace 61494770e68dSDon Brace atomic_inc(&c->refcount); 615073153fe5SWebb Scales 615173153fe5SWebb Scales hpsa_cmd_partial_init(h, idx, c); 615273153fe5SWebb Scales return c; 615373153fe5SWebb Scales } 615473153fe5SWebb Scales 615573153fe5SWebb Scales static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) 615673153fe5SWebb Scales { 615773153fe5SWebb Scales /* 615873153fe5SWebb Scales * Release our reference to the block. We don't need to do anything 615908ec46f6SDon Brace * else to free it, because it is accessed by index. 616073153fe5SWebb Scales */ 616173153fe5SWebb Scales (void)atomic_dec(&c->refcount); 616273153fe5SWebb Scales } 616373153fe5SWebb Scales 616473153fe5SWebb Scales /* 6165edd16368SStephen M. Cameron * For operations that cannot sleep, a command block is allocated at init, 6166edd16368SStephen M. Cameron * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track 6167edd16368SStephen M. Cameron * which ones are free or in use. Lock must be held when calling this. 6168edd16368SStephen M. Cameron * cmd_free() is the complement. 6169bf43caf3SRobert Elliott * This function never gives up and returns NULL. If it hangs, 6170bf43caf3SRobert Elliott * another thread must call cmd_free() to free some tags. 6171edd16368SStephen M. Cameron */ 6172281a7fd0SWebb Scales 6173edd16368SStephen M. Cameron static struct CommandList *cmd_alloc(struct ctlr_info *h) 6174edd16368SStephen M. Cameron { 6175edd16368SStephen M. Cameron struct CommandList *c; 6176360c73bdSStephen Cameron int refcount, i; 617773153fe5SWebb Scales int offset = 0; 6178edd16368SStephen M. Cameron 617933811026SRobert Elliott /* 618033811026SRobert Elliott * There is some *extremely* small but non-zero chance that that 61814c413128SStephen M. Cameron * multiple threads could get in here, and one thread could 61824c413128SStephen M. Cameron * be scanning through the list of bits looking for a free 61834c413128SStephen M. Cameron * one, but the free ones are always behind him, and other 61844c413128SStephen M. Cameron * threads sneak in behind him and eat them before he can 61854c413128SStephen M. Cameron * get to them, so that while there is always a free one, a 61864c413128SStephen M. Cameron * very unlucky thread might be starved anyway, never able to 61874c413128SStephen M. Cameron * beat the other threads. In reality, this happens so 61884c413128SStephen M. Cameron * infrequently as to be indistinguishable from never. 618973153fe5SWebb Scales * 619073153fe5SWebb Scales * Note that we start allocating commands before the SCSI host structure 619173153fe5SWebb Scales * is initialized. Since the search starts at bit zero, this 619273153fe5SWebb Scales * all works, since we have at least one command structure available; 619373153fe5SWebb Scales * however, it means that the structures with the low indexes have to be 619473153fe5SWebb Scales * reserved for driver-initiated requests, while requests from the block 619573153fe5SWebb Scales * layer will use the higher indexes. 61964c413128SStephen M. Cameron */ 61974c413128SStephen M. Cameron 6198281a7fd0SWebb Scales for (;;) { 619973153fe5SWebb Scales i = find_next_zero_bit(h->cmd_pool_bits, 620073153fe5SWebb Scales HPSA_NRESERVED_CMDS, 620173153fe5SWebb Scales offset); 620273153fe5SWebb Scales if (unlikely(i >= HPSA_NRESERVED_CMDS)) { 6203281a7fd0SWebb Scales offset = 0; 6204281a7fd0SWebb Scales continue; 6205281a7fd0SWebb Scales } 6206edd16368SStephen M. Cameron c = h->cmd_pool + i; 6207281a7fd0SWebb Scales refcount = atomic_inc_return(&c->refcount); 6208281a7fd0SWebb Scales if (unlikely(refcount > 1)) { 6209281a7fd0SWebb Scales cmd_free(h, c); /* already in use */ 621073153fe5SWebb Scales offset = (i + 1) % HPSA_NRESERVED_CMDS; 6211281a7fd0SWebb Scales continue; 6212281a7fd0SWebb Scales } 6213281a7fd0SWebb Scales set_bit(i & (BITS_PER_LONG - 1), 6214281a7fd0SWebb Scales h->cmd_pool_bits + (i / BITS_PER_LONG)); 6215281a7fd0SWebb Scales break; /* it's ours now. */ 6216281a7fd0SWebb Scales } 6217360c73bdSStephen Cameron hpsa_cmd_partial_init(h, i, c); 6218c5dfd106SDon Brace c->device = NULL; 6219edd16368SStephen M. Cameron return c; 6220edd16368SStephen M. Cameron } 6221edd16368SStephen M. Cameron 622273153fe5SWebb Scales /* 622373153fe5SWebb Scales * This is the complementary operation to cmd_alloc(). Note, however, in some 622473153fe5SWebb Scales * corner cases it may also be used to free blocks allocated by 622573153fe5SWebb Scales * cmd_tagged_alloc() in which case the ref-count decrement does the trick and 622673153fe5SWebb Scales * the clear-bit is harmless. 622773153fe5SWebb Scales */ 6228edd16368SStephen M. Cameron static void cmd_free(struct ctlr_info *h, struct CommandList *c) 6229edd16368SStephen M. Cameron { 6230281a7fd0SWebb Scales if (atomic_dec_and_test(&c->refcount)) { 6231edd16368SStephen M. Cameron int i; 6232edd16368SStephen M. Cameron 6233edd16368SStephen M. Cameron i = c - h->cmd_pool; 6234edd16368SStephen M. Cameron clear_bit(i & (BITS_PER_LONG - 1), 6235edd16368SStephen M. Cameron h->cmd_pool_bits + (i / BITS_PER_LONG)); 6236edd16368SStephen M. Cameron } 6237281a7fd0SWebb Scales } 6238edd16368SStephen M. Cameron 6239edd16368SStephen M. Cameron #ifdef CONFIG_COMPAT 6240edd16368SStephen M. Cameron 62416f4e626fSNathan Chancellor static int hpsa_ioctl32_passthru(struct scsi_device *dev, unsigned int cmd, 624242a91641SDon Brace void __user *arg) 6243edd16368SStephen M. Cameron { 624410100ffdSAl Viro struct ctlr_info *h = sdev_to_hba(dev); 624510100ffdSAl Viro IOCTL32_Command_struct __user *arg32 = arg; 6246edd16368SStephen M. Cameron IOCTL_Command_struct arg64; 6247edd16368SStephen M. Cameron int err; 6248edd16368SStephen M. Cameron u32 cp; 6249edd16368SStephen M. Cameron 625010100ffdSAl Viro if (!arg) 625110100ffdSAl Viro return -EINVAL; 625210100ffdSAl Viro 6253938abd84SVasiliy Kulikov memset(&arg64, 0, sizeof(arg64)); 625410100ffdSAl Viro if (copy_from_user(&arg64, arg32, offsetof(IOCTL_Command_struct, buf))) 625510100ffdSAl Viro return -EFAULT; 625610100ffdSAl Viro if (get_user(cp, &arg32->buf)) 625710100ffdSAl Viro return -EFAULT; 6258edd16368SStephen M. Cameron arg64.buf = compat_ptr(cp); 6259edd16368SStephen M. Cameron 626010100ffdSAl Viro if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 626110100ffdSAl Viro return -EAGAIN; 626210100ffdSAl Viro err = hpsa_passthru_ioctl(h, &arg64); 626310100ffdSAl Viro atomic_inc(&h->passthru_cmds_avail); 6264edd16368SStephen M. Cameron if (err) 6265edd16368SStephen M. Cameron return err; 626610100ffdSAl Viro if (copy_to_user(&arg32->error_info, &arg64.error_info, 626710100ffdSAl Viro sizeof(arg32->error_info))) 6268edd16368SStephen M. Cameron return -EFAULT; 626910100ffdSAl Viro return 0; 6270edd16368SStephen M. Cameron } 6271edd16368SStephen M. Cameron 6272edd16368SStephen M. Cameron static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, 62736f4e626fSNathan Chancellor unsigned int cmd, void __user *arg) 6274edd16368SStephen M. Cameron { 627510100ffdSAl Viro struct ctlr_info *h = sdev_to_hba(dev); 627610100ffdSAl Viro BIG_IOCTL32_Command_struct __user *arg32 = arg; 6277edd16368SStephen M. Cameron BIG_IOCTL_Command_struct arg64; 6278edd16368SStephen M. Cameron int err; 6279edd16368SStephen M. Cameron u32 cp; 6280edd16368SStephen M. Cameron 628110100ffdSAl Viro if (!arg) 628210100ffdSAl Viro return -EINVAL; 6283938abd84SVasiliy Kulikov memset(&arg64, 0, sizeof(arg64)); 628410100ffdSAl Viro if (copy_from_user(&arg64, arg32, 628510100ffdSAl Viro offsetof(BIG_IOCTL32_Command_struct, buf))) 628610100ffdSAl Viro return -EFAULT; 628710100ffdSAl Viro if (get_user(cp, &arg32->buf)) 628810100ffdSAl Viro return -EFAULT; 6289edd16368SStephen M. Cameron arg64.buf = compat_ptr(cp); 6290edd16368SStephen M. Cameron 629110100ffdSAl Viro if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 629210100ffdSAl Viro return -EAGAIN; 629310100ffdSAl Viro err = hpsa_big_passthru_ioctl(h, &arg64); 629410100ffdSAl Viro atomic_inc(&h->passthru_cmds_avail); 6295edd16368SStephen M. Cameron if (err) 6296edd16368SStephen M. Cameron return err; 629710100ffdSAl Viro if (copy_to_user(&arg32->error_info, &arg64.error_info, 629810100ffdSAl Viro sizeof(arg32->error_info))) 6299edd16368SStephen M. Cameron return -EFAULT; 630010100ffdSAl Viro return 0; 6301edd16368SStephen M. Cameron } 630271fe75a7SStephen M. Cameron 63036f4e626fSNathan Chancellor static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd, 63046f4e626fSNathan Chancellor void __user *arg) 630571fe75a7SStephen M. Cameron { 630671fe75a7SStephen M. Cameron switch (cmd) { 630771fe75a7SStephen M. Cameron case CCISS_GETPCIINFO: 630871fe75a7SStephen M. Cameron case CCISS_GETINTINFO: 630971fe75a7SStephen M. Cameron case CCISS_SETINTINFO: 631071fe75a7SStephen M. Cameron case CCISS_GETNODENAME: 631171fe75a7SStephen M. Cameron case CCISS_SETNODENAME: 631271fe75a7SStephen M. Cameron case CCISS_GETHEARTBEAT: 631371fe75a7SStephen M. Cameron case CCISS_GETBUSTYPES: 631471fe75a7SStephen M. Cameron case CCISS_GETFIRMVER: 631571fe75a7SStephen M. Cameron case CCISS_GETDRIVVER: 631671fe75a7SStephen M. Cameron case CCISS_REVALIDVOLS: 631771fe75a7SStephen M. Cameron case CCISS_DEREGDISK: 631871fe75a7SStephen M. Cameron case CCISS_REGNEWDISK: 631971fe75a7SStephen M. Cameron case CCISS_REGNEWD: 632071fe75a7SStephen M. Cameron case CCISS_RESCANDISK: 632171fe75a7SStephen M. Cameron case CCISS_GETLUNINFO: 632271fe75a7SStephen M. Cameron return hpsa_ioctl(dev, cmd, arg); 632371fe75a7SStephen M. Cameron 632471fe75a7SStephen M. Cameron case CCISS_PASSTHRU32: 632571fe75a7SStephen M. Cameron return hpsa_ioctl32_passthru(dev, cmd, arg); 632671fe75a7SStephen M. Cameron case CCISS_BIG_PASSTHRU32: 632771fe75a7SStephen M. Cameron return hpsa_ioctl32_big_passthru(dev, cmd, arg); 632871fe75a7SStephen M. Cameron 632971fe75a7SStephen M. Cameron default: 633071fe75a7SStephen M. Cameron return -ENOIOCTLCMD; 633171fe75a7SStephen M. Cameron } 633271fe75a7SStephen M. Cameron } 6333edd16368SStephen M. Cameron #endif 6334edd16368SStephen M. Cameron 6335edd16368SStephen M. Cameron static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) 6336edd16368SStephen M. Cameron { 6337edd16368SStephen M. Cameron struct hpsa_pci_info pciinfo; 6338edd16368SStephen M. Cameron 6339edd16368SStephen M. Cameron if (!argp) 6340edd16368SStephen M. Cameron return -EINVAL; 6341edd16368SStephen M. Cameron pciinfo.domain = pci_domain_nr(h->pdev->bus); 6342edd16368SStephen M. Cameron pciinfo.bus = h->pdev->bus->number; 6343edd16368SStephen M. Cameron pciinfo.dev_fn = h->pdev->devfn; 6344edd16368SStephen M. Cameron pciinfo.board_id = h->board_id; 6345edd16368SStephen M. Cameron if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) 6346edd16368SStephen M. Cameron return -EFAULT; 6347edd16368SStephen M. Cameron return 0; 6348edd16368SStephen M. Cameron } 6349edd16368SStephen M. Cameron 6350edd16368SStephen M. Cameron static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) 6351edd16368SStephen M. Cameron { 6352edd16368SStephen M. Cameron DriverVer_type DriverVer; 6353edd16368SStephen M. Cameron unsigned char vmaj, vmin, vsubmin; 6354edd16368SStephen M. Cameron int rc; 6355edd16368SStephen M. Cameron 6356edd16368SStephen M. Cameron rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", 6357edd16368SStephen M. Cameron &vmaj, &vmin, &vsubmin); 6358edd16368SStephen M. Cameron if (rc != 3) { 6359edd16368SStephen M. Cameron dev_info(&h->pdev->dev, "driver version string '%s' " 6360edd16368SStephen M. Cameron "unrecognized.", HPSA_DRIVER_VERSION); 6361edd16368SStephen M. Cameron vmaj = 0; 6362edd16368SStephen M. Cameron vmin = 0; 6363edd16368SStephen M. Cameron vsubmin = 0; 6364edd16368SStephen M. Cameron } 6365edd16368SStephen M. Cameron DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; 6366edd16368SStephen M. Cameron if (!argp) 6367edd16368SStephen M. Cameron return -EINVAL; 6368edd16368SStephen M. Cameron if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) 6369edd16368SStephen M. Cameron return -EFAULT; 6370edd16368SStephen M. Cameron return 0; 6371edd16368SStephen M. Cameron } 6372edd16368SStephen M. Cameron 6373138125f7SAl Viro static int hpsa_passthru_ioctl(struct ctlr_info *h, 6374138125f7SAl Viro IOCTL_Command_struct *iocommand) 6375edd16368SStephen M. Cameron { 6376edd16368SStephen M. Cameron struct CommandList *c; 6377edd16368SStephen M. Cameron char *buff = NULL; 637850a0decfSStephen M. Cameron u64 temp64; 6379c1f63c8fSStephen M. Cameron int rc = 0; 6380edd16368SStephen M. Cameron 6381edd16368SStephen M. Cameron if (!capable(CAP_SYS_RAWIO)) 6382edd16368SStephen M. Cameron return -EPERM; 6383138125f7SAl Viro if ((iocommand->buf_size < 1) && 6384138125f7SAl Viro (iocommand->Request.Type.Direction != XFER_NONE)) { 6385edd16368SStephen M. Cameron return -EINVAL; 6386edd16368SStephen M. Cameron } 6387138125f7SAl Viro if (iocommand->buf_size > 0) { 6388138125f7SAl Viro buff = kmalloc(iocommand->buf_size, GFP_KERNEL); 6389edd16368SStephen M. Cameron if (buff == NULL) 63902dd02d74SRobert Elliott return -ENOMEM; 6391138125f7SAl Viro if (iocommand->Request.Type.Direction & XFER_WRITE) { 6392edd16368SStephen M. Cameron /* Copy the data into the buffer we created */ 6393138125f7SAl Viro if (copy_from_user(buff, iocommand->buf, 6394138125f7SAl Viro iocommand->buf_size)) { 6395c1f63c8fSStephen M. Cameron rc = -EFAULT; 6396c1f63c8fSStephen M. Cameron goto out_kfree; 6397edd16368SStephen M. Cameron } 6398b03a7771SStephen M. Cameron } else { 6399138125f7SAl Viro memset(buff, 0, iocommand->buf_size); 6400b03a7771SStephen M. Cameron } 6401b03a7771SStephen M. Cameron } 640245fcb86eSStephen Cameron c = cmd_alloc(h); 6403bf43caf3SRobert Elliott 6404edd16368SStephen M. Cameron /* Fill in the command type */ 6405edd16368SStephen M. Cameron c->cmd_type = CMD_IOCTL_PEND; 6406a58e7e53SWebb Scales c->scsi_cmd = SCSI_CMD_BUSY; 6407edd16368SStephen M. Cameron /* Fill in Command Header */ 6408edd16368SStephen M. Cameron c->Header.ReplyQueue = 0; /* unused in simple mode */ 6409138125f7SAl Viro if (iocommand->buf_size > 0) { /* buffer to fill */ 6410edd16368SStephen M. Cameron c->Header.SGList = 1; 641150a0decfSStephen M. Cameron c->Header.SGTotal = cpu_to_le16(1); 6412edd16368SStephen M. Cameron } else { /* no buffers to fill */ 6413edd16368SStephen M. Cameron c->Header.SGList = 0; 641450a0decfSStephen M. Cameron c->Header.SGTotal = cpu_to_le16(0); 6415edd16368SStephen M. Cameron } 6416138125f7SAl Viro memcpy(&c->Header.LUN, &iocommand->LUN_info, sizeof(c->Header.LUN)); 6417edd16368SStephen M. Cameron 6418edd16368SStephen M. Cameron /* Fill in Request block */ 6419138125f7SAl Viro memcpy(&c->Request, &iocommand->Request, 6420edd16368SStephen M. Cameron sizeof(c->Request)); 6421edd16368SStephen M. Cameron 6422edd16368SStephen M. Cameron /* Fill in the scatter gather information */ 6423138125f7SAl Viro if (iocommand->buf_size > 0) { 64248bc8f47eSChristoph Hellwig temp64 = dma_map_single(&h->pdev->dev, buff, 6425138125f7SAl Viro iocommand->buf_size, DMA_BIDIRECTIONAL); 642650a0decfSStephen M. Cameron if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { 642750a0decfSStephen M. Cameron c->SG[0].Addr = cpu_to_le64(0); 642850a0decfSStephen M. Cameron c->SG[0].Len = cpu_to_le32(0); 6429bcc48ffaSStephen M. Cameron rc = -ENOMEM; 6430bcc48ffaSStephen M. Cameron goto out; 6431bcc48ffaSStephen M. Cameron } 643250a0decfSStephen M. Cameron c->SG[0].Addr = cpu_to_le64(temp64); 6433138125f7SAl Viro c->SG[0].Len = cpu_to_le32(iocommand->buf_size); 643450a0decfSStephen M. Cameron c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ 6435edd16368SStephen M. Cameron } 6436c448ecfaSDon Brace rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 64373fb134cbSDon Brace NO_TIMEOUT); 6438138125f7SAl Viro if (iocommand->buf_size > 0) 64398bc8f47eSChristoph Hellwig hpsa_pci_unmap(h->pdev, c, 1, DMA_BIDIRECTIONAL); 6440edd16368SStephen M. Cameron check_ioctl_unit_attention(h, c); 644125163bd5SWebb Scales if (rc) { 644225163bd5SWebb Scales rc = -EIO; 644325163bd5SWebb Scales goto out; 644425163bd5SWebb Scales } 6445edd16368SStephen M. Cameron 6446edd16368SStephen M. Cameron /* Copy the error information out */ 6447138125f7SAl Viro memcpy(&iocommand->error_info, c->err_info, 6448138125f7SAl Viro sizeof(iocommand->error_info)); 6449138125f7SAl Viro if ((iocommand->Request.Type.Direction & XFER_READ) && 6450138125f7SAl Viro iocommand->buf_size > 0) { 6451edd16368SStephen M. Cameron /* Copy the data out of the buffer we created */ 6452138125f7SAl Viro if (copy_to_user(iocommand->buf, buff, iocommand->buf_size)) { 6453c1f63c8fSStephen M. Cameron rc = -EFAULT; 6454c1f63c8fSStephen M. Cameron goto out; 6455edd16368SStephen M. Cameron } 6456edd16368SStephen M. Cameron } 6457c1f63c8fSStephen M. Cameron out: 645845fcb86eSStephen Cameron cmd_free(h, c); 6459c1f63c8fSStephen M. Cameron out_kfree: 6460c1f63c8fSStephen M. Cameron kfree(buff); 6461c1f63c8fSStephen M. Cameron return rc; 6462edd16368SStephen M. Cameron } 6463edd16368SStephen M. Cameron 6464138125f7SAl Viro static int hpsa_big_passthru_ioctl(struct ctlr_info *h, 6465138125f7SAl Viro BIG_IOCTL_Command_struct *ioc) 6466edd16368SStephen M. Cameron { 6467edd16368SStephen M. Cameron struct CommandList *c; 6468edd16368SStephen M. Cameron unsigned char **buff = NULL; 6469edd16368SStephen M. Cameron int *buff_size = NULL; 647050a0decfSStephen M. Cameron u64 temp64; 6471edd16368SStephen M. Cameron BYTE sg_used = 0; 6472edd16368SStephen M. Cameron int status = 0; 647301a02ffcSStephen M. Cameron u32 left; 647401a02ffcSStephen M. Cameron u32 sz; 6475edd16368SStephen M. Cameron BYTE __user *data_ptr; 6476edd16368SStephen M. Cameron 6477edd16368SStephen M. Cameron if (!capable(CAP_SYS_RAWIO)) 6478edd16368SStephen M. Cameron return -EPERM; 6479138125f7SAl Viro 6480edd16368SStephen M. Cameron if ((ioc->buf_size < 1) && 6481138125f7SAl Viro (ioc->Request.Type.Direction != XFER_NONE)) 6482138125f7SAl Viro return -EINVAL; 6483edd16368SStephen M. Cameron /* Check kmalloc limits using all SGs */ 6484138125f7SAl Viro if (ioc->malloc_size > MAX_KMALLOC_SIZE) 6485138125f7SAl Viro return -EINVAL; 6486138125f7SAl Viro if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) 6487138125f7SAl Viro return -EINVAL; 64886396bb22SKees Cook buff = kcalloc(SG_ENTRIES_IN_CMD, sizeof(char *), GFP_KERNEL); 6489edd16368SStephen M. Cameron if (!buff) { 6490edd16368SStephen M. Cameron status = -ENOMEM; 6491edd16368SStephen M. Cameron goto cleanup1; 6492edd16368SStephen M. Cameron } 64936da2ec56SKees Cook buff_size = kmalloc_array(SG_ENTRIES_IN_CMD, sizeof(int), GFP_KERNEL); 6494edd16368SStephen M. Cameron if (!buff_size) { 6495edd16368SStephen M. Cameron status = -ENOMEM; 6496edd16368SStephen M. Cameron goto cleanup1; 6497edd16368SStephen M. Cameron } 6498edd16368SStephen M. Cameron left = ioc->buf_size; 6499edd16368SStephen M. Cameron data_ptr = ioc->buf; 6500edd16368SStephen M. Cameron while (left) { 6501edd16368SStephen M. Cameron sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; 6502edd16368SStephen M. Cameron buff_size[sg_used] = sz; 6503edd16368SStephen M. Cameron buff[sg_used] = kmalloc(sz, GFP_KERNEL); 6504edd16368SStephen M. Cameron if (buff[sg_used] == NULL) { 6505edd16368SStephen M. Cameron status = -ENOMEM; 6506edd16368SStephen M. Cameron goto cleanup1; 6507edd16368SStephen M. Cameron } 65089233fb10SStephen M. Cameron if (ioc->Request.Type.Direction & XFER_WRITE) { 6509edd16368SStephen M. Cameron if (copy_from_user(buff[sg_used], data_ptr, sz)) { 65100758f4f7SStephen M. Cameron status = -EFAULT; 6511edd16368SStephen M. Cameron goto cleanup1; 6512edd16368SStephen M. Cameron } 6513edd16368SStephen M. Cameron } else 6514edd16368SStephen M. Cameron memset(buff[sg_used], 0, sz); 6515edd16368SStephen M. Cameron left -= sz; 6516edd16368SStephen M. Cameron data_ptr += sz; 6517edd16368SStephen M. Cameron sg_used++; 6518edd16368SStephen M. Cameron } 651945fcb86eSStephen Cameron c = cmd_alloc(h); 6520bf43caf3SRobert Elliott 6521edd16368SStephen M. Cameron c->cmd_type = CMD_IOCTL_PEND; 6522a58e7e53SWebb Scales c->scsi_cmd = SCSI_CMD_BUSY; 6523edd16368SStephen M. Cameron c->Header.ReplyQueue = 0; 652450a0decfSStephen M. Cameron c->Header.SGList = (u8) sg_used; 652550a0decfSStephen M. Cameron c->Header.SGTotal = cpu_to_le16(sg_used); 6526edd16368SStephen M. Cameron memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); 6527edd16368SStephen M. Cameron memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); 6528edd16368SStephen M. Cameron if (ioc->buf_size > 0) { 6529edd16368SStephen M. Cameron int i; 6530edd16368SStephen M. Cameron for (i = 0; i < sg_used; i++) { 65318bc8f47eSChristoph Hellwig temp64 = dma_map_single(&h->pdev->dev, buff[i], 65328bc8f47eSChristoph Hellwig buff_size[i], DMA_BIDIRECTIONAL); 653350a0decfSStephen M. Cameron if (dma_mapping_error(&h->pdev->dev, 653450a0decfSStephen M. Cameron (dma_addr_t) temp64)) { 653550a0decfSStephen M. Cameron c->SG[i].Addr = cpu_to_le64(0); 653650a0decfSStephen M. Cameron c->SG[i].Len = cpu_to_le32(0); 6537bcc48ffaSStephen M. Cameron hpsa_pci_unmap(h->pdev, c, i, 65388bc8f47eSChristoph Hellwig DMA_BIDIRECTIONAL); 6539bcc48ffaSStephen M. Cameron status = -ENOMEM; 6540e2d4a1f6SStephen M. Cameron goto cleanup0; 6541bcc48ffaSStephen M. Cameron } 654250a0decfSStephen M. Cameron c->SG[i].Addr = cpu_to_le64(temp64); 654350a0decfSStephen M. Cameron c->SG[i].Len = cpu_to_le32(buff_size[i]); 654450a0decfSStephen M. Cameron c->SG[i].Ext = cpu_to_le32(0); 6545edd16368SStephen M. Cameron } 654650a0decfSStephen M. Cameron c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); 6547edd16368SStephen M. Cameron } 6548c448ecfaSDon Brace status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 65493fb134cbSDon Brace NO_TIMEOUT); 6550b03a7771SStephen M. Cameron if (sg_used) 65518bc8f47eSChristoph Hellwig hpsa_pci_unmap(h->pdev, c, sg_used, DMA_BIDIRECTIONAL); 6552edd16368SStephen M. Cameron check_ioctl_unit_attention(h, c); 655325163bd5SWebb Scales if (status) { 655425163bd5SWebb Scales status = -EIO; 655525163bd5SWebb Scales goto cleanup0; 655625163bd5SWebb Scales } 655725163bd5SWebb Scales 6558edd16368SStephen M. Cameron /* Copy the error information out */ 6559edd16368SStephen M. Cameron memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); 65609233fb10SStephen M. Cameron if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { 65612b08b3e9SDon Brace int i; 65622b08b3e9SDon Brace 6563edd16368SStephen M. Cameron /* Copy the data out of the buffer we created */ 6564edd16368SStephen M. Cameron BYTE __user *ptr = ioc->buf; 6565edd16368SStephen M. Cameron for (i = 0; i < sg_used; i++) { 6566edd16368SStephen M. Cameron if (copy_to_user(ptr, buff[i], buff_size[i])) { 6567edd16368SStephen M. Cameron status = -EFAULT; 6568e2d4a1f6SStephen M. Cameron goto cleanup0; 6569edd16368SStephen M. Cameron } 6570edd16368SStephen M. Cameron ptr += buff_size[i]; 6571edd16368SStephen M. Cameron } 6572edd16368SStephen M. Cameron } 6573edd16368SStephen M. Cameron status = 0; 6574e2d4a1f6SStephen M. Cameron cleanup0: 657545fcb86eSStephen Cameron cmd_free(h, c); 6576edd16368SStephen M. Cameron cleanup1: 6577edd16368SStephen M. Cameron if (buff) { 65782b08b3e9SDon Brace int i; 65792b08b3e9SDon Brace 6580edd16368SStephen M. Cameron for (i = 0; i < sg_used; i++) 6581edd16368SStephen M. Cameron kfree(buff[i]); 6582edd16368SStephen M. Cameron kfree(buff); 6583edd16368SStephen M. Cameron } 6584edd16368SStephen M. Cameron kfree(buff_size); 6585edd16368SStephen M. Cameron return status; 6586edd16368SStephen M. Cameron } 6587edd16368SStephen M. Cameron 6588edd16368SStephen M. Cameron static void check_ioctl_unit_attention(struct ctlr_info *h, 6589edd16368SStephen M. Cameron struct CommandList *c) 6590edd16368SStephen M. Cameron { 6591edd16368SStephen M. Cameron if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 6592edd16368SStephen M. Cameron c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) 6593edd16368SStephen M. Cameron (void) check_for_unit_attention(h, c); 6594edd16368SStephen M. Cameron } 65950390f0c0SStephen M. Cameron 6596edd16368SStephen M. Cameron /* 6597edd16368SStephen M. Cameron * ioctl 6598edd16368SStephen M. Cameron */ 65996f4e626fSNathan Chancellor static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd, 660006b43f96SAl Viro void __user *argp) 6601edd16368SStephen M. Cameron { 660206b43f96SAl Viro struct ctlr_info *h = sdev_to_hba(dev); 66030390f0c0SStephen M. Cameron int rc; 6604edd16368SStephen M. Cameron 6605edd16368SStephen M. Cameron switch (cmd) { 6606edd16368SStephen M. Cameron case CCISS_DEREGDISK: 6607edd16368SStephen M. Cameron case CCISS_REGNEWDISK: 6608edd16368SStephen M. Cameron case CCISS_REGNEWD: 6609a08a8471SStephen M. Cameron hpsa_scan_start(h->scsi_host); 6610edd16368SStephen M. Cameron return 0; 6611edd16368SStephen M. Cameron case CCISS_GETPCIINFO: 6612edd16368SStephen M. Cameron return hpsa_getpciinfo_ioctl(h, argp); 6613edd16368SStephen M. Cameron case CCISS_GETDRIVVER: 6614edd16368SStephen M. Cameron return hpsa_getdrivver_ioctl(h, argp); 6615138125f7SAl Viro case CCISS_PASSTHRU: { 6616138125f7SAl Viro IOCTL_Command_struct iocommand; 6617138125f7SAl Viro 6618138125f7SAl Viro if (!argp) 6619138125f7SAl Viro return -EINVAL; 6620138125f7SAl Viro if (copy_from_user(&iocommand, argp, sizeof(iocommand))) 6621138125f7SAl Viro return -EFAULT; 662234f0c627SDon Brace if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 66230390f0c0SStephen M. Cameron return -EAGAIN; 6624138125f7SAl Viro rc = hpsa_passthru_ioctl(h, &iocommand); 662534f0c627SDon Brace atomic_inc(&h->passthru_cmds_avail); 6626138125f7SAl Viro if (!rc && copy_to_user(argp, &iocommand, sizeof(iocommand))) 6627138125f7SAl Viro rc = -EFAULT; 66280390f0c0SStephen M. Cameron return rc; 6629138125f7SAl Viro } 6630138125f7SAl Viro case CCISS_BIG_PASSTHRU: { 6631cb17c1b6SAl Viro BIG_IOCTL_Command_struct ioc; 6632138125f7SAl Viro if (!argp) 6633138125f7SAl Viro return -EINVAL; 6634cb17c1b6SAl Viro if (copy_from_user(&ioc, argp, sizeof(ioc))) 6635cb17c1b6SAl Viro return -EFAULT; 663634f0c627SDon Brace if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 66370390f0c0SStephen M. Cameron return -EAGAIN; 6638cb17c1b6SAl Viro rc = hpsa_big_passthru_ioctl(h, &ioc); 663934f0c627SDon Brace atomic_inc(&h->passthru_cmds_avail); 6640cb17c1b6SAl Viro if (!rc && copy_to_user(argp, &ioc, sizeof(ioc))) 6641138125f7SAl Viro rc = -EFAULT; 66420390f0c0SStephen M. Cameron return rc; 6643138125f7SAl Viro } 6644edd16368SStephen M. Cameron default: 6645edd16368SStephen M. Cameron return -ENOTTY; 6646edd16368SStephen M. Cameron } 6647edd16368SStephen M. Cameron } 6648edd16368SStephen M. Cameron 6649c5dfd106SDon Brace static void hpsa_send_host_reset(struct ctlr_info *h, u8 reset_type) 665064670ac8SStephen M. Cameron { 665164670ac8SStephen M. Cameron struct CommandList *c; 665264670ac8SStephen M. Cameron 665364670ac8SStephen M. Cameron c = cmd_alloc(h); 6654bf43caf3SRobert Elliott 6655a2dac136SStephen M. Cameron /* fill_cmd can't fail here, no data buffer to map */ 6656a2dac136SStephen M. Cameron (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, 665764670ac8SStephen M. Cameron RAID_CTLR_LUNID, TYPE_MSG); 665864670ac8SStephen M. Cameron c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ 665964670ac8SStephen M. Cameron c->waiting = NULL; 666064670ac8SStephen M. Cameron enqueue_cmd_and_start_io(h, c); 666164670ac8SStephen M. Cameron /* Don't wait for completion, the reset won't complete. Don't free 666264670ac8SStephen M. Cameron * the command either. This is the last command we will send before 666364670ac8SStephen M. Cameron * re-initializing everything, so it doesn't matter and won't leak. 666464670ac8SStephen M. Cameron */ 6665bf43caf3SRobert Elliott return; 666664670ac8SStephen M. Cameron } 666764670ac8SStephen M. Cameron 6668a2dac136SStephen M. Cameron static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 6669b7bb24ebSStephen M. Cameron void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 6670edd16368SStephen M. Cameron int cmd_type) 6671edd16368SStephen M. Cameron { 66728bc8f47eSChristoph Hellwig enum dma_data_direction dir = DMA_NONE; 6673edd16368SStephen M. Cameron 6674edd16368SStephen M. Cameron c->cmd_type = CMD_IOCTL_PEND; 6675a58e7e53SWebb Scales c->scsi_cmd = SCSI_CMD_BUSY; 6676edd16368SStephen M. Cameron c->Header.ReplyQueue = 0; 6677edd16368SStephen M. Cameron if (buff != NULL && size > 0) { 6678edd16368SStephen M. Cameron c->Header.SGList = 1; 667950a0decfSStephen M. Cameron c->Header.SGTotal = cpu_to_le16(1); 6680edd16368SStephen M. Cameron } else { 6681edd16368SStephen M. Cameron c->Header.SGList = 0; 668250a0decfSStephen M. Cameron c->Header.SGTotal = cpu_to_le16(0); 6683edd16368SStephen M. Cameron } 6684edd16368SStephen M. Cameron memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); 6685edd16368SStephen M. Cameron 6686edd16368SStephen M. Cameron if (cmd_type == TYPE_CMD) { 6687edd16368SStephen M. Cameron switch (cmd) { 6688edd16368SStephen M. Cameron case HPSA_INQUIRY: 6689edd16368SStephen M. Cameron /* are we trying to read a vital product page */ 6690b7bb24ebSStephen M. Cameron if (page_code & VPD_PAGE) { 6691edd16368SStephen M. Cameron c->Request.CDB[1] = 0x01; 6692b7bb24ebSStephen M. Cameron c->Request.CDB[2] = (page_code & 0xff); 6693edd16368SStephen M. Cameron } 6694edd16368SStephen M. Cameron c->Request.CDBLen = 6; 6695a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6696a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6697edd16368SStephen M. Cameron c->Request.Timeout = 0; 6698edd16368SStephen M. Cameron c->Request.CDB[0] = HPSA_INQUIRY; 6699edd16368SStephen M. Cameron c->Request.CDB[4] = size & 0xFF; 6700edd16368SStephen M. Cameron break; 67010a7c3bb8SDon Brace case RECEIVE_DIAGNOSTIC: 67020a7c3bb8SDon Brace c->Request.CDBLen = 6; 67030a7c3bb8SDon Brace c->Request.type_attr_dir = 67040a7c3bb8SDon Brace TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 67050a7c3bb8SDon Brace c->Request.Timeout = 0; 67060a7c3bb8SDon Brace c->Request.CDB[0] = cmd; 67070a7c3bb8SDon Brace c->Request.CDB[1] = 1; 67080a7c3bb8SDon Brace c->Request.CDB[2] = 1; 67090a7c3bb8SDon Brace c->Request.CDB[3] = (size >> 8) & 0xFF; 67100a7c3bb8SDon Brace c->Request.CDB[4] = size & 0xFF; 67110a7c3bb8SDon Brace break; 6712edd16368SStephen M. Cameron case HPSA_REPORT_LOG: 6713edd16368SStephen M. Cameron case HPSA_REPORT_PHYS: 6714edd16368SStephen M. Cameron /* Talking to controller so It's a physical command 6715edd16368SStephen M. Cameron mode = 00 target = 0. Nothing to write. 6716edd16368SStephen M. Cameron */ 6717edd16368SStephen M. Cameron c->Request.CDBLen = 12; 6718a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6719a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6720edd16368SStephen M. Cameron c->Request.Timeout = 0; 6721edd16368SStephen M. Cameron c->Request.CDB[0] = cmd; 6722edd16368SStephen M. Cameron c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6723edd16368SStephen M. Cameron c->Request.CDB[7] = (size >> 16) & 0xFF; 6724edd16368SStephen M. Cameron c->Request.CDB[8] = (size >> 8) & 0xFF; 6725edd16368SStephen M. Cameron c->Request.CDB[9] = size & 0xFF; 6726edd16368SStephen M. Cameron break; 6727c2adae44SScott Teel case BMIC_SENSE_DIAG_OPTIONS: 6728c2adae44SScott Teel c->Request.CDBLen = 16; 6729c2adae44SScott Teel c->Request.type_attr_dir = 6730c2adae44SScott Teel TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6731c2adae44SScott Teel c->Request.Timeout = 0; 6732c2adae44SScott Teel /* Spec says this should be BMIC_WRITE */ 6733c2adae44SScott Teel c->Request.CDB[0] = BMIC_READ; 6734c2adae44SScott Teel c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; 6735c2adae44SScott Teel break; 6736c2adae44SScott Teel case BMIC_SET_DIAG_OPTIONS: 6737c2adae44SScott Teel c->Request.CDBLen = 16; 6738c2adae44SScott Teel c->Request.type_attr_dir = 6739c2adae44SScott Teel TYPE_ATTR_DIR(cmd_type, 6740c2adae44SScott Teel ATTR_SIMPLE, XFER_WRITE); 6741c2adae44SScott Teel c->Request.Timeout = 0; 6742c2adae44SScott Teel c->Request.CDB[0] = BMIC_WRITE; 6743c2adae44SScott Teel c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; 6744c2adae44SScott Teel break; 6745edd16368SStephen M. Cameron case HPSA_CACHE_FLUSH: 6746edd16368SStephen M. Cameron c->Request.CDBLen = 12; 6747a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6748a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, 6749a505b86fSStephen M. Cameron ATTR_SIMPLE, XFER_WRITE); 6750edd16368SStephen M. Cameron c->Request.Timeout = 0; 6751edd16368SStephen M. Cameron c->Request.CDB[0] = BMIC_WRITE; 6752edd16368SStephen M. Cameron c->Request.CDB[6] = BMIC_CACHE_FLUSH; 6753bb158eabSStephen M. Cameron c->Request.CDB[7] = (size >> 8) & 0xFF; 6754bb158eabSStephen M. Cameron c->Request.CDB[8] = size & 0xFF; 6755edd16368SStephen M. Cameron break; 6756edd16368SStephen M. Cameron case TEST_UNIT_READY: 6757edd16368SStephen M. Cameron c->Request.CDBLen = 6; 6758a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6759a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6760edd16368SStephen M. Cameron c->Request.Timeout = 0; 6761edd16368SStephen M. Cameron break; 6762283b4a9bSStephen M. Cameron case HPSA_GET_RAID_MAP: 6763283b4a9bSStephen M. Cameron c->Request.CDBLen = 12; 6764a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6765a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6766283b4a9bSStephen M. Cameron c->Request.Timeout = 0; 6767283b4a9bSStephen M. Cameron c->Request.CDB[0] = HPSA_CISS_READ; 6768283b4a9bSStephen M. Cameron c->Request.CDB[1] = cmd; 6769283b4a9bSStephen M. Cameron c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6770283b4a9bSStephen M. Cameron c->Request.CDB[7] = (size >> 16) & 0xFF; 6771283b4a9bSStephen M. Cameron c->Request.CDB[8] = (size >> 8) & 0xFF; 6772283b4a9bSStephen M. Cameron c->Request.CDB[9] = size & 0xFF; 6773283b4a9bSStephen M. Cameron break; 6774316b221aSStephen M. Cameron case BMIC_SENSE_CONTROLLER_PARAMETERS: 6775316b221aSStephen M. Cameron c->Request.CDBLen = 10; 6776a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6777a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6778316b221aSStephen M. Cameron c->Request.Timeout = 0; 6779316b221aSStephen M. Cameron c->Request.CDB[0] = BMIC_READ; 6780316b221aSStephen M. Cameron c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; 6781316b221aSStephen M. Cameron c->Request.CDB[7] = (size >> 16) & 0xFF; 6782316b221aSStephen M. Cameron c->Request.CDB[8] = (size >> 8) & 0xFF; 6783316b221aSStephen M. Cameron break; 678403383736SDon Brace case BMIC_IDENTIFY_PHYSICAL_DEVICE: 678503383736SDon Brace c->Request.CDBLen = 10; 678603383736SDon Brace c->Request.type_attr_dir = 678703383736SDon Brace TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 678803383736SDon Brace c->Request.Timeout = 0; 678903383736SDon Brace c->Request.CDB[0] = BMIC_READ; 679003383736SDon Brace c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; 679103383736SDon Brace c->Request.CDB[7] = (size >> 16) & 0xFF; 679203383736SDon Brace c->Request.CDB[8] = (size >> 8) & 0XFF; 679303383736SDon Brace break; 6794d04e62b9SKevin Barnett case BMIC_SENSE_SUBSYSTEM_INFORMATION: 6795d04e62b9SKevin Barnett c->Request.CDBLen = 10; 6796d04e62b9SKevin Barnett c->Request.type_attr_dir = 6797d04e62b9SKevin Barnett TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6798d04e62b9SKevin Barnett c->Request.Timeout = 0; 6799d04e62b9SKevin Barnett c->Request.CDB[0] = BMIC_READ; 6800d04e62b9SKevin Barnett c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; 6801d04e62b9SKevin Barnett c->Request.CDB[7] = (size >> 16) & 0xFF; 6802d04e62b9SKevin Barnett c->Request.CDB[8] = (size >> 8) & 0XFF; 6803d04e62b9SKevin Barnett break; 6804cca8f13bSDon Brace case BMIC_SENSE_STORAGE_BOX_PARAMS: 6805cca8f13bSDon Brace c->Request.CDBLen = 10; 6806cca8f13bSDon Brace c->Request.type_attr_dir = 6807cca8f13bSDon Brace TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6808cca8f13bSDon Brace c->Request.Timeout = 0; 6809cca8f13bSDon Brace c->Request.CDB[0] = BMIC_READ; 6810cca8f13bSDon Brace c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS; 6811cca8f13bSDon Brace c->Request.CDB[7] = (size >> 16) & 0xFF; 6812cca8f13bSDon Brace c->Request.CDB[8] = (size >> 8) & 0XFF; 6813cca8f13bSDon Brace break; 681466749d0dSScott Teel case BMIC_IDENTIFY_CONTROLLER: 681566749d0dSScott Teel c->Request.CDBLen = 10; 681666749d0dSScott Teel c->Request.type_attr_dir = 681766749d0dSScott Teel TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 681866749d0dSScott Teel c->Request.Timeout = 0; 681966749d0dSScott Teel c->Request.CDB[0] = BMIC_READ; 682066749d0dSScott Teel c->Request.CDB[1] = 0; 682166749d0dSScott Teel c->Request.CDB[2] = 0; 682266749d0dSScott Teel c->Request.CDB[3] = 0; 682366749d0dSScott Teel c->Request.CDB[4] = 0; 682466749d0dSScott Teel c->Request.CDB[5] = 0; 682566749d0dSScott Teel c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; 682666749d0dSScott Teel c->Request.CDB[7] = (size >> 16) & 0xFF; 682766749d0dSScott Teel c->Request.CDB[8] = (size >> 8) & 0XFF; 682866749d0dSScott Teel c->Request.CDB[9] = 0; 682966749d0dSScott Teel break; 6830edd16368SStephen M. Cameron default: 6831edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); 6832edd16368SStephen M. Cameron BUG(); 6833edd16368SStephen M. Cameron } 6834edd16368SStephen M. Cameron } else if (cmd_type == TYPE_MSG) { 6835edd16368SStephen M. Cameron switch (cmd) { 6836edd16368SStephen M. Cameron 68370b9b7b6eSScott Teel case HPSA_PHYS_TARGET_RESET: 68380b9b7b6eSScott Teel c->Request.CDBLen = 16; 68390b9b7b6eSScott Teel c->Request.type_attr_dir = 68400b9b7b6eSScott Teel TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 68410b9b7b6eSScott Teel c->Request.Timeout = 0; /* Don't time out */ 68420b9b7b6eSScott Teel memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 68430b9b7b6eSScott Teel c->Request.CDB[0] = HPSA_RESET; 68440b9b7b6eSScott Teel c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; 68450b9b7b6eSScott Teel /* Physical target reset needs no control bytes 4-7*/ 68460b9b7b6eSScott Teel c->Request.CDB[4] = 0x00; 68470b9b7b6eSScott Teel c->Request.CDB[5] = 0x00; 68480b9b7b6eSScott Teel c->Request.CDB[6] = 0x00; 68490b9b7b6eSScott Teel c->Request.CDB[7] = 0x00; 68500b9b7b6eSScott Teel break; 6851edd16368SStephen M. Cameron case HPSA_DEVICE_RESET_MSG: 6852edd16368SStephen M. Cameron c->Request.CDBLen = 16; 6853a505b86fSStephen M. Cameron c->Request.type_attr_dir = 6854a505b86fSStephen M. Cameron TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6855edd16368SStephen M. Cameron c->Request.Timeout = 0; /* Don't time out */ 685664670ac8SStephen M. Cameron memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 685764670ac8SStephen M. Cameron c->Request.CDB[0] = cmd; 685821e89afdSStephen M. Cameron c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; 6859edd16368SStephen M. Cameron /* If bytes 4-7 are zero, it means reset the */ 6860edd16368SStephen M. Cameron /* LunID device */ 6861edd16368SStephen M. Cameron c->Request.CDB[4] = 0x00; 6862edd16368SStephen M. Cameron c->Request.CDB[5] = 0x00; 6863edd16368SStephen M. Cameron c->Request.CDB[6] = 0x00; 6864edd16368SStephen M. Cameron c->Request.CDB[7] = 0x00; 6865edd16368SStephen M. Cameron break; 6866edd16368SStephen M. Cameron default: 6867edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "unknown message type %d\n", 6868edd16368SStephen M. Cameron cmd); 6869edd16368SStephen M. Cameron BUG(); 6870edd16368SStephen M. Cameron } 6871edd16368SStephen M. Cameron } else { 6872edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); 6873edd16368SStephen M. Cameron BUG(); 6874edd16368SStephen M. Cameron } 6875edd16368SStephen M. Cameron 6876a505b86fSStephen M. Cameron switch (GET_DIR(c->Request.type_attr_dir)) { 6877edd16368SStephen M. Cameron case XFER_READ: 68788bc8f47eSChristoph Hellwig dir = DMA_FROM_DEVICE; 6879edd16368SStephen M. Cameron break; 6880edd16368SStephen M. Cameron case XFER_WRITE: 68818bc8f47eSChristoph Hellwig dir = DMA_TO_DEVICE; 6882edd16368SStephen M. Cameron break; 6883edd16368SStephen M. Cameron case XFER_NONE: 68848bc8f47eSChristoph Hellwig dir = DMA_NONE; 6885edd16368SStephen M. Cameron break; 6886edd16368SStephen M. Cameron default: 68878bc8f47eSChristoph Hellwig dir = DMA_BIDIRECTIONAL; 6888edd16368SStephen M. Cameron } 68898bc8f47eSChristoph Hellwig if (hpsa_map_one(h->pdev, c, buff, size, dir)) 6890a2dac136SStephen M. Cameron return -1; 6891a2dac136SStephen M. Cameron return 0; 6892edd16368SStephen M. Cameron } 6893edd16368SStephen M. Cameron 6894edd16368SStephen M. Cameron /* 6895edd16368SStephen M. Cameron * Map (physical) PCI mem into (virtual) kernel space 6896edd16368SStephen M. Cameron */ 6897edd16368SStephen M. Cameron static void __iomem *remap_pci_mem(ulong base, ulong size) 6898edd16368SStephen M. Cameron { 6899edd16368SStephen M. Cameron ulong page_base = ((ulong) base) & PAGE_MASK; 6900edd16368SStephen M. Cameron ulong page_offs = ((ulong) base) - page_base; 69014bdc0d67SChristoph Hellwig void __iomem *page_remapped = ioremap(page_base, 6902088ba34cSStephen M. Cameron page_offs + size); 6903edd16368SStephen M. Cameron 6904edd16368SStephen M. Cameron return page_remapped ? (page_remapped + page_offs) : NULL; 6905edd16368SStephen M. Cameron } 6906edd16368SStephen M. Cameron 6907254f796bSMatt Gates static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) 6908edd16368SStephen M. Cameron { 6909254f796bSMatt Gates return h->access.command_completed(h, q); 6910edd16368SStephen M. Cameron } 6911edd16368SStephen M. Cameron 6912900c5440SStephen M. Cameron static inline bool interrupt_pending(struct ctlr_info *h) 6913edd16368SStephen M. Cameron { 6914edd16368SStephen M. Cameron return h->access.intr_pending(h); 6915edd16368SStephen M. Cameron } 6916edd16368SStephen M. Cameron 6917edd16368SStephen M. Cameron static inline long interrupt_not_for_us(struct ctlr_info *h) 6918edd16368SStephen M. Cameron { 691910f66018SStephen M. Cameron return (h->access.intr_pending(h) == 0) || 692010f66018SStephen M. Cameron (h->interrupts_enabled == 0); 6921edd16368SStephen M. Cameron } 6922edd16368SStephen M. Cameron 692301a02ffcSStephen M. Cameron static inline int bad_tag(struct ctlr_info *h, u32 tag_index, 692401a02ffcSStephen M. Cameron u32 raw_tag) 6925edd16368SStephen M. Cameron { 6926edd16368SStephen M. Cameron if (unlikely(tag_index >= h->nr_cmds)) { 6927edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); 6928edd16368SStephen M. Cameron return 1; 6929edd16368SStephen M. Cameron } 6930edd16368SStephen M. Cameron return 0; 6931edd16368SStephen M. Cameron } 6932edd16368SStephen M. Cameron 69335a3d16f5SStephen M. Cameron static inline void finish_cmd(struct CommandList *c) 6934edd16368SStephen M. Cameron { 6935e85c5974SStephen M. Cameron dial_up_lockup_detection_on_fw_flash_complete(c->h, c); 6936c349775eSScott Teel if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI 6937c349775eSScott Teel || c->cmd_type == CMD_IOACCEL2)) 69381fb011fbSStephen M. Cameron complete_scsi_command(c); 69398be986ccSStephen Cameron else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) 6940edd16368SStephen M. Cameron complete(c->waiting); 6941a104c99fSStephen M. Cameron } 6942a104c99fSStephen M. Cameron 6943303932fdSDon Brace /* process completion of an indexed ("direct lookup") command */ 69441d94f94dSStephen M. Cameron static inline void process_indexed_cmd(struct ctlr_info *h, 6945303932fdSDon Brace u32 raw_tag) 6946303932fdSDon Brace { 6947303932fdSDon Brace u32 tag_index; 6948303932fdSDon Brace struct CommandList *c; 6949303932fdSDon Brace 6950f2405db8SDon Brace tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; 69511d94f94dSStephen M. Cameron if (!bad_tag(h, tag_index, raw_tag)) { 6952303932fdSDon Brace c = h->cmd_pool + tag_index; 69535a3d16f5SStephen M. Cameron finish_cmd(c); 69541d94f94dSStephen M. Cameron } 6955303932fdSDon Brace } 6956303932fdSDon Brace 695764670ac8SStephen M. Cameron /* Some controllers, like p400, will give us one interrupt 695864670ac8SStephen M. Cameron * after a soft reset, even if we turned interrupts off. 695964670ac8SStephen M. Cameron * Only need to check for this in the hpsa_xxx_discard_completions 696064670ac8SStephen M. Cameron * functions. 696164670ac8SStephen M. Cameron */ 696264670ac8SStephen M. Cameron static int ignore_bogus_interrupt(struct ctlr_info *h) 696364670ac8SStephen M. Cameron { 696464670ac8SStephen M. Cameron if (likely(!reset_devices)) 696564670ac8SStephen M. Cameron return 0; 696664670ac8SStephen M. Cameron 696764670ac8SStephen M. Cameron if (likely(h->interrupts_enabled)) 696864670ac8SStephen M. Cameron return 0; 696964670ac8SStephen M. Cameron 697064670ac8SStephen M. Cameron dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " 697164670ac8SStephen M. Cameron "(known firmware bug.) Ignoring.\n"); 697264670ac8SStephen M. Cameron 697364670ac8SStephen M. Cameron return 1; 697464670ac8SStephen M. Cameron } 697564670ac8SStephen M. Cameron 6976254f796bSMatt Gates /* 6977254f796bSMatt Gates * Convert &h->q[x] (passed to interrupt handlers) back to h. 6978254f796bSMatt Gates * Relies on (h-q[x] == x) being true for x such that 6979254f796bSMatt Gates * 0 <= x < MAX_REPLY_QUEUES. 6980254f796bSMatt Gates */ 6981254f796bSMatt Gates static struct ctlr_info *queue_to_hba(u8 *queue) 698264670ac8SStephen M. Cameron { 6983254f796bSMatt Gates return container_of((queue - *queue), struct ctlr_info, q[0]); 6984254f796bSMatt Gates } 6985254f796bSMatt Gates 6986254f796bSMatt Gates static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) 6987254f796bSMatt Gates { 6988254f796bSMatt Gates struct ctlr_info *h = queue_to_hba(queue); 6989254f796bSMatt Gates u8 q = *(u8 *) queue; 699064670ac8SStephen M. Cameron u32 raw_tag; 699164670ac8SStephen M. Cameron 699264670ac8SStephen M. Cameron if (ignore_bogus_interrupt(h)) 699364670ac8SStephen M. Cameron return IRQ_NONE; 699464670ac8SStephen M. Cameron 699564670ac8SStephen M. Cameron if (interrupt_not_for_us(h)) 699664670ac8SStephen M. Cameron return IRQ_NONE; 6997a0c12413SStephen M. Cameron h->last_intr_timestamp = get_jiffies_64(); 699864670ac8SStephen M. Cameron while (interrupt_pending(h)) { 6999254f796bSMatt Gates raw_tag = get_next_completion(h, q); 700064670ac8SStephen M. Cameron while (raw_tag != FIFO_EMPTY) 7001254f796bSMatt Gates raw_tag = next_command(h, q); 700264670ac8SStephen M. Cameron } 700364670ac8SStephen M. Cameron return IRQ_HANDLED; 700464670ac8SStephen M. Cameron } 700564670ac8SStephen M. Cameron 7006254f796bSMatt Gates static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) 700764670ac8SStephen M. Cameron { 7008254f796bSMatt Gates struct ctlr_info *h = queue_to_hba(queue); 700964670ac8SStephen M. Cameron u32 raw_tag; 7010254f796bSMatt Gates u8 q = *(u8 *) queue; 701164670ac8SStephen M. Cameron 701264670ac8SStephen M. Cameron if (ignore_bogus_interrupt(h)) 701364670ac8SStephen M. Cameron return IRQ_NONE; 701464670ac8SStephen M. Cameron 7015a0c12413SStephen M. Cameron h->last_intr_timestamp = get_jiffies_64(); 7016254f796bSMatt Gates raw_tag = get_next_completion(h, q); 701764670ac8SStephen M. Cameron while (raw_tag != FIFO_EMPTY) 7018254f796bSMatt Gates raw_tag = next_command(h, q); 701964670ac8SStephen M. Cameron return IRQ_HANDLED; 702064670ac8SStephen M. Cameron } 702164670ac8SStephen M. Cameron 7022254f796bSMatt Gates static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) 7023edd16368SStephen M. Cameron { 7024254f796bSMatt Gates struct ctlr_info *h = queue_to_hba((u8 *) queue); 7025303932fdSDon Brace u32 raw_tag; 7026254f796bSMatt Gates u8 q = *(u8 *) queue; 7027edd16368SStephen M. Cameron 7028edd16368SStephen M. Cameron if (interrupt_not_for_us(h)) 7029edd16368SStephen M. Cameron return IRQ_NONE; 7030a0c12413SStephen M. Cameron h->last_intr_timestamp = get_jiffies_64(); 703110f66018SStephen M. Cameron while (interrupt_pending(h)) { 7032254f796bSMatt Gates raw_tag = get_next_completion(h, q); 703310f66018SStephen M. Cameron while (raw_tag != FIFO_EMPTY) { 70341d94f94dSStephen M. Cameron process_indexed_cmd(h, raw_tag); 7035254f796bSMatt Gates raw_tag = next_command(h, q); 703610f66018SStephen M. Cameron } 703710f66018SStephen M. Cameron } 703810f66018SStephen M. Cameron return IRQ_HANDLED; 703910f66018SStephen M. Cameron } 704010f66018SStephen M. Cameron 7041254f796bSMatt Gates static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) 704210f66018SStephen M. Cameron { 7043254f796bSMatt Gates struct ctlr_info *h = queue_to_hba(queue); 704410f66018SStephen M. Cameron u32 raw_tag; 7045254f796bSMatt Gates u8 q = *(u8 *) queue; 704610f66018SStephen M. Cameron 7047a0c12413SStephen M. Cameron h->last_intr_timestamp = get_jiffies_64(); 7048254f796bSMatt Gates raw_tag = get_next_completion(h, q); 7049303932fdSDon Brace while (raw_tag != FIFO_EMPTY) { 70501d94f94dSStephen M. Cameron process_indexed_cmd(h, raw_tag); 7051254f796bSMatt Gates raw_tag = next_command(h, q); 7052edd16368SStephen M. Cameron } 7053edd16368SStephen M. Cameron return IRQ_HANDLED; 7054edd16368SStephen M. Cameron } 7055edd16368SStephen M. Cameron 7056a9a3a273SStephen M. Cameron /* Send a message CDB to the firmware. Careful, this only works 7057a9a3a273SStephen M. Cameron * in simple mode, not performant mode due to the tag lookup. 7058a9a3a273SStephen M. Cameron * We only ever use this immediately after a controller reset. 7059a9a3a273SStephen M. Cameron */ 70606f039790SGreg Kroah-Hartman static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, 7061edd16368SStephen M. Cameron unsigned char type) 7062edd16368SStephen M. Cameron { 7063edd16368SStephen M. Cameron struct Command { 7064edd16368SStephen M. Cameron struct CommandListHeader CommandHeader; 7065edd16368SStephen M. Cameron struct RequestBlock Request; 7066edd16368SStephen M. Cameron struct ErrDescriptor ErrorDescriptor; 7067edd16368SStephen M. Cameron }; 7068edd16368SStephen M. Cameron struct Command *cmd; 7069edd16368SStephen M. Cameron static const size_t cmd_sz = sizeof(*cmd) + 7070edd16368SStephen M. Cameron sizeof(cmd->ErrorDescriptor); 7071edd16368SStephen M. Cameron dma_addr_t paddr64; 70722b08b3e9SDon Brace __le32 paddr32; 70732b08b3e9SDon Brace u32 tag; 7074edd16368SStephen M. Cameron void __iomem *vaddr; 7075edd16368SStephen M. Cameron int i, err; 7076edd16368SStephen M. Cameron 7077edd16368SStephen M. Cameron vaddr = pci_ioremap_bar(pdev, 0); 7078edd16368SStephen M. Cameron if (vaddr == NULL) 7079edd16368SStephen M. Cameron return -ENOMEM; 7080edd16368SStephen M. Cameron 7081edd16368SStephen M. Cameron /* The Inbound Post Queue only accepts 32-bit physical addresses for the 7082edd16368SStephen M. Cameron * CCISS commands, so they must be allocated from the lower 4GiB of 7083edd16368SStephen M. Cameron * memory. 7084edd16368SStephen M. Cameron */ 70858bc8f47eSChristoph Hellwig err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 7086edd16368SStephen M. Cameron if (err) { 7087edd16368SStephen M. Cameron iounmap(vaddr); 70881eaec8f3SRobert Elliott return err; 7089edd16368SStephen M. Cameron } 7090edd16368SStephen M. Cameron 70918bc8f47eSChristoph Hellwig cmd = dma_alloc_coherent(&pdev->dev, cmd_sz, &paddr64, GFP_KERNEL); 7092edd16368SStephen M. Cameron if (cmd == NULL) { 7093edd16368SStephen M. Cameron iounmap(vaddr); 7094edd16368SStephen M. Cameron return -ENOMEM; 7095edd16368SStephen M. Cameron } 7096edd16368SStephen M. Cameron 7097edd16368SStephen M. Cameron /* This must fit, because of the 32-bit consistent DMA mask. Also, 7098edd16368SStephen M. Cameron * although there's no guarantee, we assume that the address is at 7099edd16368SStephen M. Cameron * least 4-byte aligned (most likely, it's page-aligned). 7100edd16368SStephen M. Cameron */ 71012b08b3e9SDon Brace paddr32 = cpu_to_le32(paddr64); 7102edd16368SStephen M. Cameron 7103edd16368SStephen M. Cameron cmd->CommandHeader.ReplyQueue = 0; 7104edd16368SStephen M. Cameron cmd->CommandHeader.SGList = 0; 710550a0decfSStephen M. Cameron cmd->CommandHeader.SGTotal = cpu_to_le16(0); 71062b08b3e9SDon Brace cmd->CommandHeader.tag = cpu_to_le64(paddr64); 7107edd16368SStephen M. Cameron memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); 7108edd16368SStephen M. Cameron 7109edd16368SStephen M. Cameron cmd->Request.CDBLen = 16; 7110a505b86fSStephen M. Cameron cmd->Request.type_attr_dir = 7111a505b86fSStephen M. Cameron TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); 7112edd16368SStephen M. Cameron cmd->Request.Timeout = 0; /* Don't time out */ 7113edd16368SStephen M. Cameron cmd->Request.CDB[0] = opcode; 7114edd16368SStephen M. Cameron cmd->Request.CDB[1] = type; 7115edd16368SStephen M. Cameron memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ 711650a0decfSStephen M. Cameron cmd->ErrorDescriptor.Addr = 71172b08b3e9SDon Brace cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); 711850a0decfSStephen M. Cameron cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); 7119edd16368SStephen M. Cameron 71202b08b3e9SDon Brace writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); 7121edd16368SStephen M. Cameron 7122edd16368SStephen M. Cameron for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { 7123edd16368SStephen M. Cameron tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); 71242b08b3e9SDon Brace if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) 7125edd16368SStephen M. Cameron break; 7126edd16368SStephen M. Cameron msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); 7127edd16368SStephen M. Cameron } 7128edd16368SStephen M. Cameron 7129edd16368SStephen M. Cameron iounmap(vaddr); 7130edd16368SStephen M. Cameron 7131edd16368SStephen M. Cameron /* we leak the DMA buffer here ... no choice since the controller could 7132edd16368SStephen M. Cameron * still complete the command. 7133edd16368SStephen M. Cameron */ 7134edd16368SStephen M. Cameron if (i == HPSA_MSG_SEND_RETRY_LIMIT) { 7135edd16368SStephen M. Cameron dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", 7136edd16368SStephen M. Cameron opcode, type); 7137edd16368SStephen M. Cameron return -ETIMEDOUT; 7138edd16368SStephen M. Cameron } 7139edd16368SStephen M. Cameron 71408bc8f47eSChristoph Hellwig dma_free_coherent(&pdev->dev, cmd_sz, cmd, paddr64); 7141edd16368SStephen M. Cameron 7142edd16368SStephen M. Cameron if (tag & HPSA_ERROR_BIT) { 7143edd16368SStephen M. Cameron dev_err(&pdev->dev, "controller message %02x:%02x failed\n", 7144edd16368SStephen M. Cameron opcode, type); 7145edd16368SStephen M. Cameron return -EIO; 7146edd16368SStephen M. Cameron } 7147edd16368SStephen M. Cameron 7148edd16368SStephen M. Cameron dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", 7149edd16368SStephen M. Cameron opcode, type); 7150edd16368SStephen M. Cameron return 0; 7151edd16368SStephen M. Cameron } 7152edd16368SStephen M. Cameron 7153edd16368SStephen M. Cameron #define hpsa_noop(p) hpsa_message(p, 3, 0) 7154edd16368SStephen M. Cameron 71551df8552aSStephen M. Cameron static int hpsa_controller_hard_reset(struct pci_dev *pdev, 715642a91641SDon Brace void __iomem *vaddr, u32 use_doorbell) 7157edd16368SStephen M. Cameron { 7158edd16368SStephen M. Cameron 71591df8552aSStephen M. Cameron if (use_doorbell) { 71601df8552aSStephen M. Cameron /* For everything after the P600, the PCI power state method 71611df8552aSStephen M. Cameron * of resetting the controller doesn't work, so we have this 71621df8552aSStephen M. Cameron * other way using the doorbell register. 7163edd16368SStephen M. Cameron */ 71641df8552aSStephen M. Cameron dev_info(&pdev->dev, "using doorbell to reset controller\n"); 7165cf0b08d0SStephen M. Cameron writel(use_doorbell, vaddr + SA5_DOORBELL); 716685009239SStephen M. Cameron 716700701a96SJustin Lindley /* PMC hardware guys tell us we need a 10 second delay after 716885009239SStephen M. Cameron * doorbell reset and before any attempt to talk to the board 716985009239SStephen M. Cameron * at all to ensure that this actually works and doesn't fall 717085009239SStephen M. Cameron * over in some weird corner cases. 717185009239SStephen M. Cameron */ 717200701a96SJustin Lindley msleep(10000); 71731df8552aSStephen M. Cameron } else { /* Try to do it the PCI power state way */ 7174edd16368SStephen M. Cameron 7175edd16368SStephen M. Cameron /* Quoting from the Open CISS Specification: "The Power 7176edd16368SStephen M. Cameron * Management Control/Status Register (CSR) controls the power 7177edd16368SStephen M. Cameron * state of the device. The normal operating state is D0, 7178edd16368SStephen M. Cameron * CSR=00h. The software off state is D3, CSR=03h. To reset 71791df8552aSStephen M. Cameron * the controller, place the interface device in D3 then to D0, 71801df8552aSStephen M. Cameron * this causes a secondary PCI reset which will reset the 71811df8552aSStephen M. Cameron * controller." */ 7182edd16368SStephen M. Cameron 71832662cab8SDon Brace int rc = 0; 71842662cab8SDon Brace 71851df8552aSStephen M. Cameron dev_info(&pdev->dev, "using PCI PM to reset controller\n"); 71862662cab8SDon Brace 7187edd16368SStephen M. Cameron /* enter the D3hot power management state */ 71882662cab8SDon Brace rc = pci_set_power_state(pdev, PCI_D3hot); 71892662cab8SDon Brace if (rc) 71902662cab8SDon Brace return rc; 7191edd16368SStephen M. Cameron 7192edd16368SStephen M. Cameron msleep(500); 7193edd16368SStephen M. Cameron 7194edd16368SStephen M. Cameron /* enter the D0 power management state */ 71952662cab8SDon Brace rc = pci_set_power_state(pdev, PCI_D0); 71962662cab8SDon Brace if (rc) 71972662cab8SDon Brace return rc; 7198c4853efeSMike Miller 7199c4853efeSMike Miller /* 7200c4853efeSMike Miller * The P600 requires a small delay when changing states. 7201c4853efeSMike Miller * Otherwise we may think the board did not reset and we bail. 7202c4853efeSMike Miller * This for kdump only and is particular to the P600. 7203c4853efeSMike Miller */ 7204c4853efeSMike Miller msleep(500); 72051df8552aSStephen M. Cameron } 72061df8552aSStephen M. Cameron return 0; 72071df8552aSStephen M. Cameron } 72081df8552aSStephen M. Cameron 72096f039790SGreg Kroah-Hartman static void init_driver_version(char *driver_version, int len) 7210580ada3cSStephen M. Cameron { 7211580ada3cSStephen M. Cameron memset(driver_version, 0, len); 7212f79cfec6SStephen M. Cameron strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); 7213580ada3cSStephen M. Cameron } 7214580ada3cSStephen M. Cameron 72156f039790SGreg Kroah-Hartman static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) 7216580ada3cSStephen M. Cameron { 7217580ada3cSStephen M. Cameron char *driver_version; 7218580ada3cSStephen M. Cameron int i, size = sizeof(cfgtable->driver_version); 7219580ada3cSStephen M. Cameron 7220580ada3cSStephen M. Cameron driver_version = kmalloc(size, GFP_KERNEL); 7221580ada3cSStephen M. Cameron if (!driver_version) 7222580ada3cSStephen M. Cameron return -ENOMEM; 7223580ada3cSStephen M. Cameron 7224580ada3cSStephen M. Cameron init_driver_version(driver_version, size); 7225580ada3cSStephen M. Cameron for (i = 0; i < size; i++) 7226580ada3cSStephen M. Cameron writeb(driver_version[i], &cfgtable->driver_version[i]); 7227580ada3cSStephen M. Cameron kfree(driver_version); 7228580ada3cSStephen M. Cameron return 0; 7229580ada3cSStephen M. Cameron } 7230580ada3cSStephen M. Cameron 72316f039790SGreg Kroah-Hartman static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, 72326f039790SGreg Kroah-Hartman unsigned char *driver_ver) 7233580ada3cSStephen M. Cameron { 7234580ada3cSStephen M. Cameron int i; 7235580ada3cSStephen M. Cameron 7236580ada3cSStephen M. Cameron for (i = 0; i < sizeof(cfgtable->driver_version); i++) 7237580ada3cSStephen M. Cameron driver_ver[i] = readb(&cfgtable->driver_version[i]); 7238580ada3cSStephen M. Cameron } 7239580ada3cSStephen M. Cameron 72406f039790SGreg Kroah-Hartman static int controller_reset_failed(struct CfgTable __iomem *cfgtable) 7241580ada3cSStephen M. Cameron { 7242580ada3cSStephen M. Cameron 7243580ada3cSStephen M. Cameron char *driver_ver, *old_driver_ver; 7244580ada3cSStephen M. Cameron int rc, size = sizeof(cfgtable->driver_version); 7245580ada3cSStephen M. Cameron 72466da2ec56SKees Cook old_driver_ver = kmalloc_array(2, size, GFP_KERNEL); 7247580ada3cSStephen M. Cameron if (!old_driver_ver) 7248580ada3cSStephen M. Cameron return -ENOMEM; 7249580ada3cSStephen M. Cameron driver_ver = old_driver_ver + size; 7250580ada3cSStephen M. Cameron 7251580ada3cSStephen M. Cameron /* After a reset, the 32 bytes of "driver version" in the cfgtable 7252580ada3cSStephen M. Cameron * should have been changed, otherwise we know the reset failed. 7253580ada3cSStephen M. Cameron */ 7254580ada3cSStephen M. Cameron init_driver_version(old_driver_ver, size); 7255580ada3cSStephen M. Cameron read_driver_ver_from_cfgtable(cfgtable, driver_ver); 7256580ada3cSStephen M. Cameron rc = !memcmp(driver_ver, old_driver_ver, size); 7257580ada3cSStephen M. Cameron kfree(old_driver_ver); 7258580ada3cSStephen M. Cameron return rc; 7259580ada3cSStephen M. Cameron } 72601df8552aSStephen M. Cameron /* This does a hard reset of the controller using PCI power management 72611df8552aSStephen M. Cameron * states or the using the doorbell register. 72621df8552aSStephen M. Cameron */ 72636b6c1cd7STomas Henzl static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) 72641df8552aSStephen M. Cameron { 72651df8552aSStephen M. Cameron u64 cfg_offset; 72661df8552aSStephen M. Cameron u32 cfg_base_addr; 72671df8552aSStephen M. Cameron u64 cfg_base_addr_index; 72681df8552aSStephen M. Cameron void __iomem *vaddr; 72691df8552aSStephen M. Cameron unsigned long paddr; 7270580ada3cSStephen M. Cameron u32 misc_fw_support; 7271270d05deSStephen M. Cameron int rc; 72721df8552aSStephen M. Cameron struct CfgTable __iomem *cfgtable; 7273cf0b08d0SStephen M. Cameron u32 use_doorbell; 7274270d05deSStephen M. Cameron u16 command_register; 72751df8552aSStephen M. Cameron 72761df8552aSStephen M. Cameron /* For controllers as old as the P600, this is very nearly 72771df8552aSStephen M. Cameron * the same thing as 72781df8552aSStephen M. Cameron * 72791df8552aSStephen M. Cameron * pci_save_state(pci_dev); 72801df8552aSStephen M. Cameron * pci_set_power_state(pci_dev, PCI_D3hot); 72811df8552aSStephen M. Cameron * pci_set_power_state(pci_dev, PCI_D0); 72821df8552aSStephen M. Cameron * pci_restore_state(pci_dev); 72831df8552aSStephen M. Cameron * 72841df8552aSStephen M. Cameron * For controllers newer than the P600, the pci power state 72851df8552aSStephen M. Cameron * method of resetting doesn't work so we have another way 72861df8552aSStephen M. Cameron * using the doorbell register. 72871df8552aSStephen M. Cameron */ 728818867659SStephen M. Cameron 728960f923b9SRobert Elliott if (!ctlr_is_resettable(board_id)) { 729060f923b9SRobert Elliott dev_warn(&pdev->dev, "Controller not resettable\n"); 729125c1e56aSStephen M. Cameron return -ENODEV; 729225c1e56aSStephen M. Cameron } 729346380786SStephen M. Cameron 729446380786SStephen M. Cameron /* if controller is soft- but not hard resettable... */ 729546380786SStephen M. Cameron if (!ctlr_is_hard_resettable(board_id)) 729646380786SStephen M. Cameron return -ENOTSUPP; /* try soft reset later. */ 729718867659SStephen M. Cameron 7298270d05deSStephen M. Cameron /* Save the PCI command register */ 7299270d05deSStephen M. Cameron pci_read_config_word(pdev, 4, &command_register); 7300270d05deSStephen M. Cameron pci_save_state(pdev); 73011df8552aSStephen M. Cameron 73021df8552aSStephen M. Cameron /* find the first memory BAR, so we can find the cfg table */ 73031df8552aSStephen M. Cameron rc = hpsa_pci_find_memory_BAR(pdev, &paddr); 73041df8552aSStephen M. Cameron if (rc) 73051df8552aSStephen M. Cameron return rc; 73061df8552aSStephen M. Cameron vaddr = remap_pci_mem(paddr, 0x250); 73071df8552aSStephen M. Cameron if (!vaddr) 73081df8552aSStephen M. Cameron return -ENOMEM; 73091df8552aSStephen M. Cameron 73101df8552aSStephen M. Cameron /* find cfgtable in order to check if reset via doorbell is supported */ 73111df8552aSStephen M. Cameron rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, 73121df8552aSStephen M. Cameron &cfg_base_addr_index, &cfg_offset); 73131df8552aSStephen M. Cameron if (rc) 73141df8552aSStephen M. Cameron goto unmap_vaddr; 73151df8552aSStephen M. Cameron cfgtable = remap_pci_mem(pci_resource_start(pdev, 73161df8552aSStephen M. Cameron cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); 73171df8552aSStephen M. Cameron if (!cfgtable) { 73181df8552aSStephen M. Cameron rc = -ENOMEM; 73191df8552aSStephen M. Cameron goto unmap_vaddr; 73201df8552aSStephen M. Cameron } 7321580ada3cSStephen M. Cameron rc = write_driver_ver_to_cfgtable(cfgtable); 7322580ada3cSStephen M. Cameron if (rc) 732303741d95STomas Henzl goto unmap_cfgtable; 73241df8552aSStephen M. Cameron 7325cf0b08d0SStephen M. Cameron /* If reset via doorbell register is supported, use that. 7326cf0b08d0SStephen M. Cameron * There are two such methods. Favor the newest method. 7327cf0b08d0SStephen M. Cameron */ 73281df8552aSStephen M. Cameron misc_fw_support = readl(&cfgtable->misc_fw_support); 7329cf0b08d0SStephen M. Cameron use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; 7330cf0b08d0SStephen M. Cameron if (use_doorbell) { 7331cf0b08d0SStephen M. Cameron use_doorbell = DOORBELL_CTLR_RESET2; 7332cf0b08d0SStephen M. Cameron } else { 73331df8552aSStephen M. Cameron use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; 7334cf0b08d0SStephen M. Cameron if (use_doorbell) { 7335050f7147SStephen Cameron dev_warn(&pdev->dev, 7336050f7147SStephen Cameron "Soft reset not supported. Firmware update is required.\n"); 733764670ac8SStephen M. Cameron rc = -ENOTSUPP; /* try soft reset */ 7338cf0b08d0SStephen M. Cameron goto unmap_cfgtable; 7339cf0b08d0SStephen M. Cameron } 7340cf0b08d0SStephen M. Cameron } 73411df8552aSStephen M. Cameron 73421df8552aSStephen M. Cameron rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); 73431df8552aSStephen M. Cameron if (rc) 73441df8552aSStephen M. Cameron goto unmap_cfgtable; 7345edd16368SStephen M. Cameron 7346270d05deSStephen M. Cameron pci_restore_state(pdev); 7347270d05deSStephen M. Cameron pci_write_config_word(pdev, 4, command_register); 7348edd16368SStephen M. Cameron 73491df8552aSStephen M. Cameron /* Some devices (notably the HP Smart Array 5i Controller) 73501df8552aSStephen M. Cameron need a little pause here */ 73511df8552aSStephen M. Cameron msleep(HPSA_POST_RESET_PAUSE_MSECS); 73521df8552aSStephen M. Cameron 7353fe5389c8SStephen M. Cameron rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); 7354fe5389c8SStephen M. Cameron if (rc) { 7355fe5389c8SStephen M. Cameron dev_warn(&pdev->dev, 7356050f7147SStephen Cameron "Failed waiting for board to become ready after hard reset\n"); 7357fe5389c8SStephen M. Cameron goto unmap_cfgtable; 7358fe5389c8SStephen M. Cameron } 7359fe5389c8SStephen M. Cameron 7360580ada3cSStephen M. Cameron rc = controller_reset_failed(vaddr); 7361580ada3cSStephen M. Cameron if (rc < 0) 7362580ada3cSStephen M. Cameron goto unmap_cfgtable; 7363580ada3cSStephen M. Cameron if (rc) { 736464670ac8SStephen M. Cameron dev_warn(&pdev->dev, "Unable to successfully reset " 736564670ac8SStephen M. Cameron "controller. Will try soft reset.\n"); 736664670ac8SStephen M. Cameron rc = -ENOTSUPP; 7367580ada3cSStephen M. Cameron } else { 736864670ac8SStephen M. Cameron dev_info(&pdev->dev, "board ready after hard reset.\n"); 73691df8552aSStephen M. Cameron } 73701df8552aSStephen M. Cameron 73711df8552aSStephen M. Cameron unmap_cfgtable: 73721df8552aSStephen M. Cameron iounmap(cfgtable); 73731df8552aSStephen M. Cameron 73741df8552aSStephen M. Cameron unmap_vaddr: 73751df8552aSStephen M. Cameron iounmap(vaddr); 73761df8552aSStephen M. Cameron return rc; 7377edd16368SStephen M. Cameron } 7378edd16368SStephen M. Cameron 7379edd16368SStephen M. Cameron /* 7380edd16368SStephen M. Cameron * We cannot read the structure directly, for portability we must use 7381edd16368SStephen M. Cameron * the io functions. 7382edd16368SStephen M. Cameron * This is for debug only. 7383edd16368SStephen M. Cameron */ 738442a91641SDon Brace static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) 7385edd16368SStephen M. Cameron { 738658f8665cSStephen M. Cameron #ifdef HPSA_DEBUG 7387edd16368SStephen M. Cameron int i; 7388edd16368SStephen M. Cameron char temp_name[17]; 7389edd16368SStephen M. Cameron 7390edd16368SStephen M. Cameron dev_info(dev, "Controller Configuration information\n"); 7391edd16368SStephen M. Cameron dev_info(dev, "------------------------------------\n"); 7392edd16368SStephen M. Cameron for (i = 0; i < 4; i++) 7393edd16368SStephen M. Cameron temp_name[i] = readb(&(tb->Signature[i])); 7394edd16368SStephen M. Cameron temp_name[4] = '\0'; 7395edd16368SStephen M. Cameron dev_info(dev, " Signature = %s\n", temp_name); 7396edd16368SStephen M. Cameron dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); 7397edd16368SStephen M. Cameron dev_info(dev, " Transport methods supported = 0x%x\n", 7398edd16368SStephen M. Cameron readl(&(tb->TransportSupport))); 7399edd16368SStephen M. Cameron dev_info(dev, " Transport methods active = 0x%x\n", 7400edd16368SStephen M. Cameron readl(&(tb->TransportActive))); 7401edd16368SStephen M. Cameron dev_info(dev, " Requested transport Method = 0x%x\n", 7402edd16368SStephen M. Cameron readl(&(tb->HostWrite.TransportRequest))); 7403edd16368SStephen M. Cameron dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", 7404edd16368SStephen M. Cameron readl(&(tb->HostWrite.CoalIntDelay))); 7405edd16368SStephen M. Cameron dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", 7406edd16368SStephen M. Cameron readl(&(tb->HostWrite.CoalIntCount))); 740769d6e33dSRobert Elliott dev_info(dev, " Max outstanding commands = %d\n", 7408edd16368SStephen M. Cameron readl(&(tb->CmdsOutMax))); 7409edd16368SStephen M. Cameron dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); 7410edd16368SStephen M. Cameron for (i = 0; i < 16; i++) 7411edd16368SStephen M. Cameron temp_name[i] = readb(&(tb->ServerName[i])); 7412edd16368SStephen M. Cameron temp_name[16] = '\0'; 7413edd16368SStephen M. Cameron dev_info(dev, " Server Name = %s\n", temp_name); 7414edd16368SStephen M. Cameron dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", 7415edd16368SStephen M. Cameron readl(&(tb->HeartBeat))); 7416edd16368SStephen M. Cameron #endif /* HPSA_DEBUG */ 741758f8665cSStephen M. Cameron } 7418edd16368SStephen M. Cameron 7419edd16368SStephen M. Cameron static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) 7420edd16368SStephen M. Cameron { 7421edd16368SStephen M. Cameron int i, offset, mem_type, bar_type; 7422edd16368SStephen M. Cameron 7423edd16368SStephen M. Cameron if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ 7424edd16368SStephen M. Cameron return 0; 7425edd16368SStephen M. Cameron offset = 0; 7426edd16368SStephen M. Cameron for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 7427edd16368SStephen M. Cameron bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; 7428edd16368SStephen M. Cameron if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) 7429edd16368SStephen M. Cameron offset += 4; 7430edd16368SStephen M. Cameron else { 7431edd16368SStephen M. Cameron mem_type = pci_resource_flags(pdev, i) & 7432edd16368SStephen M. Cameron PCI_BASE_ADDRESS_MEM_TYPE_MASK; 7433edd16368SStephen M. Cameron switch (mem_type) { 7434edd16368SStephen M. Cameron case PCI_BASE_ADDRESS_MEM_TYPE_32: 7435edd16368SStephen M. Cameron case PCI_BASE_ADDRESS_MEM_TYPE_1M: 7436edd16368SStephen M. Cameron offset += 4; /* 32 bit */ 7437edd16368SStephen M. Cameron break; 7438edd16368SStephen M. Cameron case PCI_BASE_ADDRESS_MEM_TYPE_64: 7439edd16368SStephen M. Cameron offset += 8; 7440edd16368SStephen M. Cameron break; 7441edd16368SStephen M. Cameron default: /* reserved in PCI 2.2 */ 7442edd16368SStephen M. Cameron dev_warn(&pdev->dev, 7443edd16368SStephen M. Cameron "base address is invalid\n"); 7444edd16368SStephen M. Cameron return -1; 7445edd16368SStephen M. Cameron break; 7446edd16368SStephen M. Cameron } 7447edd16368SStephen M. Cameron } 7448edd16368SStephen M. Cameron if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) 7449edd16368SStephen M. Cameron return i + 1; 7450edd16368SStephen M. Cameron } 7451edd16368SStephen M. Cameron return -1; 7452edd16368SStephen M. Cameron } 7453edd16368SStephen M. Cameron 7454cc64c817SRobert Elliott static void hpsa_disable_interrupt_mode(struct ctlr_info *h) 7455cc64c817SRobert Elliott { 7456bc2bb154SChristoph Hellwig pci_free_irq_vectors(h->pdev); 7457bc2bb154SChristoph Hellwig h->msix_vectors = 0; 7458cc64c817SRobert Elliott } 7459cc64c817SRobert Elliott 74608b834bffSMing Lei static void hpsa_setup_reply_map(struct ctlr_info *h) 74618b834bffSMing Lei { 74628b834bffSMing Lei const struct cpumask *mask; 74638b834bffSMing Lei unsigned int queue, cpu; 74648b834bffSMing Lei 74658b834bffSMing Lei for (queue = 0; queue < h->msix_vectors; queue++) { 74668b834bffSMing Lei mask = pci_irq_get_affinity(h->pdev, queue); 74678b834bffSMing Lei if (!mask) 74688b834bffSMing Lei goto fallback; 74698b834bffSMing Lei 74708b834bffSMing Lei for_each_cpu(cpu, mask) 74718b834bffSMing Lei h->reply_map[cpu] = queue; 74728b834bffSMing Lei } 74738b834bffSMing Lei return; 74748b834bffSMing Lei 74758b834bffSMing Lei fallback: 74768b834bffSMing Lei for_each_possible_cpu(cpu) 74778b834bffSMing Lei h->reply_map[cpu] = 0; 74788b834bffSMing Lei } 74798b834bffSMing Lei 7480edd16368SStephen M. Cameron /* If MSI/MSI-X is supported by the kernel we will try to enable it on 7481050f7147SStephen Cameron * controllers that are capable. If not, we use legacy INTx mode. 7482edd16368SStephen M. Cameron */ 7483bc2bb154SChristoph Hellwig static int hpsa_interrupt_mode(struct ctlr_info *h) 7484edd16368SStephen M. Cameron { 7485bc2bb154SChristoph Hellwig unsigned int flags = PCI_IRQ_LEGACY; 7486bc2bb154SChristoph Hellwig int ret; 7487edd16368SStephen M. Cameron 7488edd16368SStephen M. Cameron /* Some boards advertise MSI but don't really support it */ 7489bc2bb154SChristoph Hellwig switch (h->board_id) { 7490bc2bb154SChristoph Hellwig case 0x40700E11: 7491bc2bb154SChristoph Hellwig case 0x40800E11: 7492bc2bb154SChristoph Hellwig case 0x40820E11: 7493bc2bb154SChristoph Hellwig case 0x40830E11: 7494bc2bb154SChristoph Hellwig break; 7495bc2bb154SChristoph Hellwig default: 7496bc2bb154SChristoph Hellwig ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES, 7497bc2bb154SChristoph Hellwig PCI_IRQ_MSIX | PCI_IRQ_AFFINITY); 7498bc2bb154SChristoph Hellwig if (ret > 0) { 7499bc2bb154SChristoph Hellwig h->msix_vectors = ret; 7500bc2bb154SChristoph Hellwig return 0; 7501eee0f03aSHannes Reinecke } 7502bc2bb154SChristoph Hellwig 7503bc2bb154SChristoph Hellwig flags |= PCI_IRQ_MSI; 7504bc2bb154SChristoph Hellwig break; 7505edd16368SStephen M. Cameron } 7506bc2bb154SChristoph Hellwig 7507bc2bb154SChristoph Hellwig ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags); 7508bc2bb154SChristoph Hellwig if (ret < 0) 7509bc2bb154SChristoph Hellwig return ret; 7510bc2bb154SChristoph Hellwig return 0; 7511edd16368SStephen M. Cameron } 7512edd16368SStephen M. Cameron 7513135ae6edSHannes Reinecke static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 7514135ae6edSHannes Reinecke bool *legacy_board) 7515e5c880d1SStephen M. Cameron { 7516e5c880d1SStephen M. Cameron int i; 7517e5c880d1SStephen M. Cameron u32 subsystem_vendor_id, subsystem_device_id; 7518e5c880d1SStephen M. Cameron 7519e5c880d1SStephen M. Cameron subsystem_vendor_id = pdev->subsystem_vendor; 7520e5c880d1SStephen M. Cameron subsystem_device_id = pdev->subsystem_device; 7521e5c880d1SStephen M. Cameron *board_id = ((subsystem_device_id << 16) & 0xffff0000) | 7522e5c880d1SStephen M. Cameron subsystem_vendor_id; 7523e5c880d1SStephen M. Cameron 7524135ae6edSHannes Reinecke if (legacy_board) 7525135ae6edSHannes Reinecke *legacy_board = false; 7526e5c880d1SStephen M. Cameron for (i = 0; i < ARRAY_SIZE(products); i++) 7527135ae6edSHannes Reinecke if (*board_id == products[i].board_id) { 7528135ae6edSHannes Reinecke if (products[i].access != &SA5A_access && 7529135ae6edSHannes Reinecke products[i].access != &SA5B_access) 7530e5c880d1SStephen M. Cameron return i; 7531135ae6edSHannes Reinecke dev_warn(&pdev->dev, 7532135ae6edSHannes Reinecke "legacy board ID: 0x%08x\n", 7533135ae6edSHannes Reinecke *board_id); 7534135ae6edSHannes Reinecke if (legacy_board) 7535135ae6edSHannes Reinecke *legacy_board = true; 7536135ae6edSHannes Reinecke return i; 7537135ae6edSHannes Reinecke } 7538e5c880d1SStephen M. Cameron 7539c8cd71f1SHannes Reinecke dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id); 7540135ae6edSHannes Reinecke if (legacy_board) 7541135ae6edSHannes Reinecke *legacy_board = true; 7542e5c880d1SStephen M. Cameron return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ 7543e5c880d1SStephen M. Cameron } 7544e5c880d1SStephen M. Cameron 75456f039790SGreg Kroah-Hartman static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 75463a7774ceSStephen M. Cameron unsigned long *memory_bar) 75473a7774ceSStephen M. Cameron { 75483a7774ceSStephen M. Cameron int i; 75493a7774ceSStephen M. Cameron 75503a7774ceSStephen M. Cameron for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 755112d2cd47SStephen M. Cameron if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 75523a7774ceSStephen M. Cameron /* addressing mode bits already removed */ 755312d2cd47SStephen M. Cameron *memory_bar = pci_resource_start(pdev, i); 755412d2cd47SStephen M. Cameron dev_dbg(&pdev->dev, "memory BAR = %lx\n", 75553a7774ceSStephen M. Cameron *memory_bar); 75563a7774ceSStephen M. Cameron return 0; 75573a7774ceSStephen M. Cameron } 755812d2cd47SStephen M. Cameron dev_warn(&pdev->dev, "no memory BAR found\n"); 75593a7774ceSStephen M. Cameron return -ENODEV; 75603a7774ceSStephen M. Cameron } 75613a7774ceSStephen M. Cameron 75626f039790SGreg Kroah-Hartman static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 75636f039790SGreg Kroah-Hartman int wait_for_ready) 75642c4c8c8bSStephen M. Cameron { 7565fe5389c8SStephen M. Cameron int i, iterations; 75662c4c8c8bSStephen M. Cameron u32 scratchpad; 7567fe5389c8SStephen M. Cameron if (wait_for_ready) 7568fe5389c8SStephen M. Cameron iterations = HPSA_BOARD_READY_ITERATIONS; 7569fe5389c8SStephen M. Cameron else 7570fe5389c8SStephen M. Cameron iterations = HPSA_BOARD_NOT_READY_ITERATIONS; 75712c4c8c8bSStephen M. Cameron 7572fe5389c8SStephen M. Cameron for (i = 0; i < iterations; i++) { 7573fe5389c8SStephen M. Cameron scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); 7574fe5389c8SStephen M. Cameron if (wait_for_ready) { 75752c4c8c8bSStephen M. Cameron if (scratchpad == HPSA_FIRMWARE_READY) 75762c4c8c8bSStephen M. Cameron return 0; 7577fe5389c8SStephen M. Cameron } else { 7578fe5389c8SStephen M. Cameron if (scratchpad != HPSA_FIRMWARE_READY) 7579fe5389c8SStephen M. Cameron return 0; 7580fe5389c8SStephen M. Cameron } 75812c4c8c8bSStephen M. Cameron msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); 75822c4c8c8bSStephen M. Cameron } 7583fe5389c8SStephen M. Cameron dev_warn(&pdev->dev, "board not ready, timed out.\n"); 75842c4c8c8bSStephen M. Cameron return -ENODEV; 75852c4c8c8bSStephen M. Cameron } 75862c4c8c8bSStephen M. Cameron 75876f039790SGreg Kroah-Hartman static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 75886f039790SGreg Kroah-Hartman u32 *cfg_base_addr, u64 *cfg_base_addr_index, 7589a51fd47fSStephen M. Cameron u64 *cfg_offset) 7590a51fd47fSStephen M. Cameron { 7591a51fd47fSStephen M. Cameron *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); 7592a51fd47fSStephen M. Cameron *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); 7593a51fd47fSStephen M. Cameron *cfg_base_addr &= (u32) 0x0000ffff; 7594a51fd47fSStephen M. Cameron *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); 7595a51fd47fSStephen M. Cameron if (*cfg_base_addr_index == -1) { 7596a51fd47fSStephen M. Cameron dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); 7597a51fd47fSStephen M. Cameron return -ENODEV; 7598a51fd47fSStephen M. Cameron } 7599a51fd47fSStephen M. Cameron return 0; 7600a51fd47fSStephen M. Cameron } 7601a51fd47fSStephen M. Cameron 7602195f2c65SRobert Elliott static void hpsa_free_cfgtables(struct ctlr_info *h) 7603195f2c65SRobert Elliott { 7604105a3dbcSRobert Elliott if (h->transtable) { 7605195f2c65SRobert Elliott iounmap(h->transtable); 7606105a3dbcSRobert Elliott h->transtable = NULL; 7607105a3dbcSRobert Elliott } 7608105a3dbcSRobert Elliott if (h->cfgtable) { 7609195f2c65SRobert Elliott iounmap(h->cfgtable); 7610105a3dbcSRobert Elliott h->cfgtable = NULL; 7611105a3dbcSRobert Elliott } 7612195f2c65SRobert Elliott } 7613195f2c65SRobert Elliott 7614195f2c65SRobert Elliott /* Find and map CISS config table and transfer table 7615195f2c65SRobert Elliott + * several items must be unmapped (freed) later 7616195f2c65SRobert Elliott + * */ 76176f039790SGreg Kroah-Hartman static int hpsa_find_cfgtables(struct ctlr_info *h) 7618edd16368SStephen M. Cameron { 761901a02ffcSStephen M. Cameron u64 cfg_offset; 762001a02ffcSStephen M. Cameron u32 cfg_base_addr; 762101a02ffcSStephen M. Cameron u64 cfg_base_addr_index; 7622303932fdSDon Brace u32 trans_offset; 7623a51fd47fSStephen M. Cameron int rc; 762477c4495cSStephen M. Cameron 7625a51fd47fSStephen M. Cameron rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 7626a51fd47fSStephen M. Cameron &cfg_base_addr_index, &cfg_offset); 7627a51fd47fSStephen M. Cameron if (rc) 7628a51fd47fSStephen M. Cameron return rc; 762977c4495cSStephen M. Cameron h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, 7630a51fd47fSStephen M. Cameron cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); 7631cd3c81c4SRobert Elliott if (!h->cfgtable) { 7632cd3c81c4SRobert Elliott dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); 763377c4495cSStephen M. Cameron return -ENOMEM; 7634cd3c81c4SRobert Elliott } 7635580ada3cSStephen M. Cameron rc = write_driver_ver_to_cfgtable(h->cfgtable); 7636580ada3cSStephen M. Cameron if (rc) 7637580ada3cSStephen M. Cameron return rc; 763877c4495cSStephen M. Cameron /* Find performant mode table. */ 7639a51fd47fSStephen M. Cameron trans_offset = readl(&h->cfgtable->TransMethodOffset); 764077c4495cSStephen M. Cameron h->transtable = remap_pci_mem(pci_resource_start(h->pdev, 764177c4495cSStephen M. Cameron cfg_base_addr_index)+cfg_offset+trans_offset, 764277c4495cSStephen M. Cameron sizeof(*h->transtable)); 7643195f2c65SRobert Elliott if (!h->transtable) { 7644195f2c65SRobert Elliott dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); 7645195f2c65SRobert Elliott hpsa_free_cfgtables(h); 764677c4495cSStephen M. Cameron return -ENOMEM; 7647195f2c65SRobert Elliott } 764877c4495cSStephen M. Cameron return 0; 764977c4495cSStephen M. Cameron } 765077c4495cSStephen M. Cameron 76516f039790SGreg Kroah-Hartman static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) 7652cba3d38bSStephen M. Cameron { 765341ce4c35SStephen Cameron #define MIN_MAX_COMMANDS 16 765441ce4c35SStephen Cameron BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); 765541ce4c35SStephen Cameron 765641ce4c35SStephen Cameron h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); 765772ceeaecSStephen M. Cameron 765872ceeaecSStephen M. Cameron /* Limit commands in memory limited kdump scenario. */ 765972ceeaecSStephen M. Cameron if (reset_devices && h->max_commands > 32) 766072ceeaecSStephen M. Cameron h->max_commands = 32; 766172ceeaecSStephen M. Cameron 766241ce4c35SStephen Cameron if (h->max_commands < MIN_MAX_COMMANDS) { 766341ce4c35SStephen Cameron dev_warn(&h->pdev->dev, 766441ce4c35SStephen Cameron "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", 766541ce4c35SStephen Cameron h->max_commands, 766641ce4c35SStephen Cameron MIN_MAX_COMMANDS); 766741ce4c35SStephen Cameron h->max_commands = MIN_MAX_COMMANDS; 7668cba3d38bSStephen M. Cameron } 7669cba3d38bSStephen M. Cameron } 7670cba3d38bSStephen M. Cameron 7671c7ee65b3SWebb Scales /* If the controller reports that the total max sg entries is greater than 512, 7672c7ee65b3SWebb Scales * then we know that chained SG blocks work. (Original smart arrays did not 7673c7ee65b3SWebb Scales * support chained SG blocks and would return zero for max sg entries.) 7674c7ee65b3SWebb Scales */ 7675c7ee65b3SWebb Scales static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) 7676c7ee65b3SWebb Scales { 7677c7ee65b3SWebb Scales return h->maxsgentries > 512; 7678c7ee65b3SWebb Scales } 7679c7ee65b3SWebb Scales 7680b93d7536SStephen M. Cameron /* Interrogate the hardware for some limits: 7681b93d7536SStephen M. Cameron * max commands, max SG elements without chaining, and with chaining, 7682b93d7536SStephen M. Cameron * SG chain block size, etc. 7683b93d7536SStephen M. Cameron */ 76846f039790SGreg Kroah-Hartman static void hpsa_find_board_params(struct ctlr_info *h) 7685b93d7536SStephen M. Cameron { 7686cba3d38bSStephen M. Cameron hpsa_get_max_perf_mode_cmds(h); 768745fcb86eSStephen Cameron h->nr_cmds = h->max_commands; 7688b93d7536SStephen M. Cameron h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); 7689283b4a9bSStephen M. Cameron h->fw_support = readl(&(h->cfgtable->misc_fw_support)); 7690c7ee65b3SWebb Scales if (hpsa_supports_chained_sg_blocks(h)) { 7691c7ee65b3SWebb Scales /* Limit in-command s/g elements to 32 save dma'able memory. */ 7692b93d7536SStephen M. Cameron h->max_cmd_sg_entries = 32; 76931a63ea6fSWebb Scales h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; 7694b93d7536SStephen M. Cameron h->maxsgentries--; /* save one for chain pointer */ 7695b93d7536SStephen M. Cameron } else { 7696c7ee65b3SWebb Scales /* 7697c7ee65b3SWebb Scales * Original smart arrays supported at most 31 s/g entries 7698c7ee65b3SWebb Scales * embedded inline in the command (trying to use more 7699c7ee65b3SWebb Scales * would lock up the controller) 7700c7ee65b3SWebb Scales */ 7701c7ee65b3SWebb Scales h->max_cmd_sg_entries = 31; 77021a63ea6fSWebb Scales h->maxsgentries = 31; /* default to traditional values */ 7703c7ee65b3SWebb Scales h->chainsize = 0; 7704b93d7536SStephen M. Cameron } 770575167d2cSStephen M. Cameron 770675167d2cSStephen M. Cameron /* Find out what task management functions are supported and cache */ 770775167d2cSStephen M. Cameron h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); 77080e7a7fceSScott Teel if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) 77090e7a7fceSScott Teel dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); 77100e7a7fceSScott Teel if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) 77110e7a7fceSScott Teel dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); 77128be986ccSStephen Cameron if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) 77138be986ccSStephen Cameron dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); 7714b93d7536SStephen M. Cameron } 7715b93d7536SStephen M. Cameron 771676c46e49SStephen M. Cameron static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) 771776c46e49SStephen M. Cameron { 77180fc9fd40SAkinobu Mita if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { 7719050f7147SStephen Cameron dev_err(&h->pdev->dev, "not a valid CISS config table\n"); 772076c46e49SStephen M. Cameron return false; 772176c46e49SStephen M. Cameron } 772276c46e49SStephen M. Cameron return true; 772376c46e49SStephen M. Cameron } 772476c46e49SStephen M. Cameron 772597a5e98cSStephen M. Cameron static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) 7726f7c39101SStephen M. Cameron { 772797a5e98cSStephen M. Cameron u32 driver_support; 7728f7c39101SStephen M. Cameron 772997a5e98cSStephen M. Cameron driver_support = readl(&(h->cfgtable->driver_support)); 77300b9e7b74SArnd Bergmann /* Need to enable prefetch in the SCSI core for 6400 in x86 */ 77310b9e7b74SArnd Bergmann #ifdef CONFIG_X86 773297a5e98cSStephen M. Cameron driver_support |= ENABLE_SCSI_PREFETCH; 7733f7c39101SStephen M. Cameron #endif 773428e13446SStephen M. Cameron driver_support |= ENABLE_UNIT_ATTN; 773528e13446SStephen M. Cameron writel(driver_support, &(h->cfgtable->driver_support)); 7736f7c39101SStephen M. Cameron } 7737f7c39101SStephen M. Cameron 77383d0eab67SStephen M. Cameron /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result 77393d0eab67SStephen M. Cameron * in a prefetch beyond physical memory. 77403d0eab67SStephen M. Cameron */ 77413d0eab67SStephen M. Cameron static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) 77423d0eab67SStephen M. Cameron { 77433d0eab67SStephen M. Cameron u32 dma_prefetch; 77443d0eab67SStephen M. Cameron 77453d0eab67SStephen M. Cameron if (h->board_id != 0x3225103C) 77463d0eab67SStephen M. Cameron return; 77473d0eab67SStephen M. Cameron dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); 77483d0eab67SStephen M. Cameron dma_prefetch |= 0x8000; 77493d0eab67SStephen M. Cameron writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); 77503d0eab67SStephen M. Cameron } 77513d0eab67SStephen M. Cameron 7752c706a795SRobert Elliott static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) 775376438d08SStephen M. Cameron { 775476438d08SStephen M. Cameron int i; 775576438d08SStephen M. Cameron u32 doorbell_value; 775676438d08SStephen M. Cameron unsigned long flags; 775776438d08SStephen M. Cameron /* wait until the clear_event_notify bit 6 is cleared by controller. */ 7758007e7aa9SRobert Elliott for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { 775976438d08SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 776076438d08SStephen M. Cameron doorbell_value = readl(h->vaddr + SA5_DOORBELL); 776176438d08SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 776276438d08SStephen M. Cameron if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) 7763c706a795SRobert Elliott goto done; 776476438d08SStephen M. Cameron /* delay and try again */ 7765007e7aa9SRobert Elliott msleep(CLEAR_EVENT_WAIT_INTERVAL); 776676438d08SStephen M. Cameron } 7767c706a795SRobert Elliott return -ENODEV; 7768c706a795SRobert Elliott done: 7769c706a795SRobert Elliott return 0; 777076438d08SStephen M. Cameron } 777176438d08SStephen M. Cameron 7772c706a795SRobert Elliott static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) 7773eb6b2ae9SStephen M. Cameron { 7774eb6b2ae9SStephen M. Cameron int i; 77756eaf46fdSStephen M. Cameron u32 doorbell_value; 77766eaf46fdSStephen M. Cameron unsigned long flags; 7777eb6b2ae9SStephen M. Cameron 7778eb6b2ae9SStephen M. Cameron /* under certain very rare conditions, this can take awhile. 7779eb6b2ae9SStephen M. Cameron * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right 7780eb6b2ae9SStephen M. Cameron * as we enter this code.) 7781eb6b2ae9SStephen M. Cameron */ 7782007e7aa9SRobert Elliott for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { 778325163bd5SWebb Scales if (h->remove_in_progress) 778425163bd5SWebb Scales goto done; 77856eaf46fdSStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 77866eaf46fdSStephen M. Cameron doorbell_value = readl(h->vaddr + SA5_DOORBELL); 77876eaf46fdSStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 7788382be668SDan Carpenter if (!(doorbell_value & CFGTBL_ChangeReq)) 7789c706a795SRobert Elliott goto done; 7790eb6b2ae9SStephen M. Cameron /* delay and try again */ 7791007e7aa9SRobert Elliott msleep(MODE_CHANGE_WAIT_INTERVAL); 7792eb6b2ae9SStephen M. Cameron } 7793c706a795SRobert Elliott return -ENODEV; 7794c706a795SRobert Elliott done: 7795c706a795SRobert Elliott return 0; 77963f4336f3SStephen M. Cameron } 77973f4336f3SStephen M. Cameron 7798c706a795SRobert Elliott /* return -ENODEV or other reason on error, 0 on success */ 77996f039790SGreg Kroah-Hartman static int hpsa_enter_simple_mode(struct ctlr_info *h) 78003f4336f3SStephen M. Cameron { 78013f4336f3SStephen M. Cameron u32 trans_support; 78023f4336f3SStephen M. Cameron 78033f4336f3SStephen M. Cameron trans_support = readl(&(h->cfgtable->TransportSupport)); 78043f4336f3SStephen M. Cameron if (!(trans_support & SIMPLE_MODE)) 78053f4336f3SStephen M. Cameron return -ENOTSUPP; 78063f4336f3SStephen M. Cameron 78073f4336f3SStephen M. Cameron h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); 7808283b4a9bSStephen M. Cameron 78093f4336f3SStephen M. Cameron /* Update the field, and then ring the doorbell */ 78103f4336f3SStephen M. Cameron writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); 7811b9af4937SStephen M. Cameron writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 78123f4336f3SStephen M. Cameron writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 7813c706a795SRobert Elliott if (hpsa_wait_for_mode_change_ack(h)) 7814c706a795SRobert Elliott goto error; 7815eb6b2ae9SStephen M. Cameron print_cfg_table(&h->pdev->dev, h->cfgtable); 7816283b4a9bSStephen M. Cameron if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) 7817283b4a9bSStephen M. Cameron goto error; 7818960a30e7SStephen M. Cameron h->transMethod = CFGTBL_Trans_Simple; 7819eb6b2ae9SStephen M. Cameron return 0; 7820283b4a9bSStephen M. Cameron error: 7821050f7147SStephen Cameron dev_err(&h->pdev->dev, "failed to enter simple mode\n"); 7822283b4a9bSStephen M. Cameron return -ENODEV; 7823eb6b2ae9SStephen M. Cameron } 7824eb6b2ae9SStephen M. Cameron 7825195f2c65SRobert Elliott /* free items allocated or mapped by hpsa_pci_init */ 7826195f2c65SRobert Elliott static void hpsa_free_pci_init(struct ctlr_info *h) 7827195f2c65SRobert Elliott { 7828195f2c65SRobert Elliott hpsa_free_cfgtables(h); /* pci_init 4 */ 7829195f2c65SRobert Elliott iounmap(h->vaddr); /* pci_init 3 */ 7830105a3dbcSRobert Elliott h->vaddr = NULL; 7831195f2c65SRobert Elliott hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 7832943a7021SRobert Elliott /* 7833943a7021SRobert Elliott * call pci_disable_device before pci_release_regions per 7834bff9e34cSMauro Carvalho Chehab * Documentation/driver-api/pci/pci.rst 7835943a7021SRobert Elliott */ 7836195f2c65SRobert Elliott pci_disable_device(h->pdev); /* pci_init 1 */ 7837943a7021SRobert Elliott pci_release_regions(h->pdev); /* pci_init 2 */ 7838195f2c65SRobert Elliott } 7839195f2c65SRobert Elliott 7840195f2c65SRobert Elliott /* several items must be freed later */ 78416f039790SGreg Kroah-Hartman static int hpsa_pci_init(struct ctlr_info *h) 784277c4495cSStephen M. Cameron { 7843eb6b2ae9SStephen M. Cameron int prod_index, err; 7844135ae6edSHannes Reinecke bool legacy_board; 7845edd16368SStephen M. Cameron 7846135ae6edSHannes Reinecke prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board); 7847e5c880d1SStephen M. Cameron if (prod_index < 0) 784860f923b9SRobert Elliott return prod_index; 7849e5c880d1SStephen M. Cameron h->product_name = products[prod_index].product_name; 7850e5c880d1SStephen M. Cameron h->access = *(products[prod_index].access); 7851135ae6edSHannes Reinecke h->legacy_board = legacy_board; 7852e5a44df8SMatthew Garrett pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | 7853e5a44df8SMatthew Garrett PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); 7854e5a44df8SMatthew Garrett 785555c06c71SStephen M. Cameron err = pci_enable_device(h->pdev); 7856edd16368SStephen M. Cameron if (err) { 7857195f2c65SRobert Elliott dev_err(&h->pdev->dev, "failed to enable PCI device\n"); 7858943a7021SRobert Elliott pci_disable_device(h->pdev); 7859edd16368SStephen M. Cameron return err; 7860edd16368SStephen M. Cameron } 7861edd16368SStephen M. Cameron 7862f79cfec6SStephen M. Cameron err = pci_request_regions(h->pdev, HPSA); 7863edd16368SStephen M. Cameron if (err) { 786455c06c71SStephen M. Cameron dev_err(&h->pdev->dev, 7865195f2c65SRobert Elliott "failed to obtain PCI resources\n"); 7866943a7021SRobert Elliott pci_disable_device(h->pdev); 7867943a7021SRobert Elliott return err; 7868edd16368SStephen M. Cameron } 78694fa604e1SRobert Elliott 78704fa604e1SRobert Elliott pci_set_master(h->pdev); 78714fa604e1SRobert Elliott 7872bc2bb154SChristoph Hellwig err = hpsa_interrupt_mode(h); 7873bc2bb154SChristoph Hellwig if (err) 7874bc2bb154SChristoph Hellwig goto clean1; 78758b834bffSMing Lei 78768b834bffSMing Lei /* setup mapping between CPU and reply queue */ 78778b834bffSMing Lei hpsa_setup_reply_map(h); 78788b834bffSMing Lei 787912d2cd47SStephen M. Cameron err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); 78803a7774ceSStephen M. Cameron if (err) 7881195f2c65SRobert Elliott goto clean2; /* intmode+region, pci */ 7882edd16368SStephen M. Cameron h->vaddr = remap_pci_mem(h->paddr, 0x250); 7883204892e9SStephen M. Cameron if (!h->vaddr) { 7884195f2c65SRobert Elliott dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); 7885204892e9SStephen M. Cameron err = -ENOMEM; 7886195f2c65SRobert Elliott goto clean2; /* intmode+region, pci */ 7887204892e9SStephen M. Cameron } 7888fe5389c8SStephen M. Cameron err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 78892c4c8c8bSStephen M. Cameron if (err) 7890195f2c65SRobert Elliott goto clean3; /* vaddr, intmode+region, pci */ 789177c4495cSStephen M. Cameron err = hpsa_find_cfgtables(h); 789277c4495cSStephen M. Cameron if (err) 7893195f2c65SRobert Elliott goto clean3; /* vaddr, intmode+region, pci */ 7894b93d7536SStephen M. Cameron hpsa_find_board_params(h); 7895edd16368SStephen M. Cameron 789676c46e49SStephen M. Cameron if (!hpsa_CISS_signature_present(h)) { 7897edd16368SStephen M. Cameron err = -ENODEV; 7898195f2c65SRobert Elliott goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7899edd16368SStephen M. Cameron } 790097a5e98cSStephen M. Cameron hpsa_set_driver_support_bits(h); 79013d0eab67SStephen M. Cameron hpsa_p600_dma_prefetch_quirk(h); 7902eb6b2ae9SStephen M. Cameron err = hpsa_enter_simple_mode(h); 7903eb6b2ae9SStephen M. Cameron if (err) 7904195f2c65SRobert Elliott goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7905edd16368SStephen M. Cameron return 0; 7906edd16368SStephen M. Cameron 7907195f2c65SRobert Elliott clean4: /* cfgtables, vaddr, intmode+region, pci */ 7908195f2c65SRobert Elliott hpsa_free_cfgtables(h); 7909195f2c65SRobert Elliott clean3: /* vaddr, intmode+region, pci */ 7910204892e9SStephen M. Cameron iounmap(h->vaddr); 7911105a3dbcSRobert Elliott h->vaddr = NULL; 7912195f2c65SRobert Elliott clean2: /* intmode+region, pci */ 7913195f2c65SRobert Elliott hpsa_disable_interrupt_mode(h); 7914bc2bb154SChristoph Hellwig clean1: 7915943a7021SRobert Elliott /* 7916943a7021SRobert Elliott * call pci_disable_device before pci_release_regions per 7917bff9e34cSMauro Carvalho Chehab * Documentation/driver-api/pci/pci.rst 7918943a7021SRobert Elliott */ 7919195f2c65SRobert Elliott pci_disable_device(h->pdev); 7920943a7021SRobert Elliott pci_release_regions(h->pdev); 7921edd16368SStephen M. Cameron return err; 7922edd16368SStephen M. Cameron } 7923edd16368SStephen M. Cameron 79246f039790SGreg Kroah-Hartman static void hpsa_hba_inquiry(struct ctlr_info *h) 7925339b2b14SStephen M. Cameron { 7926339b2b14SStephen M. Cameron int rc; 7927339b2b14SStephen M. Cameron 7928339b2b14SStephen M. Cameron #define HBA_INQUIRY_BYTE_COUNT 64 7929339b2b14SStephen M. Cameron h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); 7930339b2b14SStephen M. Cameron if (!h->hba_inquiry_data) 7931339b2b14SStephen M. Cameron return; 7932339b2b14SStephen M. Cameron rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, 7933339b2b14SStephen M. Cameron h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); 7934339b2b14SStephen M. Cameron if (rc != 0) { 7935339b2b14SStephen M. Cameron kfree(h->hba_inquiry_data); 7936339b2b14SStephen M. Cameron h->hba_inquiry_data = NULL; 7937339b2b14SStephen M. Cameron } 7938339b2b14SStephen M. Cameron } 7939339b2b14SStephen M. Cameron 79406b6c1cd7STomas Henzl static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) 7941edd16368SStephen M. Cameron { 79421df8552aSStephen M. Cameron int rc, i; 79433b747298STomas Henzl void __iomem *vaddr; 7944edd16368SStephen M. Cameron 79454c2a8c40SStephen M. Cameron if (!reset_devices) 79464c2a8c40SStephen M. Cameron return 0; 79474c2a8c40SStephen M. Cameron 7948132aa220STomas Henzl /* kdump kernel is loading, we don't know in which state is 7949132aa220STomas Henzl * the pci interface. The dev->enable_cnt is equal zero 7950132aa220STomas Henzl * so we call enable+disable, wait a while and switch it on. 7951132aa220STomas Henzl */ 7952132aa220STomas Henzl rc = pci_enable_device(pdev); 7953132aa220STomas Henzl if (rc) { 7954132aa220STomas Henzl dev_warn(&pdev->dev, "Failed to enable PCI device\n"); 7955132aa220STomas Henzl return -ENODEV; 7956132aa220STomas Henzl } 7957132aa220STomas Henzl pci_disable_device(pdev); 7958132aa220STomas Henzl msleep(260); /* a randomly chosen number */ 7959132aa220STomas Henzl rc = pci_enable_device(pdev); 7960132aa220STomas Henzl if (rc) { 7961132aa220STomas Henzl dev_warn(&pdev->dev, "failed to enable device.\n"); 7962132aa220STomas Henzl return -ENODEV; 7963132aa220STomas Henzl } 79644fa604e1SRobert Elliott 7965859c75abSTomas Henzl pci_set_master(pdev); 79664fa604e1SRobert Elliott 79673b747298STomas Henzl vaddr = pci_ioremap_bar(pdev, 0); 79683b747298STomas Henzl if (vaddr == NULL) { 79693b747298STomas Henzl rc = -ENOMEM; 79703b747298STomas Henzl goto out_disable; 79713b747298STomas Henzl } 79723b747298STomas Henzl writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); 79733b747298STomas Henzl iounmap(vaddr); 79743b747298STomas Henzl 79751df8552aSStephen M. Cameron /* Reset the controller with a PCI power-cycle or via doorbell */ 79766b6c1cd7STomas Henzl rc = hpsa_kdump_hard_reset_controller(pdev, board_id); 7977edd16368SStephen M. Cameron 79781df8552aSStephen M. Cameron /* -ENOTSUPP here means we cannot reset the controller 79791df8552aSStephen M. Cameron * but it's already (and still) up and running in 798018867659SStephen M. Cameron * "performant mode". Or, it might be 640x, which can't reset 798118867659SStephen M. Cameron * due to concerns about shared bbwc between 6402/6404 pair. 79821df8552aSStephen M. Cameron */ 7983adf1b3a3SRobert Elliott if (rc) 7984132aa220STomas Henzl goto out_disable; 7985edd16368SStephen M. Cameron 7986edd16368SStephen M. Cameron /* Now try to get the controller to respond to a no-op */ 79871ba66c9cSRobert Elliott dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); 7988edd16368SStephen M. Cameron for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { 7989edd16368SStephen M. Cameron if (hpsa_noop(pdev) == 0) 7990edd16368SStephen M. Cameron break; 7991edd16368SStephen M. Cameron else 7992edd16368SStephen M. Cameron dev_warn(&pdev->dev, "no-op failed%s\n", 7993edd16368SStephen M. Cameron (i < 11 ? "; re-trying" : "")); 7994edd16368SStephen M. Cameron } 7995132aa220STomas Henzl 7996132aa220STomas Henzl out_disable: 7997132aa220STomas Henzl 7998132aa220STomas Henzl pci_disable_device(pdev); 7999132aa220STomas Henzl return rc; 8000edd16368SStephen M. Cameron } 8001edd16368SStephen M. Cameron 80021fb7c98aSRobert Elliott static void hpsa_free_cmd_pool(struct ctlr_info *h) 80031fb7c98aSRobert Elliott { 80041fb7c98aSRobert Elliott kfree(h->cmd_pool_bits); 8005105a3dbcSRobert Elliott h->cmd_pool_bits = NULL; 8006105a3dbcSRobert Elliott if (h->cmd_pool) { 80078bc8f47eSChristoph Hellwig dma_free_coherent(&h->pdev->dev, 80081fb7c98aSRobert Elliott h->nr_cmds * sizeof(struct CommandList), 80091fb7c98aSRobert Elliott h->cmd_pool, 80101fb7c98aSRobert Elliott h->cmd_pool_dhandle); 8011105a3dbcSRobert Elliott h->cmd_pool = NULL; 8012105a3dbcSRobert Elliott h->cmd_pool_dhandle = 0; 8013105a3dbcSRobert Elliott } 8014105a3dbcSRobert Elliott if (h->errinfo_pool) { 80158bc8f47eSChristoph Hellwig dma_free_coherent(&h->pdev->dev, 80161fb7c98aSRobert Elliott h->nr_cmds * sizeof(struct ErrorInfo), 80171fb7c98aSRobert Elliott h->errinfo_pool, 80181fb7c98aSRobert Elliott h->errinfo_pool_dhandle); 8019105a3dbcSRobert Elliott h->errinfo_pool = NULL; 8020105a3dbcSRobert Elliott h->errinfo_pool_dhandle = 0; 8021105a3dbcSRobert Elliott } 80221fb7c98aSRobert Elliott } 80231fb7c98aSRobert Elliott 8024d37ffbe4SRobert Elliott static int hpsa_alloc_cmd_pool(struct ctlr_info *h) 80252e9d1b36SStephen M. Cameron { 80266396bb22SKees Cook h->cmd_pool_bits = kcalloc(DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG), 80276396bb22SKees Cook sizeof(unsigned long), 80286396bb22SKees Cook GFP_KERNEL); 80298bc8f47eSChristoph Hellwig h->cmd_pool = dma_alloc_coherent(&h->pdev->dev, 80302e9d1b36SStephen M. Cameron h->nr_cmds * sizeof(*h->cmd_pool), 80318bc8f47eSChristoph Hellwig &h->cmd_pool_dhandle, GFP_KERNEL); 80328bc8f47eSChristoph Hellwig h->errinfo_pool = dma_alloc_coherent(&h->pdev->dev, 80332e9d1b36SStephen M. Cameron h->nr_cmds * sizeof(*h->errinfo_pool), 80348bc8f47eSChristoph Hellwig &h->errinfo_pool_dhandle, GFP_KERNEL); 80352e9d1b36SStephen M. Cameron if ((h->cmd_pool_bits == NULL) 80362e9d1b36SStephen M. Cameron || (h->cmd_pool == NULL) 80372e9d1b36SStephen M. Cameron || (h->errinfo_pool == NULL)) { 80382e9d1b36SStephen M. Cameron dev_err(&h->pdev->dev, "out of memory in %s", __func__); 80392c143342SRobert Elliott goto clean_up; 80402e9d1b36SStephen M. Cameron } 8041360c73bdSStephen Cameron hpsa_preinitialize_commands(h); 80422e9d1b36SStephen M. Cameron return 0; 80432c143342SRobert Elliott clean_up: 80442c143342SRobert Elliott hpsa_free_cmd_pool(h); 80452c143342SRobert Elliott return -ENOMEM; 80462e9d1b36SStephen M. Cameron } 80472e9d1b36SStephen M. Cameron 8048ec501a18SRobert Elliott /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ 8049ec501a18SRobert Elliott static void hpsa_free_irqs(struct ctlr_info *h) 8050ec501a18SRobert Elliott { 8051ec501a18SRobert Elliott int i; 8052a68fdb3aSDon Brace int irq_vector = 0; 8053a68fdb3aSDon Brace 8054a68fdb3aSDon Brace if (hpsa_simple_mode) 8055a68fdb3aSDon Brace irq_vector = h->intr_mode; 8056ec501a18SRobert Elliott 8057bc2bb154SChristoph Hellwig if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) { 8058ec501a18SRobert Elliott /* Single reply queue, only one irq to free */ 8059a68fdb3aSDon Brace free_irq(pci_irq_vector(h->pdev, irq_vector), 8060a68fdb3aSDon Brace &h->q[h->intr_mode]); 8061bc2bb154SChristoph Hellwig h->q[h->intr_mode] = 0; 8062ec501a18SRobert Elliott return; 8063ec501a18SRobert Elliott } 8064ec501a18SRobert Elliott 8065bc2bb154SChristoph Hellwig for (i = 0; i < h->msix_vectors; i++) { 8066bc2bb154SChristoph Hellwig free_irq(pci_irq_vector(h->pdev, i), &h->q[i]); 8067105a3dbcSRobert Elliott h->q[i] = 0; 8068ec501a18SRobert Elliott } 8069a4e17fc1SRobert Elliott for (; i < MAX_REPLY_QUEUES; i++) 8070a4e17fc1SRobert Elliott h->q[i] = 0; 8071ec501a18SRobert Elliott } 8072ec501a18SRobert Elliott 80739ee61794SRobert Elliott /* returns 0 on success; cleans up and returns -Enn on error */ 80749ee61794SRobert Elliott static int hpsa_request_irqs(struct ctlr_info *h, 80750ae01a32SStephen M. Cameron irqreturn_t (*msixhandler)(int, void *), 80760ae01a32SStephen M. Cameron irqreturn_t (*intxhandler)(int, void *)) 80770ae01a32SStephen M. Cameron { 8078254f796bSMatt Gates int rc, i; 8079a68fdb3aSDon Brace int irq_vector = 0; 8080a68fdb3aSDon Brace 8081a68fdb3aSDon Brace if (hpsa_simple_mode) 8082a68fdb3aSDon Brace irq_vector = h->intr_mode; 80830ae01a32SStephen M. Cameron 8084254f796bSMatt Gates /* 8085254f796bSMatt Gates * initialize h->q[x] = x so that interrupt handlers know which 8086254f796bSMatt Gates * queue to process. 8087254f796bSMatt Gates */ 8088254f796bSMatt Gates for (i = 0; i < MAX_REPLY_QUEUES; i++) 8089254f796bSMatt Gates h->q[i] = (u8) i; 8090254f796bSMatt Gates 8091bc2bb154SChristoph Hellwig if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) { 8092254f796bSMatt Gates /* If performant mode and MSI-X, use multiple reply queues */ 8093bc2bb154SChristoph Hellwig for (i = 0; i < h->msix_vectors; i++) { 80948b47004aSRobert Elliott sprintf(h->intrname[i], "%s-msix%d", h->devname, i); 8095bc2bb154SChristoph Hellwig rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler, 80968b47004aSRobert Elliott 0, h->intrname[i], 8097254f796bSMatt Gates &h->q[i]); 8098a4e17fc1SRobert Elliott if (rc) { 8099a4e17fc1SRobert Elliott int j; 8100a4e17fc1SRobert Elliott 8101a4e17fc1SRobert Elliott dev_err(&h->pdev->dev, 8102a4e17fc1SRobert Elliott "failed to get irq %d for %s\n", 8103bc2bb154SChristoph Hellwig pci_irq_vector(h->pdev, i), h->devname); 8104a4e17fc1SRobert Elliott for (j = 0; j < i; j++) { 8105bc2bb154SChristoph Hellwig free_irq(pci_irq_vector(h->pdev, j), &h->q[j]); 8106a4e17fc1SRobert Elliott h->q[j] = 0; 8107a4e17fc1SRobert Elliott } 8108a4e17fc1SRobert Elliott for (; j < MAX_REPLY_QUEUES; j++) 8109a4e17fc1SRobert Elliott h->q[j] = 0; 8110a4e17fc1SRobert Elliott return rc; 8111a4e17fc1SRobert Elliott } 8112a4e17fc1SRobert Elliott } 8113254f796bSMatt Gates } else { 8114254f796bSMatt Gates /* Use single reply pool */ 8115bc2bb154SChristoph Hellwig if (h->msix_vectors > 0 || h->pdev->msi_enabled) { 8116bc2bb154SChristoph Hellwig sprintf(h->intrname[0], "%s-msi%s", h->devname, 8117bc2bb154SChristoph Hellwig h->msix_vectors ? "x" : ""); 8118a68fdb3aSDon Brace rc = request_irq(pci_irq_vector(h->pdev, irq_vector), 81198b47004aSRobert Elliott msixhandler, 0, 8120bc2bb154SChristoph Hellwig h->intrname[0], 8121254f796bSMatt Gates &h->q[h->intr_mode]); 8122254f796bSMatt Gates } else { 81238b47004aSRobert Elliott sprintf(h->intrname[h->intr_mode], 81248b47004aSRobert Elliott "%s-intx", h->devname); 8125a68fdb3aSDon Brace rc = request_irq(pci_irq_vector(h->pdev, irq_vector), 81268b47004aSRobert Elliott intxhandler, IRQF_SHARED, 8127bc2bb154SChristoph Hellwig h->intrname[0], 8128254f796bSMatt Gates &h->q[h->intr_mode]); 8129254f796bSMatt Gates } 8130254f796bSMatt Gates } 81310ae01a32SStephen M. Cameron if (rc) { 8132195f2c65SRobert Elliott dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", 8133a68fdb3aSDon Brace pci_irq_vector(h->pdev, irq_vector), h->devname); 8134195f2c65SRobert Elliott hpsa_free_irqs(h); 81350ae01a32SStephen M. Cameron return -ENODEV; 81360ae01a32SStephen M. Cameron } 81370ae01a32SStephen M. Cameron return 0; 81380ae01a32SStephen M. Cameron } 81390ae01a32SStephen M. Cameron 81406f039790SGreg Kroah-Hartman static int hpsa_kdump_soft_reset(struct ctlr_info *h) 814164670ac8SStephen M. Cameron { 814239c53f55SRobert Elliott int rc; 8143c5dfd106SDon Brace hpsa_send_host_reset(h, HPSA_RESET_TYPE_CONTROLLER); 814464670ac8SStephen M. Cameron 814564670ac8SStephen M. Cameron dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); 814639c53f55SRobert Elliott rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); 814739c53f55SRobert Elliott if (rc) { 814864670ac8SStephen M. Cameron dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); 814939c53f55SRobert Elliott return rc; 815064670ac8SStephen M. Cameron } 815164670ac8SStephen M. Cameron 815264670ac8SStephen M. Cameron dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); 815339c53f55SRobert Elliott rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 815439c53f55SRobert Elliott if (rc) { 815564670ac8SStephen M. Cameron dev_warn(&h->pdev->dev, "Board failed to become ready " 815664670ac8SStephen M. Cameron "after soft reset.\n"); 815739c53f55SRobert Elliott return rc; 815864670ac8SStephen M. Cameron } 815964670ac8SStephen M. Cameron 816064670ac8SStephen M. Cameron return 0; 816164670ac8SStephen M. Cameron } 816264670ac8SStephen M. Cameron 8163072b0518SStephen M. Cameron static void hpsa_free_reply_queues(struct ctlr_info *h) 8164072b0518SStephen M. Cameron { 8165072b0518SStephen M. Cameron int i; 8166072b0518SStephen M. Cameron 8167072b0518SStephen M. Cameron for (i = 0; i < h->nreply_queues; i++) { 8168072b0518SStephen M. Cameron if (!h->reply_queue[i].head) 8169072b0518SStephen M. Cameron continue; 81708bc8f47eSChristoph Hellwig dma_free_coherent(&h->pdev->dev, 81711fb7c98aSRobert Elliott h->reply_queue_size, 81721fb7c98aSRobert Elliott h->reply_queue[i].head, 81731fb7c98aSRobert Elliott h->reply_queue[i].busaddr); 8174072b0518SStephen M. Cameron h->reply_queue[i].head = NULL; 8175072b0518SStephen M. Cameron h->reply_queue[i].busaddr = 0; 8176072b0518SStephen M. Cameron } 8177105a3dbcSRobert Elliott h->reply_queue_size = 0; 8178072b0518SStephen M. Cameron } 8179072b0518SStephen M. Cameron 81800097f0f4SStephen M. Cameron static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) 81810097f0f4SStephen M. Cameron { 8182105a3dbcSRobert Elliott hpsa_free_performant_mode(h); /* init_one 7 */ 8183105a3dbcSRobert Elliott hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 8184105a3dbcSRobert Elliott hpsa_free_cmd_pool(h); /* init_one 5 */ 8185105a3dbcSRobert Elliott hpsa_free_irqs(h); /* init_one 4 */ 81862946e82bSRobert Elliott scsi_host_put(h->scsi_host); /* init_one 3 */ 81872946e82bSRobert Elliott h->scsi_host = NULL; /* init_one 3 */ 81882946e82bSRobert Elliott hpsa_free_pci_init(h); /* init_one 2_5 */ 81899ecd953aSRobert Elliott free_percpu(h->lockup_detected); /* init_one 2 */ 81909ecd953aSRobert Elliott h->lockup_detected = NULL; /* init_one 2 */ 81919ecd953aSRobert Elliott if (h->resubmit_wq) { 81929ecd953aSRobert Elliott destroy_workqueue(h->resubmit_wq); /* init_one 1 */ 81939ecd953aSRobert Elliott h->resubmit_wq = NULL; 81949ecd953aSRobert Elliott } 81959ecd953aSRobert Elliott if (h->rescan_ctlr_wq) { 81969ecd953aSRobert Elliott destroy_workqueue(h->rescan_ctlr_wq); 81979ecd953aSRobert Elliott h->rescan_ctlr_wq = NULL; 81989ecd953aSRobert Elliott } 819901192088SDon Brace if (h->monitor_ctlr_wq) { 820001192088SDon Brace destroy_workqueue(h->monitor_ctlr_wq); 820101192088SDon Brace h->monitor_ctlr_wq = NULL; 820201192088SDon Brace } 820301192088SDon Brace 8204105a3dbcSRobert Elliott kfree(h); /* init_one 1 */ 820564670ac8SStephen M. Cameron } 820664670ac8SStephen M. Cameron 8207a0c12413SStephen M. Cameron /* Called when controller lockup detected. */ 8208f2405db8SDon Brace static void fail_all_outstanding_cmds(struct ctlr_info *h) 8209a0c12413SStephen M. Cameron { 8210281a7fd0SWebb Scales int i, refcount; 8211281a7fd0SWebb Scales struct CommandList *c; 821225163bd5SWebb Scales int failcount = 0; 8213a0c12413SStephen M. Cameron 8214080ef1ccSDon Brace flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ 8215f2405db8SDon Brace for (i = 0; i < h->nr_cmds; i++) { 8216f2405db8SDon Brace c = h->cmd_pool + i; 8217281a7fd0SWebb Scales refcount = atomic_inc_return(&c->refcount); 8218281a7fd0SWebb Scales if (refcount > 1) { 821925163bd5SWebb Scales c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 82205a3d16f5SStephen M. Cameron finish_cmd(c); 8221433b5f4dSStephen Cameron atomic_dec(&h->commands_outstanding); 822225163bd5SWebb Scales failcount++; 8223a0c12413SStephen M. Cameron } 8224281a7fd0SWebb Scales cmd_free(h, c); 8225281a7fd0SWebb Scales } 822625163bd5SWebb Scales dev_warn(&h->pdev->dev, 822725163bd5SWebb Scales "failed %d commands in fail_all\n", failcount); 8228a0c12413SStephen M. Cameron } 8229a0c12413SStephen M. Cameron 8230094963daSStephen M. Cameron static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) 8231094963daSStephen M. Cameron { 8232c8ed0010SRusty Russell int cpu; 8233094963daSStephen M. Cameron 8234c8ed0010SRusty Russell for_each_online_cpu(cpu) { 8235094963daSStephen M. Cameron u32 *lockup_detected; 8236094963daSStephen M. Cameron lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 8237094963daSStephen M. Cameron *lockup_detected = value; 8238094963daSStephen M. Cameron } 8239094963daSStephen M. Cameron wmb(); /* be sure the per-cpu variables are out to memory */ 8240094963daSStephen M. Cameron } 8241094963daSStephen M. Cameron 8242a0c12413SStephen M. Cameron static void controller_lockup_detected(struct ctlr_info *h) 8243a0c12413SStephen M. Cameron { 8244a0c12413SStephen M. Cameron unsigned long flags; 8245094963daSStephen M. Cameron u32 lockup_detected; 8246a0c12413SStephen M. Cameron 8247a0c12413SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_OFF); 8248a0c12413SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 8249094963daSStephen M. Cameron lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 8250094963daSStephen M. Cameron if (!lockup_detected) { 8251094963daSStephen M. Cameron /* no heartbeat, but controller gave us a zero. */ 8252094963daSStephen M. Cameron dev_warn(&h->pdev->dev, 825325163bd5SWebb Scales "lockup detected after %d but scratchpad register is zero\n", 825425163bd5SWebb Scales h->heartbeat_sample_interval / HZ); 8255094963daSStephen M. Cameron lockup_detected = 0xffffffff; 8256094963daSStephen M. Cameron } 8257094963daSStephen M. Cameron set_lockup_detected_for_all_cpus(h, lockup_detected); 8258a0c12413SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 825925163bd5SWebb Scales dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", 826025163bd5SWebb Scales lockup_detected, h->heartbeat_sample_interval / HZ); 8261b9b08cadSDon Brace if (lockup_detected == 0xffff0000) { 8262b9b08cadSDon Brace dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n"); 8263b9b08cadSDon Brace writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL); 8264b9b08cadSDon Brace } 8265a0c12413SStephen M. Cameron pci_disable_device(h->pdev); 8266f2405db8SDon Brace fail_all_outstanding_cmds(h); 8267a0c12413SStephen M. Cameron } 8268a0c12413SStephen M. Cameron 826925163bd5SWebb Scales static int detect_controller_lockup(struct ctlr_info *h) 8270a0c12413SStephen M. Cameron { 8271a0c12413SStephen M. Cameron u64 now; 8272a0c12413SStephen M. Cameron u32 heartbeat; 8273a0c12413SStephen M. Cameron unsigned long flags; 8274a0c12413SStephen M. Cameron 8275a0c12413SStephen M. Cameron now = get_jiffies_64(); 8276a0c12413SStephen M. Cameron /* If we've received an interrupt recently, we're ok. */ 8277a0c12413SStephen M. Cameron if (time_after64(h->last_intr_timestamp + 8278e85c5974SStephen M. Cameron (h->heartbeat_sample_interval), now)) 827925163bd5SWebb Scales return false; 8280a0c12413SStephen M. Cameron 8281a0c12413SStephen M. Cameron /* 8282a0c12413SStephen M. Cameron * If we've already checked the heartbeat recently, we're ok. 8283a0c12413SStephen M. Cameron * This could happen if someone sends us a signal. We 8284a0c12413SStephen M. Cameron * otherwise don't care about signals in this thread. 8285a0c12413SStephen M. Cameron */ 8286a0c12413SStephen M. Cameron if (time_after64(h->last_heartbeat_timestamp + 8287e85c5974SStephen M. Cameron (h->heartbeat_sample_interval), now)) 828825163bd5SWebb Scales return false; 8289a0c12413SStephen M. Cameron 8290a0c12413SStephen M. Cameron /* If heartbeat has not changed since we last looked, we're not ok. */ 8291a0c12413SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 8292a0c12413SStephen M. Cameron heartbeat = readl(&h->cfgtable->HeartBeat); 8293a0c12413SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 8294a0c12413SStephen M. Cameron if (h->last_heartbeat == heartbeat) { 8295a0c12413SStephen M. Cameron controller_lockup_detected(h); 829625163bd5SWebb Scales return true; 8297a0c12413SStephen M. Cameron } 8298a0c12413SStephen M. Cameron 8299a0c12413SStephen M. Cameron /* We're ok. */ 8300a0c12413SStephen M. Cameron h->last_heartbeat = heartbeat; 8301a0c12413SStephen M. Cameron h->last_heartbeat_timestamp = now; 830225163bd5SWebb Scales return false; 8303a0c12413SStephen M. Cameron } 8304a0c12413SStephen M. Cameron 8305b2582a65SDon Brace /* 8306b2582a65SDon Brace * Set ioaccel status for all ioaccel volumes. 8307b2582a65SDon Brace * 8308b2582a65SDon Brace * Called from monitor controller worker (hpsa_event_monitor_worker) 8309b2582a65SDon Brace * 83103e16e83aSDon Brace * A Volume (or Volumes that comprise an Array set) may be undergoing a 8311b2582a65SDon Brace * transformation, so we will be turning off ioaccel for all volumes that 8312b2582a65SDon Brace * make up the Array. 8313b2582a65SDon Brace */ 8314b2582a65SDon Brace static void hpsa_set_ioaccel_status(struct ctlr_info *h) 8315b2582a65SDon Brace { 8316b2582a65SDon Brace int rc; 8317b2582a65SDon Brace int i; 8318b2582a65SDon Brace u8 ioaccel_status; 8319b2582a65SDon Brace unsigned char *buf; 8320b2582a65SDon Brace struct hpsa_scsi_dev_t *device; 8321b2582a65SDon Brace 8322b2582a65SDon Brace if (!h) 8323b2582a65SDon Brace return; 8324b2582a65SDon Brace 8325b2582a65SDon Brace buf = kmalloc(64, GFP_KERNEL); 8326b2582a65SDon Brace if (!buf) 8327b2582a65SDon Brace return; 8328b2582a65SDon Brace 8329b2582a65SDon Brace /* 8330b2582a65SDon Brace * Run through current device list used during I/O requests. 8331b2582a65SDon Brace */ 8332b2582a65SDon Brace for (i = 0; i < h->ndevices; i++) { 83333e16e83aSDon Brace int offload_to_be_enabled = 0; 83343e16e83aSDon Brace int offload_config = 0; 83353e16e83aSDon Brace 8336b2582a65SDon Brace device = h->dev[i]; 8337b2582a65SDon Brace 8338b2582a65SDon Brace if (!device) 8339b2582a65SDon Brace continue; 8340b2582a65SDon Brace if (!hpsa_vpd_page_supported(h, device->scsi3addr, 8341b2582a65SDon Brace HPSA_VPD_LV_IOACCEL_STATUS)) 8342b2582a65SDon Brace continue; 8343b2582a65SDon Brace 8344b2582a65SDon Brace memset(buf, 0, 64); 8345b2582a65SDon Brace 8346b2582a65SDon Brace rc = hpsa_scsi_do_inquiry(h, device->scsi3addr, 8347b2582a65SDon Brace VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, 8348b2582a65SDon Brace buf, 64); 8349b2582a65SDon Brace if (rc != 0) 8350b2582a65SDon Brace continue; 8351b2582a65SDon Brace 8352b2582a65SDon Brace ioaccel_status = buf[IOACCEL_STATUS_BYTE]; 83533e16e83aSDon Brace 83543e16e83aSDon Brace /* 83553e16e83aSDon Brace * Check if offload is still configured on 83563e16e83aSDon Brace */ 83573e16e83aSDon Brace offload_config = 8358b2582a65SDon Brace !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); 83593e16e83aSDon Brace /* 83603e16e83aSDon Brace * If offload is configured on, check to see if ioaccel 83613e16e83aSDon Brace * needs to be enabled. 83623e16e83aSDon Brace */ 83633e16e83aSDon Brace if (offload_config) 83643e16e83aSDon Brace offload_to_be_enabled = 8365b2582a65SDon Brace !!(ioaccel_status & OFFLOAD_ENABLED_BIT); 8366b2582a65SDon Brace 8367b2582a65SDon Brace /* 83683e16e83aSDon Brace * If ioaccel is to be re-enabled, re-enable later during the 83693e16e83aSDon Brace * scan operation so the driver can get a fresh raidmap 83703e16e83aSDon Brace * before turning ioaccel back on. 83713e16e83aSDon Brace */ 83723e16e83aSDon Brace if (offload_to_be_enabled) 83733e16e83aSDon Brace continue; 83743e16e83aSDon Brace 83753e16e83aSDon Brace /* 8376b2582a65SDon Brace * Immediately turn off ioaccel for any volume the 8377b2582a65SDon Brace * controller tells us to. Some of the reasons could be: 8378b2582a65SDon Brace * transformation - change to the LVs of an Array. 8379b2582a65SDon Brace * degraded volume - component failure 8380b2582a65SDon Brace */ 83813e16e83aSDon Brace hpsa_turn_off_ioaccel_for_device(device); 8382b2582a65SDon Brace } 8383b2582a65SDon Brace 8384b2582a65SDon Brace kfree(buf); 8385b2582a65SDon Brace } 8386b2582a65SDon Brace 83879846590eSStephen M. Cameron static void hpsa_ack_ctlr_events(struct ctlr_info *h) 838876438d08SStephen M. Cameron { 838976438d08SStephen M. Cameron char *event_type; 839076438d08SStephen M. Cameron 8391e4aa3e6aSStephen Cameron if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 8392e4aa3e6aSStephen Cameron return; 8393e4aa3e6aSStephen Cameron 839476438d08SStephen M. Cameron /* Ask the controller to clear the events we're handling. */ 83951f7cee8cSStephen M. Cameron if ((h->transMethod & (CFGTBL_Trans_io_accel1 83961f7cee8cSStephen M. Cameron | CFGTBL_Trans_io_accel2)) && 839776438d08SStephen M. Cameron (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || 839876438d08SStephen M. Cameron h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { 839976438d08SStephen M. Cameron 840076438d08SStephen M. Cameron if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) 840176438d08SStephen M. Cameron event_type = "state change"; 840276438d08SStephen M. Cameron if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) 840376438d08SStephen M. Cameron event_type = "configuration change"; 840476438d08SStephen M. Cameron /* Stop sending new RAID offload reqs via the IO accelerator */ 840576438d08SStephen M. Cameron scsi_block_requests(h->scsi_host); 8406b2582a65SDon Brace hpsa_set_ioaccel_status(h); 840723100dd9SStephen M. Cameron hpsa_drain_accel_commands(h); 840876438d08SStephen M. Cameron /* Set 'accelerator path config change' bit */ 840976438d08SStephen M. Cameron dev_warn(&h->pdev->dev, 841076438d08SStephen M. Cameron "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", 841176438d08SStephen M. Cameron h->events, event_type); 841276438d08SStephen M. Cameron writel(h->events, &(h->cfgtable->clear_event_notify)); 841376438d08SStephen M. Cameron /* Set the "clear event notify field update" bit 6 */ 841476438d08SStephen M. Cameron writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 841576438d08SStephen M. Cameron /* Wait until ctlr clears 'clear event notify field', bit 6 */ 841676438d08SStephen M. Cameron hpsa_wait_for_clear_event_notify_ack(h); 841776438d08SStephen M. Cameron scsi_unblock_requests(h->scsi_host); 841876438d08SStephen M. Cameron } else { 841976438d08SStephen M. Cameron /* Acknowledge controller notification events. */ 842076438d08SStephen M. Cameron writel(h->events, &(h->cfgtable->clear_event_notify)); 842176438d08SStephen M. Cameron writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 842276438d08SStephen M. Cameron hpsa_wait_for_clear_event_notify_ack(h); 842376438d08SStephen M. Cameron } 84249846590eSStephen M. Cameron return; 842576438d08SStephen M. Cameron } 842676438d08SStephen M. Cameron 842776438d08SStephen M. Cameron /* Check a register on the controller to see if there are configuration 842876438d08SStephen M. Cameron * changes (added/changed/removed logical drives, etc.) which mean that 8429e863d68eSScott Teel * we should rescan the controller for devices. 8430e863d68eSScott Teel * Also check flag for driver-initiated rescan. 843176438d08SStephen M. Cameron */ 84329846590eSStephen M. Cameron static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) 843376438d08SStephen M. Cameron { 8434853633e8SDon Brace if (h->drv_req_rescan) { 8435853633e8SDon Brace h->drv_req_rescan = 0; 8436853633e8SDon Brace return 1; 8437853633e8SDon Brace } 8438853633e8SDon Brace 843976438d08SStephen M. Cameron if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 84409846590eSStephen M. Cameron return 0; 844176438d08SStephen M. Cameron 844276438d08SStephen M. Cameron h->events = readl(&(h->cfgtable->event_notify)); 84439846590eSStephen M. Cameron return h->events & RESCAN_REQUIRED_EVENT_BITS; 84449846590eSStephen M. Cameron } 844576438d08SStephen M. Cameron 844676438d08SStephen M. Cameron /* 84479846590eSStephen M. Cameron * Check if any of the offline devices have become ready 844876438d08SStephen M. Cameron */ 84499846590eSStephen M. Cameron static int hpsa_offline_devices_ready(struct ctlr_info *h) 84509846590eSStephen M. Cameron { 84519846590eSStephen M. Cameron unsigned long flags; 84529846590eSStephen M. Cameron struct offline_device_entry *d; 84539846590eSStephen M. Cameron struct list_head *this, *tmp; 84549846590eSStephen M. Cameron 84559846590eSStephen M. Cameron spin_lock_irqsave(&h->offline_device_lock, flags); 84569846590eSStephen M. Cameron list_for_each_safe(this, tmp, &h->offline_device_list) { 84579846590eSStephen M. Cameron d = list_entry(this, struct offline_device_entry, 84589846590eSStephen M. Cameron offline_list); 84599846590eSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 8460d1fea47cSStephen M. Cameron if (!hpsa_volume_offline(h, d->scsi3addr)) { 8461d1fea47cSStephen M. Cameron spin_lock_irqsave(&h->offline_device_lock, flags); 8462d1fea47cSStephen M. Cameron list_del(&d->offline_list); 8463d1fea47cSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 84649846590eSStephen M. Cameron return 1; 8465d1fea47cSStephen M. Cameron } 84669846590eSStephen M. Cameron spin_lock_irqsave(&h->offline_device_lock, flags); 846776438d08SStephen M. Cameron } 84689846590eSStephen M. Cameron spin_unlock_irqrestore(&h->offline_device_lock, flags); 84699846590eSStephen M. Cameron return 0; 84709846590eSStephen M. Cameron } 84719846590eSStephen M. Cameron 847234592254SScott Teel static int hpsa_luns_changed(struct ctlr_info *h) 847334592254SScott Teel { 847434592254SScott Teel int rc = 1; /* assume there are changes */ 847534592254SScott Teel struct ReportLUNdata *logdev = NULL; 847634592254SScott Teel 847734592254SScott Teel /* if we can't find out if lun data has changed, 847834592254SScott Teel * assume that it has. 847934592254SScott Teel */ 848034592254SScott Teel 848134592254SScott Teel if (!h->lastlogicals) 84827e8a9486SAmit Kushwaha return rc; 848334592254SScott Teel 848434592254SScott Teel logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); 84857e8a9486SAmit Kushwaha if (!logdev) 84867e8a9486SAmit Kushwaha return rc; 84877e8a9486SAmit Kushwaha 848834592254SScott Teel if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { 848934592254SScott Teel dev_warn(&h->pdev->dev, 849034592254SScott Teel "report luns failed, can't track lun changes.\n"); 849134592254SScott Teel goto out; 849234592254SScott Teel } 849334592254SScott Teel if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { 849434592254SScott Teel dev_info(&h->pdev->dev, 849534592254SScott Teel "Lun changes detected.\n"); 849634592254SScott Teel memcpy(h->lastlogicals, logdev, sizeof(*logdev)); 849734592254SScott Teel goto out; 849834592254SScott Teel } else 849934592254SScott Teel rc = 0; /* no changes detected. */ 850034592254SScott Teel out: 850134592254SScott Teel kfree(logdev); 850234592254SScott Teel return rc; 850334592254SScott Teel } 850434592254SScott Teel 85053d38f00cSScott Teel static void hpsa_perform_rescan(struct ctlr_info *h) 8506a0c12413SStephen M. Cameron { 85073d38f00cSScott Teel struct Scsi_Host *sh = NULL; 8508a0c12413SStephen M. Cameron unsigned long flags; 85099846590eSStephen M. Cameron 8510bfd7546cSDon Brace /* 8511bfd7546cSDon Brace * Do the scan after the reset 8512bfd7546cSDon Brace */ 8513c59d04f3SDon Brace spin_lock_irqsave(&h->reset_lock, flags); 8514bfd7546cSDon Brace if (h->reset_in_progress) { 8515bfd7546cSDon Brace h->drv_req_rescan = 1; 8516c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 8517bfd7546cSDon Brace return; 8518bfd7546cSDon Brace } 8519c59d04f3SDon Brace spin_unlock_irqrestore(&h->reset_lock, flags); 8520bfd7546cSDon Brace 852134592254SScott Teel sh = scsi_host_get(h->scsi_host); 852234592254SScott Teel if (sh != NULL) { 852334592254SScott Teel hpsa_scan_start(sh); 852434592254SScott Teel scsi_host_put(sh); 85253d38f00cSScott Teel h->drv_req_rescan = 0; 852634592254SScott Teel } 852734592254SScott Teel } 85283d38f00cSScott Teel 85293d38f00cSScott Teel /* 85303d38f00cSScott Teel * watch for controller events 85313d38f00cSScott Teel */ 85323d38f00cSScott Teel static void hpsa_event_monitor_worker(struct work_struct *work) 85333d38f00cSScott Teel { 85343d38f00cSScott Teel struct ctlr_info *h = container_of(to_delayed_work(work), 85353d38f00cSScott Teel struct ctlr_info, event_monitor_work); 85363d38f00cSScott Teel unsigned long flags; 85373d38f00cSScott Teel 85383d38f00cSScott Teel spin_lock_irqsave(&h->lock, flags); 85393d38f00cSScott Teel if (h->remove_in_progress) { 85403d38f00cSScott Teel spin_unlock_irqrestore(&h->lock, flags); 85413d38f00cSScott Teel return; 85423d38f00cSScott Teel } 85433d38f00cSScott Teel spin_unlock_irqrestore(&h->lock, flags); 85443d38f00cSScott Teel 85453d38f00cSScott Teel if (hpsa_ctlr_needs_rescan(h)) { 85463d38f00cSScott Teel hpsa_ack_ctlr_events(h); 85473d38f00cSScott Teel hpsa_perform_rescan(h); 85483d38f00cSScott Teel } 85493d38f00cSScott Teel 85503d38f00cSScott Teel spin_lock_irqsave(&h->lock, flags); 85513d38f00cSScott Teel if (!h->remove_in_progress) 855201192088SDon Brace queue_delayed_work(h->monitor_ctlr_wq, &h->event_monitor_work, 85533d38f00cSScott Teel HPSA_EVENT_MONITOR_INTERVAL); 85543d38f00cSScott Teel spin_unlock_irqrestore(&h->lock, flags); 85553d38f00cSScott Teel } 85563d38f00cSScott Teel 85573d38f00cSScott Teel static void hpsa_rescan_ctlr_worker(struct work_struct *work) 85583d38f00cSScott Teel { 85593d38f00cSScott Teel unsigned long flags; 85603d38f00cSScott Teel struct ctlr_info *h = container_of(to_delayed_work(work), 85613d38f00cSScott Teel struct ctlr_info, rescan_ctlr_work); 85623d38f00cSScott Teel 85633d38f00cSScott Teel spin_lock_irqsave(&h->lock, flags); 85643d38f00cSScott Teel if (h->remove_in_progress) { 85653d38f00cSScott Teel spin_unlock_irqrestore(&h->lock, flags); 85663d38f00cSScott Teel return; 85673d38f00cSScott Teel } 85683d38f00cSScott Teel spin_unlock_irqrestore(&h->lock, flags); 85693d38f00cSScott Teel 85703d38f00cSScott Teel if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) { 85713d38f00cSScott Teel hpsa_perform_rescan(h); 85723d38f00cSScott Teel } else if (h->discovery_polling) { 85733d38f00cSScott Teel if (hpsa_luns_changed(h)) { 85743d38f00cSScott Teel dev_info(&h->pdev->dev, 85753d38f00cSScott Teel "driver discovery polling rescan.\n"); 85763d38f00cSScott Teel hpsa_perform_rescan(h); 85773d38f00cSScott Teel } 85789846590eSStephen M. Cameron } 85796636e7f4SDon Brace spin_lock_irqsave(&h->lock, flags); 85806636e7f4SDon Brace if (!h->remove_in_progress) 85816636e7f4SDon Brace queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 85826636e7f4SDon Brace h->heartbeat_sample_interval); 85836636e7f4SDon Brace spin_unlock_irqrestore(&h->lock, flags); 85846636e7f4SDon Brace } 85856636e7f4SDon Brace 85866636e7f4SDon Brace static void hpsa_monitor_ctlr_worker(struct work_struct *work) 85876636e7f4SDon Brace { 85886636e7f4SDon Brace unsigned long flags; 85896636e7f4SDon Brace struct ctlr_info *h = container_of(to_delayed_work(work), 85906636e7f4SDon Brace struct ctlr_info, monitor_ctlr_work); 85916636e7f4SDon Brace 85926636e7f4SDon Brace detect_controller_lockup(h); 85936636e7f4SDon Brace if (lockup_detected(h)) 85946636e7f4SDon Brace return; 85959846590eSStephen M. Cameron 85968a98db73SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 85976636e7f4SDon Brace if (!h->remove_in_progress) 859801192088SDon Brace queue_delayed_work(h->monitor_ctlr_wq, &h->monitor_ctlr_work, 85998a98db73SStephen M. Cameron h->heartbeat_sample_interval); 86008a98db73SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 8601a0c12413SStephen M. Cameron } 8602a0c12413SStephen M. Cameron 86036636e7f4SDon Brace static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, 86046636e7f4SDon Brace char *name) 86056636e7f4SDon Brace { 86066636e7f4SDon Brace struct workqueue_struct *wq = NULL; 86076636e7f4SDon Brace 8608397ea9cbSDon Brace wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); 86096636e7f4SDon Brace if (!wq) 86106636e7f4SDon Brace dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); 86116636e7f4SDon Brace 86126636e7f4SDon Brace return wq; 86136636e7f4SDon Brace } 86146636e7f4SDon Brace 86158b834bffSMing Lei static void hpda_free_ctlr_info(struct ctlr_info *h) 86168b834bffSMing Lei { 86178b834bffSMing Lei kfree(h->reply_map); 86188b834bffSMing Lei kfree(h); 86198b834bffSMing Lei } 86208b834bffSMing Lei 86218b834bffSMing Lei static struct ctlr_info *hpda_alloc_ctlr_info(void) 86228b834bffSMing Lei { 86238b834bffSMing Lei struct ctlr_info *h; 86248b834bffSMing Lei 86258b834bffSMing Lei h = kzalloc(sizeof(*h), GFP_KERNEL); 86268b834bffSMing Lei if (!h) 86278b834bffSMing Lei return NULL; 86288b834bffSMing Lei 86296396bb22SKees Cook h->reply_map = kcalloc(nr_cpu_ids, sizeof(*h->reply_map), GFP_KERNEL); 86308b834bffSMing Lei if (!h->reply_map) { 86318b834bffSMing Lei kfree(h); 86328b834bffSMing Lei return NULL; 86338b834bffSMing Lei } 86348b834bffSMing Lei return h; 86358b834bffSMing Lei } 86368b834bffSMing Lei 86376f039790SGreg Kroah-Hartman static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 86384c2a8c40SStephen M. Cameron { 86394c2a8c40SStephen M. Cameron int dac, rc; 86404c2a8c40SStephen M. Cameron struct ctlr_info *h; 864164670ac8SStephen M. Cameron int try_soft_reset = 0; 864264670ac8SStephen M. Cameron unsigned long flags; 86436b6c1cd7STomas Henzl u32 board_id; 86444c2a8c40SStephen M. Cameron 86454c2a8c40SStephen M. Cameron if (number_of_controllers == 0) 86464c2a8c40SStephen M. Cameron printk(KERN_INFO DRIVER_NAME "\n"); 86474c2a8c40SStephen M. Cameron 8648135ae6edSHannes Reinecke rc = hpsa_lookup_board_id(pdev, &board_id, NULL); 86496b6c1cd7STomas Henzl if (rc < 0) { 86506b6c1cd7STomas Henzl dev_warn(&pdev->dev, "Board ID not found\n"); 86516b6c1cd7STomas Henzl return rc; 86526b6c1cd7STomas Henzl } 86536b6c1cd7STomas Henzl 86546b6c1cd7STomas Henzl rc = hpsa_init_reset_devices(pdev, board_id); 865564670ac8SStephen M. Cameron if (rc) { 865664670ac8SStephen M. Cameron if (rc != -ENOTSUPP) 86574c2a8c40SStephen M. Cameron return rc; 865864670ac8SStephen M. Cameron /* If the reset fails in a particular way (it has no way to do 865964670ac8SStephen M. Cameron * a proper hard reset, so returns -ENOTSUPP) we can try to do 866064670ac8SStephen M. Cameron * a soft reset once we get the controller configured up to the 866164670ac8SStephen M. Cameron * point that it can accept a command. 866264670ac8SStephen M. Cameron */ 866364670ac8SStephen M. Cameron try_soft_reset = 1; 866464670ac8SStephen M. Cameron rc = 0; 866564670ac8SStephen M. Cameron } 866664670ac8SStephen M. Cameron 866764670ac8SStephen M. Cameron reinit_after_soft_reset: 86684c2a8c40SStephen M. Cameron 8669303932fdSDon Brace /* Command structures must be aligned on a 32-byte boundary because 8670303932fdSDon Brace * the 5 lower bits of the address are used by the hardware. and by 8671303932fdSDon Brace * the driver. See comments in hpsa.h for more info. 8672303932fdSDon Brace */ 8673303932fdSDon Brace BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); 86748b834bffSMing Lei h = hpda_alloc_ctlr_info(); 8675105a3dbcSRobert Elliott if (!h) { 8676105a3dbcSRobert Elliott dev_err(&pdev->dev, "Failed to allocate controller head\n"); 8677ecd9aad4SStephen M. Cameron return -ENOMEM; 8678105a3dbcSRobert Elliott } 8679edd16368SStephen M. Cameron 868055c06c71SStephen M. Cameron h->pdev = pdev; 8681105a3dbcSRobert Elliott 8682a9a3a273SStephen M. Cameron h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; 86839846590eSStephen M. Cameron INIT_LIST_HEAD(&h->offline_device_list); 86846eaf46fdSStephen M. Cameron spin_lock_init(&h->lock); 86859846590eSStephen M. Cameron spin_lock_init(&h->offline_device_lock); 86866eaf46fdSStephen M. Cameron spin_lock_init(&h->scan_lock); 8687c59d04f3SDon Brace spin_lock_init(&h->reset_lock); 868834f0c627SDon Brace atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); 8689094963daSStephen M. Cameron 8690094963daSStephen M. Cameron /* Allocate and clear per-cpu variable lockup_detected */ 8691094963daSStephen M. Cameron h->lockup_detected = alloc_percpu(u32); 86922a5ac326SStephen M. Cameron if (!h->lockup_detected) { 8693105a3dbcSRobert Elliott dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); 86942a5ac326SStephen M. Cameron rc = -ENOMEM; 86952efa5929SRobert Elliott goto clean1; /* aer/h */ 86962a5ac326SStephen M. Cameron } 8697094963daSStephen M. Cameron set_lockup_detected_for_all_cpus(h, 0); 8698094963daSStephen M. Cameron 869955c06c71SStephen M. Cameron rc = hpsa_pci_init(h); 8700105a3dbcSRobert Elliott if (rc) 87012946e82bSRobert Elliott goto clean2; /* lu, aer/h */ 8702edd16368SStephen M. Cameron 87032946e82bSRobert Elliott /* relies on h-> settings made by hpsa_pci_init, including 87042946e82bSRobert Elliott * interrupt_mode h->intr */ 87052946e82bSRobert Elliott rc = hpsa_scsi_host_alloc(h); 87062946e82bSRobert Elliott if (rc) 87072946e82bSRobert Elliott goto clean2_5; /* pci, lu, aer/h */ 87082946e82bSRobert Elliott 87092946e82bSRobert Elliott sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); 8710edd16368SStephen M. Cameron h->ctlr = number_of_controllers; 8711edd16368SStephen M. Cameron number_of_controllers++; 8712edd16368SStephen M. Cameron 8713edd16368SStephen M. Cameron /* configure PCI DMA stuff */ 87148bc8f47eSChristoph Hellwig rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 8715ecd9aad4SStephen M. Cameron if (rc == 0) { 8716edd16368SStephen M. Cameron dac = 1; 8717ecd9aad4SStephen M. Cameron } else { 87188bc8f47eSChristoph Hellwig rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 8719ecd9aad4SStephen M. Cameron if (rc == 0) { 8720edd16368SStephen M. Cameron dac = 0; 8721ecd9aad4SStephen M. Cameron } else { 8722edd16368SStephen M. Cameron dev_err(&pdev->dev, "no suitable DMA available\n"); 87232946e82bSRobert Elliott goto clean3; /* shost, pci, lu, aer/h */ 8724edd16368SStephen M. Cameron } 8725ecd9aad4SStephen M. Cameron } 8726edd16368SStephen M. Cameron 8727edd16368SStephen M. Cameron /* make sure the board interrupts are off */ 8728edd16368SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_OFF); 872910f66018SStephen M. Cameron 8730105a3dbcSRobert Elliott rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); 8731105a3dbcSRobert Elliott if (rc) 87322946e82bSRobert Elliott goto clean3; /* shost, pci, lu, aer/h */ 8733d37ffbe4SRobert Elliott rc = hpsa_alloc_cmd_pool(h); 87348947fd10SRobert Elliott if (rc) 87352946e82bSRobert Elliott goto clean4; /* irq, shost, pci, lu, aer/h */ 8736105a3dbcSRobert Elliott rc = hpsa_alloc_sg_chain_blocks(h); 8737105a3dbcSRobert Elliott if (rc) 87382946e82bSRobert Elliott goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ 8739a08a8471SStephen M. Cameron init_waitqueue_head(&h->scan_wait_queue); 8740d604f533SWebb Scales init_waitqueue_head(&h->event_sync_wait_queue); 8741d604f533SWebb Scales mutex_init(&h->reset_mutex); 8742a08a8471SStephen M. Cameron h->scan_finished = 1; /* no scan currently in progress */ 874387b9e6aaSDon Brace h->scan_waiting = 0; 8744edd16368SStephen M. Cameron 8745edd16368SStephen M. Cameron pci_set_drvdata(pdev, h); 87469a41338eSStephen M. Cameron h->ndevices = 0; 87472946e82bSRobert Elliott 87489a41338eSStephen M. Cameron spin_lock_init(&h->devlock); 8749105a3dbcSRobert Elliott rc = hpsa_put_ctlr_into_performant_mode(h); 8750105a3dbcSRobert Elliott if (rc) 87512946e82bSRobert Elliott goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ 87522946e82bSRobert Elliott 87532efa5929SRobert Elliott /* create the resubmit workqueue */ 87542efa5929SRobert Elliott h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); 87552efa5929SRobert Elliott if (!h->rescan_ctlr_wq) { 87562efa5929SRobert Elliott rc = -ENOMEM; 87572efa5929SRobert Elliott goto clean7; 87582efa5929SRobert Elliott } 87592efa5929SRobert Elliott 87602efa5929SRobert Elliott h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); 87612efa5929SRobert Elliott if (!h->resubmit_wq) { 87622efa5929SRobert Elliott rc = -ENOMEM; 87632efa5929SRobert Elliott goto clean7; /* aer/h */ 87642efa5929SRobert Elliott } 876564670ac8SStephen M. Cameron 876601192088SDon Brace h->monitor_ctlr_wq = hpsa_create_controller_wq(h, "monitor"); 876701192088SDon Brace if (!h->monitor_ctlr_wq) { 876801192088SDon Brace rc = -ENOMEM; 876901192088SDon Brace goto clean7; 877001192088SDon Brace } 877101192088SDon Brace 8772105a3dbcSRobert Elliott /* 8773105a3dbcSRobert Elliott * At this point, the controller is ready to take commands. 877464670ac8SStephen M. Cameron * Now, if reset_devices and the hard reset didn't work, try 877564670ac8SStephen M. Cameron * the soft reset and see if that works. 877664670ac8SStephen M. Cameron */ 877764670ac8SStephen M. Cameron if (try_soft_reset) { 877864670ac8SStephen M. Cameron 877964670ac8SStephen M. Cameron /* This is kind of gross. We may or may not get a completion 878064670ac8SStephen M. Cameron * from the soft reset command, and if we do, then the value 878164670ac8SStephen M. Cameron * from the fifo may or may not be valid. So, we wait 10 secs 878264670ac8SStephen M. Cameron * after the reset throwing away any completions we get during 878364670ac8SStephen M. Cameron * that time. Unregister the interrupt handler and register 878464670ac8SStephen M. Cameron * fake ones to scoop up any residual completions. 878564670ac8SStephen M. Cameron */ 878664670ac8SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 878764670ac8SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_OFF); 878864670ac8SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 8789ec501a18SRobert Elliott hpsa_free_irqs(h); 87909ee61794SRobert Elliott rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, 879164670ac8SStephen M. Cameron hpsa_intx_discard_completions); 879264670ac8SStephen M. Cameron if (rc) { 87939ee61794SRobert Elliott dev_warn(&h->pdev->dev, 87949ee61794SRobert Elliott "Failed to request_irq after soft reset.\n"); 8795d498757cSRobert Elliott /* 8796b2ef480cSRobert Elliott * cannot goto clean7 or free_irqs will be called 8797b2ef480cSRobert Elliott * again. Instead, do its work 8798b2ef480cSRobert Elliott */ 8799b2ef480cSRobert Elliott hpsa_free_performant_mode(h); /* clean7 */ 8800b2ef480cSRobert Elliott hpsa_free_sg_chain_blocks(h); /* clean6 */ 8801b2ef480cSRobert Elliott hpsa_free_cmd_pool(h); /* clean5 */ 8802b2ef480cSRobert Elliott /* 8803b2ef480cSRobert Elliott * skip hpsa_free_irqs(h) clean4 since that 8804b2ef480cSRobert Elliott * was just called before request_irqs failed 8805d498757cSRobert Elliott */ 8806d498757cSRobert Elliott goto clean3; 880764670ac8SStephen M. Cameron } 880864670ac8SStephen M. Cameron 880964670ac8SStephen M. Cameron rc = hpsa_kdump_soft_reset(h); 881064670ac8SStephen M. Cameron if (rc) 881164670ac8SStephen M. Cameron /* Neither hard nor soft reset worked, we're hosed. */ 88127ef7323fSDon Brace goto clean7; 881364670ac8SStephen M. Cameron 881464670ac8SStephen M. Cameron dev_info(&h->pdev->dev, "Board READY.\n"); 881564670ac8SStephen M. Cameron dev_info(&h->pdev->dev, 881664670ac8SStephen M. Cameron "Waiting for stale completions to drain.\n"); 881764670ac8SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_ON); 881864670ac8SStephen M. Cameron msleep(10000); 881964670ac8SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_OFF); 882064670ac8SStephen M. Cameron 882164670ac8SStephen M. Cameron rc = controller_reset_failed(h->cfgtable); 882264670ac8SStephen M. Cameron if (rc) 882364670ac8SStephen M. Cameron dev_info(&h->pdev->dev, 882464670ac8SStephen M. Cameron "Soft reset appears to have failed.\n"); 882564670ac8SStephen M. Cameron 882664670ac8SStephen M. Cameron /* since the controller's reset, we have to go back and re-init 882764670ac8SStephen M. Cameron * everything. Easiest to just forget what we've done and do it 882864670ac8SStephen M. Cameron * all over again. 882964670ac8SStephen M. Cameron */ 883064670ac8SStephen M. Cameron hpsa_undo_allocations_after_kdump_soft_reset(h); 883164670ac8SStephen M. Cameron try_soft_reset = 0; 883264670ac8SStephen M. Cameron if (rc) 8833b2ef480cSRobert Elliott /* don't goto clean, we already unallocated */ 883464670ac8SStephen M. Cameron return -ENODEV; 883564670ac8SStephen M. Cameron 883664670ac8SStephen M. Cameron goto reinit_after_soft_reset; 883764670ac8SStephen M. Cameron } 8838edd16368SStephen M. Cameron 8839da0697bdSScott Teel /* Enable Accelerated IO path at driver layer */ 8840da0697bdSScott Teel h->acciopath_status = 1; 884134592254SScott Teel /* Disable discovery polling.*/ 884234592254SScott Teel h->discovery_polling = 0; 8843da0697bdSScott Teel 8844e863d68eSScott Teel 8845edd16368SStephen M. Cameron /* Turn the interrupts on so we can service requests */ 8846edd16368SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_ON); 8847edd16368SStephen M. Cameron 8848339b2b14SStephen M. Cameron hpsa_hba_inquiry(h); 88498a98db73SStephen M. Cameron 885034592254SScott Teel h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); 885134592254SScott Teel if (!h->lastlogicals) 885234592254SScott Teel dev_info(&h->pdev->dev, 885334592254SScott Teel "Can't track change to report lun data\n"); 885434592254SScott Teel 8855cf477237SDon Brace /* hook into SCSI subsystem */ 8856cf477237SDon Brace rc = hpsa_scsi_add_host(h); 8857cf477237SDon Brace if (rc) 8858*af61bc1eSKeita Suzuki goto clean8; /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8859cf477237SDon Brace 88608a98db73SStephen M. Cameron /* Monitor the controller for firmware lockups */ 88618a98db73SStephen M. Cameron h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 88628a98db73SStephen M. Cameron INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); 88638a98db73SStephen M. Cameron schedule_delayed_work(&h->monitor_ctlr_work, 88648a98db73SStephen M. Cameron h->heartbeat_sample_interval); 88656636e7f4SDon Brace INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); 88666636e7f4SDon Brace queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 88676636e7f4SDon Brace h->heartbeat_sample_interval); 88683d38f00cSScott Teel INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker); 88693d38f00cSScott Teel schedule_delayed_work(&h->event_monitor_work, 88703d38f00cSScott Teel HPSA_EVENT_MONITOR_INTERVAL); 887188bf6d62SStephen M. Cameron return 0; 8872edd16368SStephen M. Cameron 8873*af61bc1eSKeita Suzuki clean8: /* lastlogicals, perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8874*af61bc1eSKeita Suzuki kfree(h->lastlogicals); 88752946e82bSRobert Elliott clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8876105a3dbcSRobert Elliott hpsa_free_performant_mode(h); 8877105a3dbcSRobert Elliott h->access.set_intr_mask(h, HPSA_INTR_OFF); 8878105a3dbcSRobert Elliott clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ 887933a2ffceSStephen M. Cameron hpsa_free_sg_chain_blocks(h); 88802946e82bSRobert Elliott clean5: /* cmd, irq, shost, pci, lu, aer/h */ 88812e9d1b36SStephen M. Cameron hpsa_free_cmd_pool(h); 88822946e82bSRobert Elliott clean4: /* irq, shost, pci, lu, aer/h */ 8883ec501a18SRobert Elliott hpsa_free_irqs(h); 88842946e82bSRobert Elliott clean3: /* shost, pci, lu, aer/h */ 88852946e82bSRobert Elliott scsi_host_put(h->scsi_host); 88862946e82bSRobert Elliott h->scsi_host = NULL; 88872946e82bSRobert Elliott clean2_5: /* pci, lu, aer/h */ 8888195f2c65SRobert Elliott hpsa_free_pci_init(h); 88892946e82bSRobert Elliott clean2: /* lu, aer/h */ 8890105a3dbcSRobert Elliott if (h->lockup_detected) { 8891094963daSStephen M. Cameron free_percpu(h->lockup_detected); 8892105a3dbcSRobert Elliott h->lockup_detected = NULL; 8893105a3dbcSRobert Elliott } 8894105a3dbcSRobert Elliott clean1: /* wq/aer/h */ 8895105a3dbcSRobert Elliott if (h->resubmit_wq) { 8896105a3dbcSRobert Elliott destroy_workqueue(h->resubmit_wq); 8897105a3dbcSRobert Elliott h->resubmit_wq = NULL; 8898105a3dbcSRobert Elliott } 8899105a3dbcSRobert Elliott if (h->rescan_ctlr_wq) { 8900105a3dbcSRobert Elliott destroy_workqueue(h->rescan_ctlr_wq); 8901105a3dbcSRobert Elliott h->rescan_ctlr_wq = NULL; 8902105a3dbcSRobert Elliott } 890301192088SDon Brace if (h->monitor_ctlr_wq) { 890401192088SDon Brace destroy_workqueue(h->monitor_ctlr_wq); 890501192088SDon Brace h->monitor_ctlr_wq = NULL; 890601192088SDon Brace } 8907edd16368SStephen M. Cameron kfree(h); 8908ecd9aad4SStephen M. Cameron return rc; 8909edd16368SStephen M. Cameron } 8910edd16368SStephen M. Cameron 8911edd16368SStephen M. Cameron static void hpsa_flush_cache(struct ctlr_info *h) 8912edd16368SStephen M. Cameron { 8913edd16368SStephen M. Cameron char *flush_buf; 8914edd16368SStephen M. Cameron struct CommandList *c; 891525163bd5SWebb Scales int rc; 8916702890e3SStephen M. Cameron 8917094963daSStephen M. Cameron if (unlikely(lockup_detected(h))) 8918702890e3SStephen M. Cameron return; 8919edd16368SStephen M. Cameron flush_buf = kzalloc(4, GFP_KERNEL); 8920edd16368SStephen M. Cameron if (!flush_buf) 8921edd16368SStephen M. Cameron return; 8922edd16368SStephen M. Cameron 892345fcb86eSStephen Cameron c = cmd_alloc(h); 8924bf43caf3SRobert Elliott 8925a2dac136SStephen M. Cameron if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, 8926a2dac136SStephen M. Cameron RAID_CTLR_LUNID, TYPE_CMD)) { 8927a2dac136SStephen M. Cameron goto out; 8928a2dac136SStephen M. Cameron } 89298bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE, 89308bc8f47eSChristoph Hellwig DEFAULT_TIMEOUT); 893125163bd5SWebb Scales if (rc) 893225163bd5SWebb Scales goto out; 8933edd16368SStephen M. Cameron if (c->err_info->CommandStatus != 0) 8934a2dac136SStephen M. Cameron out: 8935edd16368SStephen M. Cameron dev_warn(&h->pdev->dev, 8936edd16368SStephen M. Cameron "error flushing cache on controller\n"); 893745fcb86eSStephen Cameron cmd_free(h, c); 8938edd16368SStephen M. Cameron kfree(flush_buf); 8939edd16368SStephen M. Cameron } 8940edd16368SStephen M. Cameron 8941c2adae44SScott Teel /* Make controller gather fresh report lun data each time we 8942c2adae44SScott Teel * send down a report luns request 8943c2adae44SScott Teel */ 8944c2adae44SScott Teel static void hpsa_disable_rld_caching(struct ctlr_info *h) 8945c2adae44SScott Teel { 8946c2adae44SScott Teel u32 *options; 8947c2adae44SScott Teel struct CommandList *c; 8948c2adae44SScott Teel int rc; 8949c2adae44SScott Teel 8950c2adae44SScott Teel /* Don't bother trying to set diag options if locked up */ 8951c2adae44SScott Teel if (unlikely(h->lockup_detected)) 8952c2adae44SScott Teel return; 8953c2adae44SScott Teel 8954c2adae44SScott Teel options = kzalloc(sizeof(*options), GFP_KERNEL); 89557e8a9486SAmit Kushwaha if (!options) 8956c2adae44SScott Teel return; 8957c2adae44SScott Teel 8958c2adae44SScott Teel c = cmd_alloc(h); 8959c2adae44SScott Teel 8960c2adae44SScott Teel /* first, get the current diag options settings */ 8961c2adae44SScott Teel if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8962c2adae44SScott Teel RAID_CTLR_LUNID, TYPE_CMD)) 8963c2adae44SScott Teel goto errout; 8964c2adae44SScott Teel 89658bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 89668bc8f47eSChristoph Hellwig NO_TIMEOUT); 8967c2adae44SScott Teel if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8968c2adae44SScott Teel goto errout; 8969c2adae44SScott Teel 8970c2adae44SScott Teel /* Now, set the bit for disabling the RLD caching */ 8971c2adae44SScott Teel *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; 8972c2adae44SScott Teel 8973c2adae44SScott Teel if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, 8974c2adae44SScott Teel RAID_CTLR_LUNID, TYPE_CMD)) 8975c2adae44SScott Teel goto errout; 8976c2adae44SScott Teel 89778bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE, 89788bc8f47eSChristoph Hellwig NO_TIMEOUT); 8979c2adae44SScott Teel if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8980c2adae44SScott Teel goto errout; 8981c2adae44SScott Teel 8982c2adae44SScott Teel /* Now verify that it got set: */ 8983c2adae44SScott Teel if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8984c2adae44SScott Teel RAID_CTLR_LUNID, TYPE_CMD)) 8985c2adae44SScott Teel goto errout; 8986c2adae44SScott Teel 89878bc8f47eSChristoph Hellwig rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, 89888bc8f47eSChristoph Hellwig NO_TIMEOUT); 8989c2adae44SScott Teel if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8990c2adae44SScott Teel goto errout; 8991c2adae44SScott Teel 8992d8a080c3SDan Carpenter if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) 8993c2adae44SScott Teel goto out; 8994c2adae44SScott Teel 8995c2adae44SScott Teel errout: 8996c2adae44SScott Teel dev_err(&h->pdev->dev, 8997c2adae44SScott Teel "Error: failed to disable report lun data caching.\n"); 8998c2adae44SScott Teel out: 8999c2adae44SScott Teel cmd_free(h, c); 9000c2adae44SScott Teel kfree(options); 9001c2adae44SScott Teel } 9002c2adae44SScott Teel 90030d98ba8dSSinan Kaya static void __hpsa_shutdown(struct pci_dev *pdev) 9004edd16368SStephen M. Cameron { 9005edd16368SStephen M. Cameron struct ctlr_info *h; 9006edd16368SStephen M. Cameron 9007edd16368SStephen M. Cameron h = pci_get_drvdata(pdev); 9008edd16368SStephen M. Cameron /* Turn board interrupts off and send the flush cache command 9009edd16368SStephen M. Cameron * sendcmd will turn off interrupt, and send the flush... 9010edd16368SStephen M. Cameron * To write all data in the battery backed cache to disks 9011edd16368SStephen M. Cameron */ 9012edd16368SStephen M. Cameron hpsa_flush_cache(h); 9013edd16368SStephen M. Cameron h->access.set_intr_mask(h, HPSA_INTR_OFF); 9014105a3dbcSRobert Elliott hpsa_free_irqs(h); /* init_one 4 */ 9015cc64c817SRobert Elliott hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 9016edd16368SStephen M. Cameron } 9017edd16368SStephen M. Cameron 90180d98ba8dSSinan Kaya static void hpsa_shutdown(struct pci_dev *pdev) 90190d98ba8dSSinan Kaya { 90200d98ba8dSSinan Kaya __hpsa_shutdown(pdev); 90210d98ba8dSSinan Kaya pci_disable_device(pdev); 90220d98ba8dSSinan Kaya } 90230d98ba8dSSinan Kaya 90246f039790SGreg Kroah-Hartman static void hpsa_free_device_info(struct ctlr_info *h) 902555e14e76SStephen M. Cameron { 902655e14e76SStephen M. Cameron int i; 902755e14e76SStephen M. Cameron 9028105a3dbcSRobert Elliott for (i = 0; i < h->ndevices; i++) { 902955e14e76SStephen M. Cameron kfree(h->dev[i]); 9030105a3dbcSRobert Elliott h->dev[i] = NULL; 9031105a3dbcSRobert Elliott } 903255e14e76SStephen M. Cameron } 903355e14e76SStephen M. Cameron 90346f039790SGreg Kroah-Hartman static void hpsa_remove_one(struct pci_dev *pdev) 9035edd16368SStephen M. Cameron { 9036edd16368SStephen M. Cameron struct ctlr_info *h; 90378a98db73SStephen M. Cameron unsigned long flags; 9038edd16368SStephen M. Cameron 9039edd16368SStephen M. Cameron if (pci_get_drvdata(pdev) == NULL) { 9040edd16368SStephen M. Cameron dev_err(&pdev->dev, "unable to remove device\n"); 9041edd16368SStephen M. Cameron return; 9042edd16368SStephen M. Cameron } 9043edd16368SStephen M. Cameron h = pci_get_drvdata(pdev); 90448a98db73SStephen M. Cameron 90458a98db73SStephen M. Cameron /* Get rid of any controller monitoring work items */ 90468a98db73SStephen M. Cameron spin_lock_irqsave(&h->lock, flags); 90478a98db73SStephen M. Cameron h->remove_in_progress = 1; 90488a98db73SStephen M. Cameron spin_unlock_irqrestore(&h->lock, flags); 90496636e7f4SDon Brace cancel_delayed_work_sync(&h->monitor_ctlr_work); 90506636e7f4SDon Brace cancel_delayed_work_sync(&h->rescan_ctlr_work); 90513d38f00cSScott Teel cancel_delayed_work_sync(&h->event_monitor_work); 90526636e7f4SDon Brace destroy_workqueue(h->rescan_ctlr_wq); 90536636e7f4SDon Brace destroy_workqueue(h->resubmit_wq); 905401192088SDon Brace destroy_workqueue(h->monitor_ctlr_wq); 9055cc64c817SRobert Elliott 9056dfb2e6f4SMartin Wilck hpsa_delete_sas_host(h); 9057dfb2e6f4SMartin Wilck 90582d041306SDon Brace /* 90592d041306SDon Brace * Call before disabling interrupts. 90602d041306SDon Brace * scsi_remove_host can trigger I/O operations especially 90612d041306SDon Brace * when multipath is enabled. There can be SYNCHRONIZE CACHE 90622d041306SDon Brace * operations which cannot complete and will hang the system. 90632d041306SDon Brace */ 90642d041306SDon Brace if (h->scsi_host) 90652d041306SDon Brace scsi_remove_host(h->scsi_host); /* init_one 8 */ 9066105a3dbcSRobert Elliott /* includes hpsa_free_irqs - init_one 4 */ 9067195f2c65SRobert Elliott /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 90680d98ba8dSSinan Kaya __hpsa_shutdown(pdev); 9069cc64c817SRobert Elliott 9070105a3dbcSRobert Elliott hpsa_free_device_info(h); /* scan */ 9071105a3dbcSRobert Elliott 90722946e82bSRobert Elliott kfree(h->hba_inquiry_data); /* init_one 10 */ 90732946e82bSRobert Elliott h->hba_inquiry_data = NULL; /* init_one 10 */ 90742946e82bSRobert Elliott hpsa_free_ioaccel2_sg_chain_blocks(h); 9075105a3dbcSRobert Elliott hpsa_free_performant_mode(h); /* init_one 7 */ 9076105a3dbcSRobert Elliott hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 90771fb7c98aSRobert Elliott hpsa_free_cmd_pool(h); /* init_one 5 */ 907834592254SScott Teel kfree(h->lastlogicals); 9079105a3dbcSRobert Elliott 9080105a3dbcSRobert Elliott /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ 9081195f2c65SRobert Elliott 90822946e82bSRobert Elliott scsi_host_put(h->scsi_host); /* init_one 3 */ 90832946e82bSRobert Elliott h->scsi_host = NULL; /* init_one 3 */ 90842946e82bSRobert Elliott 9085195f2c65SRobert Elliott /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 90862946e82bSRobert Elliott hpsa_free_pci_init(h); /* init_one 2.5 */ 9087195f2c65SRobert Elliott 9088105a3dbcSRobert Elliott free_percpu(h->lockup_detected); /* init_one 2 */ 9089105a3dbcSRobert Elliott h->lockup_detected = NULL; /* init_one 2 */ 9090105a3dbcSRobert Elliott /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ 9091d04e62b9SKevin Barnett 90928b834bffSMing Lei hpda_free_ctlr_info(h); /* init_one 1 */ 9093edd16368SStephen M. Cameron } 9094edd16368SStephen M. Cameron 9095edd16368SStephen M. Cameron static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, 9096edd16368SStephen M. Cameron __attribute__((unused)) pm_message_t state) 9097edd16368SStephen M. Cameron { 9098edd16368SStephen M. Cameron return -ENOSYS; 9099edd16368SStephen M. Cameron } 9100edd16368SStephen M. Cameron 9101edd16368SStephen M. Cameron static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) 9102edd16368SStephen M. Cameron { 9103edd16368SStephen M. Cameron return -ENOSYS; 9104edd16368SStephen M. Cameron } 9105edd16368SStephen M. Cameron 9106edd16368SStephen M. Cameron static struct pci_driver hpsa_pci_driver = { 9107f79cfec6SStephen M. Cameron .name = HPSA, 9108edd16368SStephen M. Cameron .probe = hpsa_init_one, 91096f039790SGreg Kroah-Hartman .remove = hpsa_remove_one, 9110edd16368SStephen M. Cameron .id_table = hpsa_pci_device_id, /* id_table */ 9111edd16368SStephen M. Cameron .shutdown = hpsa_shutdown, 9112edd16368SStephen M. Cameron .suspend = hpsa_suspend, 9113edd16368SStephen M. Cameron .resume = hpsa_resume, 9114edd16368SStephen M. Cameron }; 9115edd16368SStephen M. Cameron 9116303932fdSDon Brace /* Fill in bucket_map[], given nsgs (the max number of 9117303932fdSDon Brace * scatter gather elements supported) and bucket[], 9118303932fdSDon Brace * which is an array of 8 integers. The bucket[] array 9119303932fdSDon Brace * contains 8 different DMA transfer sizes (in 16 9120303932fdSDon Brace * byte increments) which the controller uses to fetch 9121303932fdSDon Brace * commands. This function fills in bucket_map[], which 9122303932fdSDon Brace * maps a given number of scatter gather elements to one of 9123303932fdSDon Brace * the 8 DMA transfer sizes. The point of it is to allow the 9124303932fdSDon Brace * controller to only do as much DMA as needed to fetch the 9125303932fdSDon Brace * command, with the DMA transfer size encoded in the lower 9126303932fdSDon Brace * bits of the command address. 9127303932fdSDon Brace */ 9128303932fdSDon Brace static void calc_bucket_map(int bucket[], int num_buckets, 91292b08b3e9SDon Brace int nsgs, int min_blocks, u32 *bucket_map) 9130303932fdSDon Brace { 9131303932fdSDon Brace int i, j, b, size; 9132303932fdSDon Brace 9133303932fdSDon Brace /* Note, bucket_map must have nsgs+1 entries. */ 9134303932fdSDon Brace for (i = 0; i <= nsgs; i++) { 9135303932fdSDon Brace /* Compute size of a command with i SG entries */ 9136e1f7de0cSMatt Gates size = i + min_blocks; 9137303932fdSDon Brace b = num_buckets; /* Assume the biggest bucket */ 9138303932fdSDon Brace /* Find the bucket that is just big enough */ 9139e1f7de0cSMatt Gates for (j = 0; j < num_buckets; j++) { 9140303932fdSDon Brace if (bucket[j] >= size) { 9141303932fdSDon Brace b = j; 9142303932fdSDon Brace break; 9143303932fdSDon Brace } 9144303932fdSDon Brace } 9145303932fdSDon Brace /* for a command with i SG entries, use bucket b. */ 9146303932fdSDon Brace bucket_map[i] = b; 9147303932fdSDon Brace } 9148303932fdSDon Brace } 9149303932fdSDon Brace 9150105a3dbcSRobert Elliott /* 9151105a3dbcSRobert Elliott * return -ENODEV on err, 0 on success (or no action) 9152105a3dbcSRobert Elliott * allocates numerous items that must be freed later 9153105a3dbcSRobert Elliott */ 9154c706a795SRobert Elliott static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) 9155303932fdSDon Brace { 91566c311b57SStephen M. Cameron int i; 91576c311b57SStephen M. Cameron unsigned long register_value; 9158e1f7de0cSMatt Gates unsigned long transMethod = CFGTBL_Trans_Performant | 9159e1f7de0cSMatt Gates (trans_support & CFGTBL_Trans_use_short_tags) | 9160e1f7de0cSMatt Gates CFGTBL_Trans_enable_directed_msix | 9161b9af4937SStephen M. Cameron (trans_support & (CFGTBL_Trans_io_accel1 | 9162b9af4937SStephen M. Cameron CFGTBL_Trans_io_accel2)); 9163e1f7de0cSMatt Gates struct access_method access = SA5_performant_access; 9164def342bdSStephen M. Cameron 9165def342bdSStephen M. Cameron /* This is a bit complicated. There are 8 registers on 9166def342bdSStephen M. Cameron * the controller which we write to to tell it 8 different 9167def342bdSStephen M. Cameron * sizes of commands which there may be. It's a way of 9168def342bdSStephen M. Cameron * reducing the DMA done to fetch each command. Encoded into 9169def342bdSStephen M. Cameron * each command's tag are 3 bits which communicate to the controller 9170def342bdSStephen M. Cameron * which of the eight sizes that command fits within. The size of 9171def342bdSStephen M. Cameron * each command depends on how many scatter gather entries there are. 9172def342bdSStephen M. Cameron * Each SG entry requires 16 bytes. The eight registers are programmed 9173def342bdSStephen M. Cameron * with the number of 16-byte blocks a command of that size requires. 9174def342bdSStephen M. Cameron * The smallest command possible requires 5 such 16 byte blocks. 9175d66ae08bSStephen M. Cameron * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte 9176def342bdSStephen M. Cameron * blocks. Note, this only extends to the SG entries contained 9177def342bdSStephen M. Cameron * within the command block, and does not extend to chained blocks 9178def342bdSStephen M. Cameron * of SG elements. bft[] contains the eight values we write to 9179def342bdSStephen M. Cameron * the registers. They are not evenly distributed, but have more 9180def342bdSStephen M. Cameron * sizes for small commands, and fewer sizes for larger commands. 9181def342bdSStephen M. Cameron */ 9182d66ae08bSStephen M. Cameron int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; 9183b9af4937SStephen M. Cameron #define MIN_IOACCEL2_BFT_ENTRY 5 9184b9af4937SStephen M. Cameron #define HPSA_IOACCEL2_HEADER_SZ 4 9185b9af4937SStephen M. Cameron int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, 9186b9af4937SStephen M. Cameron 13, 14, 15, 16, 17, 18, 19, 9187b9af4937SStephen M. Cameron HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; 9188b9af4937SStephen M. Cameron BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); 9189b9af4937SStephen M. Cameron BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); 9190b9af4937SStephen M. Cameron BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > 9191b9af4937SStephen M. Cameron 16 * MIN_IOACCEL2_BFT_ENTRY); 9192b9af4937SStephen M. Cameron BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); 9193d66ae08bSStephen M. Cameron BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); 9194303932fdSDon Brace /* 5 = 1 s/g entry or 4k 9195303932fdSDon Brace * 6 = 2 s/g entry or 8k 9196303932fdSDon Brace * 8 = 4 s/g entry or 16k 9197303932fdSDon Brace * 10 = 6 s/g entry or 24k 9198303932fdSDon Brace */ 9199303932fdSDon Brace 9200b3a52e79SStephen M. Cameron /* If the controller supports either ioaccel method then 9201b3a52e79SStephen M. Cameron * we can also use the RAID stack submit path that does not 9202b3a52e79SStephen M. Cameron * perform the superfluous readl() after each command submission. 9203b3a52e79SStephen M. Cameron */ 9204b3a52e79SStephen M. Cameron if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) 9205b3a52e79SStephen M. Cameron access = SA5_performant_access_no_read; 9206b3a52e79SStephen M. Cameron 9207303932fdSDon Brace /* Controller spec: zero out this buffer. */ 9208072b0518SStephen M. Cameron for (i = 0; i < h->nreply_queues; i++) 9209072b0518SStephen M. Cameron memset(h->reply_queue[i].head, 0, h->reply_queue_size); 9210303932fdSDon Brace 9211d66ae08bSStephen M. Cameron bft[7] = SG_ENTRIES_IN_CMD + 4; 9212d66ae08bSStephen M. Cameron calc_bucket_map(bft, ARRAY_SIZE(bft), 9213e1f7de0cSMatt Gates SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); 9214303932fdSDon Brace for (i = 0; i < 8; i++) 9215303932fdSDon Brace writel(bft[i], &h->transtable->BlockFetch[i]); 9216303932fdSDon Brace 9217303932fdSDon Brace /* size of controller ring buffer */ 9218303932fdSDon Brace writel(h->max_commands, &h->transtable->RepQSize); 9219254f796bSMatt Gates writel(h->nreply_queues, &h->transtable->RepQCount); 9220303932fdSDon Brace writel(0, &h->transtable->RepQCtrAddrLow32); 9221303932fdSDon Brace writel(0, &h->transtable->RepQCtrAddrHigh32); 9222254f796bSMatt Gates 9223254f796bSMatt Gates for (i = 0; i < h->nreply_queues; i++) { 9224254f796bSMatt Gates writel(0, &h->transtable->RepQAddr[i].upper); 9225072b0518SStephen M. Cameron writel(h->reply_queue[i].busaddr, 9226254f796bSMatt Gates &h->transtable->RepQAddr[i].lower); 9227254f796bSMatt Gates } 9228254f796bSMatt Gates 9229b9af4937SStephen M. Cameron writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 9230e1f7de0cSMatt Gates writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); 9231e1f7de0cSMatt Gates /* 9232e1f7de0cSMatt Gates * enable outbound interrupt coalescing in accelerator mode; 9233e1f7de0cSMatt Gates */ 9234e1f7de0cSMatt Gates if (trans_support & CFGTBL_Trans_io_accel1) { 9235e1f7de0cSMatt Gates access = SA5_ioaccel_mode1_access; 9236e1f7de0cSMatt Gates writel(10, &h->cfgtable->HostWrite.CoalIntDelay); 9237e1f7de0cSMatt Gates writel(4, &h->cfgtable->HostWrite.CoalIntCount); 923896b6ce4eSDon Brace } else 923996b6ce4eSDon Brace if (trans_support & CFGTBL_Trans_io_accel2) 9240c349775eSScott Teel access = SA5_ioaccel_mode2_access; 9241303932fdSDon Brace writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 9242c706a795SRobert Elliott if (hpsa_wait_for_mode_change_ack(h)) { 9243c706a795SRobert Elliott dev_err(&h->pdev->dev, 9244c706a795SRobert Elliott "performant mode problem - doorbell timeout\n"); 9245c706a795SRobert Elliott return -ENODEV; 9246c706a795SRobert Elliott } 9247303932fdSDon Brace register_value = readl(&(h->cfgtable->TransportActive)); 9248303932fdSDon Brace if (!(register_value & CFGTBL_Trans_Performant)) { 9249050f7147SStephen Cameron dev_err(&h->pdev->dev, 9250050f7147SStephen Cameron "performant mode problem - transport not active\n"); 9251c706a795SRobert Elliott return -ENODEV; 9252303932fdSDon Brace } 9253960a30e7SStephen M. Cameron /* Change the access methods to the performant access methods */ 9254e1f7de0cSMatt Gates h->access = access; 9255e1f7de0cSMatt Gates h->transMethod = transMethod; 9256e1f7de0cSMatt Gates 9257b9af4937SStephen M. Cameron if (!((trans_support & CFGTBL_Trans_io_accel1) || 9258b9af4937SStephen M. Cameron (trans_support & CFGTBL_Trans_io_accel2))) 9259c706a795SRobert Elliott return 0; 9260e1f7de0cSMatt Gates 9261b9af4937SStephen M. Cameron if (trans_support & CFGTBL_Trans_io_accel1) { 9262e1f7de0cSMatt Gates /* Set up I/O accelerator mode */ 9263e1f7de0cSMatt Gates for (i = 0; i < h->nreply_queues; i++) { 9264e1f7de0cSMatt Gates writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); 9265e1f7de0cSMatt Gates h->reply_queue[i].current_entry = 9266e1f7de0cSMatt Gates readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); 9267e1f7de0cSMatt Gates } 9268283b4a9bSStephen M. Cameron bft[7] = h->ioaccel_maxsg + 8; 9269283b4a9bSStephen M. Cameron calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, 9270e1f7de0cSMatt Gates h->ioaccel1_blockFetchTable); 9271e1f7de0cSMatt Gates 9272e1f7de0cSMatt Gates /* initialize all reply queue entries to unused */ 9273072b0518SStephen M. Cameron for (i = 0; i < h->nreply_queues; i++) 9274072b0518SStephen M. Cameron memset(h->reply_queue[i].head, 9275072b0518SStephen M. Cameron (u8) IOACCEL_MODE1_REPLY_UNUSED, 9276072b0518SStephen M. Cameron h->reply_queue_size); 9277e1f7de0cSMatt Gates 9278e1f7de0cSMatt Gates /* set all the constant fields in the accelerator command 9279e1f7de0cSMatt Gates * frames once at init time to save CPU cycles later. 9280e1f7de0cSMatt Gates */ 9281e1f7de0cSMatt Gates for (i = 0; i < h->nr_cmds; i++) { 9282e1f7de0cSMatt Gates struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; 9283e1f7de0cSMatt Gates 9284e1f7de0cSMatt Gates cp->function = IOACCEL1_FUNCTION_SCSIIO; 9285e1f7de0cSMatt Gates cp->err_info = (u32) (h->errinfo_pool_dhandle + 9286e1f7de0cSMatt Gates (i * sizeof(struct ErrorInfo))); 9287e1f7de0cSMatt Gates cp->err_info_len = sizeof(struct ErrorInfo); 9288e1f7de0cSMatt Gates cp->sgl_offset = IOACCEL1_SGLOFFSET; 92892b08b3e9SDon Brace cp->host_context_flags = 92902b08b3e9SDon Brace cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); 9291e1f7de0cSMatt Gates cp->timeout_sec = 0; 9292e1f7de0cSMatt Gates cp->ReplyQueue = 0; 929350a0decfSStephen M. Cameron cp->tag = 9294f2405db8SDon Brace cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); 929550a0decfSStephen M. Cameron cp->host_addr = 929650a0decfSStephen M. Cameron cpu_to_le64(h->ioaccel_cmd_pool_dhandle + 9297e1f7de0cSMatt Gates (i * sizeof(struct io_accel1_cmd))); 9298e1f7de0cSMatt Gates } 9299b9af4937SStephen M. Cameron } else if (trans_support & CFGTBL_Trans_io_accel2) { 9300b9af4937SStephen M. Cameron u64 cfg_offset, cfg_base_addr_index; 9301b9af4937SStephen M. Cameron u32 bft2_offset, cfg_base_addr; 9302b9af4937SStephen M. Cameron int rc; 9303b9af4937SStephen M. Cameron 9304b9af4937SStephen M. Cameron rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 9305b9af4937SStephen M. Cameron &cfg_base_addr_index, &cfg_offset); 9306b9af4937SStephen M. Cameron BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); 9307b9af4937SStephen M. Cameron bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; 9308b9af4937SStephen M. Cameron calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, 9309b9af4937SStephen M. Cameron 4, h->ioaccel2_blockFetchTable); 9310b9af4937SStephen M. Cameron bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); 9311b9af4937SStephen M. Cameron BUILD_BUG_ON(offsetof(struct CfgTable, 9312b9af4937SStephen M. Cameron io_accel_request_size_offset) != 0xb8); 9313b9af4937SStephen M. Cameron h->ioaccel2_bft2_regs = 9314b9af4937SStephen M. Cameron remap_pci_mem(pci_resource_start(h->pdev, 9315b9af4937SStephen M. Cameron cfg_base_addr_index) + 9316b9af4937SStephen M. Cameron cfg_offset + bft2_offset, 9317b9af4937SStephen M. Cameron ARRAY_SIZE(bft2) * 9318b9af4937SStephen M. Cameron sizeof(*h->ioaccel2_bft2_regs)); 9319b9af4937SStephen M. Cameron for (i = 0; i < ARRAY_SIZE(bft2); i++) 9320b9af4937SStephen M. Cameron writel(bft2[i], &h->ioaccel2_bft2_regs[i]); 9321b9af4937SStephen M. Cameron } 9322b9af4937SStephen M. Cameron writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 9323c706a795SRobert Elliott if (hpsa_wait_for_mode_change_ack(h)) { 9324c706a795SRobert Elliott dev_err(&h->pdev->dev, 9325c706a795SRobert Elliott "performant mode problem - enabling ioaccel mode\n"); 9326c706a795SRobert Elliott return -ENODEV; 9327c706a795SRobert Elliott } 9328c706a795SRobert Elliott return 0; 9329e1f7de0cSMatt Gates } 9330e1f7de0cSMatt Gates 93311fb7c98aSRobert Elliott /* Free ioaccel1 mode command blocks and block fetch table */ 93321fb7c98aSRobert Elliott static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) 93331fb7c98aSRobert Elliott { 9334105a3dbcSRobert Elliott if (h->ioaccel_cmd_pool) { 93358f31fa53SSuraj Upadhyay dma_free_coherent(&h->pdev->dev, 93361fb7c98aSRobert Elliott h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 93371fb7c98aSRobert Elliott h->ioaccel_cmd_pool, 93381fb7c98aSRobert Elliott h->ioaccel_cmd_pool_dhandle); 9339105a3dbcSRobert Elliott h->ioaccel_cmd_pool = NULL; 9340105a3dbcSRobert Elliott h->ioaccel_cmd_pool_dhandle = 0; 9341105a3dbcSRobert Elliott } 93421fb7c98aSRobert Elliott kfree(h->ioaccel1_blockFetchTable); 9343105a3dbcSRobert Elliott h->ioaccel1_blockFetchTable = NULL; 93441fb7c98aSRobert Elliott } 93451fb7c98aSRobert Elliott 9346d37ffbe4SRobert Elliott /* Allocate ioaccel1 mode command blocks and block fetch table */ 9347d37ffbe4SRobert Elliott static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) 9348e1f7de0cSMatt Gates { 9349283b4a9bSStephen M. Cameron h->ioaccel_maxsg = 9350283b4a9bSStephen M. Cameron readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 9351283b4a9bSStephen M. Cameron if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) 9352283b4a9bSStephen M. Cameron h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; 9353283b4a9bSStephen M. Cameron 9354e1f7de0cSMatt Gates /* Command structures must be aligned on a 128-byte boundary 9355e1f7de0cSMatt Gates * because the 7 lower bits of the address are used by the 9356e1f7de0cSMatt Gates * hardware. 9357e1f7de0cSMatt Gates */ 9358e1f7de0cSMatt Gates BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % 9359e1f7de0cSMatt Gates IOACCEL1_COMMANDLIST_ALIGNMENT); 9360e1f7de0cSMatt Gates h->ioaccel_cmd_pool = 93618bc8f47eSChristoph Hellwig dma_alloc_coherent(&h->pdev->dev, 9362e1f7de0cSMatt Gates h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 93638bc8f47eSChristoph Hellwig &h->ioaccel_cmd_pool_dhandle, GFP_KERNEL); 9364e1f7de0cSMatt Gates 9365e1f7de0cSMatt Gates h->ioaccel1_blockFetchTable = 9366283b4a9bSStephen M. Cameron kmalloc(((h->ioaccel_maxsg + 1) * 9367e1f7de0cSMatt Gates sizeof(u32)), GFP_KERNEL); 9368e1f7de0cSMatt Gates 9369e1f7de0cSMatt Gates if ((h->ioaccel_cmd_pool == NULL) || 9370e1f7de0cSMatt Gates (h->ioaccel1_blockFetchTable == NULL)) 9371e1f7de0cSMatt Gates goto clean_up; 9372e1f7de0cSMatt Gates 9373e1f7de0cSMatt Gates memset(h->ioaccel_cmd_pool, 0, 9374e1f7de0cSMatt Gates h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); 9375e1f7de0cSMatt Gates return 0; 9376e1f7de0cSMatt Gates 9377e1f7de0cSMatt Gates clean_up: 93781fb7c98aSRobert Elliott hpsa_free_ioaccel1_cmd_and_bft(h); 93792dd02d74SRobert Elliott return -ENOMEM; 93806c311b57SStephen M. Cameron } 93816c311b57SStephen M. Cameron 93821fb7c98aSRobert Elliott /* Free ioaccel2 mode command blocks and block fetch table */ 93831fb7c98aSRobert Elliott static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) 93841fb7c98aSRobert Elliott { 9385d9a729f3SWebb Scales hpsa_free_ioaccel2_sg_chain_blocks(h); 9386d9a729f3SWebb Scales 9387105a3dbcSRobert Elliott if (h->ioaccel2_cmd_pool) { 93888f31fa53SSuraj Upadhyay dma_free_coherent(&h->pdev->dev, 93891fb7c98aSRobert Elliott h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 93901fb7c98aSRobert Elliott h->ioaccel2_cmd_pool, 93911fb7c98aSRobert Elliott h->ioaccel2_cmd_pool_dhandle); 9392105a3dbcSRobert Elliott h->ioaccel2_cmd_pool = NULL; 9393105a3dbcSRobert Elliott h->ioaccel2_cmd_pool_dhandle = 0; 9394105a3dbcSRobert Elliott } 93951fb7c98aSRobert Elliott kfree(h->ioaccel2_blockFetchTable); 9396105a3dbcSRobert Elliott h->ioaccel2_blockFetchTable = NULL; 93971fb7c98aSRobert Elliott } 93981fb7c98aSRobert Elliott 9399d37ffbe4SRobert Elliott /* Allocate ioaccel2 mode command blocks and block fetch table */ 9400d37ffbe4SRobert Elliott static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) 9401aca9012aSStephen M. Cameron { 9402d9a729f3SWebb Scales int rc; 9403d9a729f3SWebb Scales 9404aca9012aSStephen M. Cameron /* Allocate ioaccel2 mode command blocks and block fetch table */ 9405aca9012aSStephen M. Cameron 9406aca9012aSStephen M. Cameron h->ioaccel_maxsg = 9407aca9012aSStephen M. Cameron readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 9408aca9012aSStephen M. Cameron if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) 9409aca9012aSStephen M. Cameron h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; 9410aca9012aSStephen M. Cameron 9411aca9012aSStephen M. Cameron BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % 9412aca9012aSStephen M. Cameron IOACCEL2_COMMANDLIST_ALIGNMENT); 9413aca9012aSStephen M. Cameron h->ioaccel2_cmd_pool = 94148bc8f47eSChristoph Hellwig dma_alloc_coherent(&h->pdev->dev, 9415aca9012aSStephen M. Cameron h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 94168bc8f47eSChristoph Hellwig &h->ioaccel2_cmd_pool_dhandle, GFP_KERNEL); 9417aca9012aSStephen M. Cameron 9418aca9012aSStephen M. Cameron h->ioaccel2_blockFetchTable = 9419aca9012aSStephen M. Cameron kmalloc(((h->ioaccel_maxsg + 1) * 9420aca9012aSStephen M. Cameron sizeof(u32)), GFP_KERNEL); 9421aca9012aSStephen M. Cameron 9422aca9012aSStephen M. Cameron if ((h->ioaccel2_cmd_pool == NULL) || 9423d9a729f3SWebb Scales (h->ioaccel2_blockFetchTable == NULL)) { 9424d9a729f3SWebb Scales rc = -ENOMEM; 9425d9a729f3SWebb Scales goto clean_up; 9426d9a729f3SWebb Scales } 9427d9a729f3SWebb Scales 9428d9a729f3SWebb Scales rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); 9429d9a729f3SWebb Scales if (rc) 9430aca9012aSStephen M. Cameron goto clean_up; 9431aca9012aSStephen M. Cameron 9432aca9012aSStephen M. Cameron memset(h->ioaccel2_cmd_pool, 0, 9433aca9012aSStephen M. Cameron h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); 9434aca9012aSStephen M. Cameron return 0; 9435aca9012aSStephen M. Cameron 9436aca9012aSStephen M. Cameron clean_up: 94371fb7c98aSRobert Elliott hpsa_free_ioaccel2_cmd_and_bft(h); 9438d9a729f3SWebb Scales return rc; 9439aca9012aSStephen M. Cameron } 9440aca9012aSStephen M. Cameron 9441105a3dbcSRobert Elliott /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ 9442105a3dbcSRobert Elliott static void hpsa_free_performant_mode(struct ctlr_info *h) 9443105a3dbcSRobert Elliott { 9444105a3dbcSRobert Elliott kfree(h->blockFetchTable); 9445105a3dbcSRobert Elliott h->blockFetchTable = NULL; 9446105a3dbcSRobert Elliott hpsa_free_reply_queues(h); 9447105a3dbcSRobert Elliott hpsa_free_ioaccel1_cmd_and_bft(h); 9448105a3dbcSRobert Elliott hpsa_free_ioaccel2_cmd_and_bft(h); 9449105a3dbcSRobert Elliott } 9450105a3dbcSRobert Elliott 9451105a3dbcSRobert Elliott /* return -ENODEV on error, 0 on success (or no action) 9452105a3dbcSRobert Elliott * allocates numerous items that must be freed later 9453105a3dbcSRobert Elliott */ 9454105a3dbcSRobert Elliott static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) 94556c311b57SStephen M. Cameron { 94566c311b57SStephen M. Cameron u32 trans_support; 9457e1f7de0cSMatt Gates unsigned long transMethod = CFGTBL_Trans_Performant | 9458e1f7de0cSMatt Gates CFGTBL_Trans_use_short_tags; 9459105a3dbcSRobert Elliott int i, rc; 94606c311b57SStephen M. Cameron 946102ec19c8SStephen M. Cameron if (hpsa_simple_mode) 9462105a3dbcSRobert Elliott return 0; 946302ec19c8SStephen M. Cameron 946467c99a72Sscameron@beardog.cce.hp.com trans_support = readl(&(h->cfgtable->TransportSupport)); 946567c99a72Sscameron@beardog.cce.hp.com if (!(trans_support & PERFORMANT_MODE)) 9466105a3dbcSRobert Elliott return 0; 946767c99a72Sscameron@beardog.cce.hp.com 9468e1f7de0cSMatt Gates /* Check for I/O accelerator mode support */ 9469e1f7de0cSMatt Gates if (trans_support & CFGTBL_Trans_io_accel1) { 9470e1f7de0cSMatt Gates transMethod |= CFGTBL_Trans_io_accel1 | 9471e1f7de0cSMatt Gates CFGTBL_Trans_enable_directed_msix; 9472105a3dbcSRobert Elliott rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); 9473105a3dbcSRobert Elliott if (rc) 9474105a3dbcSRobert Elliott return rc; 9475105a3dbcSRobert Elliott } else if (trans_support & CFGTBL_Trans_io_accel2) { 9476aca9012aSStephen M. Cameron transMethod |= CFGTBL_Trans_io_accel2 | 9477aca9012aSStephen M. Cameron CFGTBL_Trans_enable_directed_msix; 9478105a3dbcSRobert Elliott rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); 9479105a3dbcSRobert Elliott if (rc) 9480105a3dbcSRobert Elliott return rc; 9481e1f7de0cSMatt Gates } 9482e1f7de0cSMatt Gates 9483bc2bb154SChristoph Hellwig h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1; 9484cba3d38bSStephen M. Cameron hpsa_get_max_perf_mode_cmds(h); 94856c311b57SStephen M. Cameron /* Performant mode ring buffer and supporting data structures */ 9486072b0518SStephen M. Cameron h->reply_queue_size = h->max_commands * sizeof(u64); 94876c311b57SStephen M. Cameron 9488254f796bSMatt Gates for (i = 0; i < h->nreply_queues; i++) { 94898bc8f47eSChristoph Hellwig h->reply_queue[i].head = dma_alloc_coherent(&h->pdev->dev, 9490072b0518SStephen M. Cameron h->reply_queue_size, 94918bc8f47eSChristoph Hellwig &h->reply_queue[i].busaddr, 94928bc8f47eSChristoph Hellwig GFP_KERNEL); 9493105a3dbcSRobert Elliott if (!h->reply_queue[i].head) { 9494105a3dbcSRobert Elliott rc = -ENOMEM; 9495105a3dbcSRobert Elliott goto clean1; /* rq, ioaccel */ 9496105a3dbcSRobert Elliott } 9497254f796bSMatt Gates h->reply_queue[i].size = h->max_commands; 9498254f796bSMatt Gates h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ 9499254f796bSMatt Gates h->reply_queue[i].current_entry = 0; 9500254f796bSMatt Gates } 9501254f796bSMatt Gates 95026c311b57SStephen M. Cameron /* Need a block fetch table for performant mode */ 9503d66ae08bSStephen M. Cameron h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * 95046c311b57SStephen M. Cameron sizeof(u32)), GFP_KERNEL); 9505105a3dbcSRobert Elliott if (!h->blockFetchTable) { 9506105a3dbcSRobert Elliott rc = -ENOMEM; 9507105a3dbcSRobert Elliott goto clean1; /* rq, ioaccel */ 9508105a3dbcSRobert Elliott } 95096c311b57SStephen M. Cameron 9510105a3dbcSRobert Elliott rc = hpsa_enter_performant_mode(h, trans_support); 9511105a3dbcSRobert Elliott if (rc) 9512105a3dbcSRobert Elliott goto clean2; /* bft, rq, ioaccel */ 9513105a3dbcSRobert Elliott return 0; 9514303932fdSDon Brace 9515105a3dbcSRobert Elliott clean2: /* bft, rq, ioaccel */ 9516303932fdSDon Brace kfree(h->blockFetchTable); 9517105a3dbcSRobert Elliott h->blockFetchTable = NULL; 9518105a3dbcSRobert Elliott clean1: /* rq, ioaccel */ 9519105a3dbcSRobert Elliott hpsa_free_reply_queues(h); 9520105a3dbcSRobert Elliott hpsa_free_ioaccel1_cmd_and_bft(h); 9521105a3dbcSRobert Elliott hpsa_free_ioaccel2_cmd_and_bft(h); 9522105a3dbcSRobert Elliott return rc; 9523303932fdSDon Brace } 9524303932fdSDon Brace 952523100dd9SStephen M. Cameron static int is_accelerated_cmd(struct CommandList *c) 952676438d08SStephen M. Cameron { 952723100dd9SStephen M. Cameron return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; 952823100dd9SStephen M. Cameron } 952923100dd9SStephen M. Cameron 953023100dd9SStephen M. Cameron static void hpsa_drain_accel_commands(struct ctlr_info *h) 953123100dd9SStephen M. Cameron { 953223100dd9SStephen M. Cameron struct CommandList *c = NULL; 9533f2405db8SDon Brace int i, accel_cmds_out; 9534281a7fd0SWebb Scales int refcount; 953576438d08SStephen M. Cameron 9536f2405db8SDon Brace do { /* wait for all outstanding ioaccel commands to drain out */ 953723100dd9SStephen M. Cameron accel_cmds_out = 0; 9538f2405db8SDon Brace for (i = 0; i < h->nr_cmds; i++) { 9539f2405db8SDon Brace c = h->cmd_pool + i; 9540281a7fd0SWebb Scales refcount = atomic_inc_return(&c->refcount); 9541281a7fd0SWebb Scales if (refcount > 1) /* Command is allocated */ 954223100dd9SStephen M. Cameron accel_cmds_out += is_accelerated_cmd(c); 9543281a7fd0SWebb Scales cmd_free(h, c); 9544f2405db8SDon Brace } 954523100dd9SStephen M. Cameron if (accel_cmds_out <= 0) 954676438d08SStephen M. Cameron break; 954776438d08SStephen M. Cameron msleep(100); 954876438d08SStephen M. Cameron } while (1); 954976438d08SStephen M. Cameron } 955076438d08SStephen M. Cameron 9551d04e62b9SKevin Barnett static struct hpsa_sas_phy *hpsa_alloc_sas_phy( 9552d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port) 9553d04e62b9SKevin Barnett { 9554d04e62b9SKevin Barnett struct hpsa_sas_phy *hpsa_sas_phy; 9555d04e62b9SKevin Barnett struct sas_phy *phy; 9556d04e62b9SKevin Barnett 9557d04e62b9SKevin Barnett hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); 9558d04e62b9SKevin Barnett if (!hpsa_sas_phy) 9559d04e62b9SKevin Barnett return NULL; 9560d04e62b9SKevin Barnett 9561d04e62b9SKevin Barnett phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, 9562d04e62b9SKevin Barnett hpsa_sas_port->next_phy_index); 9563d04e62b9SKevin Barnett if (!phy) { 9564d04e62b9SKevin Barnett kfree(hpsa_sas_phy); 9565d04e62b9SKevin Barnett return NULL; 9566d04e62b9SKevin Barnett } 9567d04e62b9SKevin Barnett 9568d04e62b9SKevin Barnett hpsa_sas_port->next_phy_index++; 9569d04e62b9SKevin Barnett hpsa_sas_phy->phy = phy; 9570d04e62b9SKevin Barnett hpsa_sas_phy->parent_port = hpsa_sas_port; 9571d04e62b9SKevin Barnett 9572d04e62b9SKevin Barnett return hpsa_sas_phy; 9573d04e62b9SKevin Barnett } 9574d04e62b9SKevin Barnett 9575d04e62b9SKevin Barnett static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9576d04e62b9SKevin Barnett { 9577d04e62b9SKevin Barnett struct sas_phy *phy = hpsa_sas_phy->phy; 9578d04e62b9SKevin Barnett 9579d04e62b9SKevin Barnett sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); 9580d04e62b9SKevin Barnett if (hpsa_sas_phy->added_to_port) 9581d04e62b9SKevin Barnett list_del(&hpsa_sas_phy->phy_list_entry); 958255ca38b4SMartin Wilck sas_phy_delete(phy); 9583d04e62b9SKevin Barnett kfree(hpsa_sas_phy); 9584d04e62b9SKevin Barnett } 9585d04e62b9SKevin Barnett 9586d04e62b9SKevin Barnett static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9587d04e62b9SKevin Barnett { 9588d04e62b9SKevin Barnett int rc; 9589d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port; 9590d04e62b9SKevin Barnett struct sas_phy *phy; 9591d04e62b9SKevin Barnett struct sas_identify *identify; 9592d04e62b9SKevin Barnett 9593d04e62b9SKevin Barnett hpsa_sas_port = hpsa_sas_phy->parent_port; 9594d04e62b9SKevin Barnett phy = hpsa_sas_phy->phy; 9595d04e62b9SKevin Barnett 9596d04e62b9SKevin Barnett identify = &phy->identify; 9597d04e62b9SKevin Barnett memset(identify, 0, sizeof(*identify)); 9598d04e62b9SKevin Barnett identify->sas_address = hpsa_sas_port->sas_address; 9599d04e62b9SKevin Barnett identify->device_type = SAS_END_DEVICE; 9600d04e62b9SKevin Barnett identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9601d04e62b9SKevin Barnett identify->target_port_protocols = SAS_PROTOCOL_STP; 9602d04e62b9SKevin Barnett phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9603d04e62b9SKevin Barnett phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9604d04e62b9SKevin Barnett phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; 9605d04e62b9SKevin Barnett phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; 9606d04e62b9SKevin Barnett phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; 9607d04e62b9SKevin Barnett 9608d04e62b9SKevin Barnett rc = sas_phy_add(hpsa_sas_phy->phy); 9609d04e62b9SKevin Barnett if (rc) 9610d04e62b9SKevin Barnett return rc; 9611d04e62b9SKevin Barnett 9612d04e62b9SKevin Barnett sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); 9613d04e62b9SKevin Barnett list_add_tail(&hpsa_sas_phy->phy_list_entry, 9614d04e62b9SKevin Barnett &hpsa_sas_port->phy_list_head); 9615d04e62b9SKevin Barnett hpsa_sas_phy->added_to_port = true; 9616d04e62b9SKevin Barnett 9617d04e62b9SKevin Barnett return 0; 9618d04e62b9SKevin Barnett } 9619d04e62b9SKevin Barnett 9620d04e62b9SKevin Barnett static int 9621d04e62b9SKevin Barnett hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, 9622d04e62b9SKevin Barnett struct sas_rphy *rphy) 9623d04e62b9SKevin Barnett { 9624d04e62b9SKevin Barnett struct sas_identify *identify; 9625d04e62b9SKevin Barnett 9626d04e62b9SKevin Barnett identify = &rphy->identify; 9627d04e62b9SKevin Barnett identify->sas_address = hpsa_sas_port->sas_address; 9628d04e62b9SKevin Barnett identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9629d04e62b9SKevin Barnett identify->target_port_protocols = SAS_PROTOCOL_STP; 9630d04e62b9SKevin Barnett 9631d04e62b9SKevin Barnett return sas_rphy_add(rphy); 9632d04e62b9SKevin Barnett } 9633d04e62b9SKevin Barnett 9634d04e62b9SKevin Barnett static struct hpsa_sas_port 9635d04e62b9SKevin Barnett *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, 9636d04e62b9SKevin Barnett u64 sas_address) 9637d04e62b9SKevin Barnett { 9638d04e62b9SKevin Barnett int rc; 9639d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port; 9640d04e62b9SKevin Barnett struct sas_port *port; 9641d04e62b9SKevin Barnett 9642d04e62b9SKevin Barnett hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); 9643d04e62b9SKevin Barnett if (!hpsa_sas_port) 9644d04e62b9SKevin Barnett return NULL; 9645d04e62b9SKevin Barnett 9646d04e62b9SKevin Barnett INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); 9647d04e62b9SKevin Barnett hpsa_sas_port->parent_node = hpsa_sas_node; 9648d04e62b9SKevin Barnett 9649d04e62b9SKevin Barnett port = sas_port_alloc_num(hpsa_sas_node->parent_dev); 9650d04e62b9SKevin Barnett if (!port) 9651d04e62b9SKevin Barnett goto free_hpsa_port; 9652d04e62b9SKevin Barnett 9653d04e62b9SKevin Barnett rc = sas_port_add(port); 9654d04e62b9SKevin Barnett if (rc) 9655d04e62b9SKevin Barnett goto free_sas_port; 9656d04e62b9SKevin Barnett 9657d04e62b9SKevin Barnett hpsa_sas_port->port = port; 9658d04e62b9SKevin Barnett hpsa_sas_port->sas_address = sas_address; 9659d04e62b9SKevin Barnett list_add_tail(&hpsa_sas_port->port_list_entry, 9660d04e62b9SKevin Barnett &hpsa_sas_node->port_list_head); 9661d04e62b9SKevin Barnett 9662d04e62b9SKevin Barnett return hpsa_sas_port; 9663d04e62b9SKevin Barnett 9664d04e62b9SKevin Barnett free_sas_port: 9665d04e62b9SKevin Barnett sas_port_free(port); 9666d04e62b9SKevin Barnett free_hpsa_port: 9667d04e62b9SKevin Barnett kfree(hpsa_sas_port); 9668d04e62b9SKevin Barnett 9669d04e62b9SKevin Barnett return NULL; 9670d04e62b9SKevin Barnett } 9671d04e62b9SKevin Barnett 9672d04e62b9SKevin Barnett static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) 9673d04e62b9SKevin Barnett { 9674d04e62b9SKevin Barnett struct hpsa_sas_phy *hpsa_sas_phy; 9675d04e62b9SKevin Barnett struct hpsa_sas_phy *next; 9676d04e62b9SKevin Barnett 9677d04e62b9SKevin Barnett list_for_each_entry_safe(hpsa_sas_phy, next, 9678d04e62b9SKevin Barnett &hpsa_sas_port->phy_list_head, phy_list_entry) 9679d04e62b9SKevin Barnett hpsa_free_sas_phy(hpsa_sas_phy); 9680d04e62b9SKevin Barnett 9681d04e62b9SKevin Barnett sas_port_delete(hpsa_sas_port->port); 9682d04e62b9SKevin Barnett list_del(&hpsa_sas_port->port_list_entry); 9683d04e62b9SKevin Barnett kfree(hpsa_sas_port); 9684d04e62b9SKevin Barnett } 9685d04e62b9SKevin Barnett 9686d04e62b9SKevin Barnett static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) 9687d04e62b9SKevin Barnett { 9688d04e62b9SKevin Barnett struct hpsa_sas_node *hpsa_sas_node; 9689d04e62b9SKevin Barnett 9690d04e62b9SKevin Barnett hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); 9691d04e62b9SKevin Barnett if (hpsa_sas_node) { 9692d04e62b9SKevin Barnett hpsa_sas_node->parent_dev = parent_dev; 9693d04e62b9SKevin Barnett INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); 9694d04e62b9SKevin Barnett } 9695d04e62b9SKevin Barnett 9696d04e62b9SKevin Barnett return hpsa_sas_node; 9697d04e62b9SKevin Barnett } 9698d04e62b9SKevin Barnett 9699d04e62b9SKevin Barnett static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) 9700d04e62b9SKevin Barnett { 9701d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port; 9702d04e62b9SKevin Barnett struct hpsa_sas_port *next; 9703d04e62b9SKevin Barnett 9704d04e62b9SKevin Barnett if (!hpsa_sas_node) 9705d04e62b9SKevin Barnett return; 9706d04e62b9SKevin Barnett 9707d04e62b9SKevin Barnett list_for_each_entry_safe(hpsa_sas_port, next, 9708d04e62b9SKevin Barnett &hpsa_sas_node->port_list_head, port_list_entry) 9709d04e62b9SKevin Barnett hpsa_free_sas_port(hpsa_sas_port); 9710d04e62b9SKevin Barnett 9711d04e62b9SKevin Barnett kfree(hpsa_sas_node); 9712d04e62b9SKevin Barnett } 9713d04e62b9SKevin Barnett 9714d04e62b9SKevin Barnett static struct hpsa_scsi_dev_t 9715d04e62b9SKevin Barnett *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 9716d04e62b9SKevin Barnett struct sas_rphy *rphy) 9717d04e62b9SKevin Barnett { 9718d04e62b9SKevin Barnett int i; 9719d04e62b9SKevin Barnett struct hpsa_scsi_dev_t *device; 9720d04e62b9SKevin Barnett 9721d04e62b9SKevin Barnett for (i = 0; i < h->ndevices; i++) { 9722d04e62b9SKevin Barnett device = h->dev[i]; 9723d04e62b9SKevin Barnett if (!device->sas_port) 9724d04e62b9SKevin Barnett continue; 9725d04e62b9SKevin Barnett if (device->sas_port->rphy == rphy) 9726d04e62b9SKevin Barnett return device; 9727d04e62b9SKevin Barnett } 9728d04e62b9SKevin Barnett 9729d04e62b9SKevin Barnett return NULL; 9730d04e62b9SKevin Barnett } 9731d04e62b9SKevin Barnett 9732d04e62b9SKevin Barnett static int hpsa_add_sas_host(struct ctlr_info *h) 9733d04e62b9SKevin Barnett { 9734d04e62b9SKevin Barnett int rc; 9735d04e62b9SKevin Barnett struct device *parent_dev; 9736d04e62b9SKevin Barnett struct hpsa_sas_node *hpsa_sas_node; 9737d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port; 9738d04e62b9SKevin Barnett struct hpsa_sas_phy *hpsa_sas_phy; 9739d04e62b9SKevin Barnett 97400a7c3bb8SDon Brace parent_dev = &h->scsi_host->shost_dev; 9741d04e62b9SKevin Barnett 9742d04e62b9SKevin Barnett hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); 9743d04e62b9SKevin Barnett if (!hpsa_sas_node) 9744d04e62b9SKevin Barnett return -ENOMEM; 9745d04e62b9SKevin Barnett 9746d04e62b9SKevin Barnett hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); 9747d04e62b9SKevin Barnett if (!hpsa_sas_port) { 9748d04e62b9SKevin Barnett rc = -ENODEV; 9749d04e62b9SKevin Barnett goto free_sas_node; 9750d04e62b9SKevin Barnett } 9751d04e62b9SKevin Barnett 9752d04e62b9SKevin Barnett hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); 9753d04e62b9SKevin Barnett if (!hpsa_sas_phy) { 9754d04e62b9SKevin Barnett rc = -ENODEV; 9755d04e62b9SKevin Barnett goto free_sas_port; 9756d04e62b9SKevin Barnett } 9757d04e62b9SKevin Barnett 9758d04e62b9SKevin Barnett rc = hpsa_sas_port_add_phy(hpsa_sas_phy); 9759d04e62b9SKevin Barnett if (rc) 9760d04e62b9SKevin Barnett goto free_sas_phy; 9761d04e62b9SKevin Barnett 9762d04e62b9SKevin Barnett h->sas_host = hpsa_sas_node; 9763d04e62b9SKevin Barnett 9764d04e62b9SKevin Barnett return 0; 9765d04e62b9SKevin Barnett 9766d04e62b9SKevin Barnett free_sas_phy: 9767d04e62b9SKevin Barnett hpsa_free_sas_phy(hpsa_sas_phy); 9768d04e62b9SKevin Barnett free_sas_port: 9769d04e62b9SKevin Barnett hpsa_free_sas_port(hpsa_sas_port); 9770d04e62b9SKevin Barnett free_sas_node: 9771d04e62b9SKevin Barnett hpsa_free_sas_node(hpsa_sas_node); 9772d04e62b9SKevin Barnett 9773d04e62b9SKevin Barnett return rc; 9774d04e62b9SKevin Barnett } 9775d04e62b9SKevin Barnett 9776d04e62b9SKevin Barnett static void hpsa_delete_sas_host(struct ctlr_info *h) 9777d04e62b9SKevin Barnett { 9778d04e62b9SKevin Barnett hpsa_free_sas_node(h->sas_host); 9779d04e62b9SKevin Barnett } 9780d04e62b9SKevin Barnett 9781d04e62b9SKevin Barnett static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 9782d04e62b9SKevin Barnett struct hpsa_scsi_dev_t *device) 9783d04e62b9SKevin Barnett { 9784d04e62b9SKevin Barnett int rc; 9785d04e62b9SKevin Barnett struct hpsa_sas_port *hpsa_sas_port; 9786d04e62b9SKevin Barnett struct sas_rphy *rphy; 9787d04e62b9SKevin Barnett 9788d04e62b9SKevin Barnett hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); 9789d04e62b9SKevin Barnett if (!hpsa_sas_port) 9790d04e62b9SKevin Barnett return -ENOMEM; 9791d04e62b9SKevin Barnett 9792d04e62b9SKevin Barnett rphy = sas_end_device_alloc(hpsa_sas_port->port); 9793d04e62b9SKevin Barnett if (!rphy) { 9794d04e62b9SKevin Barnett rc = -ENODEV; 9795d04e62b9SKevin Barnett goto free_sas_port; 9796d04e62b9SKevin Barnett } 9797d04e62b9SKevin Barnett 9798d04e62b9SKevin Barnett hpsa_sas_port->rphy = rphy; 9799d04e62b9SKevin Barnett device->sas_port = hpsa_sas_port; 9800d04e62b9SKevin Barnett 9801d04e62b9SKevin Barnett rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); 9802d04e62b9SKevin Barnett if (rc) 9803d04e62b9SKevin Barnett goto free_sas_port; 9804d04e62b9SKevin Barnett 9805d04e62b9SKevin Barnett return 0; 9806d04e62b9SKevin Barnett 9807d04e62b9SKevin Barnett free_sas_port: 9808d04e62b9SKevin Barnett hpsa_free_sas_port(hpsa_sas_port); 9809d04e62b9SKevin Barnett device->sas_port = NULL; 9810d04e62b9SKevin Barnett 9811d04e62b9SKevin Barnett return rc; 9812d04e62b9SKevin Barnett } 9813d04e62b9SKevin Barnett 9814d04e62b9SKevin Barnett static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) 9815d04e62b9SKevin Barnett { 9816d04e62b9SKevin Barnett if (device->sas_port) { 9817d04e62b9SKevin Barnett hpsa_free_sas_port(device->sas_port); 9818d04e62b9SKevin Barnett device->sas_port = NULL; 9819d04e62b9SKevin Barnett } 9820d04e62b9SKevin Barnett } 9821d04e62b9SKevin Barnett 9822d04e62b9SKevin Barnett static int 9823d04e62b9SKevin Barnett hpsa_sas_get_linkerrors(struct sas_phy *phy) 9824d04e62b9SKevin Barnett { 9825d04e62b9SKevin Barnett return 0; 9826d04e62b9SKevin Barnett } 9827d04e62b9SKevin Barnett 9828d04e62b9SKevin Barnett static int 9829d04e62b9SKevin Barnett hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) 9830d04e62b9SKevin Barnett { 983101d0e789SDon Brace struct Scsi_Host *shost = phy_to_shost(rphy); 983201d0e789SDon Brace struct ctlr_info *h; 983301d0e789SDon Brace struct hpsa_scsi_dev_t *sd; 983401d0e789SDon Brace 983501d0e789SDon Brace if (!shost) 983601d0e789SDon Brace return -ENXIO; 983701d0e789SDon Brace 983801d0e789SDon Brace h = shost_to_hba(shost); 983901d0e789SDon Brace 984001d0e789SDon Brace if (!h) 984101d0e789SDon Brace return -ENXIO; 984201d0e789SDon Brace 984301d0e789SDon Brace sd = hpsa_find_device_by_sas_rphy(h, rphy); 984401d0e789SDon Brace if (!sd) 984501d0e789SDon Brace return -ENXIO; 984601d0e789SDon Brace 984701d0e789SDon Brace *identifier = sd->eli; 984801d0e789SDon Brace 9849d04e62b9SKevin Barnett return 0; 9850d04e62b9SKevin Barnett } 9851d04e62b9SKevin Barnett 9852d04e62b9SKevin Barnett static int 9853d04e62b9SKevin Barnett hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) 9854d04e62b9SKevin Barnett { 9855d04e62b9SKevin Barnett return -ENXIO; 9856d04e62b9SKevin Barnett } 9857d04e62b9SKevin Barnett 9858d04e62b9SKevin Barnett static int 9859d04e62b9SKevin Barnett hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) 9860d04e62b9SKevin Barnett { 9861d04e62b9SKevin Barnett return 0; 9862d04e62b9SKevin Barnett } 9863d04e62b9SKevin Barnett 9864d04e62b9SKevin Barnett static int 9865d04e62b9SKevin Barnett hpsa_sas_phy_enable(struct sas_phy *phy, int enable) 9866d04e62b9SKevin Barnett { 9867d04e62b9SKevin Barnett return 0; 9868d04e62b9SKevin Barnett } 9869d04e62b9SKevin Barnett 9870d04e62b9SKevin Barnett static int 9871d04e62b9SKevin Barnett hpsa_sas_phy_setup(struct sas_phy *phy) 9872d04e62b9SKevin Barnett { 9873d04e62b9SKevin Barnett return 0; 9874d04e62b9SKevin Barnett } 9875d04e62b9SKevin Barnett 9876d04e62b9SKevin Barnett static void 9877d04e62b9SKevin Barnett hpsa_sas_phy_release(struct sas_phy *phy) 9878d04e62b9SKevin Barnett { 9879d04e62b9SKevin Barnett } 9880d04e62b9SKevin Barnett 9881d04e62b9SKevin Barnett static int 9882d04e62b9SKevin Barnett hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) 9883d04e62b9SKevin Barnett { 9884d04e62b9SKevin Barnett return -EINVAL; 9885d04e62b9SKevin Barnett } 9886d04e62b9SKevin Barnett 9887d04e62b9SKevin Barnett static struct sas_function_template hpsa_sas_transport_functions = { 9888d04e62b9SKevin Barnett .get_linkerrors = hpsa_sas_get_linkerrors, 9889d04e62b9SKevin Barnett .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, 9890d04e62b9SKevin Barnett .get_bay_identifier = hpsa_sas_get_bay_identifier, 9891d04e62b9SKevin Barnett .phy_reset = hpsa_sas_phy_reset, 9892d04e62b9SKevin Barnett .phy_enable = hpsa_sas_phy_enable, 9893d04e62b9SKevin Barnett .phy_setup = hpsa_sas_phy_setup, 9894d04e62b9SKevin Barnett .phy_release = hpsa_sas_phy_release, 9895d04e62b9SKevin Barnett .set_phy_speed = hpsa_sas_phy_speed, 9896d04e62b9SKevin Barnett }; 9897d04e62b9SKevin Barnett 9898edd16368SStephen M. Cameron /* 9899edd16368SStephen M. Cameron * This is it. Register the PCI driver information for the cards we control 9900edd16368SStephen M. Cameron * the OS will call our registered routines when it finds one of our cards. 9901edd16368SStephen M. Cameron */ 9902edd16368SStephen M. Cameron static int __init hpsa_init(void) 9903edd16368SStephen M. Cameron { 9904d04e62b9SKevin Barnett int rc; 9905d04e62b9SKevin Barnett 9906d04e62b9SKevin Barnett hpsa_sas_transport_template = 9907d04e62b9SKevin Barnett sas_attach_transport(&hpsa_sas_transport_functions); 9908d04e62b9SKevin Barnett if (!hpsa_sas_transport_template) 9909d04e62b9SKevin Barnett return -ENODEV; 9910d04e62b9SKevin Barnett 9911d04e62b9SKevin Barnett rc = pci_register_driver(&hpsa_pci_driver); 9912d04e62b9SKevin Barnett 9913d04e62b9SKevin Barnett if (rc) 9914d04e62b9SKevin Barnett sas_release_transport(hpsa_sas_transport_template); 9915d04e62b9SKevin Barnett 9916d04e62b9SKevin Barnett return rc; 9917edd16368SStephen M. Cameron } 9918edd16368SStephen M. Cameron 9919edd16368SStephen M. Cameron static void __exit hpsa_cleanup(void) 9920edd16368SStephen M. Cameron { 9921edd16368SStephen M. Cameron pci_unregister_driver(&hpsa_pci_driver); 9922d04e62b9SKevin Barnett sas_release_transport(hpsa_sas_transport_template); 9923edd16368SStephen M. Cameron } 9924edd16368SStephen M. Cameron 9925e1f7de0cSMatt Gates static void __attribute__((unused)) verify_offsets(void) 9926e1f7de0cSMatt Gates { 9927e1f7de0cSMatt Gates #define VERIFY_OFFSET(member, offset) \ 9928dd0e19f3SScott Teel BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) 9929dd0e19f3SScott Teel 9930dd0e19f3SScott Teel VERIFY_OFFSET(structure_size, 0); 9931dd0e19f3SScott Teel VERIFY_OFFSET(volume_blk_size, 4); 9932dd0e19f3SScott Teel VERIFY_OFFSET(volume_blk_cnt, 8); 9933dd0e19f3SScott Teel VERIFY_OFFSET(phys_blk_shift, 16); 9934dd0e19f3SScott Teel VERIFY_OFFSET(parity_rotation_shift, 17); 9935dd0e19f3SScott Teel VERIFY_OFFSET(strip_size, 18); 9936dd0e19f3SScott Teel VERIFY_OFFSET(disk_starting_blk, 20); 9937dd0e19f3SScott Teel VERIFY_OFFSET(disk_blk_cnt, 28); 9938dd0e19f3SScott Teel VERIFY_OFFSET(data_disks_per_row, 36); 9939dd0e19f3SScott Teel VERIFY_OFFSET(metadata_disks_per_row, 38); 9940dd0e19f3SScott Teel VERIFY_OFFSET(row_cnt, 40); 9941dd0e19f3SScott Teel VERIFY_OFFSET(layout_map_count, 42); 9942dd0e19f3SScott Teel VERIFY_OFFSET(flags, 44); 9943dd0e19f3SScott Teel VERIFY_OFFSET(dekindex, 46); 9944dd0e19f3SScott Teel /* VERIFY_OFFSET(reserved, 48 */ 9945dd0e19f3SScott Teel VERIFY_OFFSET(data, 64); 9946dd0e19f3SScott Teel 9947dd0e19f3SScott Teel #undef VERIFY_OFFSET 9948dd0e19f3SScott Teel 9949dd0e19f3SScott Teel #define VERIFY_OFFSET(member, offset) \ 9950b66cc250SMike Miller BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) 9951b66cc250SMike Miller 9952b66cc250SMike Miller VERIFY_OFFSET(IU_type, 0); 9953b66cc250SMike Miller VERIFY_OFFSET(direction, 1); 9954b66cc250SMike Miller VERIFY_OFFSET(reply_queue, 2); 9955b66cc250SMike Miller /* VERIFY_OFFSET(reserved1, 3); */ 9956b66cc250SMike Miller VERIFY_OFFSET(scsi_nexus, 4); 9957b66cc250SMike Miller VERIFY_OFFSET(Tag, 8); 9958b66cc250SMike Miller VERIFY_OFFSET(cdb, 16); 9959b66cc250SMike Miller VERIFY_OFFSET(cciss_lun, 32); 9960b66cc250SMike Miller VERIFY_OFFSET(data_len, 40); 9961b66cc250SMike Miller VERIFY_OFFSET(cmd_priority_task_attr, 44); 9962b66cc250SMike Miller VERIFY_OFFSET(sg_count, 45); 9963b66cc250SMike Miller /* VERIFY_OFFSET(reserved3 */ 9964b66cc250SMike Miller VERIFY_OFFSET(err_ptr, 48); 9965b66cc250SMike Miller VERIFY_OFFSET(err_len, 56); 9966b66cc250SMike Miller /* VERIFY_OFFSET(reserved4 */ 9967b66cc250SMike Miller VERIFY_OFFSET(sg, 64); 9968b66cc250SMike Miller 9969b66cc250SMike Miller #undef VERIFY_OFFSET 9970b66cc250SMike Miller 9971b66cc250SMike Miller #define VERIFY_OFFSET(member, offset) \ 9972e1f7de0cSMatt Gates BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) 9973e1f7de0cSMatt Gates 9974e1f7de0cSMatt Gates VERIFY_OFFSET(dev_handle, 0x00); 9975e1f7de0cSMatt Gates VERIFY_OFFSET(reserved1, 0x02); 9976e1f7de0cSMatt Gates VERIFY_OFFSET(function, 0x03); 9977e1f7de0cSMatt Gates VERIFY_OFFSET(reserved2, 0x04); 9978e1f7de0cSMatt Gates VERIFY_OFFSET(err_info, 0x0C); 9979e1f7de0cSMatt Gates VERIFY_OFFSET(reserved3, 0x10); 9980e1f7de0cSMatt Gates VERIFY_OFFSET(err_info_len, 0x12); 9981e1f7de0cSMatt Gates VERIFY_OFFSET(reserved4, 0x13); 9982e1f7de0cSMatt Gates VERIFY_OFFSET(sgl_offset, 0x14); 9983e1f7de0cSMatt Gates VERIFY_OFFSET(reserved5, 0x15); 9984e1f7de0cSMatt Gates VERIFY_OFFSET(transfer_len, 0x1C); 9985e1f7de0cSMatt Gates VERIFY_OFFSET(reserved6, 0x20); 9986e1f7de0cSMatt Gates VERIFY_OFFSET(io_flags, 0x24); 9987e1f7de0cSMatt Gates VERIFY_OFFSET(reserved7, 0x26); 9988e1f7de0cSMatt Gates VERIFY_OFFSET(LUN, 0x34); 9989e1f7de0cSMatt Gates VERIFY_OFFSET(control, 0x3C); 9990e1f7de0cSMatt Gates VERIFY_OFFSET(CDB, 0x40); 9991e1f7de0cSMatt Gates VERIFY_OFFSET(reserved8, 0x50); 9992e1f7de0cSMatt Gates VERIFY_OFFSET(host_context_flags, 0x60); 9993e1f7de0cSMatt Gates VERIFY_OFFSET(timeout_sec, 0x62); 9994e1f7de0cSMatt Gates VERIFY_OFFSET(ReplyQueue, 0x64); 9995e1f7de0cSMatt Gates VERIFY_OFFSET(reserved9, 0x65); 999650a0decfSStephen M. Cameron VERIFY_OFFSET(tag, 0x68); 9997e1f7de0cSMatt Gates VERIFY_OFFSET(host_addr, 0x70); 9998e1f7de0cSMatt Gates VERIFY_OFFSET(CISS_LUN, 0x78); 9999e1f7de0cSMatt Gates VERIFY_OFFSET(SG, 0x78 + 8); 10000e1f7de0cSMatt Gates #undef VERIFY_OFFSET 10001e1f7de0cSMatt Gates } 10002e1f7de0cSMatt Gates 10003edd16368SStephen M. Cameron module_init(hpsa_init); 10004edd16368SStephen M. Cameron module_exit(hpsa_cleanup); 10005