1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 248e077dbSUma Krishnan /* 348e077dbSUma Krishnan * CXL Flash Device Driver 448e077dbSUma Krishnan * 548e077dbSUma Krishnan * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 648e077dbSUma Krishnan * Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation 748e077dbSUma Krishnan * 848e077dbSUma Krishnan * Copyright (C) 2018 IBM Corporation 948e077dbSUma Krishnan */ 1048e077dbSUma Krishnan 11bc65c1c7SUma Krishnan #define OCXL_MAX_IRQS 4 /* Max interrupts per process */ 12bc65c1c7SUma Krishnan 13bc65c1c7SUma Krishnan struct ocxlflash_irqs { 14bc65c1c7SUma Krishnan int hwirq; 15a06b1cfcSUma Krishnan u32 virq; 16a06b1cfcSUma Krishnan void __iomem *vtrig; 17bc65c1c7SUma Krishnan }; 18bc65c1c7SUma Krishnan 1948e077dbSUma Krishnan /* OCXL hardware AFU associated with the host */ 2048e077dbSUma Krishnan struct ocxl_hw_afu { 21f6b4557cSUma Krishnan struct ocxlflash_context *ocxl_ctx; /* Host context */ 2248e077dbSUma Krishnan struct pci_dev *pdev; /* PCI device */ 2348e077dbSUma Krishnan struct device *dev; /* Generic device */ 248b7a5521SUma Krishnan bool perst_same_image; /* Same image loaded on perst */ 25e9dfcedaSUma Krishnan 26e9dfcedaSUma Krishnan struct ocxl_fn_config fcfg; /* DVSEC config of the function */ 279cc84291SUma Krishnan struct ocxl_afu_config acfg; /* AFU configuration data */ 28e9dfcedaSUma Krishnan 292e222779SUma Krishnan int fn_actag_base; /* Function acTag base */ 302e222779SUma Krishnan int fn_actag_enabled; /* Function acTag number enabled */ 31d926519eSUma Krishnan int afu_actag_base; /* AFU acTag base */ 32d926519eSUma Krishnan int afu_actag_enabled; /* AFU acTag number enabled */ 332e222779SUma Krishnan 3454370503SUma Krishnan phys_addr_t ppmmio_phys; /* Per process MMIO space */ 3554370503SUma Krishnan phys_addr_t gmmio_phys; /* Global AFU MMIO space */ 3654370503SUma Krishnan void __iomem *gmmio_virt; /* Global MMIO map */ 3754370503SUma Krishnan 3873904823SUma Krishnan void *link_token; /* Link token for the SPA */ 39429ebfa6SUma Krishnan struct idr idr; /* IDR to manage contexts */ 4041df40d8SUma Krishnan int max_pasid; /* Maximum number of contexts */ 41e9dfcedaSUma Krishnan bool is_present; /* Function has AFUs defined */ 4248e077dbSUma Krishnan }; 43f6b4557cSUma Krishnan 44f81face7SUma Krishnan enum ocxlflash_ctx_state { 45f81face7SUma Krishnan CLOSED, 46f81face7SUma Krishnan OPENED, 47f81face7SUma Krishnan STARTED 48f81face7SUma Krishnan }; 49f81face7SUma Krishnan 50f6b4557cSUma Krishnan struct ocxlflash_context { 51f6b4557cSUma Krishnan struct ocxl_hw_afu *hw_afu; /* HW AFU back pointer */ 52926a62f9SUma Krishnan struct address_space *mapping; /* Mapping for pseudo filesystem */ 53f6b4557cSUma Krishnan bool master; /* Whether this is a master context */ 54429ebfa6SUma Krishnan int pe; /* Process element */ 556b938ac9SUma Krishnan 566b938ac9SUma Krishnan phys_addr_t psn_phys; /* Process mapping */ 576b938ac9SUma Krishnan u64 psn_size; /* Process mapping size */ 58bc65c1c7SUma Krishnan 59762c7e93SUma Krishnan spinlock_t slock; /* Protects irq/fault/event updates */ 6056f1db1aSUma Krishnan wait_queue_head_t wq; /* Wait queue for poll and interrupts */ 61f81face7SUma Krishnan struct mutex state_mutex; /* Mutex to update context state */ 62f81face7SUma Krishnan enum ocxlflash_ctx_state state; /* Context state */ 6356f1db1aSUma Krishnan 64bc65c1c7SUma Krishnan struct ocxlflash_irqs *irqs; /* Pointer to array of structures */ 65bc65c1c7SUma Krishnan int num_irqs; /* Number of interrupts */ 66762c7e93SUma Krishnan bool pending_irq; /* Pending interrupt on the context */ 67762c7e93SUma Krishnan ulong irq_bitmap; /* Bits indicating pending irq num */ 6866ae644bSUma Krishnan 6966ae644bSUma Krishnan u64 fault_addr; /* Address that triggered the fault */ 7066ae644bSUma Krishnan u64 fault_dsisr; /* Value of dsisr register at fault */ 7166ae644bSUma Krishnan bool pending_fault; /* Pending translation fault */ 72f6b4557cSUma Krishnan }; 73