1f39a7757SVikas Chaudhary /* bnx2i.h: QLogic NetXtreme II iSCSI driver. 2cf4e6363SMichael Chan * 30b3bf387SEddie Wai * Copyright (c) 2006 - 2013 Broadcom Corporation 4cf4e6363SMichael Chan * Copyright (c) 2007, 2008 Red Hat, Inc. All rights reserved. 5cf4e6363SMichael Chan * Copyright (c) 2007, 2008 Mike Christie 6f39a7757SVikas Chaudhary * Copyright (c) 2014, QLogic Corporation 7cf4e6363SMichael Chan * 8cf4e6363SMichael Chan * This program is free software; you can redistribute it and/or modify 9cf4e6363SMichael Chan * it under the terms of the GNU General Public License as published by 10cf4e6363SMichael Chan * the Free Software Foundation. 11cf4e6363SMichael Chan * 12cf4e6363SMichael Chan * Written by: Anil Veerabhadrappa (anilgv@broadcom.com) 13f39a7757SVikas Chaudhary * Previously Maintained by: Eddie Wai (eddie.wai@broadcom.com) 14f39a7757SVikas Chaudhary * Maintained by: QLogic-Storage-Upstream@qlogic.com 15cf4e6363SMichael Chan */ 16cf4e6363SMichael Chan 17cf4e6363SMichael Chan #ifndef _BNX2I_H_ 18cf4e6363SMichael Chan #define _BNX2I_H_ 19cf4e6363SMichael Chan 20cf4e6363SMichael Chan #include <linux/module.h> 21cf4e6363SMichael Chan #include <linux/moduleparam.h> 22cf4e6363SMichael Chan 23cf4e6363SMichael Chan #include <linux/errno.h> 24cf4e6363SMichael Chan #include <linux/pci.h> 25cf4e6363SMichael Chan #include <linux/spinlock.h> 26cf4e6363SMichael Chan #include <linux/interrupt.h> 27b5cf6b63SEddie Wai #include <linux/delay.h> 283f07c014SIngo Molnar #include <linux/sched/signal.h> 29cf4e6363SMichael Chan #include <linux/in.h> 30cf4e6363SMichael Chan #include <linux/kfifo.h> 31cf4e6363SMichael Chan #include <linux/netdevice.h> 32cf4e6363SMichael Chan #include <linux/completion.h> 33b5cf6b63SEddie Wai #include <linux/kthread.h> 34b5cf6b63SEddie Wai #include <linux/cpu.h> 35cf4e6363SMichael Chan 36cf4e6363SMichael Chan #include <scsi/scsi_cmnd.h> 37cf4e6363SMichael Chan #include <scsi/scsi_device.h> 38cf4e6363SMichael Chan #include <scsi/scsi_eh.h> 39cf4e6363SMichael Chan #include <scsi/scsi_host.h> 40cf4e6363SMichael Chan #include <scsi/scsi.h> 41cf4e6363SMichael Chan #include <scsi/iscsi_proto.h> 42cf4e6363SMichael Chan #include <scsi/libiscsi.h> 43cf4e6363SMichael Chan #include <scsi/scsi_transport_iscsi.h> 44cf4e6363SMichael Chan 45adfc5217SJeff Kirsher #include "../../net/ethernet/broadcom/cnic_if.h" 46cf4e6363SMichael Chan #include "57xx_iscsi_hsi.h" 47cf4e6363SMichael Chan #include "57xx_iscsi_constants.h" 48cf4e6363SMichael Chan 492e499d3cSBarak Witkowski #include "../../net/ethernet/broadcom/bnx2x/bnx2x_mfw_req.h" 502e499d3cSBarak Witkowski 51cf4e6363SMichael Chan #define BNX2_ISCSI_DRIVER_NAME "bnx2i" 52cf4e6363SMichael Chan 53cf4e6363SMichael Chan #define BNX2I_MAX_ADAPTERS 8 54cf4e6363SMichael Chan 55cf4e6363SMichael Chan #define ISCSI_MAX_CONNS_PER_HBA 128 56cf4e6363SMichael Chan #define ISCSI_MAX_SESS_PER_HBA ISCSI_MAX_CONNS_PER_HBA 57cf4e6363SMichael Chan #define ISCSI_MAX_CMDS_PER_SESS 128 58cf4e6363SMichael Chan 59cf4e6363SMichael Chan /* Total active commands across all connections supported by devices */ 60cf4e6363SMichael Chan #define ISCSI_MAX_CMDS_PER_HBA_5708 (28 * (ISCSI_MAX_CMDS_PER_SESS - 1)) 61cf4e6363SMichael Chan #define ISCSI_MAX_CMDS_PER_HBA_5709 (128 * (ISCSI_MAX_CMDS_PER_SESS - 1)) 62cf4e6363SMichael Chan #define ISCSI_MAX_CMDS_PER_HBA_57710 (256 * (ISCSI_MAX_CMDS_PER_SESS - 1)) 63cf4e6363SMichael Chan 64cf4e6363SMichael Chan #define ISCSI_MAX_BDS_PER_CMD 32 65cf4e6363SMichael Chan 66cf4e6363SMichael Chan #define MAX_PAGES_PER_CTRL_STRUCT_POOL 8 67cf4e6363SMichael Chan #define BNX2I_RESERVED_SLOW_PATH_CMD_SLOTS 4 68cf4e6363SMichael Chan 69f78afb35SMichael Chan #define BNX2X_DB_SHIFT 3 70523224a3SDmitry Kravkov 71cf4e6363SMichael Chan /* 5706/08 hardware has limit on maximum buffer size per BD it can handle */ 72cf4e6363SMichael Chan #define MAX_BD_LENGTH 65535 73cf4e6363SMichael Chan #define BD_SPLIT_SIZE 32768 74cf4e6363SMichael Chan 75cf4e6363SMichael Chan /* min, max & default values for SQ/RQ/CQ size, configurable via' modparam */ 76cf4e6363SMichael Chan #define BNX2I_SQ_WQES_MIN 16 77cf4e6363SMichael Chan #define BNX2I_570X_SQ_WQES_MAX 128 78cf4e6363SMichael Chan #define BNX2I_5770X_SQ_WQES_MAX 512 79cf4e6363SMichael Chan #define BNX2I_570X_SQ_WQES_DEFAULT 128 809ae58e14SEddie Wai #define BNX2I_5770X_SQ_WQES_DEFAULT 128 81cf4e6363SMichael Chan 82cf4e6363SMichael Chan #define BNX2I_570X_CQ_WQES_MAX 128 83cf4e6363SMichael Chan #define BNX2I_5770X_CQ_WQES_MAX 512 84cf4e6363SMichael Chan 85cf4e6363SMichael Chan #define BNX2I_RQ_WQES_MIN 16 86cf4e6363SMichael Chan #define BNX2I_RQ_WQES_MAX 32 87cf4e6363SMichael Chan #define BNX2I_RQ_WQES_DEFAULT 16 88cf4e6363SMichael Chan 89cf4e6363SMichael Chan /* CCELLs per conn */ 90cf4e6363SMichael Chan #define BNX2I_CCELLS_MIN 16 91cf4e6363SMichael Chan #define BNX2I_CCELLS_MAX 96 92cf4e6363SMichael Chan #define BNX2I_CCELLS_DEFAULT 64 93cf4e6363SMichael Chan 94cf4e6363SMichael Chan #define ITT_INVALID_SIGNATURE 0xFFFF 95cf4e6363SMichael Chan 96cf4e6363SMichael Chan #define ISCSI_CMD_CLEANUP_TIMEOUT 100 97cf4e6363SMichael Chan 98cf4e6363SMichael Chan #define BNX2I_CONN_CTX_BUF_SIZE 16384 99cf4e6363SMichael Chan 100cf4e6363SMichael Chan #define BNX2I_SQ_WQE_SIZE 64 101cf4e6363SMichael Chan #define BNX2I_RQ_WQE_SIZE 256 102cf4e6363SMichael Chan #define BNX2I_CQE_SIZE 64 103cf4e6363SMichael Chan 104cf4e6363SMichael Chan #define MB_KERNEL_CTX_SHIFT 8 105cf4e6363SMichael Chan #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) 106cf4e6363SMichael Chan 107cf4e6363SMichael Chan #define CTX_SHIFT 7 108cf4e6363SMichael Chan #define GET_CID_NUM(cid_addr) ((cid_addr) >> CTX_SHIFT) 109cf4e6363SMichael Chan 110cf4e6363SMichael Chan #define CTX_OFFSET 0x10000 111cf4e6363SMichael Chan #define MAX_CID_CNT 0x4000 112cf4e6363SMichael Chan 11353203244SAnil Veerabhadrappa #define BNX2I_570X_PAGE_SIZE_DEFAULT 4096 11453203244SAnil Veerabhadrappa 115cf4e6363SMichael Chan /* 5709 context registers */ 116cf4e6363SMichael Chan #define BNX2_MQ_CONFIG2 0x00003d00 117cf4e6363SMichael Chan #define BNX2_MQ_CONFIG2_CONT_SZ (0x7L<<4) 118cf4e6363SMichael Chan #define BNX2_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8) 119cf4e6363SMichael Chan 120cf4e6363SMichael Chan /* 57710's BAR2 is mapped to doorbell registers */ 121cf4e6363SMichael Chan #define BNX2X_DOORBELL_PCI_BAR 2 122cf4e6363SMichael Chan #define BNX2X_MAX_CQS 8 123cf4e6363SMichael Chan 124cf4e6363SMichael Chan #define CNIC_ARM_CQE 1 1259ae58e14SEddie Wai #define CNIC_ARM_CQE_FP 2 126cf4e6363SMichael Chan #define CNIC_DISARM_CQE 0 127cf4e6363SMichael Chan 128cf4e6363SMichael Chan #define REG_RD(__hba, offset) \ 129cf4e6363SMichael Chan readl(__hba->regview + offset) 130cf4e6363SMichael Chan #define REG_WR(__hba, offset, val) \ 131cf4e6363SMichael Chan writel(val, __hba->regview + offset) 132cf4e6363SMichael Chan 1332e499d3cSBarak Witkowski #ifdef CONFIG_32BIT 1342e499d3cSBarak Witkowski #define GET_STATS_64(__hba, dst, field) \ 1352e499d3cSBarak Witkowski do { \ 1362e499d3cSBarak Witkowski spin_lock_bh(&__hba->stat_lock); \ 1372e499d3cSBarak Witkowski dst->field##_lo = __hba->stats.field##_lo; \ 1382e499d3cSBarak Witkowski dst->field##_hi = __hba->stats.field##_hi; \ 1392e499d3cSBarak Witkowski spin_unlock_bh(&__hba->stat_lock); \ 1402e499d3cSBarak Witkowski } while (0) 1412e499d3cSBarak Witkowski 1422e499d3cSBarak Witkowski #define ADD_STATS_64(__hba, field, len) \ 1432e499d3cSBarak Witkowski do { \ 1442e499d3cSBarak Witkowski if (spin_trylock(&__hba->stat_lock)) { \ 1452e499d3cSBarak Witkowski if (__hba->stats.field##_lo + len < \ 1462e499d3cSBarak Witkowski __hba->stats.field##_lo) \ 1472e499d3cSBarak Witkowski __hba->stats.field##_hi++; \ 1482e499d3cSBarak Witkowski __hba->stats.field##_lo += len; \ 1492e499d3cSBarak Witkowski spin_unlock(&__hba->stat_lock); \ 1502e499d3cSBarak Witkowski } \ 1512e499d3cSBarak Witkowski } while (0) 1522e499d3cSBarak Witkowski 1532e499d3cSBarak Witkowski #else 1542e499d3cSBarak Witkowski #define GET_STATS_64(__hba, dst, field) \ 1552e499d3cSBarak Witkowski do { \ 1562e499d3cSBarak Witkowski u64 val, *out; \ 1572e499d3cSBarak Witkowski \ 1582e499d3cSBarak Witkowski val = __hba->bnx2i_stats.field; \ 1592e499d3cSBarak Witkowski out = (u64 *)&__hba->stats.field##_lo; \ 1602e499d3cSBarak Witkowski *out = cpu_to_le64(val); \ 1612e499d3cSBarak Witkowski out = (u64 *)&dst->field##_lo; \ 1622e499d3cSBarak Witkowski *out = cpu_to_le64(val); \ 1632e499d3cSBarak Witkowski } while (0) 1642e499d3cSBarak Witkowski 1652e499d3cSBarak Witkowski #define ADD_STATS_64(__hba, field, len) \ 1662e499d3cSBarak Witkowski do { \ 1672e499d3cSBarak Witkowski __hba->bnx2i_stats.field += len; \ 1682e499d3cSBarak Witkowski } while (0) 1692e499d3cSBarak Witkowski #endif 170cf4e6363SMichael Chan 171cf4e6363SMichael Chan /** 172cf4e6363SMichael Chan * struct generic_pdu_resc - login pdu resource structure 173cf4e6363SMichael Chan * 174cf4e6363SMichael Chan * @req_buf: driver buffer used to stage payload associated with 175cf4e6363SMichael Chan * the login request 176cf4e6363SMichael Chan * @req_dma_addr: dma address for iscsi login request payload buffer 177cf4e6363SMichael Chan * @req_buf_size: actual login request payload length 178cf4e6363SMichael Chan * @req_wr_ptr: pointer into login request buffer when next data is 179cf4e6363SMichael Chan * to be written 180cf4e6363SMichael Chan * @resp_hdr: iscsi header where iscsi login response header is to 181cf4e6363SMichael Chan * be recreated 182cf4e6363SMichael Chan * @resp_buf: buffer to stage login response payload 183cf4e6363SMichael Chan * @resp_dma_addr: login response payload buffer dma address 184cf4e6363SMichael Chan * @resp_buf_size: login response paylod length 185cf4e6363SMichael Chan * @resp_wr_ptr: pointer into login response buffer when next data is 186cf4e6363SMichael Chan * to be written 187cf4e6363SMichael Chan * @req_bd_tbl: iscsi login request payload BD table 188cf4e6363SMichael Chan * @req_bd_dma: login request BD table dma address 189cf4e6363SMichael Chan * @resp_bd_tbl: iscsi login response payload BD table 190cf4e6363SMichael Chan * @resp_bd_dma: login request BD table dma address 191cf4e6363SMichael Chan * 192cf4e6363SMichael Chan * following structure defines buffer info for generic pdus such as iSCSI Login, 193cf4e6363SMichael Chan * Logout and NOP 194cf4e6363SMichael Chan */ 195cf4e6363SMichael Chan struct generic_pdu_resc { 196cf4e6363SMichael Chan char *req_buf; 197cf4e6363SMichael Chan dma_addr_t req_dma_addr; 198cf4e6363SMichael Chan u32 req_buf_size; 199cf4e6363SMichael Chan char *req_wr_ptr; 200cf4e6363SMichael Chan struct iscsi_hdr resp_hdr; 201cf4e6363SMichael Chan char *resp_buf; 202cf4e6363SMichael Chan dma_addr_t resp_dma_addr; 203cf4e6363SMichael Chan u32 resp_buf_size; 204cf4e6363SMichael Chan char *resp_wr_ptr; 205cf4e6363SMichael Chan char *req_bd_tbl; 206cf4e6363SMichael Chan dma_addr_t req_bd_dma; 207cf4e6363SMichael Chan char *resp_bd_tbl; 208cf4e6363SMichael Chan dma_addr_t resp_bd_dma; 209cf4e6363SMichael Chan }; 210cf4e6363SMichael Chan 211cf4e6363SMichael Chan 212cf4e6363SMichael Chan /** 213cf4e6363SMichael Chan * struct bd_resc_page - tracks DMA'able memory allocated for BD tables 214cf4e6363SMichael Chan * 215cf4e6363SMichael Chan * @link: list head to link elements 216cf4e6363SMichael Chan * @max_ptrs: maximun pointers that can be stored in this page 217cf4e6363SMichael Chan * @num_valid: number of pointer valid in this page 218cf4e6363SMichael Chan * @page: base addess for page pointer array 219cf4e6363SMichael Chan * 220cf4e6363SMichael Chan * structure to track DMA'able memory allocated for command BD tables 221cf4e6363SMichael Chan */ 222cf4e6363SMichael Chan struct bd_resc_page { 223cf4e6363SMichael Chan struct list_head link; 224cf4e6363SMichael Chan u32 max_ptrs; 225cf4e6363SMichael Chan u32 num_valid; 226cf4e6363SMichael Chan void *page[1]; 227cf4e6363SMichael Chan }; 228cf4e6363SMichael Chan 229cf4e6363SMichael Chan 230cf4e6363SMichael Chan /** 231cf4e6363SMichael Chan * struct io_bdt - I/O buffer destricptor table 232cf4e6363SMichael Chan * 233cf4e6363SMichael Chan * @bd_tbl: BD table's virtual address 234cf4e6363SMichael Chan * @bd_tbl_dma: BD table's dma address 235cf4e6363SMichael Chan * @bd_valid: num valid BD entries 236cf4e6363SMichael Chan * 237cf4e6363SMichael Chan * IO BD table 238cf4e6363SMichael Chan */ 239cf4e6363SMichael Chan struct io_bdt { 240cf4e6363SMichael Chan struct iscsi_bd *bd_tbl; 241cf4e6363SMichael Chan dma_addr_t bd_tbl_dma; 242cf4e6363SMichael Chan u16 bd_valid; 243cf4e6363SMichael Chan }; 244cf4e6363SMichael Chan 245cf4e6363SMichael Chan 246cf4e6363SMichael Chan /** 247cf4e6363SMichael Chan * bnx2i_cmd - iscsi command structure 248cf4e6363SMichael Chan * 249b5cf6b63SEddie Wai * @hdr: iSCSI header 250b5cf6b63SEddie Wai * @conn: iscsi_conn pointer 251cf4e6363SMichael Chan * @scsi_cmd: SCSI-ML task pointer corresponding to this iscsi cmd 252cf4e6363SMichael Chan * @sg: SG list 253cf4e6363SMichael Chan * @io_tbl: buffer descriptor (BD) table 254cf4e6363SMichael Chan * @bd_tbl_dma: buffer descriptor (BD) table's dma address 255b5cf6b63SEddie Wai * @req: bnx2i specific command request struct 256cf4e6363SMichael Chan */ 257cf4e6363SMichael Chan struct bnx2i_cmd { 258cf4e6363SMichael Chan struct iscsi_hdr hdr; 259cf4e6363SMichael Chan struct bnx2i_conn *conn; 260cf4e6363SMichael Chan struct scsi_cmnd *scsi_cmd; 261cf4e6363SMichael Chan struct scatterlist *sg; 262cf4e6363SMichael Chan struct io_bdt io_tbl; 263cf4e6363SMichael Chan dma_addr_t bd_tbl_dma; 264cf4e6363SMichael Chan struct bnx2i_cmd_request req; 265cf4e6363SMichael Chan }; 266cf4e6363SMichael Chan 267cf4e6363SMichael Chan 268cf4e6363SMichael Chan /** 269cf4e6363SMichael Chan * struct bnx2i_conn - iscsi connection structure 270cf4e6363SMichael Chan * 271cf4e6363SMichael Chan * @cls_conn: pointer to iscsi cls conn 272cf4e6363SMichael Chan * @hba: adapter structure pointer 273cf4e6363SMichael Chan * @iscsi_conn_cid: iscsi conn id 274cf4e6363SMichael Chan * @fw_cid: firmware iscsi context id 275cf4e6363SMichael Chan * @ep: endpoint structure pointer 276cf4e6363SMichael Chan * @gen_pdu: login/nopout/logout pdu resources 277cf4e6363SMichael Chan * @violation_notified: bit mask used to track iscsi error/warning messages 278cf4e6363SMichael Chan * already printed out 279b5cf6b63SEddie Wai * @work_cnt: keeps track of the number of outstanding work 280cf4e6363SMichael Chan * 281cf4e6363SMichael Chan * iSCSI connection structure 282cf4e6363SMichael Chan */ 283cf4e6363SMichael Chan struct bnx2i_conn { 284cf4e6363SMichael Chan struct iscsi_cls_conn *cls_conn; 285cf4e6363SMichael Chan struct bnx2i_hba *hba; 286cf4e6363SMichael Chan struct completion cmd_cleanup_cmpl; 287cf4e6363SMichael Chan 288cf4e6363SMichael Chan u32 iscsi_conn_cid; 289cf4e6363SMichael Chan #define BNX2I_CID_RESERVED 0x5AFF 290cf4e6363SMichael Chan u32 fw_cid; 291cf4e6363SMichael Chan 292cf4e6363SMichael Chan struct timer_list poll_timer; 293cf4e6363SMichael Chan /* 294cf4e6363SMichael Chan * Queue Pair (QP) related structure elements. 295cf4e6363SMichael Chan */ 296cf4e6363SMichael Chan struct bnx2i_endpoint *ep; 297cf4e6363SMichael Chan 298cf4e6363SMichael Chan /* 299cf4e6363SMichael Chan * Buffer for login negotiation process 300cf4e6363SMichael Chan */ 301cf4e6363SMichael Chan struct generic_pdu_resc gen_pdu; 302cf4e6363SMichael Chan u64 violation_notified; 303b5cf6b63SEddie Wai 304b5cf6b63SEddie Wai atomic_t work_cnt; 305cf4e6363SMichael Chan }; 306cf4e6363SMichael Chan 307cf4e6363SMichael Chan 308cf4e6363SMichael Chan 309cf4e6363SMichael Chan /** 310cf4e6363SMichael Chan * struct iscsi_cid_queue - Per adapter iscsi cid queue 311cf4e6363SMichael Chan * 312cf4e6363SMichael Chan * @cid_que_base: queue base memory 313cf4e6363SMichael Chan * @cid_que: queue memory pointer 314cf4e6363SMichael Chan * @cid_q_prod_idx: produce index 315cf4e6363SMichael Chan * @cid_q_cons_idx: consumer index 316cf4e6363SMichael Chan * @cid_q_max_idx: max index. used to detect wrap around condition 317cf4e6363SMichael Chan * @cid_free_cnt: queue size 318cf4e6363SMichael Chan * @conn_cid_tbl: iscsi cid to conn structure mapping table 319cf4e6363SMichael Chan * 320cf4e6363SMichael Chan * Per adapter iSCSI CID Queue 321cf4e6363SMichael Chan */ 322cf4e6363SMichael Chan struct iscsi_cid_queue { 323cf4e6363SMichael Chan void *cid_que_base; 324cf4e6363SMichael Chan u32 *cid_que; 325cf4e6363SMichael Chan u32 cid_q_prod_idx; 326cf4e6363SMichael Chan u32 cid_q_cons_idx; 327cf4e6363SMichael Chan u32 cid_q_max_idx; 328cf4e6363SMichael Chan u32 cid_free_cnt; 329cf4e6363SMichael Chan struct bnx2i_conn **conn_cid_tbl; 330cf4e6363SMichael Chan }; 331cf4e6363SMichael Chan 3322e499d3cSBarak Witkowski 3332e499d3cSBarak Witkowski struct bnx2i_stats_info { 3342e499d3cSBarak Witkowski u64 rx_pdus; 3352e499d3cSBarak Witkowski u64 rx_bytes; 3362e499d3cSBarak Witkowski u64 tx_pdus; 3372e499d3cSBarak Witkowski u64 tx_bytes; 3382e499d3cSBarak Witkowski }; 3392e499d3cSBarak Witkowski 3402e499d3cSBarak Witkowski 341cf4e6363SMichael Chan /** 342cf4e6363SMichael Chan * struct bnx2i_hba - bnx2i adapter structure 343cf4e6363SMichael Chan * 344cf4e6363SMichael Chan * @link: list head to link elements 345cf4e6363SMichael Chan * @cnic: pointer to cnic device 346cf4e6363SMichael Chan * @pcidev: pointer to pci dev 347cf4e6363SMichael Chan * @netdev: pointer to netdev structure 348cf4e6363SMichael Chan * @regview: mapped PCI register space 349cf4e6363SMichael Chan * @age: age, incremented by every recovery 350cf4e6363SMichael Chan * @cnic_dev_type: cnic device type, 5706/5708/5709/57710 351cf4e6363SMichael Chan * @mail_queue_access: mailbox queue access mode, applicable to 5709 only 352cf4e6363SMichael Chan * @reg_with_cnic: indicates whether the device is register with CNIC 353cf4e6363SMichael Chan * @adapter_state: adapter state, UP, GOING_DOWN, LINK_DOWN 354cf4e6363SMichael Chan * @mtu_supported: Ethernet MTU supported 355cf4e6363SMichael Chan * @shost: scsi host pointer 356cf4e6363SMichael Chan * @max_sqes: SQ size 357cf4e6363SMichael Chan * @max_rqes: RQ size 358cf4e6363SMichael Chan * @max_cqes: CQ size 359cf4e6363SMichael Chan * @num_ccell: number of command cells per connection 360cf4e6363SMichael Chan * @ofld_conns_active: active connection list 36155e15c97SEddie Wai * @eh_wait: wait queue for the endpoint to shutdown 362cf4e6363SMichael Chan * @max_active_conns: max offload connections supported by this device 363cf4e6363SMichael Chan * @cid_que: iscsi cid queue 364cf4e6363SMichael Chan * @ep_rdwr_lock: read / write lock to synchronize various ep lists 365cf4e6363SMichael Chan * @ep_ofld_list: connection list for pending offload completion 36646012e8bSEddie Wai * @ep_active_list: connection list for active offload endpoints 367cf4e6363SMichael Chan * @ep_destroy_list: connection list for pending offload completion 368cf4e6363SMichael Chan * @mp_bd_tbl: BD table to be used with middle path requests 369cf4e6363SMichael Chan * @mp_bd_dma: DMA address of 'mp_bd_tbl' memory buffer 370cf4e6363SMichael Chan * @dummy_buffer: Dummy buffer to be used with zero length scsicmd reqs 371cf4e6363SMichael Chan * @dummy_buf_dma: DMA address of 'dummy_buffer' memory buffer 372cf4e6363SMichael Chan * @lock: lock to synchonize access to hba structure 37355e15c97SEddie Wai * @hba_shutdown_tmo: Timeout value to shutdown each connection 374e37d2c47SEddie Wai * @conn_teardown_tmo: Timeout value to tear down each connection 375e37d2c47SEddie Wai * @conn_ctx_destroy_tmo: Timeout value to destroy context of each connection 376cf4e6363SMichael Chan * @pci_did: PCI device ID 377cf4e6363SMichael Chan * @pci_vid: PCI vendor ID 378cf4e6363SMichael Chan * @pci_sdid: PCI subsystem device ID 379cf4e6363SMichael Chan * @pci_svid: PCI subsystem vendor ID 380cf4e6363SMichael Chan * @pci_func: PCI function number in system pci tree 381cf4e6363SMichael Chan * @pci_devno: PCI device number in system pci tree 382cf4e6363SMichael Chan * @num_wqe_sent: statistic counter, total wqe's sent 383cf4e6363SMichael Chan * @num_cqe_rcvd: statistic counter, total cqe's received 384cf4e6363SMichael Chan * @num_intr_claimed: statistic counter, total interrupts claimed 385cf4e6363SMichael Chan * @link_changed_count: statistic counter, num of link change notifications 386cf4e6363SMichael Chan * received 387cf4e6363SMichael Chan * @ipaddr_changed_count: statistic counter, num times IP address changed while 388cf4e6363SMichael Chan * at least one connection is offloaded 389cf4e6363SMichael Chan * @num_sess_opened: statistic counter, total num sessions opened 390cf4e6363SMichael Chan * @num_conn_opened: statistic counter, total num conns opened on this hba 391cf4e6363SMichael Chan * @ctx_ccell_tasks: captures number of ccells and tasks supported by 392cf4e6363SMichael Chan * currently offloaded connection, used to decode 393cf4e6363SMichael Chan * context memory 3942e499d3cSBarak Witkowski * @stat_lock: spin lock used by the statistic collector (32 bit) 3952e499d3cSBarak Witkowski * @stats: local iSCSI statistic collection place holder 396cf4e6363SMichael Chan * 397cf4e6363SMichael Chan * Adapter Data Structure 398cf4e6363SMichael Chan */ 399cf4e6363SMichael Chan struct bnx2i_hba { 400cf4e6363SMichael Chan struct list_head link; 401cf4e6363SMichael Chan struct cnic_dev *cnic; 402cf4e6363SMichael Chan struct pci_dev *pcidev; 403cf4e6363SMichael Chan struct net_device *netdev; 404cf4e6363SMichael Chan void __iomem *regview; 405a7717180SEddie Wai resource_size_t reg_base; 406cf4e6363SMichael Chan 407cf4e6363SMichael Chan u32 age; 408cf4e6363SMichael Chan unsigned long cnic_dev_type; 409cf4e6363SMichael Chan #define BNX2I_NX2_DEV_5706 0x0 410cf4e6363SMichael Chan #define BNX2I_NX2_DEV_5708 0x1 411cf4e6363SMichael Chan #define BNX2I_NX2_DEV_5709 0x2 412cf4e6363SMichael Chan #define BNX2I_NX2_DEV_57710 0x3 413cf4e6363SMichael Chan u32 mail_queue_access; 414cf4e6363SMichael Chan #define BNX2I_MQ_KERNEL_MODE 0x0 415cf4e6363SMichael Chan #define BNX2I_MQ_KERNEL_BYPASS_MODE 0x1 416cf4e6363SMichael Chan #define BNX2I_MQ_BIN_MODE 0x2 417cf4e6363SMichael Chan unsigned long reg_with_cnic; 418cf4e6363SMichael Chan #define BNX2I_CNIC_REGISTERED 1 419cf4e6363SMichael Chan 420cf4e6363SMichael Chan unsigned long adapter_state; 421cf4e6363SMichael Chan #define ADAPTER_STATE_UP 0 422cf4e6363SMichael Chan #define ADAPTER_STATE_GOING_DOWN 1 423cf4e6363SMichael Chan #define ADAPTER_STATE_LINK_DOWN 2 424cf4e6363SMichael Chan #define ADAPTER_STATE_INIT_FAILED 31 425cf4e6363SMichael Chan unsigned int mtu_supported; 42645188354SEddie Wai #define BNX2I_MAX_MTU_SUPPORTED 9000 427cf4e6363SMichael Chan 428cf4e6363SMichael Chan struct Scsi_Host *shost; 429cf4e6363SMichael Chan 430cf4e6363SMichael Chan u32 max_sqes; 431cf4e6363SMichael Chan u32 max_rqes; 432cf4e6363SMichael Chan u32 max_cqes; 433cf4e6363SMichael Chan u32 num_ccell; 434cf4e6363SMichael Chan 435cf4e6363SMichael Chan int ofld_conns_active; 436490475a9SAnil Veerabhadrappa wait_queue_head_t eh_wait; 437cf4e6363SMichael Chan 438cf4e6363SMichael Chan int max_active_conns; 439cf4e6363SMichael Chan struct iscsi_cid_queue cid_que; 440cf4e6363SMichael Chan 441cf4e6363SMichael Chan rwlock_t ep_rdwr_lock; 442cf4e6363SMichael Chan struct list_head ep_ofld_list; 44346012e8bSEddie Wai struct list_head ep_active_list; 444cf4e6363SMichael Chan struct list_head ep_destroy_list; 445cf4e6363SMichael Chan 446cf4e6363SMichael Chan /* 447cf4e6363SMichael Chan * BD table to be used with MP (Middle Path requests. 448cf4e6363SMichael Chan */ 449cf4e6363SMichael Chan char *mp_bd_tbl; 450cf4e6363SMichael Chan dma_addr_t mp_bd_dma; 451cf4e6363SMichael Chan char *dummy_buffer; 452cf4e6363SMichael Chan dma_addr_t dummy_buf_dma; 453cf4e6363SMichael Chan 454cf4e6363SMichael Chan spinlock_t lock; /* protects hba structure access */ 455cf4e6363SMichael Chan struct mutex net_dev_lock;/* sync net device access */ 456cf4e6363SMichael Chan 457490475a9SAnil Veerabhadrappa int hba_shutdown_tmo; 458e37d2c47SEddie Wai int conn_teardown_tmo; 459e37d2c47SEddie Wai int conn_ctx_destroy_tmo; 460cf4e6363SMichael Chan /* 461cf4e6363SMichael Chan * PCI related info. 462cf4e6363SMichael Chan */ 463cf4e6363SMichael Chan u16 pci_did; 464cf4e6363SMichael Chan u16 pci_vid; 465cf4e6363SMichael Chan u16 pci_sdid; 466cf4e6363SMichael Chan u16 pci_svid; 467cf4e6363SMichael Chan u16 pci_func; 468cf4e6363SMichael Chan u16 pci_devno; 469cf4e6363SMichael Chan 470cf4e6363SMichael Chan /* 471cf4e6363SMichael Chan * Following are a bunch of statistics useful during development 472cf4e6363SMichael Chan * and later stage for score boarding. 473cf4e6363SMichael Chan */ 474cf4e6363SMichael Chan u32 num_wqe_sent; 475cf4e6363SMichael Chan u32 num_cqe_rcvd; 476cf4e6363SMichael Chan u32 num_intr_claimed; 477cf4e6363SMichael Chan u32 link_changed_count; 478cf4e6363SMichael Chan u32 ipaddr_changed_count; 479cf4e6363SMichael Chan u32 num_sess_opened; 480cf4e6363SMichael Chan u32 num_conn_opened; 481cf4e6363SMichael Chan unsigned int ctx_ccell_tasks; 4822e499d3cSBarak Witkowski 4832e499d3cSBarak Witkowski #ifdef CONFIG_32BIT 4842e499d3cSBarak Witkowski spinlock_t stat_lock; 4852e499d3cSBarak Witkowski #endif 4862e499d3cSBarak Witkowski struct bnx2i_stats_info bnx2i_stats; 4872e499d3cSBarak Witkowski struct iscsi_stats_info stats; 488cf4e6363SMichael Chan }; 489cf4e6363SMichael Chan 490cf4e6363SMichael Chan 491cf4e6363SMichael Chan /******************************************************************************* 492cf4e6363SMichael Chan * QP [ SQ / RQ / CQ ] info. 493cf4e6363SMichael Chan ******************************************************************************/ 494cf4e6363SMichael Chan 495cf4e6363SMichael Chan /* 496cf4e6363SMichael Chan * SQ/RQ/CQ generic structure definition 497cf4e6363SMichael Chan */ 498cf4e6363SMichael Chan struct sqe { 499cf4e6363SMichael Chan u8 sqe_byte[BNX2I_SQ_WQE_SIZE]; 500cf4e6363SMichael Chan }; 501cf4e6363SMichael Chan 502cf4e6363SMichael Chan struct rqe { 503cf4e6363SMichael Chan u8 rqe_byte[BNX2I_RQ_WQE_SIZE]; 504cf4e6363SMichael Chan }; 505cf4e6363SMichael Chan 506cf4e6363SMichael Chan struct cqe { 507cf4e6363SMichael Chan u8 cqe_byte[BNX2I_CQE_SIZE]; 508cf4e6363SMichael Chan }; 509cf4e6363SMichael Chan 510cf4e6363SMichael Chan 511cf4e6363SMichael Chan enum { 512cf4e6363SMichael Chan #if defined(__LITTLE_ENDIAN) 513cf4e6363SMichael Chan CNIC_EVENT_COAL_INDEX = 0x0, 514cf4e6363SMichael Chan CNIC_SEND_DOORBELL = 0x4, 515cf4e6363SMichael Chan CNIC_EVENT_CQ_ARM = 0x7, 516cf4e6363SMichael Chan CNIC_RECV_DOORBELL = 0x8 517cf4e6363SMichael Chan #elif defined(__BIG_ENDIAN) 518cf4e6363SMichael Chan CNIC_EVENT_COAL_INDEX = 0x2, 519cf4e6363SMichael Chan CNIC_SEND_DOORBELL = 0x6, 520cf4e6363SMichael Chan CNIC_EVENT_CQ_ARM = 0x4, 521cf4e6363SMichael Chan CNIC_RECV_DOORBELL = 0xa 522cf4e6363SMichael Chan #endif 523cf4e6363SMichael Chan }; 524cf4e6363SMichael Chan 525cf4e6363SMichael Chan 526cf4e6363SMichael Chan /* 527cf4e6363SMichael Chan * CQ DB 528cf4e6363SMichael Chan */ 529cf4e6363SMichael Chan struct bnx2x_iscsi_cq_pend_cmpl { 530cf4e6363SMichael Chan /* CQ producer, updated by Ustorm */ 531cf4e6363SMichael Chan u16 ustrom_prod; 532cf4e6363SMichael Chan /* CQ pending completion counter */ 533cf4e6363SMichael Chan u16 pend_cntr; 534cf4e6363SMichael Chan }; 535cf4e6363SMichael Chan 536cf4e6363SMichael Chan 537cf4e6363SMichael Chan struct bnx2i_5771x_cq_db { 538cf4e6363SMichael Chan struct bnx2x_iscsi_cq_pend_cmpl qp_pend_cmpl[BNX2X_MAX_CQS]; 539cf4e6363SMichael Chan /* CQ pending completion ITT array */ 540cf4e6363SMichael Chan u16 itt[BNX2X_MAX_CQS]; 541cf4e6363SMichael Chan /* Cstorm CQ sequence to notify array, updated by driver */; 542cf4e6363SMichael Chan u16 sqn[BNX2X_MAX_CQS]; 543cf4e6363SMichael Chan u32 reserved[4] /* 16 byte allignment */; 544cf4e6363SMichael Chan }; 545cf4e6363SMichael Chan 546cf4e6363SMichael Chan 547cf4e6363SMichael Chan struct bnx2i_5771x_sq_rq_db { 548cf4e6363SMichael Chan u16 prod_idx; 549f4b5ad26SMichael Chan u8 reserved0[62]; /* Pad structure size to 64 bytes */ 550cf4e6363SMichael Chan }; 551cf4e6363SMichael Chan 552cf4e6363SMichael Chan 553cf4e6363SMichael Chan struct bnx2i_5771x_dbell_hdr { 554cf4e6363SMichael Chan u8 header; 555cf4e6363SMichael Chan /* 1 for rx doorbell, 0 for tx doorbell */ 556cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_RX (0x1<<0) 557cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_RX_SHIFT 0 558cf4e6363SMichael Chan /* 0 for normal doorbell, 1 for advertise wnd doorbell */ 559cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1) 560cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1 561cf4e6363SMichael Chan /* rdma tx only: DPM transaction size specifier (64/128/256/512B) */ 562cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2) 563cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2 564cf4e6363SMichael Chan /* connection type */ 565cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4) 566cf4e6363SMichael Chan #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4 567cf4e6363SMichael Chan }; 568cf4e6363SMichael Chan 569cf4e6363SMichael Chan struct bnx2i_5771x_dbell { 570cf4e6363SMichael Chan struct bnx2i_5771x_dbell_hdr dbell; 571cf4e6363SMichael Chan u8 pad[3]; 572cf4e6363SMichael Chan 573cf4e6363SMichael Chan }; 574cf4e6363SMichael Chan 575cf4e6363SMichael Chan /** 576cf4e6363SMichael Chan * struct qp_info - QP (share queue region) atrributes structure 577cf4e6363SMichael Chan * 578cf4e6363SMichael Chan * @ctx_base: ioremapped pci register base to access doorbell register 579cf4e6363SMichael Chan * pertaining to this offloaded connection 580cf4e6363SMichael Chan * @sq_virt: virtual address of send queue (SQ) region 581cf4e6363SMichael Chan * @sq_phys: DMA address of SQ memory region 582cf4e6363SMichael Chan * @sq_mem_size: SQ size 583cf4e6363SMichael Chan * @sq_prod_qe: SQ producer entry pointer 584cf4e6363SMichael Chan * @sq_cons_qe: SQ consumer entry pointer 585b23f7a09SMasanari Iida * @sq_first_qe: virtual address of first entry in SQ 586b23f7a09SMasanari Iida * @sq_last_qe: virtual address of last entry in SQ 587cf4e6363SMichael Chan * @sq_prod_idx: SQ producer index 588cf4e6363SMichael Chan * @sq_cons_idx: SQ consumer index 589cf4e6363SMichael Chan * @sqe_left: number sq entry left 590cf4e6363SMichael Chan * @sq_pgtbl_virt: page table describing buffer consituting SQ region 591cf4e6363SMichael Chan * @sq_pgtbl_phys: dma address of 'sq_pgtbl_virt' 592cf4e6363SMichael Chan * @sq_pgtbl_size: SQ page table size 593cf4e6363SMichael Chan * @cq_virt: virtual address of completion queue (CQ) region 594cf4e6363SMichael Chan * @cq_phys: DMA address of RQ memory region 595cf4e6363SMichael Chan * @cq_mem_size: CQ size 596cf4e6363SMichael Chan * @cq_prod_qe: CQ producer entry pointer 597cf4e6363SMichael Chan * @cq_cons_qe: CQ consumer entry pointer 598b23f7a09SMasanari Iida * @cq_first_qe: virtual address of first entry in CQ 599b23f7a09SMasanari Iida * @cq_last_qe: virtual address of last entry in CQ 600cf4e6363SMichael Chan * @cq_prod_idx: CQ producer index 601cf4e6363SMichael Chan * @cq_cons_idx: CQ consumer index 602cf4e6363SMichael Chan * @cqe_left: number cq entry left 603cf4e6363SMichael Chan * @cqe_size: size of each CQ entry 604cf4e6363SMichael Chan * @cqe_exp_seq_sn: next expected CQE sequence number 605cf4e6363SMichael Chan * @cq_pgtbl_virt: page table describing buffer consituting CQ region 606cf4e6363SMichael Chan * @cq_pgtbl_phys: dma address of 'cq_pgtbl_virt' 607cf4e6363SMichael Chan * @cq_pgtbl_size: CQ page table size 608cf4e6363SMichael Chan * @rq_virt: virtual address of receive queue (RQ) region 609cf4e6363SMichael Chan * @rq_phys: DMA address of RQ memory region 610cf4e6363SMichael Chan * @rq_mem_size: RQ size 611cf4e6363SMichael Chan * @rq_prod_qe: RQ producer entry pointer 612cf4e6363SMichael Chan * @rq_cons_qe: RQ consumer entry pointer 613b23f7a09SMasanari Iida * @rq_first_qe: virtual address of first entry in RQ 614b23f7a09SMasanari Iida * @rq_last_qe: virtual address of last entry in RQ 615cf4e6363SMichael Chan * @rq_prod_idx: RQ producer index 616cf4e6363SMichael Chan * @rq_cons_idx: RQ consumer index 617cf4e6363SMichael Chan * @rqe_left: number rq entry left 618cf4e6363SMichael Chan * @rq_pgtbl_virt: page table describing buffer consituting RQ region 619cf4e6363SMichael Chan * @rq_pgtbl_phys: dma address of 'rq_pgtbl_virt' 620cf4e6363SMichael Chan * @rq_pgtbl_size: RQ page table size 621cf4e6363SMichael Chan * 622cf4e6363SMichael Chan * queue pair (QP) is a per connection shared data structure which is used 623cf4e6363SMichael Chan * to send work requests (SQ), receive completion notifications (CQ) 624cf4e6363SMichael Chan * and receive asynchoronous / scsi sense info (RQ). 'qp_info' structure 625cf4e6363SMichael Chan * below holds queue memory, consumer/producer indexes and page table 626cf4e6363SMichael Chan * information 627cf4e6363SMichael Chan */ 628cf4e6363SMichael Chan struct qp_info { 629cf4e6363SMichael Chan void __iomem *ctx_base; 630cf4e6363SMichael Chan #define DPM_TRIGER_TYPE 0x40 631cf4e6363SMichael Chan 632cf4e6363SMichael Chan #define BNX2I_570x_QUE_DB_SIZE 0 633cf4e6363SMichael Chan #define BNX2I_5771x_QUE_DB_SIZE 16 634cf4e6363SMichael Chan struct sqe *sq_virt; 635cf4e6363SMichael Chan dma_addr_t sq_phys; 636cf4e6363SMichael Chan u32 sq_mem_size; 637cf4e6363SMichael Chan 638cf4e6363SMichael Chan struct sqe *sq_prod_qe; 639cf4e6363SMichael Chan struct sqe *sq_cons_qe; 640cf4e6363SMichael Chan struct sqe *sq_first_qe; 641cf4e6363SMichael Chan struct sqe *sq_last_qe; 642cf4e6363SMichael Chan u16 sq_prod_idx; 643cf4e6363SMichael Chan u16 sq_cons_idx; 644cf4e6363SMichael Chan u32 sqe_left; 645cf4e6363SMichael Chan 646cf4e6363SMichael Chan void *sq_pgtbl_virt; 647cf4e6363SMichael Chan dma_addr_t sq_pgtbl_phys; 648cf4e6363SMichael Chan u32 sq_pgtbl_size; /* set to PAGE_SIZE for 5708 & 5709 */ 649cf4e6363SMichael Chan 650cf4e6363SMichael Chan struct cqe *cq_virt; 651cf4e6363SMichael Chan dma_addr_t cq_phys; 652cf4e6363SMichael Chan u32 cq_mem_size; 653cf4e6363SMichael Chan 654cf4e6363SMichael Chan struct cqe *cq_prod_qe; 655cf4e6363SMichael Chan struct cqe *cq_cons_qe; 656cf4e6363SMichael Chan struct cqe *cq_first_qe; 657cf4e6363SMichael Chan struct cqe *cq_last_qe; 658cf4e6363SMichael Chan u16 cq_prod_idx; 659cf4e6363SMichael Chan u16 cq_cons_idx; 660cf4e6363SMichael Chan u32 cqe_left; 661cf4e6363SMichael Chan u32 cqe_size; 662cf4e6363SMichael Chan u32 cqe_exp_seq_sn; 663cf4e6363SMichael Chan 664cf4e6363SMichael Chan void *cq_pgtbl_virt; 665cf4e6363SMichael Chan dma_addr_t cq_pgtbl_phys; 666cf4e6363SMichael Chan u32 cq_pgtbl_size; /* set to PAGE_SIZE for 5708 & 5709 */ 667cf4e6363SMichael Chan 668cf4e6363SMichael Chan struct rqe *rq_virt; 669cf4e6363SMichael Chan dma_addr_t rq_phys; 670cf4e6363SMichael Chan u32 rq_mem_size; 671cf4e6363SMichael Chan 672cf4e6363SMichael Chan struct rqe *rq_prod_qe; 673cf4e6363SMichael Chan struct rqe *rq_cons_qe; 674cf4e6363SMichael Chan struct rqe *rq_first_qe; 675cf4e6363SMichael Chan struct rqe *rq_last_qe; 676cf4e6363SMichael Chan u16 rq_prod_idx; 677cf4e6363SMichael Chan u16 rq_cons_idx; 678cf4e6363SMichael Chan u32 rqe_left; 679cf4e6363SMichael Chan 680cf4e6363SMichael Chan void *rq_pgtbl_virt; 681cf4e6363SMichael Chan dma_addr_t rq_pgtbl_phys; 682cf4e6363SMichael Chan u32 rq_pgtbl_size; /* set to PAGE_SIZE for 5708 & 5709 */ 683cf4e6363SMichael Chan }; 684cf4e6363SMichael Chan 685cf4e6363SMichael Chan 686cf4e6363SMichael Chan 687cf4e6363SMichael Chan /* 688cf4e6363SMichael Chan * CID handles 689cf4e6363SMichael Chan */ 690cf4e6363SMichael Chan struct ep_handles { 691cf4e6363SMichael Chan u32 fw_cid; 692cf4e6363SMichael Chan u32 drv_iscsi_cid; 693cf4e6363SMichael Chan u16 pg_cid; 694cf4e6363SMichael Chan u16 rsvd; 695cf4e6363SMichael Chan }; 696cf4e6363SMichael Chan 697cf4e6363SMichael Chan 698cf4e6363SMichael Chan enum { 699cf4e6363SMichael Chan EP_STATE_IDLE = 0x0, 700cf4e6363SMichael Chan EP_STATE_PG_OFLD_START = 0x1, 701cf4e6363SMichael Chan EP_STATE_PG_OFLD_COMPL = 0x2, 702cf4e6363SMichael Chan EP_STATE_OFLD_START = 0x4, 703cf4e6363SMichael Chan EP_STATE_OFLD_COMPL = 0x8, 704cf4e6363SMichael Chan EP_STATE_CONNECT_START = 0x10, 705cf4e6363SMichael Chan EP_STATE_CONNECT_COMPL = 0x20, 706cf4e6363SMichael Chan EP_STATE_ULP_UPDATE_START = 0x40, 707cf4e6363SMichael Chan EP_STATE_ULP_UPDATE_COMPL = 0x80, 708cf4e6363SMichael Chan EP_STATE_DISCONN_START = 0x100, 709cf4e6363SMichael Chan EP_STATE_DISCONN_COMPL = 0x200, 710cf4e6363SMichael Chan EP_STATE_CLEANUP_START = 0x400, 711cf4e6363SMichael Chan EP_STATE_CLEANUP_CMPL = 0x800, 712cf4e6363SMichael Chan EP_STATE_TCP_FIN_RCVD = 0x1000, 713cf4e6363SMichael Chan EP_STATE_TCP_RST_RCVD = 0x2000, 7142eefb20dSEddie Wai EP_STATE_LOGOUT_SENT = 0x4000, 7152eefb20dSEddie Wai EP_STATE_LOGOUT_RESP_RCVD = 0x8000, 716cf4e6363SMichael Chan EP_STATE_PG_OFLD_FAILED = 0x1000000, 717cf4e6363SMichael Chan EP_STATE_ULP_UPDATE_FAILED = 0x2000000, 718cf4e6363SMichael Chan EP_STATE_CLEANUP_FAILED = 0x4000000, 719cf4e6363SMichael Chan EP_STATE_OFLD_FAILED = 0x8000000, 720cf4e6363SMichael Chan EP_STATE_CONNECT_FAILED = 0x10000000, 721cf4e6363SMichael Chan EP_STATE_DISCONN_TIMEDOUT = 0x20000000, 722bee34877SEddie Wai EP_STATE_OFLD_FAILED_CID_BUSY = 0x80000000, 723cf4e6363SMichael Chan }; 724cf4e6363SMichael Chan 725cf4e6363SMichael Chan /** 726cf4e6363SMichael Chan * struct bnx2i_endpoint - representation of tcp connection in NX2 world 727cf4e6363SMichael Chan * 728cf4e6363SMichael Chan * @link: list head to link elements 729cf4e6363SMichael Chan * @hba: adapter to which this connection belongs 730cf4e6363SMichael Chan * @conn: iscsi connection this EP is linked to 73146012e8bSEddie Wai * @cls_ep: associated iSCSI endpoint pointer 732cf4e6363SMichael Chan * @cm_sk: cnic sock struct 733cf4e6363SMichael Chan * @hba_age: age to detect if 'iscsid' issues ep_disconnect() 734cf4e6363SMichael Chan * after HBA reset is completed by bnx2i/cnic/bnx2 735cf4e6363SMichael Chan * modules 736cf4e6363SMichael Chan * @state: tracks offload connection state machine 7379ae58e14SEddie Wai * @timestamp: tracks the start time when the ep begins to connect 7389ae58e14SEddie Wai * @num_active_cmds: tracks the number of outstanding commands for this ep 7399ae58e14SEddie Wai * @ec_shift: the amount of shift as part of the event coal calc 740cf4e6363SMichael Chan * @qp: QP information 741cf4e6363SMichael Chan * @ids: contains chip allocated *context id* & driver assigned 742cf4e6363SMichael Chan * *iscsi cid* 743cf4e6363SMichael Chan * @ofld_timer: offload timer to detect timeout 744cf4e6363SMichael Chan * @ofld_wait: wait queue 745cf4e6363SMichael Chan * 746cf4e6363SMichael Chan * Endpoint Structure - equivalent of tcp socket structure 747cf4e6363SMichael Chan */ 748cf4e6363SMichael Chan struct bnx2i_endpoint { 749cf4e6363SMichael Chan struct list_head link; 750cf4e6363SMichael Chan struct bnx2i_hba *hba; 751cf4e6363SMichael Chan struct bnx2i_conn *conn; 75246012e8bSEddie Wai struct iscsi_endpoint *cls_ep; 753cf4e6363SMichael Chan struct cnic_sock *cm_sk; 754cf4e6363SMichael Chan u32 hba_age; 755cf4e6363SMichael Chan u32 state; 756cf4e6363SMichael Chan unsigned long timestamp; 757b5cf6b63SEddie Wai atomic_t num_active_cmds; 7589ae58e14SEddie Wai u32 ec_shift; 759cf4e6363SMichael Chan 760cf4e6363SMichael Chan struct qp_info qp; 761cf4e6363SMichael Chan struct ep_handles ids; 762cf4e6363SMichael Chan #define ep_iscsi_cid ids.drv_iscsi_cid 763cf4e6363SMichael Chan #define ep_cid ids.fw_cid 764cf4e6363SMichael Chan #define ep_pg_cid ids.pg_cid 765cf4e6363SMichael Chan struct timer_list ofld_timer; 766cf4e6363SMichael Chan wait_queue_head_t ofld_wait; 767cf4e6363SMichael Chan }; 768cf4e6363SMichael Chan 769cf4e6363SMichael Chan 770b5cf6b63SEddie Wai struct bnx2i_work { 771b5cf6b63SEddie Wai struct list_head list; 772b5cf6b63SEddie Wai struct iscsi_session *session; 773b5cf6b63SEddie Wai struct bnx2i_conn *bnx2i_conn; 774b5cf6b63SEddie Wai struct cqe cqe; 775b5cf6b63SEddie Wai }; 776b5cf6b63SEddie Wai 777b5cf6b63SEddie Wai struct bnx2i_percpu_s { 778b5cf6b63SEddie Wai struct task_struct *iothread; 779b5cf6b63SEddie Wai struct list_head work_list; 780b5cf6b63SEddie Wai spinlock_t p_work_lock; 781b5cf6b63SEddie Wai }; 782b5cf6b63SEddie Wai 783cf4e6363SMichael Chan 784cf4e6363SMichael Chan /* Global variables */ 785cf4e6363SMichael Chan extern unsigned int error_mask1, error_mask2; 786cf4e6363SMichael Chan extern u64 iscsi_error_mask; 787cf4e6363SMichael Chan extern unsigned int en_tcp_dack; 788cf4e6363SMichael Chan extern unsigned int event_coal_div; 7898776193bSAnil Veerabhadrappa extern unsigned int event_coal_min; 790cf4e6363SMichael Chan 791cf4e6363SMichael Chan extern struct scsi_transport_template *bnx2i_scsi_xport_template; 792cf4e6363SMichael Chan extern struct iscsi_transport bnx2i_iscsi_transport; 793cf4e6363SMichael Chan extern struct cnic_ulp_ops bnx2i_cnic_cb; 794cf4e6363SMichael Chan 795cf4e6363SMichael Chan extern unsigned int sq_size; 796cf4e6363SMichael Chan extern unsigned int rq_size; 797cf4e6363SMichael Chan 798*eb78ac7aSBart Van Assche extern const struct attribute_group *bnx2i_dev_groups[]; 799cf4e6363SMichael Chan 800cf4e6363SMichael Chan 801cf4e6363SMichael Chan 802cf4e6363SMichael Chan /* 803cf4e6363SMichael Chan * Function Prototypes 804cf4e6363SMichael Chan */ 805b83908ceSEddie Wai extern void bnx2i_identify_device(struct bnx2i_hba *hba, struct cnic_dev *dev); 806cf4e6363SMichael Chan 807cf4e6363SMichael Chan extern void bnx2i_ulp_init(struct cnic_dev *dev); 808cf4e6363SMichael Chan extern void bnx2i_ulp_exit(struct cnic_dev *dev); 809cf4e6363SMichael Chan extern void bnx2i_start(void *handle); 810cf4e6363SMichael Chan extern void bnx2i_stop(void *handle); 8112e499d3cSBarak Witkowski extern int bnx2i_get_stats(void *handle); 8122e499d3cSBarak Witkowski 813cf4e6363SMichael Chan extern struct bnx2i_hba *get_adapter_list_head(void); 814cf4e6363SMichael Chan 815cf4e6363SMichael Chan struct bnx2i_conn *bnx2i_get_conn_from_id(struct bnx2i_hba *hba, 816cf4e6363SMichael Chan u16 iscsi_cid); 817cf4e6363SMichael Chan 818cf4e6363SMichael Chan int bnx2i_alloc_ep_pool(void); 819cf4e6363SMichael Chan void bnx2i_release_ep_pool(void); 820cf4e6363SMichael Chan struct bnx2i_endpoint *bnx2i_ep_ofld_list_next(struct bnx2i_hba *hba); 821cf4e6363SMichael Chan struct bnx2i_endpoint *bnx2i_ep_destroy_list_next(struct bnx2i_hba *hba); 822cf4e6363SMichael Chan 823cf4e6363SMichael Chan struct bnx2i_hba *bnx2i_find_hba_for_cnic(struct cnic_dev *cnic); 824cf4e6363SMichael Chan 825cf4e6363SMichael Chan struct bnx2i_hba *bnx2i_alloc_hba(struct cnic_dev *cnic); 826cf4e6363SMichael Chan void bnx2i_free_hba(struct bnx2i_hba *hba); 827cf4e6363SMichael Chan 828cf4e6363SMichael Chan void bnx2i_get_rq_buf(struct bnx2i_conn *conn, char *ptr, int len); 829cf4e6363SMichael Chan void bnx2i_put_rq_buf(struct bnx2i_conn *conn, int count); 830cf4e6363SMichael Chan 831cf4e6363SMichael Chan void bnx2i_iscsi_unmap_sg_list(struct bnx2i_cmd *cmd); 832cf4e6363SMichael Chan 833cf4e6363SMichael Chan void bnx2i_drop_session(struct iscsi_cls_session *session); 834cf4e6363SMichael Chan 835cf4e6363SMichael Chan extern int bnx2i_send_fw_iscsi_init_msg(struct bnx2i_hba *hba); 836cf4e6363SMichael Chan extern int bnx2i_send_iscsi_login(struct bnx2i_conn *conn, 837cf4e6363SMichael Chan struct iscsi_task *mtask); 838cf4e6363SMichael Chan extern int bnx2i_send_iscsi_tmf(struct bnx2i_conn *conn, 839cf4e6363SMichael Chan struct iscsi_task *mtask); 84009813ba5SEddie Wai extern int bnx2i_send_iscsi_text(struct bnx2i_conn *conn, 84109813ba5SEddie Wai struct iscsi_task *mtask); 842cf4e6363SMichael Chan extern int bnx2i_send_iscsi_scsicmd(struct bnx2i_conn *conn, 843cf4e6363SMichael Chan struct bnx2i_cmd *cmnd); 844cf4e6363SMichael Chan extern int bnx2i_send_iscsi_nopout(struct bnx2i_conn *conn, 84539304072SEddie Wai struct iscsi_task *mtask, 846cf4e6363SMichael Chan char *datap, int data_len, int unsol); 847cf4e6363SMichael Chan extern int bnx2i_send_iscsi_logout(struct bnx2i_conn *conn, 848cf4e6363SMichael Chan struct iscsi_task *mtask); 849cf4e6363SMichael Chan extern void bnx2i_send_cmd_cleanup_req(struct bnx2i_hba *hba, 850cf4e6363SMichael Chan struct bnx2i_cmd *cmd); 851bee34877SEddie Wai extern int bnx2i_send_conn_ofld_req(struct bnx2i_hba *hba, 852cf4e6363SMichael Chan struct bnx2i_endpoint *ep); 853cf4e6363SMichael Chan extern void bnx2i_update_iscsi_conn(struct iscsi_conn *conn); 854bee34877SEddie Wai extern int bnx2i_send_conn_destroy(struct bnx2i_hba *hba, 855cf4e6363SMichael Chan struct bnx2i_endpoint *ep); 856cf4e6363SMichael Chan 857cf4e6363SMichael Chan extern int bnx2i_alloc_qp_resc(struct bnx2i_hba *hba, 858cf4e6363SMichael Chan struct bnx2i_endpoint *ep); 859cf4e6363SMichael Chan extern void bnx2i_free_qp_resc(struct bnx2i_hba *hba, 860cf4e6363SMichael Chan struct bnx2i_endpoint *ep); 861abef7510SKees Cook extern void bnx2i_ep_ofld_timer(struct timer_list *t); 862cf4e6363SMichael Chan extern struct bnx2i_endpoint *bnx2i_find_ep_in_ofld_list( 863cf4e6363SMichael Chan struct bnx2i_hba *hba, u32 iscsi_cid); 864cf4e6363SMichael Chan extern struct bnx2i_endpoint *bnx2i_find_ep_in_destroy_list( 865cf4e6363SMichael Chan struct bnx2i_hba *hba, u32 iscsi_cid); 866cf4e6363SMichael Chan 867cf4e6363SMichael Chan extern int bnx2i_map_ep_dbell_regs(struct bnx2i_endpoint *ep); 868b5cf6b63SEddie Wai extern int bnx2i_arm_cq_event_coalescing(struct bnx2i_endpoint *ep, u8 action); 869cf4e6363SMichael Chan 87055e15c97SEddie Wai extern int bnx2i_hw_ep_disconnect(struct bnx2i_endpoint *bnx2i_ep); 87155e15c97SEddie Wai 872cf4e6363SMichael Chan /* Debug related function prototypes */ 873cf4e6363SMichael Chan extern void bnx2i_print_pend_cmd_queue(struct bnx2i_conn *conn); 874cf4e6363SMichael Chan extern void bnx2i_print_active_cmd_queue(struct bnx2i_conn *conn); 875cf4e6363SMichael Chan extern void bnx2i_print_xmit_pdu_queue(struct bnx2i_conn *conn); 876cf4e6363SMichael Chan extern void bnx2i_print_recv_state(struct bnx2i_conn *conn); 877cf4e6363SMichael Chan 878b5cf6b63SEddie Wai extern int bnx2i_percpu_io_thread(void *arg); 879b5cf6b63SEddie Wai extern int bnx2i_process_scsi_cmd_resp(struct iscsi_session *session, 880b5cf6b63SEddie Wai struct bnx2i_conn *bnx2i_conn, 881b5cf6b63SEddie Wai struct cqe *cqe); 882cf4e6363SMichael Chan #endif 883