1*6e9ef509SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2942b7654SJitendra Bhivare /*
30172dc65SJitendra Bhivare * Copyright 2017 Broadcom. All Rights Reserved.
4942b7654SJitendra Bhivare * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries.
56733b39aSJayamohan Kallickal *
66733b39aSJayamohan Kallickal * Contact Information:
760f36e04SJitendra Bhivare * linux-drivers@broadcom.com
86733b39aSJayamohan Kallickal */
96733b39aSJayamohan Kallickal
106733b39aSJayamohan Kallickal #ifndef BEISCSI_H
116733b39aSJayamohan Kallickal #define BEISCSI_H
126733b39aSJayamohan Kallickal
136733b39aSJayamohan Kallickal #include <linux/pci.h>
146733b39aSJayamohan Kallickal #include <linux/if_vlan.h>
15511cbce2SChristoph Hellwig #include <linux/irq_poll.h>
166733b39aSJayamohan Kallickal #define FW_VER_LEN 32
17bfead3b2SJayamohan Kallickal #define MCC_Q_LEN 128
18bfead3b2SJayamohan Kallickal #define MCC_CQ_LEN 256
19756d29c8SJayamohan Kallickal #define MAX_MCC_CMD 16
20f98c96b0SJayamohan Kallickal /* BladeEngine Generation numbers */
21f98c96b0SJayamohan Kallickal #define BE_GEN2 2
22f98c96b0SJayamohan Kallickal #define BE_GEN3 3
23139a1b1eSJohn Soni Jose #define BE_GEN4 4
246733b39aSJayamohan Kallickal struct be_dma_mem {
256733b39aSJayamohan Kallickal void *va;
266733b39aSJayamohan Kallickal dma_addr_t dma;
276733b39aSJayamohan Kallickal u32 size;
286733b39aSJayamohan Kallickal };
296733b39aSJayamohan Kallickal
306733b39aSJayamohan Kallickal struct be_queue_info {
316733b39aSJayamohan Kallickal struct be_dma_mem dma_mem;
326733b39aSJayamohan Kallickal u16 len;
336733b39aSJayamohan Kallickal u16 entry_size; /* Size of an element in the queue */
346733b39aSJayamohan Kallickal u16 id;
356733b39aSJayamohan Kallickal u16 tail, head;
366733b39aSJayamohan Kallickal bool created;
37090e2184SJitendra Bhivare u16 used; /* Number of valid elements in the queue */
386733b39aSJayamohan Kallickal };
396733b39aSJayamohan Kallickal
MODULO(u16 val,u16 limit)406733b39aSJayamohan Kallickal static inline u32 MODULO(u16 val, u16 limit)
416733b39aSJayamohan Kallickal {
426733b39aSJayamohan Kallickal WARN_ON(limit & (limit - 1));
436733b39aSJayamohan Kallickal return val & (limit - 1);
446733b39aSJayamohan Kallickal }
456733b39aSJayamohan Kallickal
index_inc(u16 * index,u16 limit)466733b39aSJayamohan Kallickal static inline void index_inc(u16 *index, u16 limit)
476733b39aSJayamohan Kallickal {
486733b39aSJayamohan Kallickal *index = MODULO((*index + 1), limit);
496733b39aSJayamohan Kallickal }
506733b39aSJayamohan Kallickal
queue_head_node(struct be_queue_info * q)516733b39aSJayamohan Kallickal static inline void *queue_head_node(struct be_queue_info *q)
526733b39aSJayamohan Kallickal {
536733b39aSJayamohan Kallickal return q->dma_mem.va + q->head * q->entry_size;
546733b39aSJayamohan Kallickal }
556733b39aSJayamohan Kallickal
queue_get_wrb(struct be_queue_info * q,unsigned int wrb_num)56756d29c8SJayamohan Kallickal static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num)
57756d29c8SJayamohan Kallickal {
58756d29c8SJayamohan Kallickal return q->dma_mem.va + wrb_num * q->entry_size;
59756d29c8SJayamohan Kallickal }
60756d29c8SJayamohan Kallickal
queue_tail_node(struct be_queue_info * q)616733b39aSJayamohan Kallickal static inline void *queue_tail_node(struct be_queue_info *q)
626733b39aSJayamohan Kallickal {
636733b39aSJayamohan Kallickal return q->dma_mem.va + q->tail * q->entry_size;
646733b39aSJayamohan Kallickal }
656733b39aSJayamohan Kallickal
queue_head_inc(struct be_queue_info * q)666733b39aSJayamohan Kallickal static inline void queue_head_inc(struct be_queue_info *q)
676733b39aSJayamohan Kallickal {
686733b39aSJayamohan Kallickal index_inc(&q->head, q->len);
696733b39aSJayamohan Kallickal }
706733b39aSJayamohan Kallickal
queue_tail_inc(struct be_queue_info * q)716733b39aSJayamohan Kallickal static inline void queue_tail_inc(struct be_queue_info *q)
726733b39aSJayamohan Kallickal {
736733b39aSJayamohan Kallickal index_inc(&q->tail, q->len);
746733b39aSJayamohan Kallickal }
756733b39aSJayamohan Kallickal
766733b39aSJayamohan Kallickal /*ISCSI */
776733b39aSJayamohan Kallickal
7873af08e1SJayamohan Kallickal struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */
7945efc940SJitendra Bhivare unsigned long jiffies;
8045efc940SJitendra Bhivare u32 eq_prev; /* Used to calculate eqe */
8145efc940SJitendra Bhivare u32 prev_eqd;
8245efc940SJitendra Bhivare #define BEISCSI_EQ_DELAY_MIN 0
8345efc940SJitendra Bhivare #define BEISCSI_EQ_DELAY_DEF 32
8445efc940SJitendra Bhivare #define BEISCSI_EQ_DELAY_MAX 128
8573af08e1SJayamohan Kallickal };
8673af08e1SJayamohan Kallickal
876733b39aSJayamohan Kallickal struct be_eq_obj {
8873af08e1SJayamohan Kallickal u32 cq_count;
896733b39aSJayamohan Kallickal struct be_queue_info q;
90bfead3b2SJayamohan Kallickal struct beiscsi_hba *phba;
91bfead3b2SJayamohan Kallickal struct be_queue_info *cq;
92a3095016SJitendra Bhivare struct work_struct mcc_work; /* Work Item */
93511cbce2SChristoph Hellwig struct irq_poll iopoll;
946733b39aSJayamohan Kallickal };
956733b39aSJayamohan Kallickal
966733b39aSJayamohan Kallickal struct be_mcc_obj {
97bfead3b2SJayamohan Kallickal struct be_queue_info q;
98bfead3b2SJayamohan Kallickal struct be_queue_info cq;
996733b39aSJayamohan Kallickal };
1006733b39aSJayamohan Kallickal
1011957aa7fSJayamohan Kallickal struct beiscsi_mcc_tag_state {
102cdde6682SJitendra Bhivare unsigned long tag_state;
10310bcd47dSJitendra Bhivare #define MCC_TAG_STATE_RUNNING 0
10410bcd47dSJitendra Bhivare #define MCC_TAG_STATE_TIMEOUT 1
10510bcd47dSJitendra Bhivare #define MCC_TAG_STATE_ASYNC 2
10610bcd47dSJitendra Bhivare #define MCC_TAG_STATE_IGNORE 3
10750a4b824SJitendra Bhivare void (*cbfn)(struct beiscsi_hba *, unsigned int);
1081957aa7fSJayamohan Kallickal struct be_dma_mem tag_mem_state;
1091957aa7fSJayamohan Kallickal };
1101957aa7fSJayamohan Kallickal
1116733b39aSJayamohan Kallickal struct be_ctrl_info {
1126733b39aSJayamohan Kallickal u8 __iomem *csr;
1136733b39aSJayamohan Kallickal u8 __iomem *db; /* Door Bell */
1146733b39aSJayamohan Kallickal u8 __iomem *pcicfg; /* PCI config space */
1156733b39aSJayamohan Kallickal struct pci_dev *pdev;
1166733b39aSJayamohan Kallickal
1176733b39aSJayamohan Kallickal /* Mbox used for cmd request/response */
118c03a50f7SJitendra Bhivare struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
1196733b39aSJayamohan Kallickal struct be_dma_mem mbox_mem;
1206733b39aSJayamohan Kallickal /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
1216733b39aSJayamohan Kallickal * is stored for freeing purpose */
1226733b39aSJayamohan Kallickal struct be_dma_mem mbox_mem_alloced;
1236733b39aSJayamohan Kallickal
1246733b39aSJayamohan Kallickal /* MCC Rings */
1256733b39aSJayamohan Kallickal struct be_mcc_obj mcc_obj;
1266733b39aSJayamohan Kallickal spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
1276733b39aSJayamohan Kallickal
128756d29c8SJayamohan Kallickal wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1];
129756d29c8SJayamohan Kallickal unsigned int mcc_tag[MAX_MCC_CMD];
13067296ad9SJitendra Bhivare unsigned int mcc_tag_status[MAX_MCC_CMD + 1];
131756d29c8SJayamohan Kallickal unsigned short mcc_alloc_index;
132756d29c8SJayamohan Kallickal unsigned short mcc_free_index;
133756d29c8SJayamohan Kallickal unsigned int mcc_tag_available;
1341957aa7fSJayamohan Kallickal
1351957aa7fSJayamohan Kallickal struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1];
1366733b39aSJayamohan Kallickal };
1376733b39aSJayamohan Kallickal
1386733b39aSJayamohan Kallickal #include "be_cmds.h"
1396733b39aSJayamohan Kallickal
14067296ad9SJitendra Bhivare /* WRB index mask for MCC_Q_LEN queue entries */
14167296ad9SJitendra Bhivare #define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK
14267296ad9SJitendra Bhivare #define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT
14367296ad9SJitendra Bhivare /* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */
14467296ad9SJitendra Bhivare #define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1)
14567296ad9SJitendra Bhivare
1466733b39aSJayamohan Kallickal #define PAGE_SHIFT_4K 12
1476733b39aSJayamohan Kallickal #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
1486733b39aSJayamohan Kallickal
1496733b39aSJayamohan Kallickal /* Returns number of pages spanned by the data starting at the given addr */
1506733b39aSJayamohan Kallickal #define PAGES_4K_SPANNED(_address, size) \
1516733b39aSJayamohan Kallickal ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
1526733b39aSJayamohan Kallickal (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
1536733b39aSJayamohan Kallickal
1546733b39aSJayamohan Kallickal /* Returns bit offset within a DWORD of a bitfield */
1556733b39aSJayamohan Kallickal #define AMAP_BIT_OFFSET(_struct, field) \
1566733b39aSJayamohan Kallickal (((size_t)&(((_struct *)0)->field))%32)
1576733b39aSJayamohan Kallickal
1586733b39aSJayamohan Kallickal /* Returns the bit mask of the field that is NOT shifted into location. */
amap_mask(u32 bitsize)1596733b39aSJayamohan Kallickal static inline u32 amap_mask(u32 bitsize)
1606733b39aSJayamohan Kallickal {
1616733b39aSJayamohan Kallickal return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
1626733b39aSJayamohan Kallickal }
1636733b39aSJayamohan Kallickal
amap_set(void * ptr,u32 dw_offset,u32 mask,u32 offset,u32 value)1646733b39aSJayamohan Kallickal static inline void amap_set(void *ptr, u32 dw_offset, u32 mask,
1656733b39aSJayamohan Kallickal u32 offset, u32 value)
1666733b39aSJayamohan Kallickal {
1676733b39aSJayamohan Kallickal u32 *dw = (u32 *) ptr + dw_offset;
1686733b39aSJayamohan Kallickal *dw &= ~(mask << offset);
1696733b39aSJayamohan Kallickal *dw |= (mask & value) << offset;
1706733b39aSJayamohan Kallickal }
1716733b39aSJayamohan Kallickal
1726733b39aSJayamohan Kallickal #define AMAP_SET_BITS(_struct, field, ptr, val) \
1736733b39aSJayamohan Kallickal amap_set(ptr, \
1746733b39aSJayamohan Kallickal offsetof(_struct, field)/32, \
1756733b39aSJayamohan Kallickal amap_mask(sizeof(((_struct *)0)->field)), \
1766733b39aSJayamohan Kallickal AMAP_BIT_OFFSET(_struct, field), \
1776733b39aSJayamohan Kallickal val)
1786733b39aSJayamohan Kallickal
amap_get(void * ptr,u32 dw_offset,u32 mask,u32 offset)1796733b39aSJayamohan Kallickal static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
1806733b39aSJayamohan Kallickal {
1816733b39aSJayamohan Kallickal u32 *dw = ptr;
1826733b39aSJayamohan Kallickal return mask & (*(dw + dw_offset) >> offset);
1836733b39aSJayamohan Kallickal }
1846733b39aSJayamohan Kallickal
1856733b39aSJayamohan Kallickal #define AMAP_GET_BITS(_struct, field, ptr) \
1866733b39aSJayamohan Kallickal amap_get(ptr, \
1876733b39aSJayamohan Kallickal offsetof(_struct, field)/32, \
1886733b39aSJayamohan Kallickal amap_mask(sizeof(((_struct *)0)->field)), \
1896733b39aSJayamohan Kallickal AMAP_BIT_OFFSET(_struct, field))
1906733b39aSJayamohan Kallickal
1916733b39aSJayamohan Kallickal #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
1926733b39aSJayamohan Kallickal #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
swap_dws(void * wrb,int len)1936733b39aSJayamohan Kallickal static inline void swap_dws(void *wrb, int len)
1946733b39aSJayamohan Kallickal {
1956733b39aSJayamohan Kallickal #ifdef __BIG_ENDIAN
1966733b39aSJayamohan Kallickal u32 *dw = wrb;
1976733b39aSJayamohan Kallickal WARN_ON(len % 4);
1986733b39aSJayamohan Kallickal do {
1996733b39aSJayamohan Kallickal *dw = cpu_to_le32(*dw);
2006733b39aSJayamohan Kallickal dw++;
2016733b39aSJayamohan Kallickal len -= 4;
2026733b39aSJayamohan Kallickal } while (len);
2036733b39aSJayamohan Kallickal #endif /* __BIG_ENDIAN */
2046733b39aSJayamohan Kallickal }
2056733b39aSJayamohan Kallickal #endif /* BEISCSI_H */
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