1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2e0ac4761SAtsushi Nemoto /*
3e0ac4761SAtsushi Nemoto * A SPI driver for the Ricoh RS5C348 RTC
4e0ac4761SAtsushi Nemoto *
5e0ac4761SAtsushi Nemoto * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
6e0ac4761SAtsushi Nemoto *
7e0ac4761SAtsushi Nemoto * The board specific init code should provide characteristics of this
8e0ac4761SAtsushi Nemoto * device:
9e0ac4761SAtsushi Nemoto * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
10e0ac4761SAtsushi Nemoto */
11e0ac4761SAtsushi Nemoto
12e0ac4761SAtsushi Nemoto #include <linux/bcd.h>
13e0ac4761SAtsushi Nemoto #include <linux/delay.h>
14e0ac4761SAtsushi Nemoto #include <linux/device.h>
15e0ac4761SAtsushi Nemoto #include <linux/errno.h>
16e0ac4761SAtsushi Nemoto #include <linux/init.h>
17e0ac4761SAtsushi Nemoto #include <linux/kernel.h>
18e0ac4761SAtsushi Nemoto #include <linux/string.h>
195a0e3ad6STejun Heo #include <linux/slab.h>
20e0ac4761SAtsushi Nemoto #include <linux/rtc.h>
21e0ac4761SAtsushi Nemoto #include <linux/workqueue.h>
22e0ac4761SAtsushi Nemoto #include <linux/spi/spi.h>
232113852bSPaul Gortmaker #include <linux/module.h>
24e0ac4761SAtsushi Nemoto
25e0ac4761SAtsushi Nemoto #define RS5C348_REG_SECS 0
26e0ac4761SAtsushi Nemoto #define RS5C348_REG_MINS 1
27e0ac4761SAtsushi Nemoto #define RS5C348_REG_HOURS 2
28e0ac4761SAtsushi Nemoto #define RS5C348_REG_WDAY 3
29e0ac4761SAtsushi Nemoto #define RS5C348_REG_DAY 4
30e0ac4761SAtsushi Nemoto #define RS5C348_REG_MONTH 5
31e0ac4761SAtsushi Nemoto #define RS5C348_REG_YEAR 6
32e0ac4761SAtsushi Nemoto #define RS5C348_REG_CTL1 14
33e0ac4761SAtsushi Nemoto #define RS5C348_REG_CTL2 15
34e0ac4761SAtsushi Nemoto
35e0ac4761SAtsushi Nemoto #define RS5C348_SECS_MASK 0x7f
36e0ac4761SAtsushi Nemoto #define RS5C348_MINS_MASK 0x7f
37e0ac4761SAtsushi Nemoto #define RS5C348_HOURS_MASK 0x3f
38e0ac4761SAtsushi Nemoto #define RS5C348_WDAY_MASK 0x03
39e0ac4761SAtsushi Nemoto #define RS5C348_DAY_MASK 0x3f
40e0ac4761SAtsushi Nemoto #define RS5C348_MONTH_MASK 0x1f
41e0ac4761SAtsushi Nemoto
42e0ac4761SAtsushi Nemoto #define RS5C348_BIT_PM 0x20 /* REG_HOURS */
43e0ac4761SAtsushi Nemoto #define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */
44e0ac4761SAtsushi Nemoto #define RS5C348_BIT_24H 0x20 /* REG_CTL1 */
45e0ac4761SAtsushi Nemoto #define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */
46e0ac4761SAtsushi Nemoto #define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */
47e0ac4761SAtsushi Nemoto
48e0ac4761SAtsushi Nemoto #define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
49e0ac4761SAtsushi Nemoto #define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
50e0ac4761SAtsushi Nemoto #define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
51e0ac4761SAtsushi Nemoto #define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
52e0ac4761SAtsushi Nemoto
53e0ac4761SAtsushi Nemoto struct rs5c348_plat_data {
54e0ac4761SAtsushi Nemoto struct rtc_device *rtc;
55e0ac4761SAtsushi Nemoto int rtc_24h;
56e0ac4761SAtsushi Nemoto };
57e0ac4761SAtsushi Nemoto
58e0ac4761SAtsushi Nemoto static int
rs5c348_rtc_set_time(struct device * dev,struct rtc_time * tm)59e0ac4761SAtsushi Nemoto rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm)
60e0ac4761SAtsushi Nemoto {
61e0ac4761SAtsushi Nemoto struct spi_device *spi = to_spi_device(dev);
62f6405afeSJingoo Han struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
63e0ac4761SAtsushi Nemoto u8 txbuf[5+7], *txp;
64e0ac4761SAtsushi Nemoto int ret;
65e0ac4761SAtsushi Nemoto
661654a2b0SAlexandre Belloni ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
671654a2b0SAlexandre Belloni if (ret < 0)
681654a2b0SAlexandre Belloni return ret;
691654a2b0SAlexandre Belloni if (ret & RS5C348_BIT_XSTP) {
701654a2b0SAlexandre Belloni txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2);
711654a2b0SAlexandre Belloni txbuf[1] = 0;
721654a2b0SAlexandre Belloni ret = spi_write_then_read(spi, txbuf, 2, NULL, 0);
731654a2b0SAlexandre Belloni if (ret < 0)
741654a2b0SAlexandre Belloni return ret;
751654a2b0SAlexandre Belloni }
761654a2b0SAlexandre Belloni
77e0ac4761SAtsushi Nemoto /* Transfer 5 bytes before writing SEC. This gives 31us for carry. */
78e0ac4761SAtsushi Nemoto txp = txbuf;
79e0ac4761SAtsushi Nemoto txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
80e0ac4761SAtsushi Nemoto txbuf[1] = 0; /* dummy */
81e0ac4761SAtsushi Nemoto txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
82e0ac4761SAtsushi Nemoto txbuf[3] = 0; /* dummy */
83e0ac4761SAtsushi Nemoto txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */
84e0ac4761SAtsushi Nemoto txp = &txbuf[5];
85fe20ba70SAdrian Bunk txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec);
86fe20ba70SAdrian Bunk txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min);
87e0ac4761SAtsushi Nemoto if (pdata->rtc_24h) {
88fe20ba70SAdrian Bunk txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour);
89e0ac4761SAtsushi Nemoto } else {
90e0ac4761SAtsushi Nemoto /* hour 0 is AM12, noon is PM12 */
91fe20ba70SAdrian Bunk txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) |
92e0ac4761SAtsushi Nemoto (tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0);
93e0ac4761SAtsushi Nemoto }
94fe20ba70SAdrian Bunk txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday);
95fe20ba70SAdrian Bunk txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday);
96fe20ba70SAdrian Bunk txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) |
97e0ac4761SAtsushi Nemoto (tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0);
98fe20ba70SAdrian Bunk txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100);
99e0ac4761SAtsushi Nemoto /* write in one transfer to avoid data inconsistency */
100e0ac4761SAtsushi Nemoto ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0);
101e0ac4761SAtsushi Nemoto udelay(62); /* Tcsr 62us */
102e0ac4761SAtsushi Nemoto return ret;
103e0ac4761SAtsushi Nemoto }
104e0ac4761SAtsushi Nemoto
105e0ac4761SAtsushi Nemoto static int
rs5c348_rtc_read_time(struct device * dev,struct rtc_time * tm)106e0ac4761SAtsushi Nemoto rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
107e0ac4761SAtsushi Nemoto {
108e0ac4761SAtsushi Nemoto struct spi_device *spi = to_spi_device(dev);
109f6405afeSJingoo Han struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
110e0ac4761SAtsushi Nemoto u8 txbuf[5], rxbuf[7];
111e0ac4761SAtsushi Nemoto int ret;
112e0ac4761SAtsushi Nemoto
1131654a2b0SAlexandre Belloni ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
1141654a2b0SAlexandre Belloni if (ret < 0)
1151654a2b0SAlexandre Belloni return ret;
1161654a2b0SAlexandre Belloni if (ret & RS5C348_BIT_VDET)
1171654a2b0SAlexandre Belloni dev_warn(&spi->dev, "voltage-low detected.\n");
1181654a2b0SAlexandre Belloni if (ret & RS5C348_BIT_XSTP) {
1191654a2b0SAlexandre Belloni dev_warn(&spi->dev, "oscillator-stop detected.\n");
1201654a2b0SAlexandre Belloni return -EINVAL;
1211654a2b0SAlexandre Belloni }
1221654a2b0SAlexandre Belloni
123e0ac4761SAtsushi Nemoto /* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
124e0ac4761SAtsushi Nemoto txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
125e0ac4761SAtsushi Nemoto txbuf[1] = 0; /* dummy */
126e0ac4761SAtsushi Nemoto txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
127e0ac4761SAtsushi Nemoto txbuf[3] = 0; /* dummy */
128e0ac4761SAtsushi Nemoto txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
129e0ac4761SAtsushi Nemoto
130e0ac4761SAtsushi Nemoto /* read in one transfer to avoid data inconsistency */
131e0ac4761SAtsushi Nemoto ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
132e0ac4761SAtsushi Nemoto rxbuf, sizeof(rxbuf));
133e0ac4761SAtsushi Nemoto udelay(62); /* Tcsr 62us */
134e0ac4761SAtsushi Nemoto if (ret < 0)
135e0ac4761SAtsushi Nemoto return ret;
136e0ac4761SAtsushi Nemoto
137fe20ba70SAdrian Bunk tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
138fe20ba70SAdrian Bunk tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
139fe20ba70SAdrian Bunk tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
140e0ac4761SAtsushi Nemoto if (!pdata->rtc_24h) {
1417dbfb315SAtsushi Nemoto if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
1427dbfb315SAtsushi Nemoto tm->tm_hour -= 20;
143e0ac4761SAtsushi Nemoto tm->tm_hour %= 12;
144e0ac4761SAtsushi Nemoto tm->tm_hour += 12;
1457dbfb315SAtsushi Nemoto } else
1467dbfb315SAtsushi Nemoto tm->tm_hour %= 12;
147e0ac4761SAtsushi Nemoto }
148fe20ba70SAdrian Bunk tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
149fe20ba70SAdrian Bunk tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
150e0ac4761SAtsushi Nemoto tm->tm_mon =
151fe20ba70SAdrian Bunk bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
152e0ac4761SAtsushi Nemoto /* year is 1900 + tm->tm_year */
153fe20ba70SAdrian Bunk tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
154e0ac4761SAtsushi Nemoto ((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
155e0ac4761SAtsushi Nemoto
156e0ac4761SAtsushi Nemoto return 0;
157e0ac4761SAtsushi Nemoto }
158e0ac4761SAtsushi Nemoto
159ff8371acSDavid Brownell static const struct rtc_class_ops rs5c348_rtc_ops = {
160e0ac4761SAtsushi Nemoto .read_time = rs5c348_rtc_read_time,
161e0ac4761SAtsushi Nemoto .set_time = rs5c348_rtc_set_time,
162e0ac4761SAtsushi Nemoto };
163e0ac4761SAtsushi Nemoto
rs5c348_probe(struct spi_device * spi)1645a167f45SGreg Kroah-Hartman static int rs5c348_probe(struct spi_device *spi)
165e0ac4761SAtsushi Nemoto {
166e0ac4761SAtsushi Nemoto int ret;
167e0ac4761SAtsushi Nemoto struct rtc_device *rtc;
168e0ac4761SAtsushi Nemoto struct rs5c348_plat_data *pdata;
169e0ac4761SAtsushi Nemoto
1708fb1ecb3SJingoo Han pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data),
1718fb1ecb3SJingoo Han GFP_KERNEL);
172e0ac4761SAtsushi Nemoto if (!pdata)
173e0ac4761SAtsushi Nemoto return -ENOMEM;
174e0ac4761SAtsushi Nemoto spi->dev.platform_data = pdata;
175e0ac4761SAtsushi Nemoto
176e0ac4761SAtsushi Nemoto /* Check D7 of SECOND register */
177e0ac4761SAtsushi Nemoto ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS));
178e0ac4761SAtsushi Nemoto if (ret < 0 || (ret & 0x80)) {
179e0ac4761SAtsushi Nemoto dev_err(&spi->dev, "not found.\n");
18002a6e129SAlexandre Belloni return ret;
181e0ac4761SAtsushi Nemoto }
182e0ac4761SAtsushi Nemoto
183e0ac4761SAtsushi Nemoto dev_info(&spi->dev, "spiclk %u KHz.\n",
184e0ac4761SAtsushi Nemoto (spi->max_speed_hz + 500) / 1000);
185e0ac4761SAtsushi Nemoto
186e0ac4761SAtsushi Nemoto ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1));
187e0ac4761SAtsushi Nemoto if (ret < 0)
18802a6e129SAlexandre Belloni return ret;
189e0ac4761SAtsushi Nemoto if (ret & RS5C348_BIT_24H)
190e0ac4761SAtsushi Nemoto pdata->rtc_24h = 1;
191e0ac4761SAtsushi Nemoto
1922d7be4edSAlexandre Belloni rtc = devm_rtc_allocate_device(&spi->dev);
19302a6e129SAlexandre Belloni if (IS_ERR(rtc))
19402a6e129SAlexandre Belloni return PTR_ERR(rtc);
195e0ac4761SAtsushi Nemoto
196e0ac4761SAtsushi Nemoto pdata->rtc = rtc;
197e0ac4761SAtsushi Nemoto
1982d7be4edSAlexandre Belloni rtc->ops = &rs5c348_rtc_ops;
1992d7be4edSAlexandre Belloni
200*fdcfd854SBartosz Golaszewski return devm_rtc_register_device(rtc);
201e0ac4761SAtsushi Nemoto }
202e0ac4761SAtsushi Nemoto
203e0ac4761SAtsushi Nemoto static struct spi_driver rs5c348_driver = {
204e0ac4761SAtsushi Nemoto .driver = {
2059f90a03aSAtsushi Nemoto .name = "rtc-rs5c348",
206e0ac4761SAtsushi Nemoto },
207e0ac4761SAtsushi Nemoto .probe = rs5c348_probe,
208e0ac4761SAtsushi Nemoto };
209e0ac4761SAtsushi Nemoto
210109e9418SAxel Lin module_spi_driver(rs5c348_driver);
211e0ac4761SAtsushi Nemoto
212e0ac4761SAtsushi Nemoto MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
213e0ac4761SAtsushi Nemoto MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver");
214e0ac4761SAtsushi Nemoto MODULE_LICENSE("GPL");
215e0626e38SAnton Vorontsov MODULE_ALIAS("spi:rtc-rs5c348");
216