17342e2a7SAlexandre Belloni // SPDX-License-Identifier: GPL-2.0+
29aa449beSKevin Wells /*
39aa449beSKevin Wells * Copyright (C) 2010 NXP Semiconductors
49aa449beSKevin Wells */
59aa449beSKevin Wells
69aa449beSKevin Wells #include <linux/kernel.h>
79aa449beSKevin Wells #include <linux/module.h>
89aa449beSKevin Wells #include <linux/init.h>
99aa449beSKevin Wells #include <linux/platform_device.h>
109aa449beSKevin Wells #include <linux/spinlock.h>
119aa449beSKevin Wells #include <linux/rtc.h>
129aa449beSKevin Wells #include <linux/slab.h>
139aa449beSKevin Wells #include <linux/io.h>
14e862e7c4SRoland Stigge #include <linux/of.h>
159aa449beSKevin Wells
169aa449beSKevin Wells /*
179aa449beSKevin Wells * Clock and Power control register offsets
189aa449beSKevin Wells */
199aa449beSKevin Wells #define LPC32XX_RTC_UCOUNT 0x00
209aa449beSKevin Wells #define LPC32XX_RTC_DCOUNT 0x04
219aa449beSKevin Wells #define LPC32XX_RTC_MATCH0 0x08
229aa449beSKevin Wells #define LPC32XX_RTC_MATCH1 0x0C
239aa449beSKevin Wells #define LPC32XX_RTC_CTRL 0x10
249aa449beSKevin Wells #define LPC32XX_RTC_INTSTAT 0x14
259aa449beSKevin Wells #define LPC32XX_RTC_KEY 0x18
269aa449beSKevin Wells #define LPC32XX_RTC_SRAM 0x80
279aa449beSKevin Wells
289aa449beSKevin Wells #define LPC32XX_RTC_CTRL_MATCH0 (1 << 0)
299aa449beSKevin Wells #define LPC32XX_RTC_CTRL_MATCH1 (1 << 1)
309aa449beSKevin Wells #define LPC32XX_RTC_CTRL_ONSW_MATCH0 (1 << 2)
319aa449beSKevin Wells #define LPC32XX_RTC_CTRL_ONSW_MATCH1 (1 << 3)
329aa449beSKevin Wells #define LPC32XX_RTC_CTRL_SW_RESET (1 << 4)
339aa449beSKevin Wells #define LPC32XX_RTC_CTRL_CNTR_DIS (1 << 6)
349aa449beSKevin Wells #define LPC32XX_RTC_CTRL_ONSW_FORCE_HI (1 << 7)
359aa449beSKevin Wells
369aa449beSKevin Wells #define LPC32XX_RTC_INTSTAT_MATCH0 (1 << 0)
379aa449beSKevin Wells #define LPC32XX_RTC_INTSTAT_MATCH1 (1 << 1)
389aa449beSKevin Wells #define LPC32XX_RTC_INTSTAT_ONSW (1 << 2)
399aa449beSKevin Wells
409aa449beSKevin Wells #define LPC32XX_RTC_KEY_ONSW_LOADVAL 0xB5C13F27
419aa449beSKevin Wells
429aa449beSKevin Wells #define rtc_readl(dev, reg) \
439aa449beSKevin Wells __raw_readl((dev)->rtc_base + (reg))
449aa449beSKevin Wells #define rtc_writel(dev, reg, val) \
459aa449beSKevin Wells __raw_writel((val), (dev)->rtc_base + (reg))
469aa449beSKevin Wells
479aa449beSKevin Wells struct lpc32xx_rtc {
489aa449beSKevin Wells void __iomem *rtc_base;
499aa449beSKevin Wells int irq;
509aa449beSKevin Wells unsigned char alarm_enabled;
519aa449beSKevin Wells struct rtc_device *rtc;
529aa449beSKevin Wells spinlock_t lock;
539aa449beSKevin Wells };
549aa449beSKevin Wells
lpc32xx_rtc_read_time(struct device * dev,struct rtc_time * time)559aa449beSKevin Wells static int lpc32xx_rtc_read_time(struct device *dev, struct rtc_time *time)
569aa449beSKevin Wells {
579aa449beSKevin Wells unsigned long elapsed_sec;
589aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
599aa449beSKevin Wells
609aa449beSKevin Wells elapsed_sec = rtc_readl(rtc, LPC32XX_RTC_UCOUNT);
61f04dd349SAlexandre Belloni rtc_time64_to_tm(elapsed_sec, time);
629aa449beSKevin Wells
63ab62670eSAlexandre Belloni return 0;
649aa449beSKevin Wells }
659aa449beSKevin Wells
lpc32xx_rtc_set_time(struct device * dev,struct rtc_time * time)6634b21c9eSAlexandre Belloni static int lpc32xx_rtc_set_time(struct device *dev, struct rtc_time *time)
679aa449beSKevin Wells {
689aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
6934b21c9eSAlexandre Belloni u32 secs = rtc_tm_to_time64(time);
709aa449beSKevin Wells u32 tmp;
719aa449beSKevin Wells
729aa449beSKevin Wells spin_lock_irq(&rtc->lock);
739aa449beSKevin Wells
749aa449beSKevin Wells /* RTC must be disabled during count update */
759aa449beSKevin Wells tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
769aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp | LPC32XX_RTC_CTRL_CNTR_DIS);
779aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_UCOUNT, secs);
789aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_DCOUNT, 0xFFFFFFFF - secs);
799aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp &= ~LPC32XX_RTC_CTRL_CNTR_DIS);
809aa449beSKevin Wells
819aa449beSKevin Wells spin_unlock_irq(&rtc->lock);
829aa449beSKevin Wells
839aa449beSKevin Wells return 0;
849aa449beSKevin Wells }
859aa449beSKevin Wells
lpc32xx_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * wkalrm)869aa449beSKevin Wells static int lpc32xx_rtc_read_alarm(struct device *dev,
879aa449beSKevin Wells struct rtc_wkalrm *wkalrm)
889aa449beSKevin Wells {
899aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
909aa449beSKevin Wells
91f04dd349SAlexandre Belloni rtc_time64_to_tm(rtc_readl(rtc, LPC32XX_RTC_MATCH0), &wkalrm->time);
929aa449beSKevin Wells wkalrm->enabled = rtc->alarm_enabled;
939aa449beSKevin Wells wkalrm->pending = !!(rtc_readl(rtc, LPC32XX_RTC_INTSTAT) &
949aa449beSKevin Wells LPC32XX_RTC_INTSTAT_MATCH0);
959aa449beSKevin Wells
969aa449beSKevin Wells return rtc_valid_tm(&wkalrm->time);
979aa449beSKevin Wells }
989aa449beSKevin Wells
lpc32xx_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * wkalrm)999aa449beSKevin Wells static int lpc32xx_rtc_set_alarm(struct device *dev,
1009aa449beSKevin Wells struct rtc_wkalrm *wkalrm)
1019aa449beSKevin Wells {
1029aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
1039aa449beSKevin Wells unsigned long alarmsecs;
1049aa449beSKevin Wells u32 tmp;
1059aa449beSKevin Wells
106f04dd349SAlexandre Belloni alarmsecs = rtc_tm_to_time64(&wkalrm->time);
1079aa449beSKevin Wells
1089aa449beSKevin Wells spin_lock_irq(&rtc->lock);
1099aa449beSKevin Wells
1109aa449beSKevin Wells /* Disable alarm during update */
1119aa449beSKevin Wells tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
1129aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp & ~LPC32XX_RTC_CTRL_MATCH0);
1139aa449beSKevin Wells
1149aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_MATCH0, alarmsecs);
1159aa449beSKevin Wells
1169aa449beSKevin Wells rtc->alarm_enabled = wkalrm->enabled;
1179aa449beSKevin Wells if (wkalrm->enabled) {
1189aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
1199aa449beSKevin Wells LPC32XX_RTC_INTSTAT_MATCH0);
1209aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp |
1219aa449beSKevin Wells LPC32XX_RTC_CTRL_MATCH0);
1229aa449beSKevin Wells }
1239aa449beSKevin Wells
1249aa449beSKevin Wells spin_unlock_irq(&rtc->lock);
1259aa449beSKevin Wells
1269aa449beSKevin Wells return 0;
1279aa449beSKevin Wells }
1289aa449beSKevin Wells
lpc32xx_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)1299aa449beSKevin Wells static int lpc32xx_rtc_alarm_irq_enable(struct device *dev,
1309aa449beSKevin Wells unsigned int enabled)
1319aa449beSKevin Wells {
1329aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
1339aa449beSKevin Wells u32 tmp;
1349aa449beSKevin Wells
1359aa449beSKevin Wells spin_lock_irq(&rtc->lock);
1369aa449beSKevin Wells tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
1379aa449beSKevin Wells
1389aa449beSKevin Wells if (enabled) {
1399aa449beSKevin Wells rtc->alarm_enabled = 1;
1409aa449beSKevin Wells tmp |= LPC32XX_RTC_CTRL_MATCH0;
1419aa449beSKevin Wells } else {
1429aa449beSKevin Wells rtc->alarm_enabled = 0;
1439aa449beSKevin Wells tmp &= ~LPC32XX_RTC_CTRL_MATCH0;
1449aa449beSKevin Wells }
1459aa449beSKevin Wells
1469aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
1479aa449beSKevin Wells spin_unlock_irq(&rtc->lock);
1489aa449beSKevin Wells
1499aa449beSKevin Wells return 0;
1509aa449beSKevin Wells }
1519aa449beSKevin Wells
lpc32xx_rtc_alarm_interrupt(int irq,void * dev)1529aa449beSKevin Wells static irqreturn_t lpc32xx_rtc_alarm_interrupt(int irq, void *dev)
1539aa449beSKevin Wells {
1549aa449beSKevin Wells struct lpc32xx_rtc *rtc = dev;
1559aa449beSKevin Wells
1569aa449beSKevin Wells spin_lock(&rtc->lock);
1579aa449beSKevin Wells
1589aa449beSKevin Wells /* Disable alarm interrupt */
1599aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL,
1609aa449beSKevin Wells rtc_readl(rtc, LPC32XX_RTC_CTRL) &
1619aa449beSKevin Wells ~LPC32XX_RTC_CTRL_MATCH0);
1629aa449beSKevin Wells rtc->alarm_enabled = 0;
1639aa449beSKevin Wells
1649aa449beSKevin Wells /*
1659aa449beSKevin Wells * Write a large value to the match value so the RTC won't
1669aa449beSKevin Wells * keep firing the match status
1679aa449beSKevin Wells */
1689aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
1699aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_INTSTAT, LPC32XX_RTC_INTSTAT_MATCH0);
1709aa449beSKevin Wells
1719aa449beSKevin Wells spin_unlock(&rtc->lock);
1729aa449beSKevin Wells
1739aa449beSKevin Wells rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
1749aa449beSKevin Wells
1759aa449beSKevin Wells return IRQ_HANDLED;
1769aa449beSKevin Wells }
1779aa449beSKevin Wells
1789aa449beSKevin Wells static const struct rtc_class_ops lpc32xx_rtc_ops = {
1799aa449beSKevin Wells .read_time = lpc32xx_rtc_read_time,
18034b21c9eSAlexandre Belloni .set_time = lpc32xx_rtc_set_time,
1819aa449beSKevin Wells .read_alarm = lpc32xx_rtc_read_alarm,
1829aa449beSKevin Wells .set_alarm = lpc32xx_rtc_set_alarm,
1839aa449beSKevin Wells .alarm_irq_enable = lpc32xx_rtc_alarm_irq_enable,
1849aa449beSKevin Wells };
1859aa449beSKevin Wells
lpc32xx_rtc_probe(struct platform_device * pdev)1865a167f45SGreg Kroah-Hartman static int lpc32xx_rtc_probe(struct platform_device *pdev)
1879aa449beSKevin Wells {
1889aa449beSKevin Wells struct lpc32xx_rtc *rtc;
189ba4a84f5SAlexandre Belloni int err;
1909aa449beSKevin Wells u32 tmp;
1919aa449beSKevin Wells
1929aa449beSKevin Wells rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
1935c336b0aSJingoo Han if (unlikely(!rtc))
1949aa449beSKevin Wells return -ENOMEM;
1955c336b0aSJingoo Han
19609ef18bcSYueHaibing rtc->rtc_base = devm_platform_ioremap_resource(pdev, 0);
1977c1d69eeSJulia Lawall if (IS_ERR(rtc->rtc_base))
1987c1d69eeSJulia Lawall return PTR_ERR(rtc->rtc_base);
1999aa449beSKevin Wells
2009aa449beSKevin Wells spin_lock_init(&rtc->lock);
2019aa449beSKevin Wells
2029aa449beSKevin Wells /*
20325985edcSLucas De Marchi * The RTC is on a separate power domain and can keep it's state
2049aa449beSKevin Wells * across a chip power cycle. If the RTC has never been previously
2059aa449beSKevin Wells * setup, then set it up now for the first time.
2069aa449beSKevin Wells */
2079aa449beSKevin Wells tmp = rtc_readl(rtc, LPC32XX_RTC_CTRL);
2089aa449beSKevin Wells if (rtc_readl(rtc, LPC32XX_RTC_KEY) != LPC32XX_RTC_KEY_ONSW_LOADVAL) {
2099aa449beSKevin Wells tmp &= ~(LPC32XX_RTC_CTRL_SW_RESET |
2109aa449beSKevin Wells LPC32XX_RTC_CTRL_CNTR_DIS |
2119aa449beSKevin Wells LPC32XX_RTC_CTRL_MATCH0 |
2129aa449beSKevin Wells LPC32XX_RTC_CTRL_MATCH1 |
2139aa449beSKevin Wells LPC32XX_RTC_CTRL_ONSW_MATCH0 |
2149aa449beSKevin Wells LPC32XX_RTC_CTRL_ONSW_MATCH1 |
2159aa449beSKevin Wells LPC32XX_RTC_CTRL_ONSW_FORCE_HI);
2169aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL, tmp);
2179aa449beSKevin Wells
2189aa449beSKevin Wells /* Clear latched interrupt states */
2199aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_MATCH0, 0xFFFFFFFF);
2209aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_INTSTAT,
2219aa449beSKevin Wells LPC32XX_RTC_INTSTAT_MATCH0 |
2229aa449beSKevin Wells LPC32XX_RTC_INTSTAT_MATCH1 |
2239aa449beSKevin Wells LPC32XX_RTC_INTSTAT_ONSW);
2249aa449beSKevin Wells
2259aa449beSKevin Wells /* Write key value to RTC so it won't reload on reset */
2269aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_KEY,
2279aa449beSKevin Wells LPC32XX_RTC_KEY_ONSW_LOADVAL);
2289aa449beSKevin Wells } else {
2299aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL,
2309aa449beSKevin Wells tmp & ~LPC32XX_RTC_CTRL_MATCH0);
2319aa449beSKevin Wells }
2329aa449beSKevin Wells
2339aa449beSKevin Wells platform_set_drvdata(pdev, rtc);
2349aa449beSKevin Wells
2356bbad585SAlexandre Belloni rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
2366bbad585SAlexandre Belloni if (IS_ERR(rtc->rtc))
2379aa449beSKevin Wells return PTR_ERR(rtc->rtc);
2386bbad585SAlexandre Belloni
2396bbad585SAlexandre Belloni rtc->rtc->ops = &lpc32xx_rtc_ops;
2403a134269SAlexandre Belloni rtc->rtc->range_max = U32_MAX;
2416bbad585SAlexandre Belloni
242*fdcfd854SBartosz Golaszewski err = devm_rtc_register_device(rtc->rtc);
2436bbad585SAlexandre Belloni if (err)
2446bbad585SAlexandre Belloni return err;
2459aa449beSKevin Wells
2469aa449beSKevin Wells /*
2479aa449beSKevin Wells * IRQ is enabled after device registration in case alarm IRQ
2489aa449beSKevin Wells * is pending upon suspend exit.
2499aa449beSKevin Wells */
250ba4a84f5SAlexandre Belloni rtc->irq = platform_get_irq(pdev, 0);
251ba4a84f5SAlexandre Belloni if (rtc->irq < 0) {
252ba4a84f5SAlexandre Belloni dev_warn(&pdev->dev, "Can't get interrupt resource\n");
253ba4a84f5SAlexandre Belloni } else {
2549aa449beSKevin Wells if (devm_request_irq(&pdev->dev, rtc->irq,
2559aa449beSKevin Wells lpc32xx_rtc_alarm_interrupt,
2562f6e5f94SYong Zhang 0, pdev->name, rtc) < 0) {
2579aa449beSKevin Wells dev_warn(&pdev->dev, "Can't request interrupt.\n");
2589aa449beSKevin Wells rtc->irq = -1;
2599aa449beSKevin Wells } else {
2609aa449beSKevin Wells device_init_wakeup(&pdev->dev, 1);
2619aa449beSKevin Wells }
2629aa449beSKevin Wells }
2639aa449beSKevin Wells
2649aa449beSKevin Wells return 0;
2659aa449beSKevin Wells }
2669aa449beSKevin Wells
2679aa449beSKevin Wells #ifdef CONFIG_PM
lpc32xx_rtc_suspend(struct device * dev)2689aa449beSKevin Wells static int lpc32xx_rtc_suspend(struct device *dev)
2699aa449beSKevin Wells {
27085368bb9SWolfram Sang struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
2719aa449beSKevin Wells
2729aa449beSKevin Wells if (rtc->irq >= 0) {
27385368bb9SWolfram Sang if (device_may_wakeup(dev))
2749aa449beSKevin Wells enable_irq_wake(rtc->irq);
2759aa449beSKevin Wells else
2769aa449beSKevin Wells disable_irq_wake(rtc->irq);
2779aa449beSKevin Wells }
2789aa449beSKevin Wells
2799aa449beSKevin Wells return 0;
2809aa449beSKevin Wells }
2819aa449beSKevin Wells
lpc32xx_rtc_resume(struct device * dev)2829aa449beSKevin Wells static int lpc32xx_rtc_resume(struct device *dev)
2839aa449beSKevin Wells {
28485368bb9SWolfram Sang struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
2859aa449beSKevin Wells
28685368bb9SWolfram Sang if (rtc->irq >= 0 && device_may_wakeup(dev))
2879aa449beSKevin Wells disable_irq_wake(rtc->irq);
2889aa449beSKevin Wells
2899aa449beSKevin Wells return 0;
2909aa449beSKevin Wells }
2919aa449beSKevin Wells
2929aa449beSKevin Wells /* Unconditionally disable the alarm */
lpc32xx_rtc_freeze(struct device * dev)2939aa449beSKevin Wells static int lpc32xx_rtc_freeze(struct device *dev)
2949aa449beSKevin Wells {
29585368bb9SWolfram Sang struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
2969aa449beSKevin Wells
2979aa449beSKevin Wells spin_lock_irq(&rtc->lock);
2989aa449beSKevin Wells
2999aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL,
3009aa449beSKevin Wells rtc_readl(rtc, LPC32XX_RTC_CTRL) &
3019aa449beSKevin Wells ~LPC32XX_RTC_CTRL_MATCH0);
3029aa449beSKevin Wells
3039aa449beSKevin Wells spin_unlock_irq(&rtc->lock);
3049aa449beSKevin Wells
3059aa449beSKevin Wells return 0;
3069aa449beSKevin Wells }
3079aa449beSKevin Wells
lpc32xx_rtc_thaw(struct device * dev)3089aa449beSKevin Wells static int lpc32xx_rtc_thaw(struct device *dev)
3099aa449beSKevin Wells {
31085368bb9SWolfram Sang struct lpc32xx_rtc *rtc = dev_get_drvdata(dev);
3119aa449beSKevin Wells
3129aa449beSKevin Wells if (rtc->alarm_enabled) {
3139aa449beSKevin Wells spin_lock_irq(&rtc->lock);
3149aa449beSKevin Wells
3159aa449beSKevin Wells rtc_writel(rtc, LPC32XX_RTC_CTRL,
3169aa449beSKevin Wells rtc_readl(rtc, LPC32XX_RTC_CTRL) |
3179aa449beSKevin Wells LPC32XX_RTC_CTRL_MATCH0);
3189aa449beSKevin Wells
3199aa449beSKevin Wells spin_unlock_irq(&rtc->lock);
3209aa449beSKevin Wells }
3219aa449beSKevin Wells
3229aa449beSKevin Wells return 0;
3239aa449beSKevin Wells }
3249aa449beSKevin Wells
3259aa449beSKevin Wells static const struct dev_pm_ops lpc32xx_rtc_pm_ops = {
3269aa449beSKevin Wells .suspend = lpc32xx_rtc_suspend,
3279aa449beSKevin Wells .resume = lpc32xx_rtc_resume,
3289aa449beSKevin Wells .freeze = lpc32xx_rtc_freeze,
3299aa449beSKevin Wells .thaw = lpc32xx_rtc_thaw,
3309aa449beSKevin Wells .restore = lpc32xx_rtc_resume
3319aa449beSKevin Wells };
3329aa449beSKevin Wells
3339aa449beSKevin Wells #define LPC32XX_RTC_PM_OPS (&lpc32xx_rtc_pm_ops)
3349aa449beSKevin Wells #else
3359aa449beSKevin Wells #define LPC32XX_RTC_PM_OPS NULL
3369aa449beSKevin Wells #endif
3379aa449beSKevin Wells
338e862e7c4SRoland Stigge #ifdef CONFIG_OF
339e862e7c4SRoland Stigge static const struct of_device_id lpc32xx_rtc_match[] = {
340e862e7c4SRoland Stigge { .compatible = "nxp,lpc3220-rtc" },
341e862e7c4SRoland Stigge { }
342e862e7c4SRoland Stigge };
343e862e7c4SRoland Stigge MODULE_DEVICE_TABLE(of, lpc32xx_rtc_match);
344e862e7c4SRoland Stigge #endif
345e862e7c4SRoland Stigge
3469aa449beSKevin Wells static struct platform_driver lpc32xx_rtc_driver = {
3479aa449beSKevin Wells .probe = lpc32xx_rtc_probe,
3489aa449beSKevin Wells .driver = {
3496bbad585SAlexandre Belloni .name = "rtc-lpc32xx",
350e862e7c4SRoland Stigge .pm = LPC32XX_RTC_PM_OPS,
351e862e7c4SRoland Stigge .of_match_table = of_match_ptr(lpc32xx_rtc_match),
3529aa449beSKevin Wells },
3539aa449beSKevin Wells };
3549aa449beSKevin Wells
3550c4eae66SAxel Lin module_platform_driver(lpc32xx_rtc_driver);
3569aa449beSKevin Wells
3579aa449beSKevin Wells MODULE_AUTHOR("Kevin Wells <wellsk40@gmail.com");
3589aa449beSKevin Wells MODULE_DESCRIPTION("RTC driver for the LPC32xx SoC");
3599aa449beSKevin Wells MODULE_LICENSE("GPL");
3609aa449beSKevin Wells MODULE_ALIAS("platform:rtc-lpc32xx");
361