xref: /openbmc/linux/drivers/rtc/rtc-loongson.c (revision 060f35a317ef09101b128f399dce7ed13d019461)
11b733a9eSBinbin Zhou // SPDX-License-Identifier: GPL-2.0-or-later
21b733a9eSBinbin Zhou /*
31b733a9eSBinbin Zhou  * Loongson RTC driver
41b733a9eSBinbin Zhou  *
51b733a9eSBinbin Zhou  * Maintained out-of-tree by Huacai Chen <chenhuacai@kernel.org>.
61b733a9eSBinbin Zhou  * Rewritten for mainline by WANG Xuerui <git@xen0n.name>.
71b733a9eSBinbin Zhou  *                           Binbin Zhou <zhoubinbin@loongson.cn>
81b733a9eSBinbin Zhou  */
91b733a9eSBinbin Zhou 
101b733a9eSBinbin Zhou #include <linux/bitfield.h>
111b733a9eSBinbin Zhou #include <linux/kernel.h>
121b733a9eSBinbin Zhou #include <linux/module.h>
131b733a9eSBinbin Zhou #include <linux/platform_device.h>
141b733a9eSBinbin Zhou #include <linux/regmap.h>
151b733a9eSBinbin Zhou #include <linux/rtc.h>
161b733a9eSBinbin Zhou #include <linux/acpi.h>
171b733a9eSBinbin Zhou 
181b733a9eSBinbin Zhou /* Time Of Year(TOY) counters registers */
191b733a9eSBinbin Zhou #define TOY_TRIM_REG		0x20 /* Must be initialized to 0 */
201b733a9eSBinbin Zhou #define TOY_WRITE0_REG		0x24 /* TOY low 32-bits value (write-only) */
211b733a9eSBinbin Zhou #define TOY_WRITE1_REG		0x28 /* TOY high 32-bits value (write-only) */
221b733a9eSBinbin Zhou #define TOY_READ0_REG		0x2c /* TOY low 32-bits value (read-only) */
231b733a9eSBinbin Zhou #define TOY_READ1_REG		0x30 /* TOY high 32-bits value (read-only) */
241b733a9eSBinbin Zhou #define TOY_MATCH0_REG		0x34 /* TOY timing interrupt 0 */
251b733a9eSBinbin Zhou #define TOY_MATCH1_REG		0x38 /* TOY timing interrupt 1 */
261b733a9eSBinbin Zhou #define TOY_MATCH2_REG		0x3c /* TOY timing interrupt 2 */
271b733a9eSBinbin Zhou 
281b733a9eSBinbin Zhou /* RTC counters registers */
291b733a9eSBinbin Zhou #define RTC_CTRL_REG		0x40 /* TOY and RTC control register */
301b733a9eSBinbin Zhou #define RTC_TRIM_REG		0x60 /* Must be initialized to 0 */
311b733a9eSBinbin Zhou #define RTC_WRITE0_REG		0x64 /* RTC counters value (write-only) */
321b733a9eSBinbin Zhou #define RTC_READ0_REG		0x68 /* RTC counters value (read-only) */
331b733a9eSBinbin Zhou #define RTC_MATCH0_REG		0x6c /* RTC timing interrupt 0 */
341b733a9eSBinbin Zhou #define RTC_MATCH1_REG		0x70 /* RTC timing interrupt 1 */
351b733a9eSBinbin Zhou #define RTC_MATCH2_REG		0x74 /* RTC timing interrupt 2 */
361b733a9eSBinbin Zhou 
371b733a9eSBinbin Zhou /* bitmask of TOY_WRITE0_REG */
381b733a9eSBinbin Zhou #define TOY_MON			GENMASK(31, 26)
391b733a9eSBinbin Zhou #define TOY_DAY			GENMASK(25, 21)
401b733a9eSBinbin Zhou #define TOY_HOUR		GENMASK(20, 16)
411b733a9eSBinbin Zhou #define TOY_MIN			GENMASK(15, 10)
421b733a9eSBinbin Zhou #define TOY_SEC			GENMASK(9, 4)
431b733a9eSBinbin Zhou #define TOY_MSEC		GENMASK(3, 0)
441b733a9eSBinbin Zhou 
451b733a9eSBinbin Zhou /* bitmask of TOY_MATCH0/1/2_REG */
461b733a9eSBinbin Zhou #define TOY_MATCH_YEAR		GENMASK(31, 26)
471b733a9eSBinbin Zhou #define TOY_MATCH_MON		GENMASK(25, 22)
481b733a9eSBinbin Zhou #define TOY_MATCH_DAY		GENMASK(21, 17)
491b733a9eSBinbin Zhou #define TOY_MATCH_HOUR		GENMASK(16, 12)
501b733a9eSBinbin Zhou #define TOY_MATCH_MIN		GENMASK(11, 6)
511b733a9eSBinbin Zhou #define TOY_MATCH_SEC		GENMASK(5, 0)
521b733a9eSBinbin Zhou 
531b733a9eSBinbin Zhou /* bitmask of RTC_CTRL_REG */
541b733a9eSBinbin Zhou #define RTC_ENABLE		BIT(13) /* 1: RTC counters enable */
551b733a9eSBinbin Zhou #define TOY_ENABLE		BIT(11) /* 1: TOY counters enable */
561b733a9eSBinbin Zhou #define OSC_ENABLE		BIT(8) /* 1: 32.768k crystal enable */
571b733a9eSBinbin Zhou #define TOY_ENABLE_MASK		(TOY_ENABLE | OSC_ENABLE)
581b733a9eSBinbin Zhou 
591b733a9eSBinbin Zhou /* PM domain registers */
601b733a9eSBinbin Zhou #define PM1_STS_REG		0x0c	/* Power management 1 status register */
611b733a9eSBinbin Zhou #define RTC_STS			BIT(10)	/* RTC status */
621b733a9eSBinbin Zhou #define PM1_EN_REG		0x10	/* Power management 1 enable register */
631b733a9eSBinbin Zhou #define RTC_EN			BIT(10)	/* RTC event enable */
641b733a9eSBinbin Zhou 
651b733a9eSBinbin Zhou /*
661b733a9eSBinbin Zhou  * According to the LS1C manual, RTC_CTRL and alarm-related registers are not defined.
671b733a9eSBinbin Zhou  * Accessing the relevant registers will cause the system to hang.
681b733a9eSBinbin Zhou  */
691b733a9eSBinbin Zhou #define LS1C_RTC_CTRL_WORKAROUND	BIT(0)
701b733a9eSBinbin Zhou 
711b733a9eSBinbin Zhou struct loongson_rtc_config {
721b733a9eSBinbin Zhou 	u32 pm_offset;	/* Offset of PM domain, for RTC alarm wakeup */
731b733a9eSBinbin Zhou 	u32 flags;	/* Workaround bits */
741b733a9eSBinbin Zhou };
751b733a9eSBinbin Zhou 
761b733a9eSBinbin Zhou struct loongson_rtc_priv {
771b733a9eSBinbin Zhou 	spinlock_t lock;	/* protects PM registers access */
781b733a9eSBinbin Zhou 	u32 fix_year;		/* RTC alarm year compensation value */
791b733a9eSBinbin Zhou 	struct rtc_device *rtcdev;
801b733a9eSBinbin Zhou 	struct regmap *regmap;
811b733a9eSBinbin Zhou 	void __iomem *pm_base;	/* PM domain base, for RTC alarm wakeup */
821b733a9eSBinbin Zhou 	const struct loongson_rtc_config *config;
831b733a9eSBinbin Zhou };
841b733a9eSBinbin Zhou 
851b733a9eSBinbin Zhou static const struct loongson_rtc_config ls1b_rtc_config = {
861b733a9eSBinbin Zhou 	.pm_offset = 0,
871b733a9eSBinbin Zhou 	.flags = 0,
881b733a9eSBinbin Zhou };
891b733a9eSBinbin Zhou 
901b733a9eSBinbin Zhou static const struct loongson_rtc_config ls1c_rtc_config = {
911b733a9eSBinbin Zhou 	.pm_offset = 0,
921b733a9eSBinbin Zhou 	.flags = LS1C_RTC_CTRL_WORKAROUND,
931b733a9eSBinbin Zhou };
941b733a9eSBinbin Zhou 
951b733a9eSBinbin Zhou static const struct loongson_rtc_config generic_rtc_config = {
961b733a9eSBinbin Zhou 	.pm_offset = 0x100,
971b733a9eSBinbin Zhou 	.flags = 0,
981b733a9eSBinbin Zhou };
991b733a9eSBinbin Zhou 
1001b733a9eSBinbin Zhou static const struct loongson_rtc_config ls2k1000_rtc_config = {
1011b733a9eSBinbin Zhou 	.pm_offset = 0x800,
1021b733a9eSBinbin Zhou 	.flags = 0,
1031b733a9eSBinbin Zhou };
1041b733a9eSBinbin Zhou 
1051b733a9eSBinbin Zhou static const struct regmap_config loongson_rtc_regmap_config = {
1061b733a9eSBinbin Zhou 	.reg_bits = 32,
1071b733a9eSBinbin Zhou 	.val_bits = 32,
1081b733a9eSBinbin Zhou 	.reg_stride = 4,
1091b733a9eSBinbin Zhou };
1101b733a9eSBinbin Zhou 
1111b733a9eSBinbin Zhou /* RTC alarm irq handler */
loongson_rtc_isr(int irq,void * id)1121b733a9eSBinbin Zhou static irqreturn_t loongson_rtc_isr(int irq, void *id)
1131b733a9eSBinbin Zhou {
1141b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = (struct loongson_rtc_priv *)id;
1151b733a9eSBinbin Zhou 
1161b733a9eSBinbin Zhou 	rtc_update_irq(priv->rtcdev, 1, RTC_AF | RTC_IRQF);
117*20f0f55eSMing Wang 
118*20f0f55eSMing Wang 	/*
119*20f0f55eSMing Wang 	 * The TOY_MATCH0_REG should be cleared 0 here,
120*20f0f55eSMing Wang 	 * otherwise the interrupt cannot be cleared.
121*20f0f55eSMing Wang 	 */
122*20f0f55eSMing Wang 	regmap_write(priv->regmap, TOY_MATCH0_REG, 0);
123*20f0f55eSMing Wang 
1241b733a9eSBinbin Zhou 	return IRQ_HANDLED;
1251b733a9eSBinbin Zhou }
1261b733a9eSBinbin Zhou 
1271b733a9eSBinbin Zhou /* For ACPI fixed event handler */
loongson_rtc_handler(void * id)1281b733a9eSBinbin Zhou static u32 loongson_rtc_handler(void *id)
1291b733a9eSBinbin Zhou {
1301b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = (struct loongson_rtc_priv *)id;
1311b733a9eSBinbin Zhou 
1321b733a9eSBinbin Zhou 	spin_lock(&priv->lock);
1331b733a9eSBinbin Zhou 	/* Disable RTC alarm wakeup and interrupt */
1341b733a9eSBinbin Zhou 	writel(readl(priv->pm_base + PM1_EN_REG) & ~RTC_EN,
1351b733a9eSBinbin Zhou 	       priv->pm_base + PM1_EN_REG);
1361b733a9eSBinbin Zhou 
1371b733a9eSBinbin Zhou 	/* Clear RTC interrupt status */
1381b733a9eSBinbin Zhou 	writel(RTC_STS, priv->pm_base + PM1_STS_REG);
1391b733a9eSBinbin Zhou 	spin_unlock(&priv->lock);
1401b733a9eSBinbin Zhou 
141*20f0f55eSMing Wang 	return ACPI_INTERRUPT_HANDLED;
1421b733a9eSBinbin Zhou }
1431b733a9eSBinbin Zhou 
loongson_rtc_set_enabled(struct device * dev)1441b733a9eSBinbin Zhou static int loongson_rtc_set_enabled(struct device *dev)
1451b733a9eSBinbin Zhou {
1461b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
1471b733a9eSBinbin Zhou 
1481b733a9eSBinbin Zhou 	if (priv->config->flags & LS1C_RTC_CTRL_WORKAROUND)
1491b733a9eSBinbin Zhou 		return 0;
1501b733a9eSBinbin Zhou 
1511b733a9eSBinbin Zhou 	/* Enable RTC TOY counters and crystal */
1521b733a9eSBinbin Zhou 	return regmap_update_bits(priv->regmap, RTC_CTRL_REG, TOY_ENABLE_MASK,
1531b733a9eSBinbin Zhou 				  TOY_ENABLE_MASK);
1541b733a9eSBinbin Zhou }
1551b733a9eSBinbin Zhou 
loongson_rtc_get_enabled(struct device * dev)1561b733a9eSBinbin Zhou static bool loongson_rtc_get_enabled(struct device *dev)
1571b733a9eSBinbin Zhou {
1581b733a9eSBinbin Zhou 	int ret;
1591b733a9eSBinbin Zhou 	u32 ctrl_data;
1601b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
1611b733a9eSBinbin Zhou 
1621b733a9eSBinbin Zhou 	if (priv->config->flags & LS1C_RTC_CTRL_WORKAROUND)
1631b733a9eSBinbin Zhou 		return true;
1641b733a9eSBinbin Zhou 
1651b733a9eSBinbin Zhou 	ret = regmap_read(priv->regmap, RTC_CTRL_REG, &ctrl_data);
1661b733a9eSBinbin Zhou 	if (ret < 0)
1671b733a9eSBinbin Zhou 		return false;
1681b733a9eSBinbin Zhou 
1691b733a9eSBinbin Zhou 	return ctrl_data & TOY_ENABLE_MASK;
1701b733a9eSBinbin Zhou }
1711b733a9eSBinbin Zhou 
loongson_rtc_read_time(struct device * dev,struct rtc_time * tm)1721b733a9eSBinbin Zhou static int loongson_rtc_read_time(struct device *dev, struct rtc_time *tm)
1731b733a9eSBinbin Zhou {
1741b733a9eSBinbin Zhou 	int ret;
1751b733a9eSBinbin Zhou 	u32 rtc_data[2];
1761b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
1771b733a9eSBinbin Zhou 
1781b733a9eSBinbin Zhou 	if (!loongson_rtc_get_enabled(dev))
1791b733a9eSBinbin Zhou 		return -EINVAL;
1801b733a9eSBinbin Zhou 
1811b733a9eSBinbin Zhou 	ret = regmap_bulk_read(priv->regmap, TOY_READ0_REG, rtc_data,
1821b733a9eSBinbin Zhou 			       ARRAY_SIZE(rtc_data));
1831b733a9eSBinbin Zhou 	if (ret < 0)
1841b733a9eSBinbin Zhou 		return ret;
1851b733a9eSBinbin Zhou 
1861b733a9eSBinbin Zhou 	tm->tm_sec = FIELD_GET(TOY_SEC, rtc_data[0]);
1871b733a9eSBinbin Zhou 	tm->tm_min = FIELD_GET(TOY_MIN, rtc_data[0]);
1881b733a9eSBinbin Zhou 	tm->tm_hour = FIELD_GET(TOY_HOUR, rtc_data[0]);
1891b733a9eSBinbin Zhou 	tm->tm_mday = FIELD_GET(TOY_DAY, rtc_data[0]);
1901b733a9eSBinbin Zhou 	tm->tm_mon = FIELD_GET(TOY_MON, rtc_data[0]) - 1;
1911b733a9eSBinbin Zhou 	tm->tm_year = rtc_data[1];
1921b733a9eSBinbin Zhou 
1931b733a9eSBinbin Zhou 	/* Prepare for RTC alarm year compensation value. */
1941b733a9eSBinbin Zhou 	priv->fix_year = tm->tm_year / 64 * 64;
1951b733a9eSBinbin Zhou 	return 0;
1961b733a9eSBinbin Zhou }
1971b733a9eSBinbin Zhou 
loongson_rtc_set_time(struct device * dev,struct rtc_time * tm)1981b733a9eSBinbin Zhou static int loongson_rtc_set_time(struct device *dev, struct rtc_time *tm)
1991b733a9eSBinbin Zhou {
2001b733a9eSBinbin Zhou 	int ret;
2011b733a9eSBinbin Zhou 	u32 rtc_data[2];
2021b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
2031b733a9eSBinbin Zhou 
2041b733a9eSBinbin Zhou 	rtc_data[0] = FIELD_PREP(TOY_SEC, tm->tm_sec)
2051b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_MIN, tm->tm_min)
2061b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_HOUR, tm->tm_hour)
2071b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_DAY, tm->tm_mday)
2081b733a9eSBinbin Zhou 		    | FIELD_PREP(TOY_MON, tm->tm_mon + 1);
2091b733a9eSBinbin Zhou 	rtc_data[1] = tm->tm_year;
2101b733a9eSBinbin Zhou 
2111b733a9eSBinbin Zhou 	ret = regmap_bulk_write(priv->regmap, TOY_WRITE0_REG, rtc_data,
2121b733a9eSBinbin Zhou 				ARRAY_SIZE(rtc_data));
2131b733a9eSBinbin Zhou 	if (ret < 0)
2141b733a9eSBinbin Zhou 		return ret;
2151b733a9eSBinbin Zhou 
2161b733a9eSBinbin Zhou 	return loongson_rtc_set_enabled(dev);
2171b733a9eSBinbin Zhou }
2181b733a9eSBinbin Zhou 
loongson_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alrm)2191b733a9eSBinbin Zhou static int loongson_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
2201b733a9eSBinbin Zhou {
2211b733a9eSBinbin Zhou 	int ret;
2221b733a9eSBinbin Zhou 	u32 alarm_data;
2231b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
2241b733a9eSBinbin Zhou 
2251b733a9eSBinbin Zhou 	ret = regmap_read(priv->regmap, TOY_MATCH0_REG, &alarm_data);
2261b733a9eSBinbin Zhou 	if (ret < 0)
2271b733a9eSBinbin Zhou 		return ret;
2281b733a9eSBinbin Zhou 
2291b733a9eSBinbin Zhou 	alrm->time.tm_sec = FIELD_GET(TOY_MATCH_SEC, alarm_data);
2301b733a9eSBinbin Zhou 	alrm->time.tm_min = FIELD_GET(TOY_MATCH_MIN, alarm_data);
2311b733a9eSBinbin Zhou 	alrm->time.tm_hour = FIELD_GET(TOY_MATCH_HOUR, alarm_data);
2321b733a9eSBinbin Zhou 	alrm->time.tm_mday = FIELD_GET(TOY_MATCH_DAY, alarm_data);
2331b733a9eSBinbin Zhou 	alrm->time.tm_mon = FIELD_GET(TOY_MATCH_MON, alarm_data) - 1;
2341b733a9eSBinbin Zhou 	/*
2351b733a9eSBinbin Zhou 	 * This is a hardware bug: the year field of SYS_TOYMATCH is only 6 bits,
2361b733a9eSBinbin Zhou 	 * making it impossible to save year values larger than 64.
2371b733a9eSBinbin Zhou 	 *
2381b733a9eSBinbin Zhou 	 * SYS_TOYMATCH is used to match the alarm time value and determine if
2391b733a9eSBinbin Zhou 	 * an alarm is triggered, so we must keep the lower 6 bits of the year
2401b733a9eSBinbin Zhou 	 * value constant during the value conversion.
2411b733a9eSBinbin Zhou 	 *
2421b733a9eSBinbin Zhou 	 * In summary, we need to manually add 64(or a multiple of 64) to the
2431b733a9eSBinbin Zhou 	 * year value to avoid the invalid alarm prompt at startup.
2441b733a9eSBinbin Zhou 	 */
2451b733a9eSBinbin Zhou 	alrm->time.tm_year = FIELD_GET(TOY_MATCH_YEAR, alarm_data) + priv->fix_year;
2461b733a9eSBinbin Zhou 
2471b733a9eSBinbin Zhou 	alrm->enabled = !!(readl(priv->pm_base + PM1_EN_REG) & RTC_EN);
2481b733a9eSBinbin Zhou 	return 0;
2491b733a9eSBinbin Zhou }
2501b733a9eSBinbin Zhou 
loongson_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)2511b733a9eSBinbin Zhou static int loongson_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
2521b733a9eSBinbin Zhou {
2531b733a9eSBinbin Zhou 	u32 val;
2541b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
2551b733a9eSBinbin Zhou 
2561b733a9eSBinbin Zhou 	spin_lock(&priv->lock);
2571b733a9eSBinbin Zhou 	val = readl(priv->pm_base + PM1_EN_REG);
2581b733a9eSBinbin Zhou 	/* Enable RTC alarm wakeup */
2591b733a9eSBinbin Zhou 	writel(enabled ? val | RTC_EN : val & ~RTC_EN,
2601b733a9eSBinbin Zhou 	       priv->pm_base + PM1_EN_REG);
2611b733a9eSBinbin Zhou 	spin_unlock(&priv->lock);
2621b733a9eSBinbin Zhou 
2631b733a9eSBinbin Zhou 	return 0;
2641b733a9eSBinbin Zhou }
2651b733a9eSBinbin Zhou 
loongson_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alrm)2661b733a9eSBinbin Zhou static int loongson_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
2671b733a9eSBinbin Zhou {
2681b733a9eSBinbin Zhou 	int ret;
2691b733a9eSBinbin Zhou 	u32 alarm_data;
2701b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
2711b733a9eSBinbin Zhou 
2721b733a9eSBinbin Zhou 	alarm_data = FIELD_PREP(TOY_MATCH_SEC, alrm->time.tm_sec)
2731b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_MIN, alrm->time.tm_min)
2741b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_HOUR, alrm->time.tm_hour)
2751b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_DAY, alrm->time.tm_mday)
2761b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_MON, alrm->time.tm_mon + 1)
2771b733a9eSBinbin Zhou 		   | FIELD_PREP(TOY_MATCH_YEAR, alrm->time.tm_year - priv->fix_year);
2781b733a9eSBinbin Zhou 
2791b733a9eSBinbin Zhou 	ret = regmap_write(priv->regmap, TOY_MATCH0_REG, alarm_data);
2801b733a9eSBinbin Zhou 	if (ret < 0)
2811b733a9eSBinbin Zhou 		return ret;
2821b733a9eSBinbin Zhou 
2831b733a9eSBinbin Zhou 	return loongson_rtc_alarm_irq_enable(dev, alrm->enabled);
2841b733a9eSBinbin Zhou }
2851b733a9eSBinbin Zhou 
2861b733a9eSBinbin Zhou static const struct rtc_class_ops loongson_rtc_ops = {
2871b733a9eSBinbin Zhou 	.read_time = loongson_rtc_read_time,
2881b733a9eSBinbin Zhou 	.set_time = loongson_rtc_set_time,
2891b733a9eSBinbin Zhou 	.read_alarm = loongson_rtc_read_alarm,
2901b733a9eSBinbin Zhou 	.set_alarm = loongson_rtc_set_alarm,
2911b733a9eSBinbin Zhou 	.alarm_irq_enable = loongson_rtc_alarm_irq_enable,
2921b733a9eSBinbin Zhou };
2931b733a9eSBinbin Zhou 
loongson_rtc_probe(struct platform_device * pdev)2941b733a9eSBinbin Zhou static int loongson_rtc_probe(struct platform_device *pdev)
2951b733a9eSBinbin Zhou {
2961b733a9eSBinbin Zhou 	int ret, alarm_irq;
2971b733a9eSBinbin Zhou 	void __iomem *regs;
2981b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv;
2991b733a9eSBinbin Zhou 	struct device *dev = &pdev->dev;
3001b733a9eSBinbin Zhou 
3011b733a9eSBinbin Zhou 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3021b733a9eSBinbin Zhou 	if (!priv)
3031b733a9eSBinbin Zhou 		return -ENOMEM;
3041b733a9eSBinbin Zhou 
3051b733a9eSBinbin Zhou 	regs = devm_platform_ioremap_resource(pdev, 0);
3061b733a9eSBinbin Zhou 	if (IS_ERR(regs))
3071b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(regs),
3081b733a9eSBinbin Zhou 				     "devm_platform_ioremap_resource failed\n");
3091b733a9eSBinbin Zhou 
3101b733a9eSBinbin Zhou 	priv->regmap = devm_regmap_init_mmio(dev, regs,
3111b733a9eSBinbin Zhou 					     &loongson_rtc_regmap_config);
3121b733a9eSBinbin Zhou 	if (IS_ERR(priv->regmap))
3131b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(priv->regmap),
3141b733a9eSBinbin Zhou 				     "devm_regmap_init_mmio failed\n");
3151b733a9eSBinbin Zhou 
3161b733a9eSBinbin Zhou 	priv->config = device_get_match_data(dev);
3171b733a9eSBinbin Zhou 	spin_lock_init(&priv->lock);
3181b733a9eSBinbin Zhou 	platform_set_drvdata(pdev, priv);
3191b733a9eSBinbin Zhou 
3201b733a9eSBinbin Zhou 	priv->rtcdev = devm_rtc_allocate_device(dev);
3211b733a9eSBinbin Zhou 	if (IS_ERR(priv->rtcdev))
3221b733a9eSBinbin Zhou 		return dev_err_probe(dev, PTR_ERR(priv->rtcdev),
3231b733a9eSBinbin Zhou 				     "devm_rtc_allocate_device failed\n");
3241b733a9eSBinbin Zhou 
3251b733a9eSBinbin Zhou 	/* Get RTC alarm irq */
3261b733a9eSBinbin Zhou 	alarm_irq = platform_get_irq(pdev, 0);
3271b733a9eSBinbin Zhou 	if (alarm_irq > 0) {
3281b733a9eSBinbin Zhou 		ret = devm_request_irq(dev, alarm_irq, loongson_rtc_isr,
3291b733a9eSBinbin Zhou 				       0, "loongson-alarm", priv);
3301b733a9eSBinbin Zhou 		if (ret < 0)
3311b733a9eSBinbin Zhou 			return dev_err_probe(dev, ret, "Unable to request irq %d\n",
3321b733a9eSBinbin Zhou 					     alarm_irq);
3331b733a9eSBinbin Zhou 
3341b733a9eSBinbin Zhou 		priv->pm_base = regs - priv->config->pm_offset;
3351b733a9eSBinbin Zhou 		device_init_wakeup(dev, 1);
3361b733a9eSBinbin Zhou 
3371b733a9eSBinbin Zhou 		if (has_acpi_companion(dev))
3381b733a9eSBinbin Zhou 			acpi_install_fixed_event_handler(ACPI_EVENT_RTC,
3391b733a9eSBinbin Zhou 							 loongson_rtc_handler, priv);
3401b733a9eSBinbin Zhou 	} else {
3411b733a9eSBinbin Zhou 		/* Loongson-1C RTC does not support alarm */
3421b733a9eSBinbin Zhou 		clear_bit(RTC_FEATURE_ALARM, priv->rtcdev->features);
3431b733a9eSBinbin Zhou 	}
3441b733a9eSBinbin Zhou 
3451b733a9eSBinbin Zhou 	/* Loongson RTC does not support UIE */
3461b733a9eSBinbin Zhou 	clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, priv->rtcdev->features);
3471b733a9eSBinbin Zhou 	priv->rtcdev->ops = &loongson_rtc_ops;
3481b733a9eSBinbin Zhou 	priv->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
3491b733a9eSBinbin Zhou 	priv->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
3501b733a9eSBinbin Zhou 
3511b733a9eSBinbin Zhou 	return devm_rtc_register_device(priv->rtcdev);
3521b733a9eSBinbin Zhou }
3531b733a9eSBinbin Zhou 
loongson_rtc_remove(struct platform_device * pdev)3541b733a9eSBinbin Zhou static void loongson_rtc_remove(struct platform_device *pdev)
3551b733a9eSBinbin Zhou {
3561b733a9eSBinbin Zhou 	struct device *dev = &pdev->dev;
3571b733a9eSBinbin Zhou 	struct loongson_rtc_priv *priv = dev_get_drvdata(dev);
3581b733a9eSBinbin Zhou 
3591b733a9eSBinbin Zhou 	if (!test_bit(RTC_FEATURE_ALARM, priv->rtcdev->features))
3601b733a9eSBinbin Zhou 		return;
3611b733a9eSBinbin Zhou 
3621b733a9eSBinbin Zhou 	if (has_acpi_companion(dev))
3631b733a9eSBinbin Zhou 		acpi_remove_fixed_event_handler(ACPI_EVENT_RTC,
3641b733a9eSBinbin Zhou 						loongson_rtc_handler);
3651b733a9eSBinbin Zhou 
3661b733a9eSBinbin Zhou 	device_init_wakeup(dev, 0);
3671b733a9eSBinbin Zhou 	loongson_rtc_alarm_irq_enable(dev, 0);
3681b733a9eSBinbin Zhou }
3691b733a9eSBinbin Zhou 
3701b733a9eSBinbin Zhou static const struct of_device_id loongson_rtc_of_match[] = {
3711b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls1b-rtc", .data = &ls1b_rtc_config },
3721b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls1c-rtc", .data = &ls1c_rtc_config },
3731b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls7a-rtc", .data = &generic_rtc_config },
3741b733a9eSBinbin Zhou 	{ .compatible = "loongson,ls2k1000-rtc", .data = &ls2k1000_rtc_config },
3751b733a9eSBinbin Zhou 	{ /* sentinel */ }
3761b733a9eSBinbin Zhou };
3771b733a9eSBinbin Zhou MODULE_DEVICE_TABLE(of, loongson_rtc_of_match);
3781b733a9eSBinbin Zhou 
3791b733a9eSBinbin Zhou static const struct acpi_device_id loongson_rtc_acpi_match[] = {
3801b733a9eSBinbin Zhou 	{ "LOON0001", .driver_data = (kernel_ulong_t)&generic_rtc_config },
3811b733a9eSBinbin Zhou 	{ }
3821b733a9eSBinbin Zhou };
3831b733a9eSBinbin Zhou MODULE_DEVICE_TABLE(acpi, loongson_rtc_acpi_match);
3841b733a9eSBinbin Zhou 
3851b733a9eSBinbin Zhou static struct platform_driver loongson_rtc_driver = {
3861b733a9eSBinbin Zhou 	.probe		= loongson_rtc_probe,
3871b733a9eSBinbin Zhou 	.remove_new	= loongson_rtc_remove,
3881b733a9eSBinbin Zhou 	.driver		= {
3891b733a9eSBinbin Zhou 		.name	= "loongson-rtc",
3901b733a9eSBinbin Zhou 		.of_match_table = loongson_rtc_of_match,
3911b733a9eSBinbin Zhou 		.acpi_match_table = loongson_rtc_acpi_match,
3921b733a9eSBinbin Zhou 	},
3931b733a9eSBinbin Zhou };
3941b733a9eSBinbin Zhou module_platform_driver(loongson_rtc_driver);
3951b733a9eSBinbin Zhou 
3961b733a9eSBinbin Zhou MODULE_DESCRIPTION("Loongson RTC driver");
3971b733a9eSBinbin Zhou MODULE_AUTHOR("Binbin Zhou <zhoubinbin@loongson.cn>");
3981b733a9eSBinbin Zhou MODULE_AUTHOR("WANG Xuerui <git@xen0n.name>");
3991b733a9eSBinbin Zhou MODULE_AUTHOR("Huacai Chen <chenhuacai@kernel.org>");
4001b733a9eSBinbin Zhou MODULE_LICENSE("GPL");
401