17b0b551dSBiwen Li // SPDX-License-Identifier: GPL-2.0+
27b0b551dSBiwen Li /*
37b0b551dSBiwen Li * Freescale FlexTimer Module (FTM) alarm device driver.
47b0b551dSBiwen Li *
57b0b551dSBiwen Li * Copyright 2014 Freescale Semiconductor, Inc.
60d982de3SPeng Ma * Copyright 2019-2020 NXP
77b0b551dSBiwen Li *
87b0b551dSBiwen Li */
97b0b551dSBiwen Li
107b0b551dSBiwen Li #include <linux/device.h>
117b0b551dSBiwen Li #include <linux/err.h>
127b0b551dSBiwen Li #include <linux/interrupt.h>
137b0b551dSBiwen Li #include <linux/io.h>
147b0b551dSBiwen Li #include <linux/platform_device.h>
15*48144c28SRob Herring #include <linux/mod_devicetable.h>
167b0b551dSBiwen Li #include <linux/module.h>
177b0b551dSBiwen Li #include <linux/fsl/ftm.h>
187b0b551dSBiwen Li #include <linux/rtc.h>
197b0b551dSBiwen Li #include <linux/time.h>
20929a3270SPeng Ma #include <linux/acpi.h>
213a8ce46cSRan Wang #include <linux/pm_wakeirq.h>
227b0b551dSBiwen Li
237b0b551dSBiwen Li #define FTM_SC_CLK(c) ((c) << FTM_SC_CLK_MASK_SHIFT)
247b0b551dSBiwen Li
257b0b551dSBiwen Li /*
267b0b551dSBiwen Li * Select Fixed frequency clock (32KHz) as clock source
277b0b551dSBiwen Li * of FlexTimer Module
287b0b551dSBiwen Li */
297b0b551dSBiwen Li #define FTM_SC_CLKS_FIXED_FREQ 0x02
307b0b551dSBiwen Li #define FIXED_FREQ_CLK 32000
317b0b551dSBiwen Li
327b0b551dSBiwen Li /* Select 128 (2^7) as divider factor */
337b0b551dSBiwen Li #define MAX_FREQ_DIV (1 << FTM_SC_PS_MASK)
347b0b551dSBiwen Li
357b0b551dSBiwen Li /* Maximum counter value in FlexTimer's CNT registers */
367b0b551dSBiwen Li #define MAX_COUNT_VAL 0xffff
377b0b551dSBiwen Li
387b0b551dSBiwen Li struct ftm_rtc {
397b0b551dSBiwen Li struct rtc_device *rtc_dev;
407b0b551dSBiwen Li void __iomem *base;
417b0b551dSBiwen Li bool big_endian;
427b0b551dSBiwen Li u32 alarm_freq;
437b0b551dSBiwen Li };
447b0b551dSBiwen Li
rtc_readl(struct ftm_rtc * dev,u32 reg)457b0b551dSBiwen Li static inline u32 rtc_readl(struct ftm_rtc *dev, u32 reg)
467b0b551dSBiwen Li {
477b0b551dSBiwen Li if (dev->big_endian)
487b0b551dSBiwen Li return ioread32be(dev->base + reg);
497b0b551dSBiwen Li else
507b0b551dSBiwen Li return ioread32(dev->base + reg);
517b0b551dSBiwen Li }
527b0b551dSBiwen Li
rtc_writel(struct ftm_rtc * dev,u32 reg,u32 val)537b0b551dSBiwen Li static inline void rtc_writel(struct ftm_rtc *dev, u32 reg, u32 val)
547b0b551dSBiwen Li {
557b0b551dSBiwen Li if (dev->big_endian)
567b0b551dSBiwen Li iowrite32be(val, dev->base + reg);
577b0b551dSBiwen Li else
587b0b551dSBiwen Li iowrite32(val, dev->base + reg);
597b0b551dSBiwen Li }
607b0b551dSBiwen Li
ftm_counter_enable(struct ftm_rtc * rtc)617b0b551dSBiwen Li static inline void ftm_counter_enable(struct ftm_rtc *rtc)
627b0b551dSBiwen Li {
637b0b551dSBiwen Li u32 val;
647b0b551dSBiwen Li
657b0b551dSBiwen Li /* select and enable counter clock source */
667b0b551dSBiwen Li val = rtc_readl(rtc, FTM_SC);
677b0b551dSBiwen Li val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
687b0b551dSBiwen Li val |= (FTM_SC_PS_MASK | FTM_SC_CLK(FTM_SC_CLKS_FIXED_FREQ));
697b0b551dSBiwen Li rtc_writel(rtc, FTM_SC, val);
707b0b551dSBiwen Li }
717b0b551dSBiwen Li
ftm_counter_disable(struct ftm_rtc * rtc)727b0b551dSBiwen Li static inline void ftm_counter_disable(struct ftm_rtc *rtc)
737b0b551dSBiwen Li {
747b0b551dSBiwen Li u32 val;
757b0b551dSBiwen Li
767b0b551dSBiwen Li /* disable counter clock source */
777b0b551dSBiwen Li val = rtc_readl(rtc, FTM_SC);
787b0b551dSBiwen Li val &= ~(FTM_SC_PS_MASK | FTM_SC_CLK_MASK);
797b0b551dSBiwen Li rtc_writel(rtc, FTM_SC, val);
807b0b551dSBiwen Li }
817b0b551dSBiwen Li
ftm_irq_acknowledge(struct ftm_rtc * rtc)827b0b551dSBiwen Li static inline void ftm_irq_acknowledge(struct ftm_rtc *rtc)
837b0b551dSBiwen Li {
847b0b551dSBiwen Li unsigned int timeout = 100;
857b0b551dSBiwen Li
867b0b551dSBiwen Li /*
877b0b551dSBiwen Li *Fix errata A-007728 for flextimer
887b0b551dSBiwen Li * If the FTM counter reaches the FTM_MOD value between
897b0b551dSBiwen Li * the reading of the TOF bit and the writing of 0 to
907b0b551dSBiwen Li * the TOF bit, the process of clearing the TOF bit
917b0b551dSBiwen Li * does not work as expected when FTMx_CONF[NUMTOF] != 0
927b0b551dSBiwen Li * and the current TOF count is less than FTMx_CONF[NUMTOF].
937b0b551dSBiwen Li * If the above condition is met, the TOF bit remains set.
947b0b551dSBiwen Li * If the TOF interrupt is enabled (FTMx_SC[TOIE] = 1),the
957b0b551dSBiwen Li * TOF interrupt also remains asserted.
967b0b551dSBiwen Li *
977b0b551dSBiwen Li * Above is the errata discription
987b0b551dSBiwen Li *
997b0b551dSBiwen Li * In one word: software clearing TOF bit not works when
1007b0b551dSBiwen Li * FTMx_CONF[NUMTOF] was seted as nonzero and FTM counter
1017b0b551dSBiwen Li * reaches the FTM_MOD value.
1027b0b551dSBiwen Li *
1037b0b551dSBiwen Li * The workaround is clearing TOF bit until it works
1047b0b551dSBiwen Li * (FTM counter doesn't always reache the FTM_MOD anyway),
1057b0b551dSBiwen Li * which may cost some cycles.
1067b0b551dSBiwen Li */
1077b0b551dSBiwen Li while ((FTM_SC_TOF & rtc_readl(rtc, FTM_SC)) && timeout--)
1087b0b551dSBiwen Li rtc_writel(rtc, FTM_SC, rtc_readl(rtc, FTM_SC) & (~FTM_SC_TOF));
1097b0b551dSBiwen Li }
1107b0b551dSBiwen Li
ftm_irq_enable(struct ftm_rtc * rtc)1117b0b551dSBiwen Li static inline void ftm_irq_enable(struct ftm_rtc *rtc)
1127b0b551dSBiwen Li {
1137b0b551dSBiwen Li u32 val;
1147b0b551dSBiwen Li
1157b0b551dSBiwen Li val = rtc_readl(rtc, FTM_SC);
1167b0b551dSBiwen Li val |= FTM_SC_TOIE;
1177b0b551dSBiwen Li rtc_writel(rtc, FTM_SC, val);
1187b0b551dSBiwen Li }
1197b0b551dSBiwen Li
ftm_irq_disable(struct ftm_rtc * rtc)1207b0b551dSBiwen Li static inline void ftm_irq_disable(struct ftm_rtc *rtc)
1217b0b551dSBiwen Li {
1227b0b551dSBiwen Li u32 val;
1237b0b551dSBiwen Li
1247b0b551dSBiwen Li val = rtc_readl(rtc, FTM_SC);
1257b0b551dSBiwen Li val &= ~FTM_SC_TOIE;
1267b0b551dSBiwen Li rtc_writel(rtc, FTM_SC, val);
1277b0b551dSBiwen Li }
1287b0b551dSBiwen Li
ftm_reset_counter(struct ftm_rtc * rtc)1297b0b551dSBiwen Li static inline void ftm_reset_counter(struct ftm_rtc *rtc)
1307b0b551dSBiwen Li {
1317b0b551dSBiwen Li /*
1327b0b551dSBiwen Li * The CNT register contains the FTM counter value.
1337b0b551dSBiwen Li * Reset clears the CNT register. Writing any value to COUNT
1347b0b551dSBiwen Li * updates the counter with its initial value, CNTIN.
1357b0b551dSBiwen Li */
1367b0b551dSBiwen Li rtc_writel(rtc, FTM_CNT, 0x00);
1377b0b551dSBiwen Li }
1387b0b551dSBiwen Li
ftm_clean_alarm(struct ftm_rtc * rtc)1397b0b551dSBiwen Li static void ftm_clean_alarm(struct ftm_rtc *rtc)
1407b0b551dSBiwen Li {
1417b0b551dSBiwen Li ftm_counter_disable(rtc);
1427b0b551dSBiwen Li
1437b0b551dSBiwen Li rtc_writel(rtc, FTM_CNTIN, 0x00);
1447b0b551dSBiwen Li rtc_writel(rtc, FTM_MOD, ~0U);
1457b0b551dSBiwen Li
1467b0b551dSBiwen Li ftm_reset_counter(rtc);
1477b0b551dSBiwen Li }
1487b0b551dSBiwen Li
ftm_rtc_alarm_interrupt(int irq,void * dev)1497b0b551dSBiwen Li static irqreturn_t ftm_rtc_alarm_interrupt(int irq, void *dev)
1507b0b551dSBiwen Li {
1517b0b551dSBiwen Li struct ftm_rtc *rtc = dev;
1527b0b551dSBiwen Li
1539c328c9dSBiwen Li rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
1549c328c9dSBiwen Li
1557b0b551dSBiwen Li ftm_irq_acknowledge(rtc);
1567b0b551dSBiwen Li ftm_irq_disable(rtc);
1577b0b551dSBiwen Li ftm_clean_alarm(rtc);
1587b0b551dSBiwen Li
1597b0b551dSBiwen Li return IRQ_HANDLED;
1607b0b551dSBiwen Li }
1617b0b551dSBiwen Li
ftm_rtc_alarm_irq_enable(struct device * dev,unsigned int enabled)1627b0b551dSBiwen Li static int ftm_rtc_alarm_irq_enable(struct device *dev,
1637b0b551dSBiwen Li unsigned int enabled)
1647b0b551dSBiwen Li {
1657b0b551dSBiwen Li struct ftm_rtc *rtc = dev_get_drvdata(dev);
1667b0b551dSBiwen Li
1677b0b551dSBiwen Li if (enabled)
1687b0b551dSBiwen Li ftm_irq_enable(rtc);
1697b0b551dSBiwen Li else
1707b0b551dSBiwen Li ftm_irq_disable(rtc);
1717b0b551dSBiwen Li
1727b0b551dSBiwen Li return 0;
1737b0b551dSBiwen Li }
1747b0b551dSBiwen Li
1757b0b551dSBiwen Li /*
1767b0b551dSBiwen Li * Note:
1777b0b551dSBiwen Li * The function is not really getting time from the RTC
1787b0b551dSBiwen Li * since FlexTimer is not a RTC device, but we need to
1797b0b551dSBiwen Li * get time to setup alarm, so we are using system time
1807b0b551dSBiwen Li * for now.
1817b0b551dSBiwen Li */
ftm_rtc_read_time(struct device * dev,struct rtc_time * tm)1827b0b551dSBiwen Li static int ftm_rtc_read_time(struct device *dev, struct rtc_time *tm)
1837b0b551dSBiwen Li {
1849323e963SAlexandre Belloni rtc_time64_to_tm(ktime_get_real_seconds(), tm);
1857b0b551dSBiwen Li
1867b0b551dSBiwen Li return 0;
1877b0b551dSBiwen Li }
1887b0b551dSBiwen Li
ftm_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)1897b0b551dSBiwen Li static int ftm_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
1907b0b551dSBiwen Li {
1917b0b551dSBiwen Li return 0;
1927b0b551dSBiwen Li }
1937b0b551dSBiwen Li
1947b0b551dSBiwen Li /*
1957b0b551dSBiwen Li * 1. Select fixed frequency clock (32KHz) as clock source;
1967b0b551dSBiwen Li * 2. Select 128 (2^7) as divider factor;
1977b0b551dSBiwen Li * So clock is 250 Hz (32KHz/128).
1987b0b551dSBiwen Li *
1997b0b551dSBiwen Li * 3. FlexTimer's CNT register is a 32bit register,
2007b0b551dSBiwen Li * but the register's 16 bit as counter value,it's other 16 bit
2017b0b551dSBiwen Li * is reserved.So minimum counter value is 0x0,maximum counter
2027b0b551dSBiwen Li * value is 0xffff.
2037b0b551dSBiwen Li * So max alarm value is 262 (65536 / 250) seconds
2047b0b551dSBiwen Li */
ftm_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)2057b0b551dSBiwen Li static int ftm_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
2067b0b551dSBiwen Li {
207bb451661SAlexandre Belloni time64_t alm_time;
2089323e963SAlexandre Belloni unsigned long long cycle;
2097b0b551dSBiwen Li struct ftm_rtc *rtc = dev_get_drvdata(dev);
2107b0b551dSBiwen Li
2119323e963SAlexandre Belloni alm_time = rtc_tm_to_time64(&alm->time);
2127b0b551dSBiwen Li
2137b0b551dSBiwen Li ftm_clean_alarm(rtc);
214bb451661SAlexandre Belloni cycle = (alm_time - ktime_get_real_seconds()) * rtc->alarm_freq;
2157b0b551dSBiwen Li if (cycle > MAX_COUNT_VAL) {
2167b0b551dSBiwen Li pr_err("Out of alarm range {0~262} seconds.\n");
2177b0b551dSBiwen Li return -ERANGE;
2187b0b551dSBiwen Li }
2197b0b551dSBiwen Li
2207b0b551dSBiwen Li ftm_irq_disable(rtc);
2217b0b551dSBiwen Li
2227b0b551dSBiwen Li /*
2237b0b551dSBiwen Li * The counter increments until the value of MOD is reached,
2247b0b551dSBiwen Li * at which point the counter is reloaded with the value of CNTIN.
2257b0b551dSBiwen Li * The TOF (the overflow flag) bit is set when the FTM counter
2267b0b551dSBiwen Li * changes from MOD to CNTIN. So we should using the cycle - 1.
2277b0b551dSBiwen Li */
2287b0b551dSBiwen Li rtc_writel(rtc, FTM_MOD, cycle - 1);
2297b0b551dSBiwen Li
2307b0b551dSBiwen Li ftm_counter_enable(rtc);
2317b0b551dSBiwen Li ftm_irq_enable(rtc);
2327b0b551dSBiwen Li
2337b0b551dSBiwen Li return 0;
2347b0b551dSBiwen Li
2357b0b551dSBiwen Li }
2367b0b551dSBiwen Li
2377b0b551dSBiwen Li static const struct rtc_class_ops ftm_rtc_ops = {
2387b0b551dSBiwen Li .read_time = ftm_rtc_read_time,
2397b0b551dSBiwen Li .read_alarm = ftm_rtc_read_alarm,
2407b0b551dSBiwen Li .set_alarm = ftm_rtc_set_alarm,
2417b0b551dSBiwen Li .alarm_irq_enable = ftm_rtc_alarm_irq_enable,
2427b0b551dSBiwen Li };
2437b0b551dSBiwen Li
ftm_rtc_probe(struct platform_device * pdev)2447b0b551dSBiwen Li static int ftm_rtc_probe(struct platform_device *pdev)
2457b0b551dSBiwen Li {
2467b0b551dSBiwen Li int irq;
2477b0b551dSBiwen Li int ret;
2487b0b551dSBiwen Li struct ftm_rtc *rtc;
2497b0b551dSBiwen Li
2507b0b551dSBiwen Li rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
2517b0b551dSBiwen Li if (unlikely(!rtc)) {
2527b0b551dSBiwen Li dev_err(&pdev->dev, "cannot alloc memory for rtc\n");
2537b0b551dSBiwen Li return -ENOMEM;
2547b0b551dSBiwen Li }
2557b0b551dSBiwen Li
2567b0b551dSBiwen Li platform_set_drvdata(pdev, rtc);
2577b0b551dSBiwen Li
2587b0b551dSBiwen Li rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev);
2597b0b551dSBiwen Li if (IS_ERR(rtc->rtc_dev))
2607b0b551dSBiwen Li return PTR_ERR(rtc->rtc_dev);
2617b0b551dSBiwen Li
26289576bebSMarkus Elfring rtc->base = devm_platform_ioremap_resource(pdev, 0);
2637b0b551dSBiwen Li if (IS_ERR(rtc->base)) {
2647b0b551dSBiwen Li dev_err(&pdev->dev, "cannot ioremap resource for rtc\n");
2657b0b551dSBiwen Li return PTR_ERR(rtc->base);
2667b0b551dSBiwen Li }
2677b0b551dSBiwen Li
268929a3270SPeng Ma irq = platform_get_irq(pdev, 0);
269944ed452SMarkus Elfring if (irq < 0)
270929a3270SPeng Ma return irq;
2717b0b551dSBiwen Li
2727b0b551dSBiwen Li ret = devm_request_irq(&pdev->dev, irq, ftm_rtc_alarm_interrupt,
2733a8ce46cSRan Wang 0, dev_name(&pdev->dev), rtc);
2747b0b551dSBiwen Li if (ret < 0) {
2757b0b551dSBiwen Li dev_err(&pdev->dev, "failed to request irq\n");
2767b0b551dSBiwen Li return ret;
2777b0b551dSBiwen Li }
2787b0b551dSBiwen Li
279929a3270SPeng Ma rtc->big_endian =
280929a3270SPeng Ma device_property_read_bool(&pdev->dev, "big-endian");
281929a3270SPeng Ma
2827b0b551dSBiwen Li rtc->alarm_freq = (u32)FIXED_FREQ_CLK / (u32)MAX_FREQ_DIV;
2837b0b551dSBiwen Li rtc->rtc_dev->ops = &ftm_rtc_ops;
2847b0b551dSBiwen Li
2857b0b551dSBiwen Li device_init_wakeup(&pdev->dev, true);
2863a8ce46cSRan Wang ret = dev_pm_set_wake_irq(&pdev->dev, irq);
2873a8ce46cSRan Wang if (ret)
2883a8ce46cSRan Wang dev_err(&pdev->dev, "failed to enable irq wake\n");
2897b0b551dSBiwen Li
290fdcfd854SBartosz Golaszewski ret = devm_rtc_register_device(rtc->rtc_dev);
2917b0b551dSBiwen Li if (ret) {
2927b0b551dSBiwen Li dev_err(&pdev->dev, "can't register rtc device\n");
2937b0b551dSBiwen Li return ret;
2947b0b551dSBiwen Li }
2957b0b551dSBiwen Li
2967b0b551dSBiwen Li return 0;
2977b0b551dSBiwen Li }
2987b0b551dSBiwen Li
2997b0b551dSBiwen Li static const struct of_device_id ftm_rtc_match[] = {
3007b0b551dSBiwen Li { .compatible = "fsl,ls1012a-ftm-alarm", },
3017b0b551dSBiwen Li { .compatible = "fsl,ls1021a-ftm-alarm", },
3027b0b551dSBiwen Li { .compatible = "fsl,ls1028a-ftm-alarm", },
3037b0b551dSBiwen Li { .compatible = "fsl,ls1043a-ftm-alarm", },
3047b0b551dSBiwen Li { .compatible = "fsl,ls1046a-ftm-alarm", },
3057b0b551dSBiwen Li { .compatible = "fsl,ls1088a-ftm-alarm", },
3067b0b551dSBiwen Li { .compatible = "fsl,ls208xa-ftm-alarm", },
3077b0b551dSBiwen Li { .compatible = "fsl,lx2160a-ftm-alarm", },
3087b0b551dSBiwen Li { },
3097b0b551dSBiwen Li };
3107fcb8618SMichael Walle MODULE_DEVICE_TABLE(of, ftm_rtc_match);
3117b0b551dSBiwen Li
312929a3270SPeng Ma static const struct acpi_device_id ftm_imx_acpi_ids[] = {
3130d982de3SPeng Ma {"NXP0014",},
314929a3270SPeng Ma { }
315929a3270SPeng Ma };
316929a3270SPeng Ma MODULE_DEVICE_TABLE(acpi, ftm_imx_acpi_ids);
317929a3270SPeng Ma
3187b0b551dSBiwen Li static struct platform_driver ftm_rtc_driver = {
3197b0b551dSBiwen Li .probe = ftm_rtc_probe,
3207b0b551dSBiwen Li .driver = {
3217b0b551dSBiwen Li .name = "ftm-alarm",
3227b0b551dSBiwen Li .of_match_table = ftm_rtc_match,
323929a3270SPeng Ma .acpi_match_table = ACPI_PTR(ftm_imx_acpi_ids),
3247b0b551dSBiwen Li },
3257b0b551dSBiwen Li };
3267b0b551dSBiwen Li
3271ff56edfSZhang Jianhua module_platform_driver(ftm_rtc_driver);
3287b0b551dSBiwen Li
3297b0b551dSBiwen Li MODULE_DESCRIPTION("NXP/Freescale FlexTimer alarm driver");
3307b0b551dSBiwen Li MODULE_AUTHOR("Biwen Li <biwen.li@nxp.com>");
3317b0b551dSBiwen Li MODULE_LICENSE("GPL");
332