114556f04SAlexandre Belloni // SPDX-License-Identifier: GPL-2.0
214556f04SAlexandre Belloni // Copyright (C) 2012 Sven Schnelle <svens@stackframe.org>
37418a119SSven Schnelle
47418a119SSven Schnelle #include <linux/platform_device.h>
57418a119SSven Schnelle #include <linux/module.h>
67418a119SSven Schnelle #include <linux/init.h>
77418a119SSven Schnelle #include <linux/rtc.h>
87418a119SSven Schnelle #include <linux/types.h>
97418a119SSven Schnelle #include <linux/bcd.h>
107418a119SSven Schnelle #include <linux/delay.h>
11*d890cfc2SLinus Walleij #include <linux/gpio/consumer.h>
127418a119SSven Schnelle #include <linux/slab.h>
137418a119SSven Schnelle
147418a119SSven Schnelle #include <linux/io.h>
157418a119SSven Schnelle
167418a119SSven Schnelle #define DS2404_STATUS_REG 0x200
177418a119SSven Schnelle #define DS2404_CONTROL_REG 0x201
187418a119SSven Schnelle #define DS2404_RTC_REG 0x202
197418a119SSven Schnelle
207418a119SSven Schnelle #define DS2404_WRITE_SCRATCHPAD_CMD 0x0f
217418a119SSven Schnelle #define DS2404_READ_SCRATCHPAD_CMD 0xaa
227418a119SSven Schnelle #define DS2404_COPY_SCRATCHPAD_CMD 0x55
237418a119SSven Schnelle #define DS2404_READ_MEMORY_CMD 0xf0
247418a119SSven Schnelle
257418a119SSven Schnelle #define DS2404_RST 0
267418a119SSven Schnelle #define DS2404_CLK 1
277418a119SSven Schnelle #define DS2404_DQ 2
287418a119SSven Schnelle
297418a119SSven Schnelle struct ds2404 {
30*d890cfc2SLinus Walleij struct device *dev;
31*d890cfc2SLinus Walleij struct gpio_desc *rst_gpiod;
32*d890cfc2SLinus Walleij struct gpio_desc *clk_gpiod;
33*d890cfc2SLinus Walleij struct gpio_desc *dq_gpiod;
347418a119SSven Schnelle struct rtc_device *rtc;
357418a119SSven Schnelle };
367418a119SSven Schnelle
ds2404_gpio_map(struct ds2404 * chip,struct platform_device * pdev)37*d890cfc2SLinus Walleij static int ds2404_gpio_map(struct ds2404 *chip, struct platform_device *pdev)
387418a119SSven Schnelle {
39*d890cfc2SLinus Walleij struct device *dev = &pdev->dev;
407418a119SSven Schnelle
41*d890cfc2SLinus Walleij /* This will de-assert RESET, declare this GPIO as GPIOD_ACTIVE_LOW */
42*d890cfc2SLinus Walleij chip->rst_gpiod = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
43*d890cfc2SLinus Walleij if (IS_ERR(chip->rst_gpiod))
44*d890cfc2SLinus Walleij return PTR_ERR(chip->rst_gpiod);
457418a119SSven Schnelle
46*d890cfc2SLinus Walleij chip->clk_gpiod = devm_gpiod_get(dev, "clk", GPIOD_OUT_HIGH);
47*d890cfc2SLinus Walleij if (IS_ERR(chip->clk_gpiod))
48*d890cfc2SLinus Walleij return PTR_ERR(chip->clk_gpiod);
497418a119SSven Schnelle
50*d890cfc2SLinus Walleij chip->dq_gpiod = devm_gpiod_get(dev, "dq", GPIOD_ASIS);
51*d890cfc2SLinus Walleij if (IS_ERR(chip->dq_gpiod))
52*d890cfc2SLinus Walleij return PTR_ERR(chip->dq_gpiod);
53*d890cfc2SLinus Walleij
547418a119SSven Schnelle return 0;
557418a119SSven Schnelle }
567418a119SSven Schnelle
ds2404_reset(struct ds2404 * chip)57*d890cfc2SLinus Walleij static void ds2404_reset(struct ds2404 *chip)
587418a119SSven Schnelle {
59*d890cfc2SLinus Walleij gpiod_set_value(chip->rst_gpiod, 1);
607418a119SSven Schnelle udelay(1000);
61*d890cfc2SLinus Walleij gpiod_set_value(chip->rst_gpiod, 0);
62*d890cfc2SLinus Walleij gpiod_set_value(chip->clk_gpiod, 0);
63*d890cfc2SLinus Walleij gpiod_direction_output(chip->dq_gpiod, 0);
647418a119SSven Schnelle udelay(10);
657418a119SSven Schnelle }
667418a119SSven Schnelle
ds2404_write_byte(struct ds2404 * chip,u8 byte)67*d890cfc2SLinus Walleij static void ds2404_write_byte(struct ds2404 *chip, u8 byte)
687418a119SSven Schnelle {
697418a119SSven Schnelle int i;
707418a119SSven Schnelle
71*d890cfc2SLinus Walleij gpiod_direction_output(chip->dq_gpiod, 1);
727418a119SSven Schnelle for (i = 0; i < 8; i++) {
73*d890cfc2SLinus Walleij gpiod_set_value(chip->dq_gpiod, byte & (1 << i));
747418a119SSven Schnelle udelay(10);
75*d890cfc2SLinus Walleij gpiod_set_value(chip->clk_gpiod, 1);
767418a119SSven Schnelle udelay(10);
77*d890cfc2SLinus Walleij gpiod_set_value(chip->clk_gpiod, 0);
787418a119SSven Schnelle udelay(10);
797418a119SSven Schnelle }
807418a119SSven Schnelle }
817418a119SSven Schnelle
ds2404_read_byte(struct ds2404 * chip)82*d890cfc2SLinus Walleij static u8 ds2404_read_byte(struct ds2404 *chip)
837418a119SSven Schnelle {
847418a119SSven Schnelle int i;
857418a119SSven Schnelle u8 ret = 0;
867418a119SSven Schnelle
87*d890cfc2SLinus Walleij gpiod_direction_input(chip->dq_gpiod);
887418a119SSven Schnelle
897418a119SSven Schnelle for (i = 0; i < 8; i++) {
90*d890cfc2SLinus Walleij gpiod_set_value(chip->clk_gpiod, 0);
917418a119SSven Schnelle udelay(10);
92*d890cfc2SLinus Walleij if (gpiod_get_value(chip->dq_gpiod))
937418a119SSven Schnelle ret |= 1 << i;
94*d890cfc2SLinus Walleij gpiod_set_value(chip->clk_gpiod, 1);
957418a119SSven Schnelle udelay(10);
967418a119SSven Schnelle }
977418a119SSven Schnelle return ret;
987418a119SSven Schnelle }
997418a119SSven Schnelle
ds2404_read_memory(struct ds2404 * chip,u16 offset,int length,u8 * out)100*d890cfc2SLinus Walleij static void ds2404_read_memory(struct ds2404 *chip, u16 offset,
1017418a119SSven Schnelle int length, u8 *out)
1027418a119SSven Schnelle {
103*d890cfc2SLinus Walleij ds2404_reset(chip);
104*d890cfc2SLinus Walleij ds2404_write_byte(chip, DS2404_READ_MEMORY_CMD);
105*d890cfc2SLinus Walleij ds2404_write_byte(chip, offset & 0xff);
106*d890cfc2SLinus Walleij ds2404_write_byte(chip, (offset >> 8) & 0xff);
1077418a119SSven Schnelle while (length--)
108*d890cfc2SLinus Walleij *out++ = ds2404_read_byte(chip);
1097418a119SSven Schnelle }
1107418a119SSven Schnelle
ds2404_write_memory(struct ds2404 * chip,u16 offset,int length,u8 * out)111*d890cfc2SLinus Walleij static void ds2404_write_memory(struct ds2404 *chip, u16 offset,
1127418a119SSven Schnelle int length, u8 *out)
1137418a119SSven Schnelle {
1147418a119SSven Schnelle int i;
1157418a119SSven Schnelle u8 ta01, ta02, es;
1167418a119SSven Schnelle
117*d890cfc2SLinus Walleij ds2404_reset(chip);
118*d890cfc2SLinus Walleij ds2404_write_byte(chip, DS2404_WRITE_SCRATCHPAD_CMD);
119*d890cfc2SLinus Walleij ds2404_write_byte(chip, offset & 0xff);
120*d890cfc2SLinus Walleij ds2404_write_byte(chip, (offset >> 8) & 0xff);
1217418a119SSven Schnelle
1227418a119SSven Schnelle for (i = 0; i < length; i++)
123*d890cfc2SLinus Walleij ds2404_write_byte(chip, out[i]);
1247418a119SSven Schnelle
125*d890cfc2SLinus Walleij ds2404_reset(chip);
126*d890cfc2SLinus Walleij ds2404_write_byte(chip, DS2404_READ_SCRATCHPAD_CMD);
1277418a119SSven Schnelle
128*d890cfc2SLinus Walleij ta01 = ds2404_read_byte(chip);
129*d890cfc2SLinus Walleij ta02 = ds2404_read_byte(chip);
130*d890cfc2SLinus Walleij es = ds2404_read_byte(chip);
1317418a119SSven Schnelle
1327418a119SSven Schnelle for (i = 0; i < length; i++) {
133*d890cfc2SLinus Walleij if (out[i] != ds2404_read_byte(chip)) {
134*d890cfc2SLinus Walleij dev_err(chip->dev, "read invalid data\n");
1357418a119SSven Schnelle return;
1367418a119SSven Schnelle }
1377418a119SSven Schnelle }
1387418a119SSven Schnelle
139*d890cfc2SLinus Walleij ds2404_reset(chip);
140*d890cfc2SLinus Walleij ds2404_write_byte(chip, DS2404_COPY_SCRATCHPAD_CMD);
141*d890cfc2SLinus Walleij ds2404_write_byte(chip, ta01);
142*d890cfc2SLinus Walleij ds2404_write_byte(chip, ta02);
143*d890cfc2SLinus Walleij ds2404_write_byte(chip, es);
1447418a119SSven Schnelle
145*d890cfc2SLinus Walleij while (gpiod_get_value(chip->dq_gpiod))
1467418a119SSven Schnelle ;
1477418a119SSven Schnelle }
1487418a119SSven Schnelle
ds2404_enable_osc(struct ds2404 * chip)149*d890cfc2SLinus Walleij static void ds2404_enable_osc(struct ds2404 *chip)
1507418a119SSven Schnelle {
1517418a119SSven Schnelle u8 in[1] = { 0x10 }; /* enable oscillator */
152*d890cfc2SLinus Walleij
153*d890cfc2SLinus Walleij ds2404_write_memory(chip, 0x201, 1, in);
1547418a119SSven Schnelle }
1557418a119SSven Schnelle
ds2404_read_time(struct device * dev,struct rtc_time * dt)1567418a119SSven Schnelle static int ds2404_read_time(struct device *dev, struct rtc_time *dt)
1577418a119SSven Schnelle {
158*d890cfc2SLinus Walleij struct ds2404 *chip = dev_get_drvdata(dev);
1597418a119SSven Schnelle unsigned long time = 0;
1608aec4b87SNicholas Mc Guire __le32 hw_time = 0;
1617418a119SSven Schnelle
162*d890cfc2SLinus Walleij ds2404_read_memory(chip, 0x203, 4, (u8 *)&hw_time);
1638aec4b87SNicholas Mc Guire time = le32_to_cpu(hw_time);
1647418a119SSven Schnelle
16553523216SAlexandre Belloni rtc_time64_to_tm(time, dt);
16622652ba7SAlexandre Belloni return 0;
1677418a119SSven Schnelle }
1687418a119SSven Schnelle
ds2404_set_time(struct device * dev,struct rtc_time * dt)169be2b0437SAlexandre Belloni static int ds2404_set_time(struct device *dev, struct rtc_time *dt)
1707418a119SSven Schnelle {
171*d890cfc2SLinus Walleij struct ds2404 *chip = dev_get_drvdata(dev);
172be2b0437SAlexandre Belloni u32 time = cpu_to_le32(rtc_tm_to_time64(dt));
173*d890cfc2SLinus Walleij ds2404_write_memory(chip, 0x203, 4, (u8 *)&time);
1747418a119SSven Schnelle return 0;
1757418a119SSven Schnelle }
1767418a119SSven Schnelle
1777418a119SSven Schnelle static const struct rtc_class_ops ds2404_rtc_ops = {
1787418a119SSven Schnelle .read_time = ds2404_read_time,
179be2b0437SAlexandre Belloni .set_time = ds2404_set_time,
1807418a119SSven Schnelle };
1817418a119SSven Schnelle
rtc_probe(struct platform_device * pdev)1827418a119SSven Schnelle static int rtc_probe(struct platform_device *pdev)
1837418a119SSven Schnelle {
1847418a119SSven Schnelle struct ds2404 *chip;
1857418a119SSven Schnelle int retval = -EBUSY;
1867418a119SSven Schnelle
1872a444cf7SJingoo Han chip = devm_kzalloc(&pdev->dev, sizeof(struct ds2404), GFP_KERNEL);
1887418a119SSven Schnelle if (!chip)
1897418a119SSven Schnelle return -ENOMEM;
1907418a119SSven Schnelle
191*d890cfc2SLinus Walleij chip->dev = &pdev->dev;
192*d890cfc2SLinus Walleij
19313bfa942SAlexandre Belloni chip->rtc = devm_rtc_allocate_device(&pdev->dev);
19413bfa942SAlexandre Belloni if (IS_ERR(chip->rtc))
19513bfa942SAlexandre Belloni return PTR_ERR(chip->rtc);
19613bfa942SAlexandre Belloni
197*d890cfc2SLinus Walleij retval = ds2404_gpio_map(chip, pdev);
1987418a119SSven Schnelle if (retval)
199d9aa5ca4SAlexandre Belloni return retval;
200d9aa5ca4SAlexandre Belloni
2017418a119SSven Schnelle platform_set_drvdata(pdev, chip);
2027418a119SSven Schnelle
20313bfa942SAlexandre Belloni chip->rtc->ops = &ds2404_rtc_ops;
20413bfa942SAlexandre Belloni chip->rtc->range_max = U32_MAX;
20513bfa942SAlexandre Belloni
206fdcfd854SBartosz Golaszewski retval = devm_rtc_register_device(chip->rtc);
20713bfa942SAlexandre Belloni if (retval)
208d9aa5ca4SAlexandre Belloni return retval;
2097418a119SSven Schnelle
210*d890cfc2SLinus Walleij ds2404_enable_osc(chip);
2117418a119SSven Schnelle return 0;
2127418a119SSven Schnelle }
2137418a119SSven Schnelle
2147418a119SSven Schnelle static struct platform_driver rtc_device_driver = {
2157418a119SSven Schnelle .probe = rtc_probe,
2167418a119SSven Schnelle .driver = {
2177418a119SSven Schnelle .name = "ds2404",
2187418a119SSven Schnelle },
2197418a119SSven Schnelle };
22056ae1b8eSSrinivas Kandagatla module_platform_driver(rtc_device_driver);
2217418a119SSven Schnelle
2227418a119SSven Schnelle MODULE_DESCRIPTION("DS2404 RTC");
2237418a119SSven Schnelle MODULE_AUTHOR("Sven Schnelle");
2247418a119SSven Schnelle MODULE_LICENSE("GPL");
2257418a119SSven Schnelle MODULE_ALIAS("platform:ds2404");
226