1*2874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2e5d76075SStephen Gallimore /* 3e5d76075SStephen Gallimore * Copyright (C) 2013 STMicroelectronics (R&D) Limited 4e5d76075SStephen Gallimore * Author: Stephen Gallimore <stephen.gallimore@st.com> 5e5d76075SStephen Gallimore */ 6e5d76075SStephen Gallimore #ifndef __STI_RESET_SYSCFG_H 7e5d76075SStephen Gallimore #define __STI_RESET_SYSCFG_H 8e5d76075SStephen Gallimore 9e5d76075SStephen Gallimore #include <linux/device.h> 10e5d76075SStephen Gallimore #include <linux/regmap.h> 11e5d76075SStephen Gallimore #include <linux/reset-controller.h> 12e5d76075SStephen Gallimore 13e5d76075SStephen Gallimore /** 14e5d76075SStephen Gallimore * Reset channel description for a system configuration register based 15e5d76075SStephen Gallimore * reset controller. 16e5d76075SStephen Gallimore * 17e5d76075SStephen Gallimore * @compatible: Compatible string of the syscon regmap containing this 18e5d76075SStephen Gallimore * channel's control and ack (status) bits. 19e5d76075SStephen Gallimore * @reset: Regmap field description of the channel's reset bit. 20e5d76075SStephen Gallimore * @ack: Regmap field description of the channel's acknowledge bit. 21e5d76075SStephen Gallimore */ 22e5d76075SStephen Gallimore struct syscfg_reset_channel_data { 23e5d76075SStephen Gallimore const char *compatible; 24e5d76075SStephen Gallimore struct reg_field reset; 25e5d76075SStephen Gallimore struct reg_field ack; 26e5d76075SStephen Gallimore }; 27e5d76075SStephen Gallimore 28e5d76075SStephen Gallimore #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \ 29e5d76075SStephen Gallimore { .compatible = _c, \ 30e5d76075SStephen Gallimore .reset = REG_FIELD(_rr, _rb, _rb), \ 31e5d76075SStephen Gallimore .ack = REG_FIELD(_ar, _ab, _ab), } 32e5d76075SStephen Gallimore 33e5d76075SStephen Gallimore #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \ 34e5d76075SStephen Gallimore { .compatible = _c, \ 35e5d76075SStephen Gallimore .reset = REG_FIELD(_rr, _rb, _rb), } 36e5d76075SStephen Gallimore 37e5d76075SStephen Gallimore /** 38e5d76075SStephen Gallimore * Description of a system configuration register based reset controller. 39e5d76075SStephen Gallimore * 40e5d76075SStephen Gallimore * @wait_for_ack: The controller will wait for reset assert and de-assert to 41e5d76075SStephen Gallimore * be "ack'd" in a channel's ack field. 42e5d76075SStephen Gallimore * @active_low: Are the resets in this controller active low, i.e. clearing 43e5d76075SStephen Gallimore * the reset bit puts the hardware into reset. 44e5d76075SStephen Gallimore * @nr_channels: The number of reset channels in this controller. 45e5d76075SStephen Gallimore * @channels: An array of reset channel descriptions. 46e5d76075SStephen Gallimore */ 47e5d76075SStephen Gallimore struct syscfg_reset_controller_data { 48e5d76075SStephen Gallimore bool wait_for_ack; 49e5d76075SStephen Gallimore bool active_low; 50e5d76075SStephen Gallimore int nr_channels; 51e5d76075SStephen Gallimore const struct syscfg_reset_channel_data *channels; 52e5d76075SStephen Gallimore }; 53e5d76075SStephen Gallimore 54e5d76075SStephen Gallimore /** 55e5d76075SStephen Gallimore * syscfg_reset_probe(): platform device probe function used by syscfg 56e5d76075SStephen Gallimore * reset controller drivers. This registers a reset 57e5d76075SStephen Gallimore * controller configured by the OF match data for 58e5d76075SStephen Gallimore * the compatible device which should be of type 59e5d76075SStephen Gallimore * "struct syscfg_reset_controller_data". 60e5d76075SStephen Gallimore * 61e5d76075SStephen Gallimore * @pdev: platform device 62e5d76075SStephen Gallimore */ 63e5d76075SStephen Gallimore int syscfg_reset_probe(struct platform_device *pdev); 64e5d76075SStephen Gallimore 65e5d76075SStephen Gallimore #endif /* __STI_RESET_SYSCFG_H */ 66