1 /* 2 * Qualcomm self-authenticating modem subsystem remoteproc driver 3 * 4 * Copyright (C) 2016 Linaro Ltd. 5 * Copyright (C) 2014 Sony Mobile Communications AB 6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * version 2 as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of_address.h> 26 #include <linux/of_device.h> 27 #include <linux/platform_device.h> 28 #include <linux/regmap.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/remoteproc.h> 31 #include <linux/reset.h> 32 #include <linux/soc/qcom/mdt_loader.h> 33 #include <linux/iopoll.h> 34 35 #include "remoteproc_internal.h" 36 #include "qcom_common.h" 37 #include "qcom_q6v5.h" 38 39 #include <linux/qcom_scm.h> 40 41 #define MPSS_CRASH_REASON_SMEM 421 42 43 /* RMB Status Register Values */ 44 #define RMB_PBL_SUCCESS 0x1 45 46 #define RMB_MBA_XPU_UNLOCKED 0x1 47 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2 48 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3 49 #define RMB_MBA_AUTH_COMPLETE 0x4 50 51 /* PBL/MBA interface registers */ 52 #define RMB_MBA_IMAGE_REG 0x00 53 #define RMB_PBL_STATUS_REG 0x04 54 #define RMB_MBA_COMMAND_REG 0x08 55 #define RMB_MBA_STATUS_REG 0x0C 56 #define RMB_PMI_META_DATA_REG 0x10 57 #define RMB_PMI_CODE_START_REG 0x14 58 #define RMB_PMI_CODE_LENGTH_REG 0x18 59 #define RMB_MBA_MSS_STATUS 0x40 60 #define RMB_MBA_ALT_RESET 0x44 61 62 #define RMB_CMD_META_DATA_READY 0x1 63 #define RMB_CMD_LOAD_READY 0x2 64 65 /* QDSP6SS Register Offsets */ 66 #define QDSP6SS_RESET_REG 0x014 67 #define QDSP6SS_GFMUX_CTL_REG 0x020 68 #define QDSP6SS_PWR_CTL_REG 0x030 69 #define QDSP6SS_MEM_PWR_CTL 0x0B0 70 #define QDSP6SS_STRAP_ACC 0x110 71 72 /* AXI Halt Register Offsets */ 73 #define AXI_HALTREQ_REG 0x0 74 #define AXI_HALTACK_REG 0x4 75 #define AXI_IDLE_REG 0x8 76 77 #define HALT_ACK_TIMEOUT_MS 100 78 79 /* QDSP6SS_RESET */ 80 #define Q6SS_STOP_CORE BIT(0) 81 #define Q6SS_CORE_ARES BIT(1) 82 #define Q6SS_BUS_ARES_ENABLE BIT(2) 83 84 /* QDSP6SS_GFMUX_CTL */ 85 #define Q6SS_CLK_ENABLE BIT(1) 86 87 /* QDSP6SS_PWR_CTL */ 88 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0) 89 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1) 90 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2) 91 #define Q6SS_L2TAG_SLP_NRET_N BIT(16) 92 #define Q6SS_ETB_SLP_NRET_N BIT(17) 93 #define Q6SS_L2DATA_STBY_N BIT(18) 94 #define Q6SS_SLP_RET_N BIT(19) 95 #define Q6SS_CLAMP_IO BIT(20) 96 #define QDSS_BHS_ON BIT(21) 97 #define QDSS_LDO_BYP BIT(22) 98 99 /* QDSP6v56 parameters */ 100 #define QDSP6v56_LDO_BYP BIT(25) 101 #define QDSP6v56_BHS_ON BIT(24) 102 #define QDSP6v56_CLAMP_WL BIT(21) 103 #define QDSP6v56_CLAMP_QMC_MEM BIT(22) 104 #define HALT_CHECK_MAX_LOOPS 200 105 #define QDSP6SS_XO_CBCR 0x0038 106 #define QDSP6SS_ACC_OVERRIDE_VAL 0x20 107 108 /* QDSP6v65 parameters */ 109 #define QDSP6SS_SLEEP 0x3C 110 #define QDSP6SS_BOOT_CORE_START 0x400 111 #define QDSP6SS_BOOT_CMD 0x404 112 #define SLEEP_CHECK_MAX_LOOPS 200 113 #define BOOT_FSM_TIMEOUT 10000 114 115 struct reg_info { 116 struct regulator *reg; 117 int uV; 118 int uA; 119 }; 120 121 struct qcom_mss_reg_res { 122 const char *supply; 123 int uV; 124 int uA; 125 }; 126 127 struct rproc_hexagon_res { 128 const char *hexagon_mba_image; 129 struct qcom_mss_reg_res *proxy_supply; 130 struct qcom_mss_reg_res *active_supply; 131 char **proxy_clk_names; 132 char **reset_clk_names; 133 char **active_clk_names; 134 int version; 135 bool need_mem_protection; 136 bool has_alt_reset; 137 }; 138 139 struct q6v5 { 140 struct device *dev; 141 struct rproc *rproc; 142 143 void __iomem *reg_base; 144 void __iomem *rmb_base; 145 146 struct regmap *halt_map; 147 u32 halt_q6; 148 u32 halt_modem; 149 u32 halt_nc; 150 151 struct reset_control *mss_restart; 152 153 struct qcom_q6v5 q6v5; 154 155 struct clk *active_clks[8]; 156 struct clk *reset_clks[4]; 157 struct clk *proxy_clks[4]; 158 int active_clk_count; 159 int reset_clk_count; 160 int proxy_clk_count; 161 162 struct reg_info active_regs[1]; 163 struct reg_info proxy_regs[3]; 164 int active_reg_count; 165 int proxy_reg_count; 166 167 bool running; 168 169 phys_addr_t mba_phys; 170 void *mba_region; 171 size_t mba_size; 172 173 phys_addr_t mpss_phys; 174 phys_addr_t mpss_reloc; 175 void *mpss_region; 176 size_t mpss_size; 177 178 struct qcom_rproc_glink glink_subdev; 179 struct qcom_rproc_subdev smd_subdev; 180 struct qcom_rproc_ssr ssr_subdev; 181 struct qcom_sysmon *sysmon; 182 bool need_mem_protection; 183 bool has_alt_reset; 184 int mpss_perm; 185 int mba_perm; 186 int version; 187 }; 188 189 enum { 190 MSS_MSM8916, 191 MSS_MSM8974, 192 MSS_MSM8996, 193 MSS_SDM845, 194 }; 195 196 static int q6v5_regulator_init(struct device *dev, struct reg_info *regs, 197 const struct qcom_mss_reg_res *reg_res) 198 { 199 int rc; 200 int i; 201 202 if (!reg_res) 203 return 0; 204 205 for (i = 0; reg_res[i].supply; i++) { 206 regs[i].reg = devm_regulator_get(dev, reg_res[i].supply); 207 if (IS_ERR(regs[i].reg)) { 208 rc = PTR_ERR(regs[i].reg); 209 if (rc != -EPROBE_DEFER) 210 dev_err(dev, "Failed to get %s\n regulator", 211 reg_res[i].supply); 212 return rc; 213 } 214 215 regs[i].uV = reg_res[i].uV; 216 regs[i].uA = reg_res[i].uA; 217 } 218 219 return i; 220 } 221 222 static int q6v5_regulator_enable(struct q6v5 *qproc, 223 struct reg_info *regs, int count) 224 { 225 int ret; 226 int i; 227 228 for (i = 0; i < count; i++) { 229 if (regs[i].uV > 0) { 230 ret = regulator_set_voltage(regs[i].reg, 231 regs[i].uV, INT_MAX); 232 if (ret) { 233 dev_err(qproc->dev, 234 "Failed to request voltage for %d.\n", 235 i); 236 goto err; 237 } 238 } 239 240 if (regs[i].uA > 0) { 241 ret = regulator_set_load(regs[i].reg, 242 regs[i].uA); 243 if (ret < 0) { 244 dev_err(qproc->dev, 245 "Failed to set regulator mode\n"); 246 goto err; 247 } 248 } 249 250 ret = regulator_enable(regs[i].reg); 251 if (ret) { 252 dev_err(qproc->dev, "Regulator enable failed\n"); 253 goto err; 254 } 255 } 256 257 return 0; 258 err: 259 for (; i >= 0; i--) { 260 if (regs[i].uV > 0) 261 regulator_set_voltage(regs[i].reg, 0, INT_MAX); 262 263 if (regs[i].uA > 0) 264 regulator_set_load(regs[i].reg, 0); 265 266 regulator_disable(regs[i].reg); 267 } 268 269 return ret; 270 } 271 272 static void q6v5_regulator_disable(struct q6v5 *qproc, 273 struct reg_info *regs, int count) 274 { 275 int i; 276 277 for (i = 0; i < count; i++) { 278 if (regs[i].uV > 0) 279 regulator_set_voltage(regs[i].reg, 0, INT_MAX); 280 281 if (regs[i].uA > 0) 282 regulator_set_load(regs[i].reg, 0); 283 284 regulator_disable(regs[i].reg); 285 } 286 } 287 288 static int q6v5_clk_enable(struct device *dev, 289 struct clk **clks, int count) 290 { 291 int rc; 292 int i; 293 294 for (i = 0; i < count; i++) { 295 rc = clk_prepare_enable(clks[i]); 296 if (rc) { 297 dev_err(dev, "Clock enable failed\n"); 298 goto err; 299 } 300 } 301 302 return 0; 303 err: 304 for (i--; i >= 0; i--) 305 clk_disable_unprepare(clks[i]); 306 307 return rc; 308 } 309 310 static void q6v5_clk_disable(struct device *dev, 311 struct clk **clks, int count) 312 { 313 int i; 314 315 for (i = 0; i < count; i++) 316 clk_disable_unprepare(clks[i]); 317 } 318 319 static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm, 320 bool remote_owner, phys_addr_t addr, 321 size_t size) 322 { 323 struct qcom_scm_vmperm next; 324 325 if (!qproc->need_mem_protection) 326 return 0; 327 if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA)) 328 return 0; 329 if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS)) 330 return 0; 331 332 next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS; 333 next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX; 334 335 return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K), 336 current_perm, &next, 1); 337 } 338 339 static int q6v5_load(struct rproc *rproc, const struct firmware *fw) 340 { 341 struct q6v5 *qproc = rproc->priv; 342 343 memcpy(qproc->mba_region, fw->data, fw->size); 344 345 return 0; 346 } 347 348 static int q6v5_reset_assert(struct q6v5 *qproc) 349 { 350 if (qproc->has_alt_reset) 351 return reset_control_reset(qproc->mss_restart); 352 else 353 return reset_control_assert(qproc->mss_restart); 354 } 355 356 static int q6v5_reset_deassert(struct q6v5 *qproc) 357 { 358 int ret; 359 360 if (qproc->has_alt_reset) { 361 writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET); 362 ret = reset_control_reset(qproc->mss_restart); 363 writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET); 364 } else { 365 ret = reset_control_deassert(qproc->mss_restart); 366 } 367 368 return ret; 369 } 370 371 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms) 372 { 373 unsigned long timeout; 374 s32 val; 375 376 timeout = jiffies + msecs_to_jiffies(ms); 377 for (;;) { 378 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG); 379 if (val) 380 break; 381 382 if (time_after(jiffies, timeout)) 383 return -ETIMEDOUT; 384 385 msleep(1); 386 } 387 388 return val; 389 } 390 391 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms) 392 { 393 394 unsigned long timeout; 395 s32 val; 396 397 timeout = jiffies + msecs_to_jiffies(ms); 398 for (;;) { 399 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG); 400 if (val < 0) 401 break; 402 403 if (!status && val) 404 break; 405 else if (status && val == status) 406 break; 407 408 if (time_after(jiffies, timeout)) 409 return -ETIMEDOUT; 410 411 msleep(1); 412 } 413 414 return val; 415 } 416 417 static int q6v5proc_reset(struct q6v5 *qproc) 418 { 419 u32 val; 420 int ret; 421 int i; 422 423 if (qproc->version == MSS_SDM845) { 424 val = readl(qproc->reg_base + QDSP6SS_SLEEP); 425 val |= 0x1; 426 writel(val, qproc->reg_base + QDSP6SS_SLEEP); 427 428 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP, 429 val, !(val & BIT(31)), 1, 430 SLEEP_CHECK_MAX_LOOPS); 431 if (ret) { 432 dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n"); 433 return -ETIMEDOUT; 434 } 435 436 /* De-assert QDSP6 stop core */ 437 writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START); 438 /* Trigger boot FSM */ 439 writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD); 440 441 ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS, 442 val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT); 443 if (ret) { 444 dev_err(qproc->dev, "Boot FSM failed to complete.\n"); 445 /* Reset the modem so that boot FSM is in reset state */ 446 q6v5_reset_deassert(qproc); 447 return ret; 448 } 449 450 goto pbl_wait; 451 } else if (qproc->version == MSS_MSM8996) { 452 /* Override the ACC value if required */ 453 writel(QDSP6SS_ACC_OVERRIDE_VAL, 454 qproc->reg_base + QDSP6SS_STRAP_ACC); 455 456 /* Assert resets, stop core */ 457 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 458 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 459 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 460 461 /* BHS require xo cbcr to be enabled */ 462 val = readl(qproc->reg_base + QDSP6SS_XO_CBCR); 463 val |= 0x1; 464 writel(val, qproc->reg_base + QDSP6SS_XO_CBCR); 465 466 /* Read CLKOFF bit to go low indicating CLK is enabled */ 467 ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR, 468 val, !(val & BIT(31)), 1, 469 HALT_CHECK_MAX_LOOPS); 470 if (ret) { 471 dev_err(qproc->dev, 472 "xo cbcr enabling timed out (rc:%d)\n", ret); 473 return ret; 474 } 475 /* Enable power block headswitch and wait for it to stabilize */ 476 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 477 val |= QDSP6v56_BHS_ON; 478 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 479 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 480 udelay(1); 481 482 /* Put LDO in bypass mode */ 483 val |= QDSP6v56_LDO_BYP; 484 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 485 486 /* Deassert QDSP6 compiler memory clamp */ 487 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 488 val &= ~QDSP6v56_CLAMP_QMC_MEM; 489 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 490 491 /* Deassert memory peripheral sleep and L2 memory standby */ 492 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; 493 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 494 495 /* Turn on L1, L2, ETB and JU memories 1 at a time */ 496 val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); 497 for (i = 19; i >= 0; i--) { 498 val |= BIT(i); 499 writel(val, qproc->reg_base + 500 QDSP6SS_MEM_PWR_CTL); 501 /* 502 * Read back value to ensure the write is done then 503 * wait for 1us for both memory peripheral and data 504 * array to turn on. 505 */ 506 val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL); 507 udelay(1); 508 } 509 /* Remove word line clamp */ 510 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 511 val &= ~QDSP6v56_CLAMP_WL; 512 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 513 } else { 514 /* Assert resets, stop core */ 515 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 516 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 517 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 518 519 /* Enable power block headswitch and wait for it to stabilize */ 520 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 521 val |= QDSS_BHS_ON | QDSS_LDO_BYP; 522 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 523 val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 524 udelay(1); 525 /* 526 * Turn on memories. L2 banks should be done individually 527 * to minimize inrush current. 528 */ 529 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 530 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N | 531 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N; 532 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 533 val |= Q6SS_L2DATA_SLP_NRET_N_2; 534 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 535 val |= Q6SS_L2DATA_SLP_NRET_N_1; 536 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 537 val |= Q6SS_L2DATA_SLP_NRET_N_0; 538 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 539 } 540 /* Remove IO clamp */ 541 val &= ~Q6SS_CLAMP_IO; 542 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 543 544 /* Bring core out of reset */ 545 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 546 val &= ~Q6SS_CORE_ARES; 547 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 548 549 /* Turn on core clock */ 550 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); 551 val |= Q6SS_CLK_ENABLE; 552 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG); 553 554 /* Start core execution */ 555 val = readl(qproc->reg_base + QDSP6SS_RESET_REG); 556 val &= ~Q6SS_STOP_CORE; 557 writel(val, qproc->reg_base + QDSP6SS_RESET_REG); 558 559 pbl_wait: 560 /* Wait for PBL status */ 561 ret = q6v5_rmb_pbl_wait(qproc, 1000); 562 if (ret == -ETIMEDOUT) { 563 dev_err(qproc->dev, "PBL boot timed out\n"); 564 } else if (ret != RMB_PBL_SUCCESS) { 565 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret); 566 ret = -EINVAL; 567 } else { 568 ret = 0; 569 } 570 571 return ret; 572 } 573 574 static void q6v5proc_halt_axi_port(struct q6v5 *qproc, 575 struct regmap *halt_map, 576 u32 offset) 577 { 578 unsigned long timeout; 579 unsigned int val; 580 int ret; 581 582 /* Check if we're already idle */ 583 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 584 if (!ret && val) 585 return; 586 587 /* Assert halt request */ 588 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); 589 590 /* Wait for halt */ 591 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); 592 for (;;) { 593 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); 594 if (ret || val || time_after(jiffies, timeout)) 595 break; 596 597 msleep(1); 598 } 599 600 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 601 if (ret || !val) 602 dev_err(qproc->dev, "port failed halt\n"); 603 604 /* Clear halt request (port will remain halted until reset) */ 605 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); 606 } 607 608 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw) 609 { 610 unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS; 611 dma_addr_t phys; 612 int mdata_perm; 613 int xferop_ret; 614 void *ptr; 615 int ret; 616 617 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, dma_attrs); 618 if (!ptr) { 619 dev_err(qproc->dev, "failed to allocate mdt buffer\n"); 620 return -ENOMEM; 621 } 622 623 memcpy(ptr, fw->data, fw->size); 624 625 /* Hypervisor mapping to access metadata by modem */ 626 mdata_perm = BIT(QCOM_SCM_VMID_HLOS); 627 ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, 628 true, phys, fw->size); 629 if (ret) { 630 dev_err(qproc->dev, 631 "assigning Q6 access to metadata failed: %d\n", ret); 632 ret = -EAGAIN; 633 goto free_dma_attrs; 634 } 635 636 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG); 637 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); 638 639 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000); 640 if (ret == -ETIMEDOUT) 641 dev_err(qproc->dev, "MPSS header authentication timed out\n"); 642 else if (ret < 0) 643 dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret); 644 645 /* Metadata authentication done, remove modem access */ 646 xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, 647 false, phys, fw->size); 648 if (xferop_ret) 649 dev_warn(qproc->dev, 650 "mdt buffer not reclaimed system may become unstable\n"); 651 652 free_dma_attrs: 653 dma_free_attrs(qproc->dev, fw->size, ptr, phys, dma_attrs); 654 655 return ret < 0 ? ret : 0; 656 } 657 658 static bool q6v5_phdr_valid(const struct elf32_phdr *phdr) 659 { 660 if (phdr->p_type != PT_LOAD) 661 return false; 662 663 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH) 664 return false; 665 666 if (!phdr->p_memsz) 667 return false; 668 669 return true; 670 } 671 672 static int q6v5_mpss_load(struct q6v5 *qproc) 673 { 674 const struct elf32_phdr *phdrs; 675 const struct elf32_phdr *phdr; 676 const struct firmware *seg_fw; 677 const struct firmware *fw; 678 struct elf32_hdr *ehdr; 679 phys_addr_t mpss_reloc; 680 phys_addr_t boot_addr; 681 phys_addr_t min_addr = PHYS_ADDR_MAX; 682 phys_addr_t max_addr = 0; 683 bool relocate = false; 684 char seg_name[10]; 685 ssize_t offset; 686 size_t size = 0; 687 void *ptr; 688 int ret; 689 int i; 690 691 ret = request_firmware(&fw, "modem.mdt", qproc->dev); 692 if (ret < 0) { 693 dev_err(qproc->dev, "unable to load modem.mdt\n"); 694 return ret; 695 } 696 697 /* Initialize the RMB validator */ 698 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 699 700 ret = q6v5_mpss_init_image(qproc, fw); 701 if (ret) 702 goto release_firmware; 703 704 ehdr = (struct elf32_hdr *)fw->data; 705 phdrs = (struct elf32_phdr *)(ehdr + 1); 706 707 for (i = 0; i < ehdr->e_phnum; i++) { 708 phdr = &phdrs[i]; 709 710 if (!q6v5_phdr_valid(phdr)) 711 continue; 712 713 if (phdr->p_flags & QCOM_MDT_RELOCATABLE) 714 relocate = true; 715 716 if (phdr->p_paddr < min_addr) 717 min_addr = phdr->p_paddr; 718 719 if (phdr->p_paddr + phdr->p_memsz > max_addr) 720 max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K); 721 } 722 723 mpss_reloc = relocate ? min_addr : qproc->mpss_phys; 724 /* Load firmware segments */ 725 for (i = 0; i < ehdr->e_phnum; i++) { 726 phdr = &phdrs[i]; 727 728 if (!q6v5_phdr_valid(phdr)) 729 continue; 730 731 offset = phdr->p_paddr - mpss_reloc; 732 if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) { 733 dev_err(qproc->dev, "segment outside memory range\n"); 734 ret = -EINVAL; 735 goto release_firmware; 736 } 737 738 ptr = qproc->mpss_region + offset; 739 740 if (phdr->p_filesz) { 741 snprintf(seg_name, sizeof(seg_name), "modem.b%02d", i); 742 ret = request_firmware(&seg_fw, seg_name, qproc->dev); 743 if (ret) { 744 dev_err(qproc->dev, "failed to load %s\n", seg_name); 745 goto release_firmware; 746 } 747 748 memcpy(ptr, seg_fw->data, seg_fw->size); 749 750 release_firmware(seg_fw); 751 } 752 753 if (phdr->p_memsz > phdr->p_filesz) { 754 memset(ptr + phdr->p_filesz, 0, 755 phdr->p_memsz - phdr->p_filesz); 756 } 757 size += phdr->p_memsz; 758 } 759 760 /* Transfer ownership of modem ddr region to q6 */ 761 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true, 762 qproc->mpss_phys, qproc->mpss_size); 763 if (ret) { 764 dev_err(qproc->dev, 765 "assigning Q6 access to mpss memory failed: %d\n", ret); 766 ret = -EAGAIN; 767 goto release_firmware; 768 } 769 770 boot_addr = relocate ? qproc->mpss_phys : min_addr; 771 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG); 772 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG); 773 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG); 774 775 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000); 776 if (ret == -ETIMEDOUT) 777 dev_err(qproc->dev, "MPSS authentication timed out\n"); 778 else if (ret < 0) 779 dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret); 780 781 release_firmware: 782 release_firmware(fw); 783 784 return ret < 0 ? ret : 0; 785 } 786 787 static int q6v5_start(struct rproc *rproc) 788 { 789 struct q6v5 *qproc = (struct q6v5 *)rproc->priv; 790 int xfermemop_ret; 791 int ret; 792 793 qcom_q6v5_prepare(&qproc->q6v5); 794 795 ret = q6v5_regulator_enable(qproc, qproc->proxy_regs, 796 qproc->proxy_reg_count); 797 if (ret) { 798 dev_err(qproc->dev, "failed to enable proxy supplies\n"); 799 goto disable_irqs; 800 } 801 802 ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks, 803 qproc->proxy_clk_count); 804 if (ret) { 805 dev_err(qproc->dev, "failed to enable proxy clocks\n"); 806 goto disable_proxy_reg; 807 } 808 809 ret = q6v5_regulator_enable(qproc, qproc->active_regs, 810 qproc->active_reg_count); 811 if (ret) { 812 dev_err(qproc->dev, "failed to enable supplies\n"); 813 goto disable_proxy_clk; 814 } 815 816 ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks, 817 qproc->reset_clk_count); 818 if (ret) { 819 dev_err(qproc->dev, "failed to enable reset clocks\n"); 820 goto disable_vdd; 821 } 822 823 ret = q6v5_reset_deassert(qproc); 824 if (ret) { 825 dev_err(qproc->dev, "failed to deassert mss restart\n"); 826 goto disable_reset_clks; 827 } 828 829 ret = q6v5_clk_enable(qproc->dev, qproc->active_clks, 830 qproc->active_clk_count); 831 if (ret) { 832 dev_err(qproc->dev, "failed to enable clocks\n"); 833 goto assert_reset; 834 } 835 836 /* Assign MBA image access in DDR to q6 */ 837 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true, 838 qproc->mba_phys, qproc->mba_size); 839 if (ret) { 840 dev_err(qproc->dev, 841 "assigning Q6 access to mba memory failed: %d\n", ret); 842 goto disable_active_clks; 843 } 844 845 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG); 846 847 ret = q6v5proc_reset(qproc); 848 if (ret) 849 goto reclaim_mba; 850 851 ret = q6v5_rmb_mba_wait(qproc, 0, 5000); 852 if (ret == -ETIMEDOUT) { 853 dev_err(qproc->dev, "MBA boot timed out\n"); 854 goto halt_axi_ports; 855 } else if (ret != RMB_MBA_XPU_UNLOCKED && 856 ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) { 857 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret); 858 ret = -EINVAL; 859 goto halt_axi_ports; 860 } 861 862 dev_info(qproc->dev, "MBA booted, loading mpss\n"); 863 864 ret = q6v5_mpss_load(qproc); 865 if (ret) 866 goto reclaim_mpss; 867 868 ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000)); 869 if (ret == -ETIMEDOUT) { 870 dev_err(qproc->dev, "start timed out\n"); 871 goto reclaim_mpss; 872 } 873 874 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, 875 qproc->mba_phys, 876 qproc->mba_size); 877 if (xfermemop_ret) 878 dev_err(qproc->dev, 879 "Failed to reclaim mba buffer system may become unstable\n"); 880 qproc->running = true; 881 882 return 0; 883 884 reclaim_mpss: 885 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, 886 false, qproc->mpss_phys, 887 qproc->mpss_size); 888 WARN_ON(xfermemop_ret); 889 890 halt_axi_ports: 891 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); 892 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); 893 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); 894 895 reclaim_mba: 896 xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false, 897 qproc->mba_phys, 898 qproc->mba_size); 899 if (xfermemop_ret) { 900 dev_err(qproc->dev, 901 "Failed to reclaim mba buffer, system may become unstable\n"); 902 } 903 904 disable_active_clks: 905 q6v5_clk_disable(qproc->dev, qproc->active_clks, 906 qproc->active_clk_count); 907 908 assert_reset: 909 q6v5_reset_assert(qproc); 910 disable_reset_clks: 911 q6v5_clk_disable(qproc->dev, qproc->reset_clks, 912 qproc->reset_clk_count); 913 disable_vdd: 914 q6v5_regulator_disable(qproc, qproc->active_regs, 915 qproc->active_reg_count); 916 disable_proxy_clk: 917 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 918 qproc->proxy_clk_count); 919 disable_proxy_reg: 920 q6v5_regulator_disable(qproc, qproc->proxy_regs, 921 qproc->proxy_reg_count); 922 923 disable_irqs: 924 qcom_q6v5_unprepare(&qproc->q6v5); 925 926 return ret; 927 } 928 929 static int q6v5_stop(struct rproc *rproc) 930 { 931 struct q6v5 *qproc = (struct q6v5 *)rproc->priv; 932 int ret; 933 u32 val; 934 935 qproc->running = false; 936 937 ret = qcom_q6v5_request_stop(&qproc->q6v5); 938 if (ret == -ETIMEDOUT) 939 dev_err(qproc->dev, "timed out on wait\n"); 940 941 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6); 942 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem); 943 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc); 944 if (qproc->version == MSS_MSM8996) { 945 /* 946 * To avoid high MX current during LPASS/MSS restart. 947 */ 948 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG); 949 val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL | 950 QDSP6v56_CLAMP_QMC_MEM; 951 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG); 952 } 953 954 955 ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false, 956 qproc->mpss_phys, qproc->mpss_size); 957 WARN_ON(ret); 958 959 q6v5_reset_assert(qproc); 960 961 ret = qcom_q6v5_unprepare(&qproc->q6v5); 962 if (ret) { 963 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 964 qproc->proxy_clk_count); 965 q6v5_regulator_disable(qproc, qproc->proxy_regs, 966 qproc->proxy_reg_count); 967 } 968 969 q6v5_clk_disable(qproc->dev, qproc->reset_clks, 970 qproc->reset_clk_count); 971 q6v5_clk_disable(qproc->dev, qproc->active_clks, 972 qproc->active_clk_count); 973 q6v5_regulator_disable(qproc, qproc->active_regs, 974 qproc->active_reg_count); 975 976 return 0; 977 } 978 979 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len) 980 { 981 struct q6v5 *qproc = rproc->priv; 982 int offset; 983 984 offset = da - qproc->mpss_reloc; 985 if (offset < 0 || offset + len > qproc->mpss_size) 986 return NULL; 987 988 return qproc->mpss_region + offset; 989 } 990 991 static const struct rproc_ops q6v5_ops = { 992 .start = q6v5_start, 993 .stop = q6v5_stop, 994 .da_to_va = q6v5_da_to_va, 995 .load = q6v5_load, 996 }; 997 998 static void qcom_msa_handover(struct qcom_q6v5 *q6v5) 999 { 1000 struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5); 1001 1002 q6v5_clk_disable(qproc->dev, qproc->proxy_clks, 1003 qproc->proxy_clk_count); 1004 q6v5_regulator_disable(qproc, qproc->proxy_regs, 1005 qproc->proxy_reg_count); 1006 } 1007 1008 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev) 1009 { 1010 struct of_phandle_args args; 1011 struct resource *res; 1012 int ret; 1013 1014 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); 1015 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res); 1016 if (IS_ERR(qproc->reg_base)) 1017 return PTR_ERR(qproc->reg_base); 1018 1019 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb"); 1020 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res); 1021 if (IS_ERR(qproc->rmb_base)) 1022 return PTR_ERR(qproc->rmb_base); 1023 1024 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, 1025 "qcom,halt-regs", 3, 0, &args); 1026 if (ret < 0) { 1027 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 1028 return -EINVAL; 1029 } 1030 1031 qproc->halt_map = syscon_node_to_regmap(args.np); 1032 of_node_put(args.np); 1033 if (IS_ERR(qproc->halt_map)) 1034 return PTR_ERR(qproc->halt_map); 1035 1036 qproc->halt_q6 = args.args[0]; 1037 qproc->halt_modem = args.args[1]; 1038 qproc->halt_nc = args.args[2]; 1039 1040 return 0; 1041 } 1042 1043 static int q6v5_init_clocks(struct device *dev, struct clk **clks, 1044 char **clk_names) 1045 { 1046 int i; 1047 1048 if (!clk_names) 1049 return 0; 1050 1051 for (i = 0; clk_names[i]; i++) { 1052 clks[i] = devm_clk_get(dev, clk_names[i]); 1053 if (IS_ERR(clks[i])) { 1054 int rc = PTR_ERR(clks[i]); 1055 1056 if (rc != -EPROBE_DEFER) 1057 dev_err(dev, "Failed to get %s clock\n", 1058 clk_names[i]); 1059 return rc; 1060 } 1061 } 1062 1063 return i; 1064 } 1065 1066 static int q6v5_init_reset(struct q6v5 *qproc) 1067 { 1068 qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev, 1069 NULL); 1070 if (IS_ERR(qproc->mss_restart)) { 1071 dev_err(qproc->dev, "failed to acquire mss restart\n"); 1072 return PTR_ERR(qproc->mss_restart); 1073 } 1074 1075 return 0; 1076 } 1077 1078 static int q6v5_alloc_memory_region(struct q6v5 *qproc) 1079 { 1080 struct device_node *child; 1081 struct device_node *node; 1082 struct resource r; 1083 int ret; 1084 1085 child = of_get_child_by_name(qproc->dev->of_node, "mba"); 1086 node = of_parse_phandle(child, "memory-region", 0); 1087 ret = of_address_to_resource(node, 0, &r); 1088 if (ret) { 1089 dev_err(qproc->dev, "unable to resolve mba region\n"); 1090 return ret; 1091 } 1092 of_node_put(node); 1093 1094 qproc->mba_phys = r.start; 1095 qproc->mba_size = resource_size(&r); 1096 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size); 1097 if (!qproc->mba_region) { 1098 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", 1099 &r.start, qproc->mba_size); 1100 return -EBUSY; 1101 } 1102 1103 child = of_get_child_by_name(qproc->dev->of_node, "mpss"); 1104 node = of_parse_phandle(child, "memory-region", 0); 1105 ret = of_address_to_resource(node, 0, &r); 1106 if (ret) { 1107 dev_err(qproc->dev, "unable to resolve mpss region\n"); 1108 return ret; 1109 } 1110 of_node_put(node); 1111 1112 qproc->mpss_phys = qproc->mpss_reloc = r.start; 1113 qproc->mpss_size = resource_size(&r); 1114 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size); 1115 if (!qproc->mpss_region) { 1116 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n", 1117 &r.start, qproc->mpss_size); 1118 return -EBUSY; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static int q6v5_probe(struct platform_device *pdev) 1125 { 1126 const struct rproc_hexagon_res *desc; 1127 struct q6v5 *qproc; 1128 struct rproc *rproc; 1129 int ret; 1130 1131 desc = of_device_get_match_data(&pdev->dev); 1132 if (!desc) 1133 return -EINVAL; 1134 1135 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops, 1136 desc->hexagon_mba_image, sizeof(*qproc)); 1137 if (!rproc) { 1138 dev_err(&pdev->dev, "failed to allocate rproc\n"); 1139 return -ENOMEM; 1140 } 1141 1142 qproc = (struct q6v5 *)rproc->priv; 1143 qproc->dev = &pdev->dev; 1144 qproc->rproc = rproc; 1145 platform_set_drvdata(pdev, qproc); 1146 1147 ret = q6v5_init_mem(qproc, pdev); 1148 if (ret) 1149 goto free_rproc; 1150 1151 ret = q6v5_alloc_memory_region(qproc); 1152 if (ret) 1153 goto free_rproc; 1154 1155 ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks, 1156 desc->proxy_clk_names); 1157 if (ret < 0) { 1158 dev_err(&pdev->dev, "Failed to get proxy clocks.\n"); 1159 goto free_rproc; 1160 } 1161 qproc->proxy_clk_count = ret; 1162 1163 ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks, 1164 desc->reset_clk_names); 1165 if (ret < 0) { 1166 dev_err(&pdev->dev, "Failed to get reset clocks.\n"); 1167 goto free_rproc; 1168 } 1169 qproc->reset_clk_count = ret; 1170 1171 ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks, 1172 desc->active_clk_names); 1173 if (ret < 0) { 1174 dev_err(&pdev->dev, "Failed to get active clocks.\n"); 1175 goto free_rproc; 1176 } 1177 qproc->active_clk_count = ret; 1178 1179 ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs, 1180 desc->proxy_supply); 1181 if (ret < 0) { 1182 dev_err(&pdev->dev, "Failed to get proxy regulators.\n"); 1183 goto free_rproc; 1184 } 1185 qproc->proxy_reg_count = ret; 1186 1187 ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs, 1188 desc->active_supply); 1189 if (ret < 0) { 1190 dev_err(&pdev->dev, "Failed to get active regulators.\n"); 1191 goto free_rproc; 1192 } 1193 qproc->active_reg_count = ret; 1194 1195 ret = q6v5_init_reset(qproc); 1196 if (ret) 1197 goto free_rproc; 1198 1199 qproc->version = desc->version; 1200 qproc->has_alt_reset = desc->has_alt_reset; 1201 qproc->need_mem_protection = desc->need_mem_protection; 1202 1203 ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM, 1204 qcom_msa_handover); 1205 if (ret) 1206 goto free_rproc; 1207 1208 qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS); 1209 qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS); 1210 qcom_add_glink_subdev(rproc, &qproc->glink_subdev); 1211 qcom_add_smd_subdev(rproc, &qproc->smd_subdev); 1212 qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss"); 1213 qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12); 1214 1215 ret = rproc_add(rproc); 1216 if (ret) 1217 goto free_rproc; 1218 1219 return 0; 1220 1221 free_rproc: 1222 rproc_free(rproc); 1223 1224 return ret; 1225 } 1226 1227 static int q6v5_remove(struct platform_device *pdev) 1228 { 1229 struct q6v5 *qproc = platform_get_drvdata(pdev); 1230 1231 rproc_del(qproc->rproc); 1232 1233 qcom_remove_sysmon_subdev(qproc->sysmon); 1234 qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev); 1235 qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev); 1236 qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev); 1237 rproc_free(qproc->rproc); 1238 1239 return 0; 1240 } 1241 1242 static const struct rproc_hexagon_res sdm845_mss = { 1243 .hexagon_mba_image = "mba.mbn", 1244 .proxy_clk_names = (char*[]){ 1245 "xo", 1246 "prng", 1247 NULL 1248 }, 1249 .reset_clk_names = (char*[]){ 1250 "iface", 1251 "snoc_axi", 1252 NULL 1253 }, 1254 .active_clk_names = (char*[]){ 1255 "bus", 1256 "mem", 1257 "gpll0_mss", 1258 "mnoc_axi", 1259 NULL 1260 }, 1261 .need_mem_protection = true, 1262 .has_alt_reset = true, 1263 .version = MSS_SDM845, 1264 }; 1265 1266 static const struct rproc_hexagon_res msm8996_mss = { 1267 .hexagon_mba_image = "mba.mbn", 1268 .proxy_clk_names = (char*[]){ 1269 "xo", 1270 "pnoc", 1271 NULL 1272 }, 1273 .active_clk_names = (char*[]){ 1274 "iface", 1275 "bus", 1276 "mem", 1277 "gpll0_mss_clk", 1278 NULL 1279 }, 1280 .need_mem_protection = true, 1281 .has_alt_reset = false, 1282 .version = MSS_MSM8996, 1283 }; 1284 1285 static const struct rproc_hexagon_res msm8916_mss = { 1286 .hexagon_mba_image = "mba.mbn", 1287 .proxy_supply = (struct qcom_mss_reg_res[]) { 1288 { 1289 .supply = "mx", 1290 .uV = 1050000, 1291 }, 1292 { 1293 .supply = "cx", 1294 .uA = 100000, 1295 }, 1296 { 1297 .supply = "pll", 1298 .uA = 100000, 1299 }, 1300 {} 1301 }, 1302 .proxy_clk_names = (char*[]){ 1303 "xo", 1304 NULL 1305 }, 1306 .active_clk_names = (char*[]){ 1307 "iface", 1308 "bus", 1309 "mem", 1310 NULL 1311 }, 1312 .need_mem_protection = false, 1313 .has_alt_reset = false, 1314 .version = MSS_MSM8916, 1315 }; 1316 1317 static const struct rproc_hexagon_res msm8974_mss = { 1318 .hexagon_mba_image = "mba.b00", 1319 .proxy_supply = (struct qcom_mss_reg_res[]) { 1320 { 1321 .supply = "mx", 1322 .uV = 1050000, 1323 }, 1324 { 1325 .supply = "cx", 1326 .uA = 100000, 1327 }, 1328 { 1329 .supply = "pll", 1330 .uA = 100000, 1331 }, 1332 {} 1333 }, 1334 .active_supply = (struct qcom_mss_reg_res[]) { 1335 { 1336 .supply = "mss", 1337 .uV = 1050000, 1338 .uA = 100000, 1339 }, 1340 {} 1341 }, 1342 .proxy_clk_names = (char*[]){ 1343 "xo", 1344 NULL 1345 }, 1346 .active_clk_names = (char*[]){ 1347 "iface", 1348 "bus", 1349 "mem", 1350 NULL 1351 }, 1352 .need_mem_protection = false, 1353 .has_alt_reset = false, 1354 .version = MSS_MSM8974, 1355 }; 1356 1357 static const struct of_device_id q6v5_of_match[] = { 1358 { .compatible = "qcom,q6v5-pil", .data = &msm8916_mss}, 1359 { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss}, 1360 { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss}, 1361 { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss}, 1362 { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss}, 1363 { }, 1364 }; 1365 MODULE_DEVICE_TABLE(of, q6v5_of_match); 1366 1367 static struct platform_driver q6v5_driver = { 1368 .probe = q6v5_probe, 1369 .remove = q6v5_remove, 1370 .driver = { 1371 .name = "qcom-q6v5-mss", 1372 .of_match_table = q6v5_of_match, 1373 }, 1374 }; 1375 module_platform_driver(q6v5_driver); 1376 1377 MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver"); 1378 MODULE_LICENSE("GPL v2"); 1379