16cdae817SPascal PAILLET-LME // SPDX-License-Identifier: GPL-2.0
26cdae817SPascal PAILLET-LME // Copyright (C) STMicroelectronics 2019
36cdae817SPascal PAILLET-LME // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
46cdae817SPascal PAILLET-LME // Pascal Paillet <p.paillet@st.com>.
56cdae817SPascal PAILLET-LME
66cdae817SPascal PAILLET-LME #include <linux/io.h>
76cdae817SPascal PAILLET-LME #include <linux/iopoll.h>
86cdae817SPascal PAILLET-LME #include <linux/module.h>
9*045a44d4SRob Herring #include <linux/of.h>
106cdae817SPascal PAILLET-LME #include <linux/platform_device.h>
116cdae817SPascal PAILLET-LME #include <linux/regulator/driver.h>
126cdae817SPascal PAILLET-LME #include <linux/regulator/of_regulator.h>
136cdae817SPascal PAILLET-LME
146cdae817SPascal PAILLET-LME /*
156cdae817SPascal PAILLET-LME * Registers description
166cdae817SPascal PAILLET-LME */
176cdae817SPascal PAILLET-LME #define REG_PWR_CR3 0x0C
186cdae817SPascal PAILLET-LME
196cdae817SPascal PAILLET-LME #define USB_3_3_EN BIT(24)
206cdae817SPascal PAILLET-LME #define USB_3_3_RDY BIT(26)
216cdae817SPascal PAILLET-LME #define REG_1_8_EN BIT(28)
226cdae817SPascal PAILLET-LME #define REG_1_8_RDY BIT(29)
236cdae817SPascal PAILLET-LME #define REG_1_1_EN BIT(30)
246cdae817SPascal PAILLET-LME #define REG_1_1_RDY BIT(31)
256cdae817SPascal PAILLET-LME
266cdae817SPascal PAILLET-LME /* list of supported regulators */
276cdae817SPascal PAILLET-LME enum {
286cdae817SPascal PAILLET-LME PWR_REG11,
296cdae817SPascal PAILLET-LME PWR_REG18,
306cdae817SPascal PAILLET-LME PWR_USB33,
316cdae817SPascal PAILLET-LME STM32PWR_REG_NUM_REGS
326cdae817SPascal PAILLET-LME };
336cdae817SPascal PAILLET-LME
3482f26185Skbuild test robot static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
356cdae817SPascal PAILLET-LME [PWR_REG11] = REG_1_1_RDY,
366cdae817SPascal PAILLET-LME [PWR_REG18] = REG_1_8_RDY,
376cdae817SPascal PAILLET-LME [PWR_USB33] = USB_3_3_RDY,
386cdae817SPascal PAILLET-LME };
396cdae817SPascal PAILLET-LME
406cdae817SPascal PAILLET-LME struct stm32_pwr_reg {
416cdae817SPascal PAILLET-LME void __iomem *base;
426cdae817SPascal PAILLET-LME u32 ready_mask;
436cdae817SPascal PAILLET-LME };
446cdae817SPascal PAILLET-LME
stm32_pwr_reg_is_ready(struct regulator_dev * rdev)4582f26185Skbuild test robot static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
466cdae817SPascal PAILLET-LME {
476cdae817SPascal PAILLET-LME struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
486cdae817SPascal PAILLET-LME u32 val;
496cdae817SPascal PAILLET-LME
506cdae817SPascal PAILLET-LME val = readl_relaxed(priv->base + REG_PWR_CR3);
516cdae817SPascal PAILLET-LME
526cdae817SPascal PAILLET-LME return (val & priv->ready_mask);
536cdae817SPascal PAILLET-LME }
546cdae817SPascal PAILLET-LME
stm32_pwr_reg_is_enabled(struct regulator_dev * rdev)5582f26185Skbuild test robot static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
566cdae817SPascal PAILLET-LME {
576cdae817SPascal PAILLET-LME struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
586cdae817SPascal PAILLET-LME u32 val;
596cdae817SPascal PAILLET-LME
606cdae817SPascal PAILLET-LME val = readl_relaxed(priv->base + REG_PWR_CR3);
616cdae817SPascal PAILLET-LME
627bcbdbe0SAxel Lin return (val & rdev->desc->enable_mask);
636cdae817SPascal PAILLET-LME }
646cdae817SPascal PAILLET-LME
stm32_pwr_reg_enable(struct regulator_dev * rdev)656cdae817SPascal PAILLET-LME static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
666cdae817SPascal PAILLET-LME {
676cdae817SPascal PAILLET-LME struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
686cdae817SPascal PAILLET-LME int ret;
696cdae817SPascal PAILLET-LME u32 val;
706cdae817SPascal PAILLET-LME
716cdae817SPascal PAILLET-LME val = readl_relaxed(priv->base + REG_PWR_CR3);
727bcbdbe0SAxel Lin val |= rdev->desc->enable_mask;
736cdae817SPascal PAILLET-LME writel_relaxed(val, priv->base + REG_PWR_CR3);
746cdae817SPascal PAILLET-LME
756cdae817SPascal PAILLET-LME /* use an arbitrary timeout of 20ms */
766cdae817SPascal PAILLET-LME ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
776cdae817SPascal PAILLET-LME 100, 20 * 1000);
786cdae817SPascal PAILLET-LME if (ret)
796cdae817SPascal PAILLET-LME dev_err(&rdev->dev, "regulator enable timed out!\n");
806cdae817SPascal PAILLET-LME
816cdae817SPascal PAILLET-LME return ret;
826cdae817SPascal PAILLET-LME }
836cdae817SPascal PAILLET-LME
stm32_pwr_reg_disable(struct regulator_dev * rdev)846cdae817SPascal PAILLET-LME static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
856cdae817SPascal PAILLET-LME {
866cdae817SPascal PAILLET-LME struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
876cdae817SPascal PAILLET-LME int ret;
886cdae817SPascal PAILLET-LME u32 val;
896cdae817SPascal PAILLET-LME
906cdae817SPascal PAILLET-LME val = readl_relaxed(priv->base + REG_PWR_CR3);
917bcbdbe0SAxel Lin val &= ~rdev->desc->enable_mask;
926cdae817SPascal PAILLET-LME writel_relaxed(val, priv->base + REG_PWR_CR3);
936cdae817SPascal PAILLET-LME
946cdae817SPascal PAILLET-LME /* use an arbitrary timeout of 20ms */
95959c3476SMarek Vasut ret = readx_poll_timeout(stm32_pwr_reg_is_enabled, rdev, val, !val,
966cdae817SPascal PAILLET-LME 100, 20 * 1000);
976cdae817SPascal PAILLET-LME if (ret)
986cdae817SPascal PAILLET-LME dev_err(&rdev->dev, "regulator disable timed out!\n");
996cdae817SPascal PAILLET-LME
1006cdae817SPascal PAILLET-LME return ret;
1016cdae817SPascal PAILLET-LME }
1026cdae817SPascal PAILLET-LME
1036cdae817SPascal PAILLET-LME static const struct regulator_ops stm32_pwr_reg_ops = {
1046cdae817SPascal PAILLET-LME .enable = stm32_pwr_reg_enable,
1056cdae817SPascal PAILLET-LME .disable = stm32_pwr_reg_disable,
1066cdae817SPascal PAILLET-LME .is_enabled = stm32_pwr_reg_is_enabled,
1076cdae817SPascal PAILLET-LME };
1086cdae817SPascal PAILLET-LME
1096cdae817SPascal PAILLET-LME #define PWR_REG(_id, _name, _volt, _en, _supply) \
1106cdae817SPascal PAILLET-LME [_id] = { \
1116cdae817SPascal PAILLET-LME .id = _id, \
1126cdae817SPascal PAILLET-LME .name = _name, \
1136cdae817SPascal PAILLET-LME .of_match = of_match_ptr(_name), \
1146cdae817SPascal PAILLET-LME .n_voltages = 1, \
1156cdae817SPascal PAILLET-LME .type = REGULATOR_VOLTAGE, \
1166cdae817SPascal PAILLET-LME .fixed_uV = _volt, \
1176cdae817SPascal PAILLET-LME .ops = &stm32_pwr_reg_ops, \
1186cdae817SPascal PAILLET-LME .enable_mask = _en, \
1196cdae817SPascal PAILLET-LME .owner = THIS_MODULE, \
1206cdae817SPascal PAILLET-LME .supply_name = _supply, \
1216cdae817SPascal PAILLET-LME } \
1226cdae817SPascal PAILLET-LME
1236cdae817SPascal PAILLET-LME static const struct regulator_desc stm32_pwr_desc[] = {
1246cdae817SPascal PAILLET-LME PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
1256cdae817SPascal PAILLET-LME PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
1266cdae817SPascal PAILLET-LME PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
1276cdae817SPascal PAILLET-LME };
1286cdae817SPascal PAILLET-LME
stm32_pwr_regulator_probe(struct platform_device * pdev)1296cdae817SPascal PAILLET-LME static int stm32_pwr_regulator_probe(struct platform_device *pdev)
1306cdae817SPascal PAILLET-LME {
1316cdae817SPascal PAILLET-LME struct stm32_pwr_reg *priv;
1326cdae817SPascal PAILLET-LME void __iomem *base;
1336cdae817SPascal PAILLET-LME struct regulator_dev *rdev;
1346cdae817SPascal PAILLET-LME struct regulator_config config = { };
1356cdae817SPascal PAILLET-LME int i, ret = 0;
1366cdae817SPascal PAILLET-LME
137c4a413e5SYAN SHI base = devm_platform_ioremap_resource(pdev, 0);
138c4a413e5SYAN SHI if (IS_ERR(base)) {
1396cdae817SPascal PAILLET-LME dev_err(&pdev->dev, "Unable to map IO memory\n");
140c4a413e5SYAN SHI return PTR_ERR(base);
1416cdae817SPascal PAILLET-LME }
1426cdae817SPascal PAILLET-LME
1436cdae817SPascal PAILLET-LME config.dev = &pdev->dev;
1446cdae817SPascal PAILLET-LME
1456cdae817SPascal PAILLET-LME for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
1466cdae817SPascal PAILLET-LME priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
1476cdae817SPascal PAILLET-LME GFP_KERNEL);
1486cdae817SPascal PAILLET-LME if (!priv)
1496cdae817SPascal PAILLET-LME return -ENOMEM;
1506cdae817SPascal PAILLET-LME priv->base = base;
1516cdae817SPascal PAILLET-LME priv->ready_mask = ready_mask_table[i];
1526cdae817SPascal PAILLET-LME config.driver_data = priv;
1536cdae817SPascal PAILLET-LME
1546cdae817SPascal PAILLET-LME rdev = devm_regulator_register(&pdev->dev,
1556cdae817SPascal PAILLET-LME &stm32_pwr_desc[i],
1566cdae817SPascal PAILLET-LME &config);
1576cdae817SPascal PAILLET-LME if (IS_ERR(rdev)) {
1586cdae817SPascal PAILLET-LME ret = PTR_ERR(rdev);
1596cdae817SPascal PAILLET-LME dev_err(&pdev->dev,
1606cdae817SPascal PAILLET-LME "Failed to register regulator: %d\n", ret);
1616cdae817SPascal PAILLET-LME break;
1626cdae817SPascal PAILLET-LME }
1636cdae817SPascal PAILLET-LME }
1646cdae817SPascal PAILLET-LME return ret;
1656cdae817SPascal PAILLET-LME }
1666cdae817SPascal PAILLET-LME
167a94a11ceSJisheng Zhang static const struct of_device_id __maybe_unused stm32_pwr_of_match[] = {
1686cdae817SPascal PAILLET-LME { .compatible = "st,stm32mp1,pwr-reg", },
1696cdae817SPascal PAILLET-LME {},
1706cdae817SPascal PAILLET-LME };
1716cdae817SPascal PAILLET-LME MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
1726cdae817SPascal PAILLET-LME
1736cdae817SPascal PAILLET-LME static struct platform_driver stm32_pwr_driver = {
1746cdae817SPascal PAILLET-LME .probe = stm32_pwr_regulator_probe,
1756cdae817SPascal PAILLET-LME .driver = {
1766cdae817SPascal PAILLET-LME .name = "stm32-pwr-regulator",
177d3b81d97SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1786cdae817SPascal PAILLET-LME .of_match_table = of_match_ptr(stm32_pwr_of_match),
1796cdae817SPascal PAILLET-LME },
1806cdae817SPascal PAILLET-LME };
1816cdae817SPascal PAILLET-LME module_platform_driver(stm32_pwr_driver);
1826cdae817SPascal PAILLET-LME
1836cdae817SPascal PAILLET-LME MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
1846cdae817SPascal PAILLET-LME MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
185