1f40f9409SChiYuan Huang // SPDX-License-Identifier: GPL-2.0+
2f40f9409SChiYuan Huang
3f40f9409SChiYuan Huang #include <linux/bitops.h>
4f40f9409SChiYuan Huang #include <linux/delay.h>
5f40f9409SChiYuan Huang #include <linux/gpio/consumer.h>
6f40f9409SChiYuan Huang #include <linux/i2c.h>
7f40f9409SChiYuan Huang #include <linux/kernel.h>
8f40f9409SChiYuan Huang #include <linux/module.h>
9f40f9409SChiYuan Huang #include <linux/mutex.h>
10f40f9409SChiYuan Huang #include <linux/regmap.h>
11f40f9409SChiYuan Huang #include <linux/regulator/driver.h>
12f40f9409SChiYuan Huang
13f40f9409SChiYuan Huang enum {
14f40f9409SChiYuan Huang RTQ6752_IDX_PAVDD = 0,
15f40f9409SChiYuan Huang RTQ6752_IDX_NAVDD = 1,
16f40f9409SChiYuan Huang RTQ6752_IDX_MAX
17f40f9409SChiYuan Huang };
18f40f9409SChiYuan Huang
19f40f9409SChiYuan Huang #define RTQ6752_REG_PAVDD 0x00
20f40f9409SChiYuan Huang #define RTQ6752_REG_NAVDD 0x01
21f40f9409SChiYuan Huang #define RTQ6752_REG_PAVDDONDLY 0x07
2277eac0e1SChiYuan Huang #define RTQ6752_REG_PAVDDSSTIME 0x08
23f40f9409SChiYuan Huang #define RTQ6752_REG_NAVDDONDLY 0x0D
24f40f9409SChiYuan Huang #define RTQ6752_REG_NAVDDSSTIME 0x0E
25f40f9409SChiYuan Huang #define RTQ6752_REG_OPTION1 0x12
26f40f9409SChiYuan Huang #define RTQ6752_REG_CHSWITCH 0x16
27f40f9409SChiYuan Huang #define RTQ6752_REG_FAULT 0x1D
28f40f9409SChiYuan Huang
29f40f9409SChiYuan Huang #define RTQ6752_VOUT_MASK GENMASK(5, 0)
30f40f9409SChiYuan Huang #define RTQ6752_NAVDDEN_MASK BIT(3)
31f40f9409SChiYuan Huang #define RTQ6752_PAVDDEN_MASK BIT(0)
32f40f9409SChiYuan Huang #define RTQ6752_PAVDDAD_MASK BIT(4)
33f40f9409SChiYuan Huang #define RTQ6752_NAVDDAD_MASK BIT(3)
34f40f9409SChiYuan Huang #define RTQ6752_PAVDDF_MASK BIT(3)
35f40f9409SChiYuan Huang #define RTQ6752_NAVDDF_MASK BIT(0)
36f40f9409SChiYuan Huang #define RTQ6752_ENABLE_MASK (BIT(RTQ6752_IDX_MAX) - 1)
37f40f9409SChiYuan Huang
38f40f9409SChiYuan Huang #define RTQ6752_VOUT_MINUV 5000000
39f40f9409SChiYuan Huang #define RTQ6752_VOUT_STEPUV 50000
40f40f9409SChiYuan Huang #define RTQ6752_VOUT_NUM 47
41f40f9409SChiYuan Huang #define RTQ6752_I2CRDY_TIMEUS 1000
42f40f9409SChiYuan Huang #define RTQ6752_MINSS_TIMEUS 5000
43f40f9409SChiYuan Huang
44f40f9409SChiYuan Huang struct rtq6752_priv {
45f40f9409SChiYuan Huang struct regmap *regmap;
46f40f9409SChiYuan Huang struct gpio_desc *enable_gpio;
47f40f9409SChiYuan Huang struct mutex lock;
48f40f9409SChiYuan Huang unsigned char enable_flag;
49f40f9409SChiYuan Huang };
50f40f9409SChiYuan Huang
rtq6752_set_vdd_enable(struct regulator_dev * rdev)51f40f9409SChiYuan Huang static int rtq6752_set_vdd_enable(struct regulator_dev *rdev)
52f40f9409SChiYuan Huang {
53f40f9409SChiYuan Huang struct rtq6752_priv *priv = rdev_get_drvdata(rdev);
54f40f9409SChiYuan Huang int rid = rdev_get_id(rdev), ret;
55f40f9409SChiYuan Huang
56f40f9409SChiYuan Huang mutex_lock(&priv->lock);
576f3a9b10SChiYuan Huang if (!priv->enable_flag) {
58513d1404SChiYuan Huang if (priv->enable_gpio) {
59f40f9409SChiYuan Huang gpiod_set_value(priv->enable_gpio, 1);
60f40f9409SChiYuan Huang
61f40f9409SChiYuan Huang usleep_range(RTQ6752_I2CRDY_TIMEUS,
62f40f9409SChiYuan Huang RTQ6752_I2CRDY_TIMEUS + 100);
63513d1404SChiYuan Huang }
64f40f9409SChiYuan Huang
65f40f9409SChiYuan Huang regcache_cache_only(priv->regmap, false);
66f40f9409SChiYuan Huang ret = regcache_sync(priv->regmap);
67f40f9409SChiYuan Huang if (ret) {
68f40f9409SChiYuan Huang mutex_unlock(&priv->lock);
69f40f9409SChiYuan Huang return ret;
70f40f9409SChiYuan Huang }
71f40f9409SChiYuan Huang }
72f40f9409SChiYuan Huang
73f40f9409SChiYuan Huang priv->enable_flag |= BIT(rid);
74f40f9409SChiYuan Huang mutex_unlock(&priv->lock);
75f40f9409SChiYuan Huang
76f40f9409SChiYuan Huang return regulator_enable_regmap(rdev);
77f40f9409SChiYuan Huang }
78f40f9409SChiYuan Huang
rtq6752_set_vdd_disable(struct regulator_dev * rdev)79f40f9409SChiYuan Huang static int rtq6752_set_vdd_disable(struct regulator_dev *rdev)
80f40f9409SChiYuan Huang {
81f40f9409SChiYuan Huang struct rtq6752_priv *priv = rdev_get_drvdata(rdev);
82f40f9409SChiYuan Huang int rid = rdev_get_id(rdev), ret;
83f40f9409SChiYuan Huang
84f40f9409SChiYuan Huang ret = regulator_disable_regmap(rdev);
85f40f9409SChiYuan Huang if (ret)
86f40f9409SChiYuan Huang return ret;
87f40f9409SChiYuan Huang
88f40f9409SChiYuan Huang mutex_lock(&priv->lock);
89f40f9409SChiYuan Huang priv->enable_flag &= ~BIT(rid);
90f40f9409SChiYuan Huang
91513d1404SChiYuan Huang if (!priv->enable_flag) {
92f40f9409SChiYuan Huang regcache_cache_only(priv->regmap, true);
93f40f9409SChiYuan Huang regcache_mark_dirty(priv->regmap);
94513d1404SChiYuan Huang
95513d1404SChiYuan Huang if (priv->enable_gpio)
96513d1404SChiYuan Huang gpiod_set_value(priv->enable_gpio, 0);
97513d1404SChiYuan Huang
986f3a9b10SChiYuan Huang }
99f40f9409SChiYuan Huang mutex_unlock(&priv->lock);
100f40f9409SChiYuan Huang
101f40f9409SChiYuan Huang return 0;
102f40f9409SChiYuan Huang }
103f40f9409SChiYuan Huang
rtq6752_get_error_flags(struct regulator_dev * rdev,unsigned int * flags)104f40f9409SChiYuan Huang static int rtq6752_get_error_flags(struct regulator_dev *rdev,
105f40f9409SChiYuan Huang unsigned int *flags)
106f40f9409SChiYuan Huang {
107f40f9409SChiYuan Huang unsigned int val, events = 0;
108f40f9409SChiYuan Huang const unsigned int fault_mask[] = {
109f40f9409SChiYuan Huang RTQ6752_PAVDDF_MASK, RTQ6752_NAVDDF_MASK };
110f40f9409SChiYuan Huang int rid = rdev_get_id(rdev), ret;
111f40f9409SChiYuan Huang
112f40f9409SChiYuan Huang ret = regmap_read(rdev->regmap, RTQ6752_REG_FAULT, &val);
113f40f9409SChiYuan Huang if (ret)
114f40f9409SChiYuan Huang return ret;
115f40f9409SChiYuan Huang
116f40f9409SChiYuan Huang if (val & fault_mask[rid])
117f40f9409SChiYuan Huang events = REGULATOR_ERROR_REGULATION_OUT;
118f40f9409SChiYuan Huang
119f40f9409SChiYuan Huang *flags = events;
120f40f9409SChiYuan Huang return 0;
121f40f9409SChiYuan Huang }
122f40f9409SChiYuan Huang
123f40f9409SChiYuan Huang static const struct regulator_ops rtq6752_regulator_ops = {
124f40f9409SChiYuan Huang .list_voltage = regulator_list_voltage_linear,
125f40f9409SChiYuan Huang .set_voltage_sel = regulator_set_voltage_sel_regmap,
126f40f9409SChiYuan Huang .get_voltage_sel = regulator_get_voltage_sel_regmap,
127f40f9409SChiYuan Huang .enable = rtq6752_set_vdd_enable,
128f40f9409SChiYuan Huang .disable = rtq6752_set_vdd_disable,
129f40f9409SChiYuan Huang .is_enabled = regulator_is_enabled_regmap,
130f40f9409SChiYuan Huang .set_active_discharge = regulator_set_active_discharge_regmap,
131f40f9409SChiYuan Huang .get_error_flags = rtq6752_get_error_flags,
132f40f9409SChiYuan Huang };
133f40f9409SChiYuan Huang
134f40f9409SChiYuan Huang static const struct regulator_desc rtq6752_regulator_descs[] = {
135f40f9409SChiYuan Huang {
136f40f9409SChiYuan Huang .name = "rtq6752-pavdd",
137f40f9409SChiYuan Huang .of_match = of_match_ptr("pavdd"),
138f40f9409SChiYuan Huang .regulators_node = of_match_ptr("regulators"),
139f40f9409SChiYuan Huang .id = RTQ6752_IDX_PAVDD,
140f40f9409SChiYuan Huang .n_voltages = RTQ6752_VOUT_NUM,
141f40f9409SChiYuan Huang .ops = &rtq6752_regulator_ops,
142f40f9409SChiYuan Huang .owner = THIS_MODULE,
143f40f9409SChiYuan Huang .min_uV = RTQ6752_VOUT_MINUV,
144f40f9409SChiYuan Huang .uV_step = RTQ6752_VOUT_STEPUV,
145f40f9409SChiYuan Huang .enable_time = RTQ6752_MINSS_TIMEUS,
146f40f9409SChiYuan Huang .vsel_reg = RTQ6752_REG_PAVDD,
147f40f9409SChiYuan Huang .vsel_mask = RTQ6752_VOUT_MASK,
148f40f9409SChiYuan Huang .enable_reg = RTQ6752_REG_CHSWITCH,
149f40f9409SChiYuan Huang .enable_mask = RTQ6752_PAVDDEN_MASK,
150f40f9409SChiYuan Huang .active_discharge_reg = RTQ6752_REG_OPTION1,
151f40f9409SChiYuan Huang .active_discharge_mask = RTQ6752_PAVDDAD_MASK,
152f40f9409SChiYuan Huang .active_discharge_off = RTQ6752_PAVDDAD_MASK,
153f40f9409SChiYuan Huang },
154f40f9409SChiYuan Huang {
155f40f9409SChiYuan Huang .name = "rtq6752-navdd",
156f40f9409SChiYuan Huang .of_match = of_match_ptr("navdd"),
157f40f9409SChiYuan Huang .regulators_node = of_match_ptr("regulators"),
158f40f9409SChiYuan Huang .id = RTQ6752_IDX_NAVDD,
159f40f9409SChiYuan Huang .n_voltages = RTQ6752_VOUT_NUM,
160f40f9409SChiYuan Huang .ops = &rtq6752_regulator_ops,
161f40f9409SChiYuan Huang .owner = THIS_MODULE,
162f40f9409SChiYuan Huang .min_uV = RTQ6752_VOUT_MINUV,
163f40f9409SChiYuan Huang .uV_step = RTQ6752_VOUT_STEPUV,
164f40f9409SChiYuan Huang .enable_time = RTQ6752_MINSS_TIMEUS,
165f40f9409SChiYuan Huang .vsel_reg = RTQ6752_REG_NAVDD,
166f40f9409SChiYuan Huang .vsel_mask = RTQ6752_VOUT_MASK,
167f40f9409SChiYuan Huang .enable_reg = RTQ6752_REG_CHSWITCH,
168f40f9409SChiYuan Huang .enable_mask = RTQ6752_NAVDDEN_MASK,
169f40f9409SChiYuan Huang .active_discharge_reg = RTQ6752_REG_OPTION1,
170f40f9409SChiYuan Huang .active_discharge_mask = RTQ6752_NAVDDAD_MASK,
171f40f9409SChiYuan Huang .active_discharge_off = RTQ6752_NAVDDAD_MASK,
172f40f9409SChiYuan Huang }
173f40f9409SChiYuan Huang };
174f40f9409SChiYuan Huang
rtq6752_init_device_properties(struct rtq6752_priv * priv)175f40f9409SChiYuan Huang static int rtq6752_init_device_properties(struct rtq6752_priv *priv)
176f40f9409SChiYuan Huang {
177f40f9409SChiYuan Huang u8 raw_vals[] = { 0, 0 };
178f40f9409SChiYuan Huang int ret;
179f40f9409SChiYuan Huang
180f40f9409SChiYuan Huang /* Configure PAVDD on and softstart delay time to the minimum */
181f40f9409SChiYuan Huang ret = regmap_raw_write(priv->regmap, RTQ6752_REG_PAVDDONDLY, raw_vals,
182f40f9409SChiYuan Huang ARRAY_SIZE(raw_vals));
183f40f9409SChiYuan Huang if (ret)
184f40f9409SChiYuan Huang return ret;
185f40f9409SChiYuan Huang
186f40f9409SChiYuan Huang /* Configure NAVDD on and softstart delay time to the minimum */
187f40f9409SChiYuan Huang return regmap_raw_write(priv->regmap, RTQ6752_REG_NAVDDONDLY, raw_vals,
188f40f9409SChiYuan Huang ARRAY_SIZE(raw_vals));
189f40f9409SChiYuan Huang }
190f40f9409SChiYuan Huang
rtq6752_is_volatile_reg(struct device * dev,unsigned int reg)191f40f9409SChiYuan Huang static bool rtq6752_is_volatile_reg(struct device *dev, unsigned int reg)
192f40f9409SChiYuan Huang {
193f40f9409SChiYuan Huang if (reg == RTQ6752_REG_FAULT)
194f40f9409SChiYuan Huang return true;
195f40f9409SChiYuan Huang return false;
196f40f9409SChiYuan Huang }
197f40f9409SChiYuan Huang
198f40f9409SChiYuan Huang static const struct reg_default rtq6752_reg_defaults[] = {
199f40f9409SChiYuan Huang { RTQ6752_REG_PAVDD, 0x14 },
200f40f9409SChiYuan Huang { RTQ6752_REG_NAVDD, 0x14 },
201f40f9409SChiYuan Huang { RTQ6752_REG_PAVDDONDLY, 0x01 },
202f40f9409SChiYuan Huang { RTQ6752_REG_PAVDDSSTIME, 0x01 },
203f40f9409SChiYuan Huang { RTQ6752_REG_NAVDDONDLY, 0x01 },
204f40f9409SChiYuan Huang { RTQ6752_REG_NAVDDSSTIME, 0x01 },
205f40f9409SChiYuan Huang { RTQ6752_REG_OPTION1, 0x07 },
206f40f9409SChiYuan Huang { RTQ6752_REG_CHSWITCH, 0x29 },
207f40f9409SChiYuan Huang };
208f40f9409SChiYuan Huang
209f40f9409SChiYuan Huang static const struct regmap_config rtq6752_regmap_config = {
210f40f9409SChiYuan Huang .reg_bits = 8,
211f40f9409SChiYuan Huang .val_bits = 8,
212f40f9409SChiYuan Huang .cache_type = REGCACHE_RBTREE,
213f40f9409SChiYuan Huang .max_register = RTQ6752_REG_FAULT,
214f40f9409SChiYuan Huang .reg_defaults = rtq6752_reg_defaults,
215f40f9409SChiYuan Huang .num_reg_defaults = ARRAY_SIZE(rtq6752_reg_defaults),
216f40f9409SChiYuan Huang .volatile_reg = rtq6752_is_volatile_reg,
217f40f9409SChiYuan Huang };
218f40f9409SChiYuan Huang
rtq6752_probe(struct i2c_client * i2c)219f40f9409SChiYuan Huang static int rtq6752_probe(struct i2c_client *i2c)
220f40f9409SChiYuan Huang {
221f40f9409SChiYuan Huang struct rtq6752_priv *priv;
222f40f9409SChiYuan Huang struct regulator_config reg_cfg = {};
223f40f9409SChiYuan Huang struct regulator_dev *rdev;
224f40f9409SChiYuan Huang int i, ret;
225f40f9409SChiYuan Huang
226f40f9409SChiYuan Huang priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
227f40f9409SChiYuan Huang if (!priv)
228f40f9409SChiYuan Huang return -ENOMEM;
229f40f9409SChiYuan Huang
230f40f9409SChiYuan Huang mutex_init(&priv->lock);
231f40f9409SChiYuan Huang
232f40f9409SChiYuan Huang priv->enable_gpio = devm_gpiod_get_optional(&i2c->dev, "enable",
233f40f9409SChiYuan Huang GPIOD_OUT_HIGH);
234f40f9409SChiYuan Huang if (IS_ERR(priv->enable_gpio)) {
235f40f9409SChiYuan Huang dev_err(&i2c->dev, "Failed to get 'enable' gpio\n");
236f40f9409SChiYuan Huang return PTR_ERR(priv->enable_gpio);
237f40f9409SChiYuan Huang }
238f40f9409SChiYuan Huang
239f40f9409SChiYuan Huang usleep_range(RTQ6752_I2CRDY_TIMEUS, RTQ6752_I2CRDY_TIMEUS + 100);
240f40f9409SChiYuan Huang /* Default EN pin to high, PAVDD and NAVDD will be on */
241f40f9409SChiYuan Huang priv->enable_flag = RTQ6752_ENABLE_MASK;
242f40f9409SChiYuan Huang
243f40f9409SChiYuan Huang priv->regmap = devm_regmap_init_i2c(i2c, &rtq6752_regmap_config);
244f40f9409SChiYuan Huang if (IS_ERR(priv->regmap)) {
245f40f9409SChiYuan Huang dev_err(&i2c->dev, "Failed to init regmap\n");
246f40f9409SChiYuan Huang return PTR_ERR(priv->regmap);
247f40f9409SChiYuan Huang }
248f40f9409SChiYuan Huang
249f40f9409SChiYuan Huang ret = rtq6752_init_device_properties(priv);
250f40f9409SChiYuan Huang if (ret) {
251f40f9409SChiYuan Huang dev_err(&i2c->dev, "Failed to init device properties\n");
252f40f9409SChiYuan Huang return ret;
253f40f9409SChiYuan Huang }
254f40f9409SChiYuan Huang
255f40f9409SChiYuan Huang reg_cfg.dev = &i2c->dev;
256f40f9409SChiYuan Huang reg_cfg.regmap = priv->regmap;
257f40f9409SChiYuan Huang reg_cfg.driver_data = priv;
258f40f9409SChiYuan Huang
259f40f9409SChiYuan Huang for (i = 0; i < ARRAY_SIZE(rtq6752_regulator_descs); i++) {
260f40f9409SChiYuan Huang rdev = devm_regulator_register(&i2c->dev,
261f40f9409SChiYuan Huang rtq6752_regulator_descs + i,
262f40f9409SChiYuan Huang ®_cfg);
263f40f9409SChiYuan Huang if (IS_ERR(rdev)) {
264f40f9409SChiYuan Huang dev_err(&i2c->dev, "Failed to init %d regulator\n", i);
265f40f9409SChiYuan Huang return PTR_ERR(rdev);
266f40f9409SChiYuan Huang }
267f40f9409SChiYuan Huang }
268f40f9409SChiYuan Huang
269f40f9409SChiYuan Huang return 0;
270f40f9409SChiYuan Huang }
271f40f9409SChiYuan Huang
272f40f9409SChiYuan Huang static const struct of_device_id __maybe_unused rtq6752_device_table[] = {
273f40f9409SChiYuan Huang { .compatible = "richtek,rtq6752", },
274f40f9409SChiYuan Huang {}
275f40f9409SChiYuan Huang };
276f40f9409SChiYuan Huang MODULE_DEVICE_TABLE(of, rtq6752_device_table);
277f40f9409SChiYuan Huang
278f40f9409SChiYuan Huang static struct i2c_driver rtq6752_driver = {
279f40f9409SChiYuan Huang .driver = {
280f40f9409SChiYuan Huang .name = "rtq6752",
281*46600ab1SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
282f40f9409SChiYuan Huang .of_match_table = rtq6752_device_table,
283f40f9409SChiYuan Huang },
284f40f9409SChiYuan Huang .probe = rtq6752_probe,
285f40f9409SChiYuan Huang };
286f40f9409SChiYuan Huang module_i2c_driver(rtq6752_driver);
287f40f9409SChiYuan Huang
28877eac0e1SChiYuan Huang MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
289f40f9409SChiYuan Huang MODULE_DESCRIPTION("Richtek RTQ6752 Regulator Driver");
290f40f9409SChiYuan Huang MODULE_LICENSE("GPL v2");
291