1*fd2f02f9SAxel Lin /* SPDX-License-Identifier: GPL-2.0+ */ 21028a37dSJames Ban /* 37524c1ceSJames Ban * da9211-regulator.h - Regulator definitions for DA9211/DA9212 4707ce9eaSJames Ban * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225 57bd39354SJames Ban * Copyright (C) 2015 Dialog Semiconductor Ltd. 61028a37dSJames Ban */ 71028a37dSJames Ban 81028a37dSJames Ban #ifndef __DA9211_REGISTERS_H__ 91028a37dSJames Ban #define __DA9211_REGISTERS_H__ 101028a37dSJames Ban 111028a37dSJames Ban /* Page selection */ 121028a37dSJames Ban #define DA9211_REG_PAGE_CON 0x00 131028a37dSJames Ban 141028a37dSJames Ban /* System Control and Event Registers */ 151028a37dSJames Ban #define DA9211_REG_STATUS_A 0x50 161028a37dSJames Ban #define DA9211_REG_STATUS_B 0x51 171028a37dSJames Ban #define DA9211_REG_EVENT_A 0x52 181028a37dSJames Ban #define DA9211_REG_EVENT_B 0x53 191028a37dSJames Ban #define DA9211_REG_MASK_A 0x54 201028a37dSJames Ban #define DA9211_REG_MASK_B 0x55 211028a37dSJames Ban #define DA9211_REG_CONTROL_A 0x56 221028a37dSJames Ban 231028a37dSJames Ban /* GPIO Control Registers */ 241028a37dSJames Ban #define DA9211_REG_GPIO_0_1 0x58 251028a37dSJames Ban #define DA9211_REG_GPIO_2_3 0x59 261028a37dSJames Ban #define DA9211_REG_GPIO_4 0x5A 271028a37dSJames Ban 281028a37dSJames Ban /* Regulator Registers */ 291028a37dSJames Ban #define DA9211_REG_BUCKA_CONT 0x5D 301028a37dSJames Ban #define DA9211_REG_BUCKB_CONT 0x5E 311028a37dSJames Ban #define DA9211_REG_BUCK_ILIM 0xD0 321028a37dSJames Ban #define DA9211_REG_BUCKA_CONF 0xD1 331028a37dSJames Ban #define DA9211_REG_BUCKB_CONF 0xD2 341028a37dSJames Ban #define DA9211_REG_BUCK_CONF 0xD3 351028a37dSJames Ban #define DA9211_REG_VBACKA_MAX 0xD5 361028a37dSJames Ban #define DA9211_REG_VBACKB_MAX 0xD6 371028a37dSJames Ban #define DA9211_REG_VBUCKA_A 0xD7 381028a37dSJames Ban #define DA9211_REG_VBUCKA_B 0xD8 391028a37dSJames Ban #define DA9211_REG_VBUCKB_A 0xD9 401028a37dSJames Ban #define DA9211_REG_VBUCKB_B 0xDA 411028a37dSJames Ban 421028a37dSJames Ban /* I2C Interface Settings */ 431028a37dSJames Ban #define DA9211_REG_INTERFACE 0x105 441028a37dSJames Ban 451028a37dSJames Ban /* BUCK Phase Selection*/ 461028a37dSJames Ban #define DA9211_REG_CONFIG_E 0x147 471028a37dSJames Ban 48005547e0SJames Ban /* Device ID */ 49005547e0SJames Ban #define DA9211_REG_DEVICE_ID 0x201 50005547e0SJames Ban 511028a37dSJames Ban /* 521028a37dSJames Ban * Registers bits 531028a37dSJames Ban */ 541028a37dSJames Ban /* DA9211_REG_PAGE_CON (addr=0x00) */ 551028a37dSJames Ban #define DA9211_REG_PAGE_SHIFT 1 56005547e0SJames Ban #define DA9211_REG_PAGE_MASK 0x06 571028a37dSJames Ban /* On I2C registers 0x00 - 0xFF */ 581028a37dSJames Ban #define DA9211_REG_PAGE0 0 591028a37dSJames Ban /* On I2C registers 0x100 - 0x1FF */ 601028a37dSJames Ban #define DA9211_REG_PAGE2 2 611028a37dSJames Ban #define DA9211_PAGE_WRITE_MODE 0x00 621028a37dSJames Ban #define DA9211_REPEAT_WRITE_MODE 0x40 631028a37dSJames Ban #define DA9211_PAGE_REVERT 0x80 641028a37dSJames Ban 651028a37dSJames Ban /* DA9211_REG_STATUS_A (addr=0x50) */ 661028a37dSJames Ban #define DA9211_GPI0 0x01 671028a37dSJames Ban #define DA9211_GPI1 0x02 681028a37dSJames Ban #define DA9211_GPI2 0x04 691028a37dSJames Ban #define DA9211_GPI3 0x08 701028a37dSJames Ban #define DA9211_GPI4 0x10 711028a37dSJames Ban 721028a37dSJames Ban /* DA9211_REG_EVENT_A (addr=0x52) */ 731028a37dSJames Ban #define DA9211_E_GPI0 0x01 741028a37dSJames Ban #define DA9211_E_GPI1 0x02 751028a37dSJames Ban #define DA9211_E_GPI2 0x04 761028a37dSJames Ban #define DA9211_E_GPI3 0x08 771028a37dSJames Ban #define DA9211_E_GPI4 0x10 781028a37dSJames Ban #define DA9211_E_UVLO_IO 0x40 791028a37dSJames Ban 801028a37dSJames Ban /* DA9211_REG_EVENT_B (addr=0x53) */ 811028a37dSJames Ban #define DA9211_E_PWRGOOD_A 0x01 821028a37dSJames Ban #define DA9211_E_PWRGOOD_B 0x02 831028a37dSJames Ban #define DA9211_E_TEMP_WARN 0x04 841028a37dSJames Ban #define DA9211_E_TEMP_CRIT 0x08 851028a37dSJames Ban #define DA9211_E_OV_CURR_A 0x10 861028a37dSJames Ban #define DA9211_E_OV_CURR_B 0x20 871028a37dSJames Ban 881028a37dSJames Ban /* DA9211_REG_MASK_A (addr=0x54) */ 891028a37dSJames Ban #define DA9211_M_GPI0 0x01 901028a37dSJames Ban #define DA9211_M_GPI1 0x02 911028a37dSJames Ban #define DA9211_M_GPI2 0x04 921028a37dSJames Ban #define DA9211_M_GPI3 0x08 931028a37dSJames Ban #define DA9211_M_GPI4 0x10 941028a37dSJames Ban #define DA9211_M_UVLO_IO 0x40 951028a37dSJames Ban 961028a37dSJames Ban /* DA9211_REG_MASK_B (addr=0x55) */ 971028a37dSJames Ban #define DA9211_M_PWRGOOD_A 0x01 981028a37dSJames Ban #define DA9211_M_PWRGOOD_B 0x02 991028a37dSJames Ban #define DA9211_M_TEMP_WARN 0x04 1001028a37dSJames Ban #define DA9211_M_TEMP_CRIT 0x08 1011028a37dSJames Ban #define DA9211_M_OV_CURR_A 0x10 1021028a37dSJames Ban #define DA9211_M_OV_CURR_B 0x20 1031028a37dSJames Ban 1041028a37dSJames Ban /* DA9211_REG_CONTROL_A (addr=0x56) */ 1051028a37dSJames Ban #define DA9211_DEBOUNCING_SHIFT 0 1061028a37dSJames Ban #define DA9211_DEBOUNCING_MASK 0x07 1071028a37dSJames Ban #define DA9211_SLEW_RATE_SHIFT 3 1081028a37dSJames Ban #define DA9211_SLEW_RATE_A_MASK 0x18 1091028a37dSJames Ban #define DA9211_SLEW_RATE_B_SHIFT 5 1101028a37dSJames Ban #define DA9211_SLEW_RATE_B_MASK 0x60 1111028a37dSJames Ban #define DA9211_V_LOCK 0x80 1121028a37dSJames Ban 1131028a37dSJames Ban /* DA9211_REG_GPIO_0_1 (addr=0x58) */ 1141028a37dSJames Ban #define DA9211_GPIO0_PIN_SHIFT 0 1151028a37dSJames Ban #define DA9211_GPIO0_PIN_MASK 0x03 1161028a37dSJames Ban #define DA9211_GPIO0_PIN_GPI 0x00 1171028a37dSJames Ban #define DA9211_GPIO0_PIN_GPO_OD 0x02 1181028a37dSJames Ban #define DA9211_GPIO0_PIN_GPO 0x03 1191028a37dSJames Ban #define DA9211_GPIO0_TYPE 0x04 1201028a37dSJames Ban #define DA9211_GPIO0_TYPE_GPI 0x00 1211028a37dSJames Ban #define DA9211_GPIO0_TYPE_GPO 0x04 1221028a37dSJames Ban #define DA9211_GPIO0_MODE 0x08 1231028a37dSJames Ban #define DA9211_GPIO1_PIN_SHIFT 4 1241028a37dSJames Ban #define DA9211_GPIO1_PIN_MASK 0x30 1251028a37dSJames Ban #define DA9211_GPIO1_PIN_GPI 0x00 1261028a37dSJames Ban #define DA9211_GPIO1_PIN_VERROR 0x10 1271028a37dSJames Ban #define DA9211_GPIO1_PIN_GPO_OD 0x20 1281028a37dSJames Ban #define DA9211_GPIO1_PIN_GPO 0x30 1291028a37dSJames Ban #define DA9211_GPIO1_TYPE_SHIFT 0x40 1301028a37dSJames Ban #define DA9211_GPIO1_TYPE_GPI 0x00 1311028a37dSJames Ban #define DA9211_GPIO1_TYPE_GPO 0x40 1321028a37dSJames Ban #define DA9211_GPIO1_MODE 0x80 1331028a37dSJames Ban 1341028a37dSJames Ban /* DA9211_REG_GPIO_2_3 (addr=0x59) */ 1351028a37dSJames Ban #define DA9211_GPIO2_PIN_SHIFT 0 1361028a37dSJames Ban #define DA9211_GPIO2_PIN_MASK 0x03 1371028a37dSJames Ban #define DA9211_GPIO2_PIN_GPI 0x00 1381028a37dSJames Ban #define DA9211_GPIO5_PIN_BUCK_CLK 0x10 1391028a37dSJames Ban #define DA9211_GPIO2_PIN_GPO_OD 0x02 1401028a37dSJames Ban #define DA9211_GPIO2_PIN_GPO 0x03 1411028a37dSJames Ban #define DA9211_GPIO2_TYPE 0x04 1421028a37dSJames Ban #define DA9211_GPIO2_TYPE_GPI 0x00 1431028a37dSJames Ban #define DA9211_GPIO2_TYPE_GPO 0x04 1441028a37dSJames Ban #define DA9211_GPIO2_MODE 0x08 1451028a37dSJames Ban #define DA9211_GPIO3_PIN_SHIFT 4 1461028a37dSJames Ban #define DA9211_GPIO3_PIN_MASK 0x30 1471028a37dSJames Ban #define DA9211_GPIO3_PIN_GPI 0x00 1481028a37dSJames Ban #define DA9211_GPIO3_PIN_IERROR 0x10 1491028a37dSJames Ban #define DA9211_GPIO3_PIN_GPO_OD 0x20 1501028a37dSJames Ban #define DA9211_GPIO3_PIN_GPO 0x30 1511028a37dSJames Ban #define DA9211_GPIO3_TYPE_SHIFT 0x40 1521028a37dSJames Ban #define DA9211_GPIO3_TYPE_GPI 0x00 1531028a37dSJames Ban #define DA9211_GPIO3_TYPE_GPO 0x40 1541028a37dSJames Ban #define DA9211_GPIO3_MODE 0x80 1551028a37dSJames Ban 1561028a37dSJames Ban /* DA9211_REG_GPIO_4 (addr=0x5A) */ 1571028a37dSJames Ban #define DA9211_GPIO4_PIN_SHIFT 0 1581028a37dSJames Ban #define DA9211_GPIO4_PIN_MASK 0x03 1591028a37dSJames Ban #define DA9211_GPIO4_PIN_GPI 0x00 1601028a37dSJames Ban #define DA9211_GPIO4_PIN_GPO_OD 0x02 1611028a37dSJames Ban #define DA9211_GPIO4_PIN_GPO 0x03 1621028a37dSJames Ban #define DA9211_GPIO4_TYPE 0x04 1631028a37dSJames Ban #define DA9211_GPIO4_TYPE_GPI 0x00 1641028a37dSJames Ban #define DA9211_GPIO4_TYPE_GPO 0x04 1651028a37dSJames Ban #define DA9211_GPIO4_MODE 0x08 1661028a37dSJames Ban 1671028a37dSJames Ban /* DA9211_REG_BUCKA_CONT (addr=0x5D) */ 1681028a37dSJames Ban #define DA9211_BUCKA_EN 0x01 1691028a37dSJames Ban #define DA9211_BUCKA_GPI_SHIFT 1 1701028a37dSJames Ban #define DA9211_BUCKA_GPI_MASK 0x06 1711028a37dSJames Ban #define DA9211_BUCKA_GPI_OFF 0x00 1721028a37dSJames Ban #define DA9211_BUCKA_GPI_GPIO0 0x02 1731028a37dSJames Ban #define DA9211_BUCKA_GPI_GPIO1 0x04 1741028a37dSJames Ban #define DA9211_BUCKA_GPI_GPIO3 0x06 1751028a37dSJames Ban #define DA9211_BUCKA_PD_DIS 0x08 1761028a37dSJames Ban #define DA9211_VBUCKA_SEL 0x10 1771028a37dSJames Ban #define DA9211_VBUCKA_SEL_A 0x00 1781028a37dSJames Ban #define DA9211_VBUCKA_SEL_B 0x10 1791028a37dSJames Ban #define DA9211_VBUCKA_GPI_SHIFT 5 1801028a37dSJames Ban #define DA9211_VBUCKA_GPI_MASK 0x60 1811028a37dSJames Ban #define DA9211_VBUCKA_GPI_OFF 0x00 1821028a37dSJames Ban #define DA9211_VBUCKA_GPI_GPIO1 0x20 1831028a37dSJames Ban #define DA9211_VBUCKA_GPI_GPIO2 0x40 1841028a37dSJames Ban #define DA9211_VBUCKA_GPI_GPIO4 0x60 1851028a37dSJames Ban 1861028a37dSJames Ban /* DA9211_REG_BUCKB_CONT (addr=0x5E) */ 1871028a37dSJames Ban #define DA9211_BUCKB_EN 0x01 1881028a37dSJames Ban #define DA9211_BUCKB_GPI_SHIFT 1 1891028a37dSJames Ban #define DA9211_BUCKB_GPI_MASK 0x06 1901028a37dSJames Ban #define DA9211_BUCKB_GPI_OFF 0x00 1911028a37dSJames Ban #define DA9211_BUCKB_GPI_GPIO0 0x02 1921028a37dSJames Ban #define DA9211_BUCKB_GPI_GPIO1 0x04 1931028a37dSJames Ban #define DA9211_BUCKB_GPI_GPIO3 0x06 1941028a37dSJames Ban #define DA9211_BUCKB_PD_DIS 0x08 1951028a37dSJames Ban #define DA9211_VBUCKB_SEL 0x10 1961028a37dSJames Ban #define DA9211_VBUCKB_SEL_A 0x00 1971028a37dSJames Ban #define DA9211_VBUCKB_SEL_B 0x10 1981028a37dSJames Ban #define DA9211_VBUCKB_GPI_SHIFT 5 1991028a37dSJames Ban #define DA9211_VBUCKB_GPI_MASK 0x60 2001028a37dSJames Ban #define DA9211_VBUCKB_GPI_OFF 0x00 2011028a37dSJames Ban #define DA9211_VBUCKB_GPI_GPIO1 0x20 2021028a37dSJames Ban #define DA9211_VBUCKB_GPI_GPIO2 0x40 2031028a37dSJames Ban #define DA9211_VBUCKB_GPI_GPIO4 0x60 2041028a37dSJames Ban 2051028a37dSJames Ban /* DA9211_REG_BUCK_ILIM (addr=0xD0) */ 2061028a37dSJames Ban #define DA9211_BUCKA_ILIM_SHIFT 0 2071028a37dSJames Ban #define DA9211_BUCKA_ILIM_MASK 0x0F 2081028a37dSJames Ban #define DA9211_BUCKB_ILIM_SHIFT 4 2091028a37dSJames Ban #define DA9211_BUCKB_ILIM_MASK 0xF0 2101028a37dSJames Ban 2111028a37dSJames Ban /* DA9211_REG_BUCKA_CONF (addr=0xD1) */ 2121028a37dSJames Ban #define DA9211_BUCKA_MODE_SHIFT 0 2131028a37dSJames Ban #define DA9211_BUCKA_MODE_MASK 0x03 2141028a37dSJames Ban #define DA9211_BUCKA_MODE_MANUAL 0x00 2151028a37dSJames Ban #define DA9211_BUCKA_MODE_SLEEP 0x01 2161028a37dSJames Ban #define DA9211_BUCKA_MODE_SYNC 0x02 2171028a37dSJames Ban #define DA9211_BUCKA_MODE_AUTO 0x03 2181028a37dSJames Ban #define DA9211_BUCKA_UP_CTRL_SHIFT 2 2191028a37dSJames Ban #define DA9211_BUCKA_UP_CTRL_MASK 0x1C 2201028a37dSJames Ban #define DA9211_BUCKA_DOWN_CTRL_SHIFT 5 2211028a37dSJames Ban #define DA9211_BUCKA_DOWN_CTRL_MASK 0xE0 2221028a37dSJames Ban 2231028a37dSJames Ban /* DA9211_REG_BUCKB_CONF (addr=0xD2) */ 2241028a37dSJames Ban #define DA9211_BUCKB_MODE_SHIFT 0 2251028a37dSJames Ban #define DA9211_BUCKB_MODE_MASK 0x03 2261028a37dSJames Ban #define DA9211_BUCKB_MODE_MANUAL 0x00 2271028a37dSJames Ban #define DA9211_BUCKB_MODE_SLEEP 0x01 2281028a37dSJames Ban #define DA9211_BUCKB_MODE_SYNC 0x02 2291028a37dSJames Ban #define DA9211_BUCKB_MODE_AUTO 0x03 2301028a37dSJames Ban #define DA9211_BUCKB_UP_CTRL_SHIFT 2 2311028a37dSJames Ban #define DA9211_BUCKB_UP_CTRL_MASK 0x1C 2321028a37dSJames Ban #define DA9211_BUCKB_DOWN_CTRL_SHIFT 5 2331028a37dSJames Ban #define DA9211_BUCKB_DOWN_CTRL_MASK 0xE0 2341028a37dSJames Ban 2351028a37dSJames Ban /* DA9211_REG_BUCK_CONF (addr=0xD3) */ 2361028a37dSJames Ban #define DA9211_PHASE_SEL_A_SHIFT 0 2371028a37dSJames Ban #define DA9211_PHASE_SEL_A_MASK 0x03 2381028a37dSJames Ban #define DA9211_PHASE_SEL_B_SHIFT 2 2391028a37dSJames Ban #define DA9211_PHASE_SEL_B_MASK 0x04 2401028a37dSJames Ban #define DA9211_PH_SH_EN_A_SHIFT 3 2411028a37dSJames Ban #define DA9211_PH_SH_EN_A_MASK 0x08 2421028a37dSJames Ban #define DA9211_PH_SH_EN_B_SHIFT 4 2431028a37dSJames Ban #define DA9211_PH_SH_EN_B_MASK 0x10 2441028a37dSJames Ban 2451028a37dSJames Ban /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */ 2461028a37dSJames Ban #define DA9211_VBUCKA_BASE_SHIFT 0 2471028a37dSJames Ban #define DA9211_VBUCKA_BASE_MASK 0x7F 2481028a37dSJames Ban 2491028a37dSJames Ban /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */ 2501028a37dSJames Ban #define DA9211_VBUCKB_BASE_SHIFT 0 2511028a37dSJames Ban #define DA9211_VBUCKB_BASE_MASK 0x7F 2521028a37dSJames Ban 2531028a37dSJames Ban /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */ 2541028a37dSJames Ban #define DA9211_VBUCK_SHIFT 0 2551028a37dSJames Ban #define DA9211_VBUCK_MASK 0x7F 2561028a37dSJames Ban #define DA9211_VBUCK_BIAS 0 2571028a37dSJames Ban #define DA9211_BUCK_SL 0x80 2581028a37dSJames Ban 2591028a37dSJames Ban /* DA9211_REG_INTERFACE (addr=0x105) */ 2601028a37dSJames Ban #define DA9211_IF_BASE_ADDR_SHIFT 4 2611028a37dSJames Ban #define DA9211_IF_BASE_ADDR_MASK 0xF0 2621028a37dSJames Ban 2631028a37dSJames Ban /* DA9211_REG_CONFIG_E (addr=0x147) */ 2641028a37dSJames Ban #define DA9211_SLAVE_SEL 0x40 2651028a37dSJames Ban 2661028a37dSJames Ban #endif /* __DA9211_REGISTERS_H__ */ 267