1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2020 Facebook */ 3 4 #include <linux/err.h> 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/debugfs.h> 8 #include <linux/init.h> 9 #include <linux/pci.h> 10 #include <linux/serial_8250.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk-provider.h> 13 #include <linux/platform_device.h> 14 #include <linux/ptp_clock_kernel.h> 15 #include <linux/spi/spi.h> 16 #include <linux/spi/xilinx_spi.h> 17 #include <net/devlink.h> 18 #include <linux/i2c.h> 19 #include <linux/mtd/mtd.h> 20 21 #ifndef PCI_VENDOR_ID_FACEBOOK 22 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b 23 #endif 24 25 #ifndef PCI_DEVICE_ID_FACEBOOK_TIMECARD 26 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400 27 #endif 28 29 static struct class timecard_class = { 30 .owner = THIS_MODULE, 31 .name = "timecard", 32 }; 33 34 struct ocp_reg { 35 u32 ctrl; 36 u32 status; 37 u32 select; 38 u32 version; 39 u32 time_ns; 40 u32 time_sec; 41 u32 __pad0[2]; 42 u32 adjust_ns; 43 u32 adjust_sec; 44 u32 __pad1[2]; 45 u32 offset_ns; 46 u32 offset_window_ns; 47 u32 __pad2[2]; 48 u32 drift_ns; 49 u32 drift_window_ns; 50 u32 __pad3[6]; 51 u32 servo_offset_p; 52 u32 servo_offset_i; 53 u32 servo_drift_p; 54 u32 servo_drift_i; 55 }; 56 57 #define OCP_CTRL_ENABLE BIT(0) 58 #define OCP_CTRL_ADJUST_TIME BIT(1) 59 #define OCP_CTRL_ADJUST_OFFSET BIT(2) 60 #define OCP_CTRL_ADJUST_DRIFT BIT(3) 61 #define OCP_CTRL_ADJUST_SERVO BIT(8) 62 #define OCP_CTRL_READ_TIME_REQ BIT(30) 63 #define OCP_CTRL_READ_TIME_DONE BIT(31) 64 65 #define OCP_STATUS_IN_SYNC BIT(0) 66 #define OCP_STATUS_IN_HOLDOVER BIT(1) 67 68 #define OCP_SELECT_CLK_NONE 0 69 #define OCP_SELECT_CLK_REG 0xfe 70 71 struct tod_reg { 72 u32 ctrl; 73 u32 status; 74 u32 uart_polarity; 75 u32 version; 76 u32 adj_sec; 77 u32 __pad0[3]; 78 u32 uart_baud; 79 u32 __pad1[3]; 80 u32 utc_status; 81 u32 leap; 82 }; 83 84 #define TOD_CTRL_PROTOCOL BIT(28) 85 #define TOD_CTRL_DISABLE_FMT_A BIT(17) 86 #define TOD_CTRL_DISABLE_FMT_B BIT(16) 87 #define TOD_CTRL_ENABLE BIT(0) 88 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1) 89 #define TOD_CTRL_GNSS_SHIFT 24 90 91 #define TOD_STATUS_UTC_MASK 0xff 92 #define TOD_STATUS_UTC_VALID BIT(8) 93 #define TOD_STATUS_LEAP_VALID BIT(16) 94 95 struct ts_reg { 96 u32 enable; 97 u32 error; 98 u32 polarity; 99 u32 version; 100 u32 __pad0[4]; 101 u32 cable_delay; 102 u32 __pad1[3]; 103 u32 intr; 104 u32 intr_mask; 105 u32 event_count; 106 u32 __pad2[1]; 107 u32 ts_count; 108 u32 time_ns; 109 u32 time_sec; 110 u32 data_width; 111 u32 data; 112 }; 113 114 struct pps_reg { 115 u32 ctrl; 116 u32 status; 117 u32 __pad0[6]; 118 u32 cable_delay; 119 }; 120 121 #define PPS_STATUS_FILTER_ERR BIT(0) 122 #define PPS_STATUS_SUPERV_ERR BIT(1) 123 124 struct img_reg { 125 u32 version; 126 }; 127 128 struct gpio_reg { 129 u32 gpio1; 130 u32 __pad0; 131 u32 gpio2; 132 u32 __pad1; 133 }; 134 135 struct irig_master_reg { 136 u32 ctrl; 137 u32 status; 138 u32 __pad0; 139 u32 version; 140 u32 adj_sec; 141 u32 mode_ctrl; 142 }; 143 144 #define IRIG_M_CTRL_ENABLE BIT(0) 145 146 struct irig_slave_reg { 147 u32 ctrl; 148 u32 status; 149 u32 __pad0; 150 u32 version; 151 u32 adj_sec; 152 u32 mode_ctrl; 153 }; 154 155 #define IRIG_S_CTRL_ENABLE BIT(0) 156 157 struct dcf_master_reg { 158 u32 ctrl; 159 u32 status; 160 u32 __pad0; 161 u32 version; 162 u32 adj_sec; 163 }; 164 165 #define DCF_M_CTRL_ENABLE BIT(0) 166 167 struct dcf_slave_reg { 168 u32 ctrl; 169 u32 status; 170 u32 __pad0; 171 u32 version; 172 u32 adj_sec; 173 }; 174 175 #define DCF_S_CTRL_ENABLE BIT(0) 176 177 struct ptp_ocp_flash_info { 178 const char *name; 179 int pci_offset; 180 int data_size; 181 void *data; 182 }; 183 184 struct ptp_ocp_i2c_info { 185 const char *name; 186 unsigned long fixed_rate; 187 size_t data_size; 188 void *data; 189 }; 190 191 struct ptp_ocp_ext_info { 192 int index; 193 irqreturn_t (*irq_fcn)(int irq, void *priv); 194 int (*enable)(void *priv, u32 req, bool enable); 195 }; 196 197 struct ptp_ocp_ext_src { 198 void __iomem *mem; 199 struct ptp_ocp *bp; 200 struct ptp_ocp_ext_info *info; 201 int irq_vec; 202 }; 203 204 struct ptp_ocp { 205 struct pci_dev *pdev; 206 struct device dev; 207 spinlock_t lock; 208 struct ocp_reg __iomem *reg; 209 struct tod_reg __iomem *tod; 210 struct pps_reg __iomem *pps_to_ext; 211 struct pps_reg __iomem *pps_to_clk; 212 struct gpio_reg __iomem *pps_select; 213 struct gpio_reg __iomem *sma; 214 struct irig_master_reg __iomem *irig_out; 215 struct irig_slave_reg __iomem *irig_in; 216 struct dcf_master_reg __iomem *dcf_out; 217 struct dcf_slave_reg __iomem *dcf_in; 218 struct tod_reg __iomem *nmea_out; 219 struct ptp_ocp_ext_src *pps; 220 struct ptp_ocp_ext_src *ts0; 221 struct ptp_ocp_ext_src *ts1; 222 struct ptp_ocp_ext_src *ts2; 223 struct img_reg __iomem *image; 224 struct ptp_clock *ptp; 225 struct ptp_clock_info ptp_info; 226 struct platform_device *i2c_ctrl; 227 struct platform_device *spi_flash; 228 struct clk_hw *i2c_clk; 229 struct timer_list watchdog; 230 struct dentry *debug_root; 231 time64_t gnss_lost; 232 int id; 233 int n_irqs; 234 int gnss_port; 235 int gnss2_port; 236 int mac_port; /* miniature atomic clock */ 237 int nmea_port; 238 u8 serial[6]; 239 bool has_serial; 240 u32 pps_req_map; 241 int flash_start; 242 u32 utc_tai_offset; 243 }; 244 245 #define OCP_REQ_TIMESTAMP BIT(0) 246 #define OCP_REQ_PPS BIT(1) 247 248 struct ocp_resource { 249 unsigned long offset; 250 int size; 251 int irq_vec; 252 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); 253 void *extra; 254 unsigned long bp_offset; 255 const char * const name; 256 }; 257 258 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); 259 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); 260 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); 261 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); 262 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); 263 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 264 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); 265 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable); 266 267 #define bp_assign_entry(bp, res, val) ({ \ 268 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ 269 *(typeof(val) *)addr = val; \ 270 }) 271 272 #define OCP_RES_LOCATION(member) \ 273 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member) 274 275 #define OCP_MEM_RESOURCE(member) \ 276 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem 277 278 #define OCP_SERIAL_RESOURCE(member) \ 279 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial 280 281 #define OCP_I2C_RESOURCE(member) \ 282 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c 283 284 #define OCP_SPI_RESOURCE(member) \ 285 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi 286 287 #define OCP_EXT_RESOURCE(member) \ 288 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext 289 290 /* This is the MSI vector mapping used. 291 * 0: TS3 (and PPS) 292 * 1: TS0 293 * 2: TS1 294 * 3: GNSS 295 * 4: GNSS2 296 * 5: MAC 297 * 6: TS2 298 * 7: I2C controller 299 * 8: HWICAP (notused) 300 * 9: SPI Flash 301 * 10: NMEA 302 */ 303 304 static struct ocp_resource ocp_fb_resource[] = { 305 { 306 OCP_MEM_RESOURCE(reg), 307 .offset = 0x01000000, .size = 0x10000, 308 }, 309 { 310 OCP_EXT_RESOURCE(ts0), 311 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 312 .extra = &(struct ptp_ocp_ext_info) { 313 .index = 0, 314 .irq_fcn = ptp_ocp_ts_irq, 315 .enable = ptp_ocp_ts_enable, 316 }, 317 }, 318 { 319 OCP_EXT_RESOURCE(ts1), 320 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 321 .extra = &(struct ptp_ocp_ext_info) { 322 .index = 1, 323 .irq_fcn = ptp_ocp_ts_irq, 324 .enable = ptp_ocp_ts_enable, 325 }, 326 }, 327 { 328 OCP_EXT_RESOURCE(ts2), 329 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6, 330 .extra = &(struct ptp_ocp_ext_info) { 331 .index = 2, 332 .irq_fcn = ptp_ocp_ts_irq, 333 .enable = ptp_ocp_ts_enable, 334 }, 335 }, 336 { 337 OCP_EXT_RESOURCE(pps), 338 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0, 339 .extra = &(struct ptp_ocp_ext_info) { 340 .index = 3, 341 .irq_fcn = ptp_ocp_ts_irq, 342 .enable = ptp_ocp_ts_enable, 343 }, 344 }, 345 { 346 OCP_MEM_RESOURCE(pps_to_ext), 347 .offset = 0x01030000, .size = 0x10000, 348 }, 349 { 350 OCP_MEM_RESOURCE(pps_to_clk), 351 .offset = 0x01040000, .size = 0x10000, 352 }, 353 { 354 OCP_MEM_RESOURCE(tod), 355 .offset = 0x01050000, .size = 0x10000, 356 }, 357 { 358 OCP_MEM_RESOURCE(irig_in), 359 .offset = 0x01070000, .size = 0x10000, 360 }, 361 { 362 OCP_MEM_RESOURCE(irig_out), 363 .offset = 0x01080000, .size = 0x10000, 364 }, 365 { 366 OCP_MEM_RESOURCE(dcf_in), 367 .offset = 0x01090000, .size = 0x10000, 368 }, 369 { 370 OCP_MEM_RESOURCE(dcf_out), 371 .offset = 0x010A0000, .size = 0x10000, 372 }, 373 { 374 OCP_MEM_RESOURCE(nmea_out), 375 .offset = 0x010B0000, .size = 0x10000, 376 }, 377 { 378 OCP_MEM_RESOURCE(image), 379 .offset = 0x00020000, .size = 0x1000, 380 }, 381 { 382 OCP_MEM_RESOURCE(pps_select), 383 .offset = 0x00130000, .size = 0x1000, 384 }, 385 { 386 OCP_MEM_RESOURCE(sma), 387 .offset = 0x00140000, .size = 0x1000, 388 }, 389 { 390 OCP_I2C_RESOURCE(i2c_ctrl), 391 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, 392 .extra = &(struct ptp_ocp_i2c_info) { 393 .name = "xiic-i2c", 394 .fixed_rate = 50000000, 395 }, 396 }, 397 { 398 OCP_SERIAL_RESOURCE(gnss_port), 399 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 400 }, 401 { 402 OCP_SERIAL_RESOURCE(gnss2_port), 403 .offset = 0x00170000 + 0x1000, .irq_vec = 4, 404 }, 405 { 406 OCP_SERIAL_RESOURCE(mac_port), 407 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 408 }, 409 { 410 OCP_SERIAL_RESOURCE(nmea_port), 411 .offset = 0x00190000 + 0x1000, .irq_vec = 10, 412 }, 413 { 414 OCP_SPI_RESOURCE(spi_flash), 415 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 416 .extra = &(struct ptp_ocp_flash_info) { 417 .name = "xilinx_spi", .pci_offset = 0, 418 .data_size = sizeof(struct xspi_platform_data), 419 .data = &(struct xspi_platform_data) { 420 .num_chipselect = 1, 421 .bits_per_word = 8, 422 .num_devices = 1, 423 .devices = &(struct spi_board_info) { 424 .modalias = "spi-nor", 425 }, 426 }, 427 }, 428 }, 429 { 430 .setup = ptp_ocp_fb_board_init, 431 }, 432 { } 433 }; 434 435 static const struct pci_device_id ptp_ocp_pcidev_id[] = { 436 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) }, 437 { 0 } 438 }; 439 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); 440 441 static DEFINE_MUTEX(ptp_ocp_lock); 442 static DEFINE_IDR(ptp_ocp_idr); 443 444 struct ocp_selector { 445 const char *name; 446 int value; 447 }; 448 449 static struct ocp_selector ptp_ocp_clock[] = { 450 { .name = "NONE", .value = 0 }, 451 { .name = "TOD", .value = 1 }, 452 { .name = "IRIG", .value = 2 }, 453 { .name = "PPS", .value = 3 }, 454 { .name = "PTP", .value = 4 }, 455 { .name = "RTC", .value = 5 }, 456 { .name = "DCF", .value = 6 }, 457 { .name = "REGS", .value = 0xfe }, 458 { .name = "EXT", .value = 0xff }, 459 { } 460 }; 461 462 static struct ocp_selector ptp_ocp_sma_in[] = { 463 { .name = "10Mhz", .value = 0x00 }, 464 { .name = "PPS1", .value = 0x01 }, 465 { .name = "PPS2", .value = 0x02 }, 466 { .name = "TS1", .value = 0x04 }, 467 { .name = "TS2", .value = 0x08 }, 468 { .name = "IRIG", .value = 0x10 }, 469 { .name = "DCF", .value = 0x20 }, 470 { } 471 }; 472 473 static struct ocp_selector ptp_ocp_sma_out[] = { 474 { .name = "10Mhz", .value = 0x00 }, 475 { .name = "PHC", .value = 0x01 }, 476 { .name = "MAC", .value = 0x02 }, 477 { .name = "GNSS", .value = 0x04 }, 478 { .name = "GNSS2", .value = 0x08 }, 479 { .name = "IRIG", .value = 0x10 }, 480 { .name = "DCF", .value = 0x20 }, 481 { } 482 }; 483 484 static const char * 485 ptp_ocp_select_name_from_val(struct ocp_selector *tbl, int val) 486 { 487 int i; 488 489 for (i = 0; tbl[i].name; i++) 490 if (tbl[i].value == val) 491 return tbl[i].name; 492 return NULL; 493 } 494 495 static int 496 ptp_ocp_select_val_from_name(struct ocp_selector *tbl, const char *name) 497 { 498 const char *select; 499 int i; 500 501 for (i = 0; tbl[i].name; i++) { 502 select = tbl[i].name; 503 if (!strncasecmp(name, select, strlen(select))) 504 return tbl[i].value; 505 } 506 return -EINVAL; 507 } 508 509 static ssize_t 510 ptp_ocp_select_table_show(struct ocp_selector *tbl, char *buf) 511 { 512 ssize_t count; 513 int i; 514 515 count = 0; 516 for (i = 0; tbl[i].name; i++) 517 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name); 518 if (count) 519 count--; 520 count += sysfs_emit_at(buf, count, "\n"); 521 return count; 522 } 523 524 static int 525 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, 526 struct ptp_system_timestamp *sts) 527 { 528 u32 ctrl, time_sec, time_ns; 529 int i; 530 531 ctrl = ioread32(&bp->reg->ctrl); 532 ctrl |= OCP_CTRL_READ_TIME_REQ; 533 534 ptp_read_system_prets(sts); 535 iowrite32(ctrl, &bp->reg->ctrl); 536 537 for (i = 0; i < 100; i++) { 538 ctrl = ioread32(&bp->reg->ctrl); 539 if (ctrl & OCP_CTRL_READ_TIME_DONE) 540 break; 541 } 542 ptp_read_system_postts(sts); 543 544 time_ns = ioread32(&bp->reg->time_ns); 545 time_sec = ioread32(&bp->reg->time_sec); 546 547 ts->tv_sec = time_sec; 548 ts->tv_nsec = time_ns; 549 550 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; 551 } 552 553 static int 554 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, 555 struct ptp_system_timestamp *sts) 556 { 557 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 558 unsigned long flags; 559 int err; 560 561 spin_lock_irqsave(&bp->lock, flags); 562 err = __ptp_ocp_gettime_locked(bp, ts, sts); 563 spin_unlock_irqrestore(&bp->lock, flags); 564 565 return err; 566 } 567 568 static void 569 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) 570 { 571 u32 ctrl, time_sec, time_ns; 572 u32 select; 573 574 time_ns = ts->tv_nsec; 575 time_sec = ts->tv_sec; 576 577 select = ioread32(&bp->reg->select); 578 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 579 580 iowrite32(time_ns, &bp->reg->adjust_ns); 581 iowrite32(time_sec, &bp->reg->adjust_sec); 582 583 ctrl = ioread32(&bp->reg->ctrl); 584 ctrl |= OCP_CTRL_ADJUST_TIME; 585 iowrite32(ctrl, &bp->reg->ctrl); 586 587 /* restore clock selection */ 588 iowrite32(select >> 16, &bp->reg->select); 589 } 590 591 static int 592 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) 593 { 594 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 595 unsigned long flags; 596 597 spin_lock_irqsave(&bp->lock, flags); 598 __ptp_ocp_settime_locked(bp, ts); 599 spin_unlock_irqrestore(&bp->lock, flags); 600 601 return 0; 602 } 603 604 static void 605 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u64 adj_val) 606 { 607 u32 select, ctrl; 608 609 select = ioread32(&bp->reg->select); 610 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 611 612 iowrite32(adj_val, &bp->reg->offset_ns); 613 iowrite32(adj_val & 0x7f, &bp->reg->offset_window_ns); 614 615 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE; 616 iowrite32(ctrl, &bp->reg->ctrl); 617 618 /* restore clock selection */ 619 iowrite32(select >> 16, &bp->reg->select); 620 } 621 622 static int 623 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) 624 { 625 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 626 unsigned long flags; 627 u32 adj_ns, sign; 628 629 sign = delta_ns < 0 ? BIT(31) : 0; 630 adj_ns = sign ? -delta_ns : delta_ns; 631 632 spin_lock_irqsave(&bp->lock, flags); 633 __ptp_ocp_adjtime_locked(bp, sign | adj_ns); 634 spin_unlock_irqrestore(&bp->lock, flags); 635 636 return 0; 637 } 638 639 static int 640 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 641 { 642 if (scaled_ppm == 0) 643 return 0; 644 645 return -EOPNOTSUPP; 646 } 647 648 static int 649 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) 650 { 651 return -EOPNOTSUPP; 652 } 653 654 static int 655 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, 656 int on) 657 { 658 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 659 struct ptp_ocp_ext_src *ext = NULL; 660 u32 req; 661 int err; 662 663 switch (rq->type) { 664 case PTP_CLK_REQ_EXTTS: 665 req = OCP_REQ_TIMESTAMP; 666 switch (rq->extts.index) { 667 case 0: 668 ext = bp->ts0; 669 break; 670 case 1: 671 ext = bp->ts1; 672 break; 673 case 2: 674 ext = bp->ts2; 675 break; 676 case 3: 677 ext = bp->pps; 678 break; 679 } 680 break; 681 case PTP_CLK_REQ_PPS: 682 req = OCP_REQ_PPS; 683 ext = bp->pps; 684 break; 685 case PTP_CLK_REQ_PEROUT: 686 if (on && 687 (rq->perout.period.sec != 1 || rq->perout.period.nsec != 0)) 688 return -EINVAL; 689 /* This is a request for 1PPS on an output SMA. 690 * Allow, but assume manual configuration. 691 */ 692 return 0; 693 default: 694 return -EOPNOTSUPP; 695 } 696 697 err = -ENXIO; 698 if (ext) 699 err = ext->info->enable(ext, req, on); 700 701 return err; 702 } 703 704 static const struct ptp_clock_info ptp_ocp_clock_info = { 705 .owner = THIS_MODULE, 706 .name = KBUILD_MODNAME, 707 .max_adj = 100000000, 708 .gettimex64 = ptp_ocp_gettimex, 709 .settime64 = ptp_ocp_settime, 710 .adjtime = ptp_ocp_adjtime, 711 .adjfine = ptp_ocp_null_adjfine, 712 .adjphase = ptp_ocp_null_adjphase, 713 .enable = ptp_ocp_enable, 714 .pps = true, 715 .n_ext_ts = 4, 716 .n_per_out = 1, 717 }; 718 719 static void 720 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) 721 { 722 u32 ctrl, select; 723 724 select = ioread32(&bp->reg->select); 725 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 726 727 iowrite32(0, &bp->reg->drift_ns); 728 729 ctrl = ioread32(&bp->reg->ctrl); 730 ctrl |= OCP_CTRL_ADJUST_DRIFT; 731 iowrite32(ctrl, &bp->reg->ctrl); 732 733 /* restore clock selection */ 734 iowrite32(select >> 16, &bp->reg->select); 735 } 736 737 static void 738 ptp_ocp_watchdog(struct timer_list *t) 739 { 740 struct ptp_ocp *bp = from_timer(bp, t, watchdog); 741 unsigned long flags; 742 u32 status; 743 744 status = ioread32(&bp->pps_to_clk->status); 745 746 if (status & PPS_STATUS_SUPERV_ERR) { 747 iowrite32(status, &bp->pps_to_clk->status); 748 if (!bp->gnss_lost) { 749 spin_lock_irqsave(&bp->lock, flags); 750 __ptp_ocp_clear_drift_locked(bp); 751 spin_unlock_irqrestore(&bp->lock, flags); 752 bp->gnss_lost = ktime_get_real_seconds(); 753 } 754 755 } else if (bp->gnss_lost) { 756 bp->gnss_lost = 0; 757 } 758 759 mod_timer(&bp->watchdog, jiffies + HZ); 760 } 761 762 static int 763 ptp_ocp_init_clock(struct ptp_ocp *bp) 764 { 765 struct timespec64 ts; 766 bool sync; 767 u32 ctrl; 768 769 /* make sure clock is enabled */ 770 ctrl = ioread32(&bp->reg->ctrl); 771 ctrl |= OCP_CTRL_ENABLE; 772 iowrite32(ctrl, &bp->reg->ctrl); 773 774 /* NO DRIFT Correction */ 775 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ 776 iowrite32(0x2000, &bp->reg->servo_offset_p); 777 iowrite32(0x1000, &bp->reg->servo_offset_i); 778 iowrite32(0, &bp->reg->servo_drift_p); 779 iowrite32(0, &bp->reg->servo_drift_i); 780 781 /* latch servo values */ 782 ctrl |= OCP_CTRL_ADJUST_SERVO; 783 iowrite32(ctrl, &bp->reg->ctrl); 784 785 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { 786 dev_err(&bp->pdev->dev, "clock not enabled\n"); 787 return -ENODEV; 788 } 789 790 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 791 if (!sync) { 792 ktime_get_clocktai_ts64(&ts); 793 ptp_ocp_settime(&bp->ptp_info, &ts); 794 } 795 796 /* If there is a clock supervisor, then enable the watchdog */ 797 if (bp->pps_to_clk) { 798 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); 799 mod_timer(&bp->watchdog, jiffies + HZ); 800 } 801 802 return 0; 803 } 804 805 static void 806 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val) 807 { 808 unsigned long flags; 809 810 spin_lock_irqsave(&bp->lock, flags); 811 812 bp->utc_tai_offset = val; 813 814 if (bp->irig_out) 815 iowrite32(val, &bp->irig_out->adj_sec); 816 if (bp->dcf_out) 817 iowrite32(val, &bp->dcf_out->adj_sec); 818 if (bp->nmea_out) 819 iowrite32(val, &bp->nmea_out->adj_sec); 820 821 spin_unlock_irqrestore(&bp->lock, flags); 822 } 823 824 static void 825 ptp_ocp_tod_init(struct ptp_ocp *bp) 826 { 827 u32 ctrl, reg; 828 829 ctrl = ioread32(&bp->tod->ctrl); 830 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; 831 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); 832 iowrite32(ctrl, &bp->tod->ctrl); 833 834 reg = ioread32(&bp->tod->utc_status); 835 if (reg & TOD_STATUS_UTC_VALID) 836 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK); 837 } 838 839 static void 840 ptp_ocp_tod_info(struct ptp_ocp *bp) 841 { 842 static const char * const proto_name[] = { 843 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", 844 "UBX", "UBX_UTC", "UBX_LS", "UBX_none" 845 }; 846 static const char * const gnss_name[] = { 847 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", 848 }; 849 u32 version, ctrl, reg; 850 int idx; 851 852 version = ioread32(&bp->tod->version); 853 dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n", 854 version >> 24, (version >> 16) & 0xff, version & 0xffff); 855 856 ctrl = ioread32(&bp->tod->ctrl); 857 idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0; 858 idx += (ctrl >> 16) & 3; 859 dev_info(&bp->pdev->dev, "control: %x\n", ctrl); 860 dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx], 861 ctrl & TOD_CTRL_ENABLE ? "enabled" : ""); 862 863 idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; 864 if (idx < ARRAY_SIZE(gnss_name)) 865 dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]); 866 867 reg = ioread32(&bp->tod->status); 868 dev_info(&bp->pdev->dev, "status: %x\n", reg); 869 870 reg = ioread32(&bp->tod->adj_sec); 871 dev_info(&bp->pdev->dev, "correction: %d\n", reg); 872 873 reg = ioread32(&bp->tod->utc_status); 874 dev_info(&bp->pdev->dev, "utc_status: %x\n", reg); 875 dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n", 876 reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0, 877 reg & TOD_STATUS_LEAP_VALID ? 1 : 0); 878 } 879 880 static int 881 ptp_ocp_firstchild(struct device *dev, void *data) 882 { 883 return 1; 884 } 885 886 static int 887 ptp_ocp_read_i2c(struct i2c_adapter *adap, u8 addr, u8 reg, u8 sz, u8 *data) 888 { 889 struct i2c_msg msgs[2] = { 890 { 891 .addr = addr, 892 .len = 1, 893 .buf = ®, 894 }, 895 { 896 .addr = addr, 897 .flags = I2C_M_RD, 898 .len = 2, 899 .buf = data, 900 }, 901 }; 902 int err; 903 u8 len; 904 905 /* xiic-i2c for some stupid reason only does 2 byte reads. */ 906 while (sz) { 907 len = min_t(u8, sz, 2); 908 msgs[1].len = len; 909 err = i2c_transfer(adap, msgs, 2); 910 if (err != msgs[1].len) 911 return err; 912 msgs[1].buf += len; 913 reg += len; 914 sz -= len; 915 } 916 return 0; 917 } 918 919 static void 920 ptp_ocp_get_serial_number(struct ptp_ocp *bp) 921 { 922 struct i2c_adapter *adap; 923 struct device *dev; 924 int err; 925 926 if (!bp->i2c_ctrl) 927 return; 928 929 dev = device_find_child(&bp->i2c_ctrl->dev, NULL, ptp_ocp_firstchild); 930 if (!dev) { 931 dev_err(&bp->pdev->dev, "Can't find I2C adapter\n"); 932 return; 933 } 934 935 adap = i2c_verify_adapter(dev); 936 if (!adap) { 937 dev_err(&bp->pdev->dev, "device '%s' isn't an I2C adapter\n", 938 dev_name(dev)); 939 goto out; 940 } 941 942 err = ptp_ocp_read_i2c(adap, 0x58, 0x9A, 6, bp->serial); 943 if (err) { 944 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", err); 945 goto out; 946 } 947 948 bp->has_serial = true; 949 950 out: 951 put_device(dev); 952 } 953 954 static struct device * 955 ptp_ocp_find_flash(struct ptp_ocp *bp) 956 { 957 struct device *dev, *last; 958 959 last = NULL; 960 dev = &bp->spi_flash->dev; 961 962 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) { 963 if (!strcmp("mtd", dev_bus_name(dev))) 964 break; 965 put_device(last); 966 last = dev; 967 } 968 put_device(last); 969 970 return dev; 971 } 972 973 static int 974 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, 975 const struct firmware *fw) 976 { 977 struct mtd_info *mtd = dev_get_drvdata(dev); 978 struct ptp_ocp *bp = devlink_priv(devlink); 979 size_t off, len, resid, wrote; 980 struct erase_info erase; 981 size_t base, blksz; 982 int err = 0; 983 984 off = 0; 985 base = bp->flash_start; 986 blksz = 4096; 987 resid = fw->size; 988 989 while (resid) { 990 devlink_flash_update_status_notify(devlink, "Flashing", 991 NULL, off, fw->size); 992 993 len = min_t(size_t, resid, blksz); 994 erase.addr = base + off; 995 erase.len = blksz; 996 997 err = mtd_erase(mtd, &erase); 998 if (err) 999 goto out; 1000 1001 err = mtd_write(mtd, base + off, len, &wrote, &fw->data[off]); 1002 if (err) 1003 goto out; 1004 1005 off += blksz; 1006 resid -= len; 1007 } 1008 out: 1009 return err; 1010 } 1011 1012 static int 1013 ptp_ocp_devlink_flash_update(struct devlink *devlink, 1014 struct devlink_flash_update_params *params, 1015 struct netlink_ext_ack *extack) 1016 { 1017 struct ptp_ocp *bp = devlink_priv(devlink); 1018 struct device *dev; 1019 const char *msg; 1020 int err; 1021 1022 dev = ptp_ocp_find_flash(bp); 1023 if (!dev) { 1024 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); 1025 return -ENODEV; 1026 } 1027 1028 devlink_flash_update_status_notify(devlink, "Preparing to flash", 1029 NULL, 0, 0); 1030 1031 err = ptp_ocp_devlink_flash(devlink, dev, params->fw); 1032 1033 msg = err ? "Flash error" : "Flash complete"; 1034 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); 1035 1036 put_device(dev); 1037 return err; 1038 } 1039 1040 static int 1041 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 1042 struct netlink_ext_ack *extack) 1043 { 1044 struct ptp_ocp *bp = devlink_priv(devlink); 1045 char buf[32]; 1046 int err; 1047 1048 err = devlink_info_driver_name_put(req, KBUILD_MODNAME); 1049 if (err) 1050 return err; 1051 1052 if (bp->image) { 1053 u32 ver = ioread32(&bp->image->version); 1054 1055 if (ver & 0xffff) { 1056 sprintf(buf, "%d", ver); 1057 err = devlink_info_version_running_put(req, 1058 "fw", 1059 buf); 1060 } else { 1061 sprintf(buf, "%d", ver >> 16); 1062 err = devlink_info_version_running_put(req, 1063 "loader", 1064 buf); 1065 } 1066 if (err) 1067 return err; 1068 } 1069 1070 if (!bp->has_serial) 1071 ptp_ocp_get_serial_number(bp); 1072 1073 if (bp->has_serial) { 1074 sprintf(buf, "%pM", bp->serial); 1075 err = devlink_info_serial_number_put(req, buf); 1076 if (err) 1077 return err; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static const struct devlink_ops ptp_ocp_devlink_ops = { 1084 .flash_update = ptp_ocp_devlink_flash_update, 1085 .info_get = ptp_ocp_devlink_info_get, 1086 }; 1087 1088 static void __iomem * 1089 __ptp_ocp_get_mem(struct ptp_ocp *bp, unsigned long start, int size) 1090 { 1091 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); 1092 1093 return devm_ioremap_resource(&bp->pdev->dev, &res); 1094 } 1095 1096 static void __iomem * 1097 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1098 { 1099 unsigned long start; 1100 1101 start = pci_resource_start(bp->pdev, 0) + r->offset; 1102 return __ptp_ocp_get_mem(bp, start, r->size); 1103 } 1104 1105 static void 1106 ptp_ocp_set_irq_resource(struct resource *res, int irq) 1107 { 1108 struct resource r = DEFINE_RES_IRQ(irq); 1109 *res = r; 1110 } 1111 1112 static void 1113 ptp_ocp_set_mem_resource(struct resource *res, unsigned long start, int size) 1114 { 1115 struct resource r = DEFINE_RES_MEM(start, size); 1116 *res = r; 1117 } 1118 1119 static int 1120 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) 1121 { 1122 struct ptp_ocp_flash_info *info; 1123 struct pci_dev *pdev = bp->pdev; 1124 struct platform_device *p; 1125 struct resource res[2]; 1126 unsigned long start; 1127 int id; 1128 1129 start = pci_resource_start(pdev, 0) + r->offset; 1130 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1131 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1132 1133 info = r->extra; 1134 id = pci_dev_id(pdev) << 1; 1135 id += info->pci_offset; 1136 1137 p = platform_device_register_resndata(&pdev->dev, info->name, id, 1138 res, 2, info->data, 1139 info->data_size); 1140 if (IS_ERR(p)) 1141 return PTR_ERR(p); 1142 1143 bp_assign_entry(bp, r, p); 1144 1145 return 0; 1146 } 1147 1148 static struct platform_device * 1149 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) 1150 { 1151 struct ptp_ocp_i2c_info *info; 1152 struct resource res[2]; 1153 unsigned long start; 1154 1155 info = r->extra; 1156 start = pci_resource_start(pdev, 0) + r->offset; 1157 ptp_ocp_set_mem_resource(&res[0], start, r->size); 1158 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 1159 1160 return platform_device_register_resndata(&pdev->dev, info->name, 1161 id, res, 2, 1162 info->data, info->data_size); 1163 } 1164 1165 static int 1166 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) 1167 { 1168 struct pci_dev *pdev = bp->pdev; 1169 struct ptp_ocp_i2c_info *info; 1170 struct platform_device *p; 1171 struct clk_hw *clk; 1172 char buf[32]; 1173 int id; 1174 1175 info = r->extra; 1176 id = pci_dev_id(bp->pdev); 1177 1178 sprintf(buf, "AXI.%d", id); 1179 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, 1180 info->fixed_rate); 1181 if (IS_ERR(clk)) 1182 return PTR_ERR(clk); 1183 bp->i2c_clk = clk; 1184 1185 sprintf(buf, "%s.%d", info->name, id); 1186 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); 1187 p = ptp_ocp_i2c_bus(bp->pdev, r, id); 1188 if (IS_ERR(p)) 1189 return PTR_ERR(p); 1190 1191 bp_assign_entry(bp, r, p); 1192 1193 return 0; 1194 } 1195 1196 static irqreturn_t 1197 ptp_ocp_ts_irq(int irq, void *priv) 1198 { 1199 struct ptp_ocp_ext_src *ext = priv; 1200 struct ts_reg __iomem *reg = ext->mem; 1201 struct ptp_clock_event ev; 1202 u32 sec, nsec; 1203 1204 if (ext == ext->bp->pps) { 1205 if (ext->bp->pps_req_map & OCP_REQ_PPS) { 1206 ev.type = PTP_CLOCK_PPS; 1207 ptp_clock_event(ext->bp->ptp, &ev); 1208 } 1209 1210 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0) 1211 goto out; 1212 } 1213 1214 /* XXX should fix API - this converts s/ns -> ts -> s/ns */ 1215 sec = ioread32(®->time_sec); 1216 nsec = ioread32(®->time_ns); 1217 1218 ev.type = PTP_CLOCK_EXTTS; 1219 ev.index = ext->info->index; 1220 ev.timestamp = sec * 1000000000ULL + nsec; 1221 1222 ptp_clock_event(ext->bp->ptp, &ev); 1223 1224 out: 1225 iowrite32(1, ®->intr); /* write 1 to ack */ 1226 1227 return IRQ_HANDLED; 1228 } 1229 1230 static int 1231 ptp_ocp_ts_enable(void *priv, u32 req, bool enable) 1232 { 1233 struct ptp_ocp_ext_src *ext = priv; 1234 struct ts_reg __iomem *reg = ext->mem; 1235 struct ptp_ocp *bp = ext->bp; 1236 1237 if (ext == bp->pps) { 1238 u32 old_map = bp->pps_req_map; 1239 1240 if (enable) 1241 bp->pps_req_map |= req; 1242 else 1243 bp->pps_req_map &= ~req; 1244 1245 /* if no state change, just return */ 1246 if ((!!old_map ^ !!bp->pps_req_map) == 0) 1247 return 0; 1248 } 1249 1250 if (enable) { 1251 iowrite32(1, ®->enable); 1252 iowrite32(1, ®->intr_mask); 1253 iowrite32(1, ®->intr); 1254 } else { 1255 iowrite32(0, ®->intr_mask); 1256 iowrite32(0, ®->enable); 1257 } 1258 1259 return 0; 1260 } 1261 1262 static void 1263 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) 1264 { 1265 ext->info->enable(ext, ~0, false); 1266 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); 1267 kfree(ext); 1268 } 1269 1270 static int 1271 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) 1272 { 1273 struct pci_dev *pdev = bp->pdev; 1274 struct ptp_ocp_ext_src *ext; 1275 int err; 1276 1277 ext = kzalloc(sizeof(*ext), GFP_KERNEL); 1278 if (!ext) 1279 return -ENOMEM; 1280 1281 err = -EINVAL; 1282 ext->mem = ptp_ocp_get_mem(bp, r); 1283 if (!ext->mem) 1284 goto out; 1285 1286 ext->bp = bp; 1287 ext->info = r->extra; 1288 ext->irq_vec = r->irq_vec; 1289 1290 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, 1291 ext, "ocp%d.%s", bp->id, r->name); 1292 if (err) { 1293 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); 1294 goto out; 1295 } 1296 1297 bp_assign_entry(bp, r, ext); 1298 1299 return 0; 1300 1301 out: 1302 kfree(ext); 1303 return err; 1304 } 1305 1306 static int 1307 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) 1308 { 1309 struct pci_dev *pdev = bp->pdev; 1310 struct uart_8250_port uart; 1311 1312 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets 1313 * the serial port device claim and release the pci resource. 1314 */ 1315 memset(&uart, 0, sizeof(uart)); 1316 uart.port.dev = &pdev->dev; 1317 uart.port.iotype = UPIO_MEM; 1318 uart.port.regshift = 2; 1319 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; 1320 uart.port.irq = pci_irq_vector(pdev, r->irq_vec); 1321 uart.port.uartclk = 50000000; 1322 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP; 1323 uart.port.type = PORT_16550A; 1324 1325 return serial8250_register_8250_port(&uart); 1326 } 1327 1328 static int 1329 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) 1330 { 1331 int port; 1332 1333 port = ptp_ocp_serial_line(bp, r); 1334 if (port < 0) 1335 return port; 1336 1337 bp_assign_entry(bp, r, port); 1338 1339 return 0; 1340 } 1341 1342 static int 1343 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1344 { 1345 void __iomem *mem; 1346 1347 mem = ptp_ocp_get_mem(bp, r); 1348 if (!mem) 1349 return -EINVAL; 1350 1351 bp_assign_entry(bp, r, mem); 1352 1353 return 0; 1354 } 1355 1356 static void 1357 ptp_ocp_nmea_out_init(struct ptp_ocp *bp) 1358 { 1359 if (!bp->nmea_out) 1360 return; 1361 1362 iowrite32(0, &bp->nmea_out->ctrl); /* disable */ 1363 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */ 1364 iowrite32(1, &bp->nmea_out->ctrl); /* enable */ 1365 } 1366 1367 /* FB specific board initializers; last "resource" registered. */ 1368 static int 1369 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 1370 { 1371 bp->flash_start = 1024 * 4096; 1372 1373 ptp_ocp_tod_init(bp); 1374 ptp_ocp_nmea_out_init(bp); 1375 1376 return ptp_ocp_init_clock(bp); 1377 } 1378 1379 static bool 1380 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r) 1381 { 1382 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs; 1383 1384 if (!allow) 1385 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n", 1386 r->irq_vec, r->name); 1387 return allow; 1388 } 1389 1390 static int 1391 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) 1392 { 1393 struct ocp_resource *r, *table; 1394 int err = 0; 1395 1396 table = (struct ocp_resource *)driver_data; 1397 for (r = table; r->setup; r++) { 1398 if (!ptp_ocp_allow_irq(bp, r)) 1399 continue; 1400 err = r->setup(bp, r); 1401 if (err) { 1402 dev_err(&bp->pdev->dev, 1403 "Could not register %s: err %d\n", 1404 r->name, err); 1405 break; 1406 } 1407 } 1408 return err; 1409 } 1410 1411 static void 1412 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable) 1413 { 1414 u32 ctrl; 1415 bool on; 1416 1417 ctrl = ioread32(reg); 1418 on = ctrl & bit; 1419 if (on ^ enable) { 1420 ctrl &= ~bit; 1421 ctrl |= enable ? bit : 0; 1422 iowrite32(ctrl, reg); 1423 } 1424 } 1425 1426 static void 1427 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable) 1428 { 1429 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl, 1430 IRIG_M_CTRL_ENABLE, enable); 1431 } 1432 1433 static void 1434 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable) 1435 { 1436 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl, 1437 IRIG_S_CTRL_ENABLE, enable); 1438 } 1439 1440 static void 1441 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable) 1442 { 1443 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl, 1444 DCF_M_CTRL_ENABLE, enable); 1445 } 1446 1447 static void 1448 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable) 1449 { 1450 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl, 1451 DCF_S_CTRL_ENABLE, enable); 1452 } 1453 1454 static void 1455 __handle_signal_outputs(struct ptp_ocp *bp, u32 val) 1456 { 1457 ptp_ocp_irig_out(bp, val & 0x00100010); 1458 ptp_ocp_dcf_out(bp, val & 0x00200020); 1459 } 1460 1461 static void 1462 __handle_signal_inputs(struct ptp_ocp *bp, u32 val) 1463 { 1464 ptp_ocp_irig_in(bp, val & 0x00100010); 1465 ptp_ocp_dcf_in(bp, val & 0x00200020); 1466 } 1467 1468 /* 1469 * ANT0 == gps (in) 1470 * ANT1 == sma1 (in) 1471 * ANT2 == sma2 (in) 1472 * ANT3 == sma3 (out) 1473 * ANT4 == sma4 (out) 1474 */ 1475 1476 enum ptp_ocp_sma_mode { 1477 SMA_MODE_IN, 1478 SMA_MODE_OUT, 1479 }; 1480 1481 static struct ptp_ocp_sma_connector { 1482 enum ptp_ocp_sma_mode mode; 1483 bool fixed_mode; 1484 u16 default_out_idx; 1485 } ptp_ocp_sma_map[4] = { 1486 { 1487 .mode = SMA_MODE_IN, 1488 .fixed_mode = true, 1489 }, 1490 { 1491 .mode = SMA_MODE_IN, 1492 .fixed_mode = true, 1493 }, 1494 { 1495 .mode = SMA_MODE_OUT, 1496 .fixed_mode = true, 1497 .default_out_idx = 0, /* 10Mhz */ 1498 }, 1499 { 1500 .mode = SMA_MODE_OUT, 1501 .fixed_mode = true, 1502 .default_out_idx = 1, /* PHC */ 1503 }, 1504 }; 1505 1506 static ssize_t 1507 ptp_ocp_show_output(u32 val, char *buf, int default_idx) 1508 { 1509 const char *name; 1510 ssize_t count; 1511 1512 count = sysfs_emit(buf, "OUT: "); 1513 name = ptp_ocp_select_name_from_val(ptp_ocp_sma_out, val); 1514 if (!name) 1515 name = ptp_ocp_sma_out[default_idx].name; 1516 count += sysfs_emit_at(buf, count, "%s\n", name); 1517 return count; 1518 } 1519 1520 static ssize_t 1521 ptp_ocp_show_inputs(u32 val, char *buf, const char *zero_in) 1522 { 1523 const char *name; 1524 ssize_t count; 1525 int i; 1526 1527 count = sysfs_emit(buf, "IN: "); 1528 for (i = 0; i < ARRAY_SIZE(ptp_ocp_sma_in); i++) { 1529 if (val & ptp_ocp_sma_in[i].value) { 1530 name = ptp_ocp_sma_in[i].name; 1531 count += sysfs_emit_at(buf, count, "%s ", name); 1532 } 1533 } 1534 if (!val && zero_in) 1535 count += sysfs_emit_at(buf, count, "%s ", zero_in); 1536 if (count) 1537 count--; 1538 count += sysfs_emit_at(buf, count, "\n"); 1539 return count; 1540 } 1541 1542 static int 1543 sma_parse_inputs(const char *buf, enum ptp_ocp_sma_mode *mode) 1544 { 1545 struct ocp_selector *tbl[] = { ptp_ocp_sma_in, ptp_ocp_sma_out }; 1546 int idx, count, dir; 1547 char **argv; 1548 int ret; 1549 1550 argv = argv_split(GFP_KERNEL, buf, &count); 1551 if (!argv) 1552 return -ENOMEM; 1553 1554 ret = -EINVAL; 1555 if (!count) 1556 goto out; 1557 1558 idx = 0; 1559 dir = *mode == SMA_MODE_IN ? 0 : 1; 1560 if (!strcasecmp("IN:", argv[idx])) { 1561 dir = 0; 1562 idx++; 1563 } 1564 if (!strcasecmp("OUT:", argv[0])) { 1565 dir = 1; 1566 idx++; 1567 } 1568 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT; 1569 1570 ret = 0; 1571 for (; idx < count; idx++) 1572 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]); 1573 if (ret < 0) 1574 ret = -EINVAL; 1575 1576 out: 1577 argv_free(argv); 1578 return ret; 1579 } 1580 1581 static ssize_t 1582 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, u32 val, char *buf, 1583 const char *zero_in) 1584 { 1585 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1]; 1586 1587 if (sma->mode == SMA_MODE_IN) 1588 return ptp_ocp_show_inputs(val, buf, zero_in); 1589 1590 return ptp_ocp_show_output(val, buf, sma->default_out_idx); 1591 } 1592 1593 static ssize_t 1594 sma1_show(struct device *dev, struct device_attribute *attr, char *buf) 1595 { 1596 struct ptp_ocp *bp = dev_get_drvdata(dev); 1597 u32 val; 1598 1599 val = ioread32(&bp->sma->gpio1) & 0x3f; 1600 return ptp_ocp_sma_show(bp, 1, val, buf, ptp_ocp_sma_in[0].name); 1601 } 1602 1603 static ssize_t 1604 sma2_show(struct device *dev, struct device_attribute *attr, char *buf) 1605 { 1606 struct ptp_ocp *bp = dev_get_drvdata(dev); 1607 u32 val; 1608 1609 val = (ioread32(&bp->sma->gpio1) >> 16) & 0x3f; 1610 return ptp_ocp_sma_show(bp, 2, val, buf, NULL); 1611 } 1612 1613 static ssize_t 1614 sma3_show(struct device *dev, struct device_attribute *attr, char *buf) 1615 { 1616 struct ptp_ocp *bp = dev_get_drvdata(dev); 1617 u32 val; 1618 1619 val = ioread32(&bp->sma->gpio2) & 0x3f; 1620 return ptp_ocp_sma_show(bp, 3, val, buf, NULL); 1621 } 1622 1623 static ssize_t 1624 sma4_show(struct device *dev, struct device_attribute *attr, char *buf) 1625 { 1626 struct ptp_ocp *bp = dev_get_drvdata(dev); 1627 u32 val; 1628 1629 val = (ioread32(&bp->sma->gpio2) >> 16) & 0x3f; 1630 return ptp_ocp_sma_show(bp, 4, val, buf, NULL); 1631 } 1632 1633 static void 1634 ptp_ocp_sma_store_output(struct ptp_ocp *bp, u32 val, u32 shift) 1635 { 1636 unsigned long flags; 1637 u32 gpio, mask; 1638 1639 mask = 0xffff << (16 - shift); 1640 1641 spin_lock_irqsave(&bp->lock, flags); 1642 1643 gpio = ioread32(&bp->sma->gpio2); 1644 gpio = (gpio & mask) | (val << shift); 1645 1646 __handle_signal_outputs(bp, gpio); 1647 1648 iowrite32(gpio, &bp->sma->gpio2); 1649 1650 spin_unlock_irqrestore(&bp->lock, flags); 1651 } 1652 1653 static void 1654 ptp_ocp_sma_store_inputs(struct ptp_ocp *bp, u32 val, u32 shift) 1655 { 1656 unsigned long flags; 1657 u32 gpio, mask; 1658 1659 mask = 0xffff << (16 - shift); 1660 1661 spin_lock_irqsave(&bp->lock, flags); 1662 1663 gpio = ioread32(&bp->sma->gpio1); 1664 gpio = (gpio & mask) | (val << shift); 1665 1666 __handle_signal_inputs(bp, gpio); 1667 1668 iowrite32(gpio, &bp->sma->gpio1); 1669 1670 spin_unlock_irqrestore(&bp->lock, flags); 1671 } 1672 1673 static ssize_t 1674 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr, u32 shift) 1675 { 1676 struct ptp_ocp_sma_connector *sma = &ptp_ocp_sma_map[sma_nr - 1]; 1677 enum ptp_ocp_sma_mode mode; 1678 int val; 1679 1680 mode = sma->mode; 1681 val = sma_parse_inputs(buf, &mode); 1682 if (val < 0) 1683 return val; 1684 1685 if (mode != sma->mode && sma->fixed_mode) 1686 return -EOPNOTSUPP; 1687 1688 if (mode != sma->mode) { 1689 pr_err("Mode changes not supported yet.\n"); 1690 return -EOPNOTSUPP; 1691 } 1692 1693 if (sma->mode == SMA_MODE_IN) 1694 ptp_ocp_sma_store_inputs(bp, val, shift); 1695 else 1696 ptp_ocp_sma_store_output(bp, val, shift); 1697 1698 return 0; 1699 } 1700 1701 static ssize_t 1702 sma1_store(struct device *dev, struct device_attribute *attr, 1703 const char *buf, size_t count) 1704 { 1705 struct ptp_ocp *bp = dev_get_drvdata(dev); 1706 int err; 1707 1708 err = ptp_ocp_sma_store(bp, buf, 1, 0); 1709 return err ? err : count; 1710 } 1711 1712 static ssize_t 1713 sma2_store(struct device *dev, struct device_attribute *attr, 1714 const char *buf, size_t count) 1715 { 1716 struct ptp_ocp *bp = dev_get_drvdata(dev); 1717 int err; 1718 1719 err = ptp_ocp_sma_store(bp, buf, 2, 16); 1720 return err ? err : count; 1721 } 1722 1723 static ssize_t 1724 sma3_store(struct device *dev, struct device_attribute *attr, 1725 const char *buf, size_t count) 1726 { 1727 struct ptp_ocp *bp = dev_get_drvdata(dev); 1728 int err; 1729 1730 err = ptp_ocp_sma_store(bp, buf, 3, 0); 1731 return err ? err : count; 1732 } 1733 1734 static ssize_t 1735 sma4_store(struct device *dev, struct device_attribute *attr, 1736 const char *buf, size_t count) 1737 { 1738 struct ptp_ocp *bp = dev_get_drvdata(dev); 1739 int err; 1740 1741 err = ptp_ocp_sma_store(bp, buf, 4, 16); 1742 return err ? err : count; 1743 } 1744 static DEVICE_ATTR_RW(sma1); 1745 static DEVICE_ATTR_RW(sma2); 1746 static DEVICE_ATTR_RW(sma3); 1747 static DEVICE_ATTR_RW(sma4); 1748 1749 static ssize_t 1750 available_sma_inputs_show(struct device *dev, 1751 struct device_attribute *attr, char *buf) 1752 { 1753 return ptp_ocp_select_table_show(ptp_ocp_sma_in, buf); 1754 } 1755 static DEVICE_ATTR_RO(available_sma_inputs); 1756 1757 static ssize_t 1758 available_sma_outputs_show(struct device *dev, 1759 struct device_attribute *attr, char *buf) 1760 { 1761 return ptp_ocp_select_table_show(ptp_ocp_sma_out, buf); 1762 } 1763 static DEVICE_ATTR_RO(available_sma_outputs); 1764 1765 static ssize_t 1766 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) 1767 { 1768 struct ptp_ocp *bp = dev_get_drvdata(dev); 1769 1770 if (!bp->has_serial) 1771 ptp_ocp_get_serial_number(bp); 1772 1773 return sysfs_emit(buf, "%pM\n", bp->serial); 1774 } 1775 static DEVICE_ATTR_RO(serialnum); 1776 1777 static ssize_t 1778 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) 1779 { 1780 struct ptp_ocp *bp = dev_get_drvdata(dev); 1781 ssize_t ret; 1782 1783 if (bp->gnss_lost) 1784 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); 1785 else 1786 ret = sysfs_emit(buf, "SYNC\n"); 1787 1788 return ret; 1789 } 1790 static DEVICE_ATTR_RO(gnss_sync); 1791 1792 static ssize_t 1793 utc_tai_offset_show(struct device *dev, 1794 struct device_attribute *attr, char *buf) 1795 { 1796 struct ptp_ocp *bp = dev_get_drvdata(dev); 1797 1798 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset); 1799 } 1800 1801 static ssize_t 1802 utc_tai_offset_store(struct device *dev, 1803 struct device_attribute *attr, 1804 const char *buf, size_t count) 1805 { 1806 struct ptp_ocp *bp = dev_get_drvdata(dev); 1807 int err; 1808 u32 val; 1809 1810 err = kstrtou32(buf, 0, &val); 1811 if (err) 1812 return err; 1813 1814 ptp_ocp_utc_distribute(bp, val); 1815 1816 return count; 1817 } 1818 static DEVICE_ATTR_RW(utc_tai_offset); 1819 1820 static ssize_t 1821 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf) 1822 { 1823 struct ptp_ocp *bp = dev_get_drvdata(dev); 1824 u32 val; 1825 1826 val = ioread32(&bp->irig_out->ctrl); 1827 val = (val >> 16) & 0x07; 1828 return sysfs_emit(buf, "%d\n", val); 1829 } 1830 1831 static ssize_t 1832 irig_b_mode_store(struct device *dev, 1833 struct device_attribute *attr, 1834 const char *buf, size_t count) 1835 { 1836 struct ptp_ocp *bp = dev_get_drvdata(dev); 1837 unsigned long flags; 1838 int err; 1839 u32 reg; 1840 u8 val; 1841 1842 err = kstrtou8(buf, 0, &val); 1843 if (err) 1844 return err; 1845 if (val > 7) 1846 return -EINVAL; 1847 1848 reg = ((val & 0x7) << 16); 1849 1850 spin_lock_irqsave(&bp->lock, flags); 1851 iowrite32(0, &bp->irig_out->ctrl); /* disable */ 1852 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */ 1853 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl); 1854 spin_unlock_irqrestore(&bp->lock, flags); 1855 1856 return count; 1857 } 1858 static DEVICE_ATTR_RW(irig_b_mode); 1859 1860 static ssize_t 1861 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) 1862 { 1863 struct ptp_ocp *bp = dev_get_drvdata(dev); 1864 const char *p; 1865 u32 select; 1866 1867 select = ioread32(&bp->reg->select); 1868 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16); 1869 1870 return sysfs_emit(buf, "%s\n", p); 1871 } 1872 1873 static ssize_t 1874 clock_source_store(struct device *dev, struct device_attribute *attr, 1875 const char *buf, size_t count) 1876 { 1877 struct ptp_ocp *bp = dev_get_drvdata(dev); 1878 unsigned long flags; 1879 int val; 1880 1881 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf); 1882 if (val < 0) 1883 return val; 1884 1885 spin_lock_irqsave(&bp->lock, flags); 1886 iowrite32(val, &bp->reg->select); 1887 spin_unlock_irqrestore(&bp->lock, flags); 1888 1889 return count; 1890 } 1891 static DEVICE_ATTR_RW(clock_source); 1892 1893 static ssize_t 1894 available_clock_sources_show(struct device *dev, 1895 struct device_attribute *attr, char *buf) 1896 { 1897 return ptp_ocp_select_table_show(ptp_ocp_clock, buf); 1898 } 1899 static DEVICE_ATTR_RO(available_clock_sources); 1900 1901 static struct attribute *timecard_attrs[] = { 1902 &dev_attr_serialnum.attr, 1903 &dev_attr_gnss_sync.attr, 1904 &dev_attr_clock_source.attr, 1905 &dev_attr_available_clock_sources.attr, 1906 &dev_attr_sma1.attr, 1907 &dev_attr_sma2.attr, 1908 &dev_attr_sma3.attr, 1909 &dev_attr_sma4.attr, 1910 &dev_attr_available_sma_inputs.attr, 1911 &dev_attr_available_sma_outputs.attr, 1912 &dev_attr_irig_b_mode.attr, 1913 &dev_attr_utc_tai_offset.attr, 1914 NULL, 1915 }; 1916 ATTRIBUTE_GROUPS(timecard); 1917 1918 static const char * 1919 gpio_map(u32 gpio, u32 bit, const char *pri, const char *sec, const char *def) 1920 { 1921 const char *ans; 1922 1923 if (gpio & (1 << bit)) 1924 ans = pri; 1925 else if (gpio & (1 << (bit + 16))) 1926 ans = sec; 1927 else 1928 ans = def; 1929 return ans; 1930 } 1931 1932 static void 1933 gpio_multi_map(char *buf, u32 gpio, u32 bit, 1934 const char *pri, const char *sec, const char *def) 1935 { 1936 char *ans = buf; 1937 1938 strcpy(ans, def); 1939 if (gpio & (1 << bit)) 1940 ans += sprintf(ans, "%s ", pri); 1941 if (gpio & (1 << (bit + 16))) 1942 ans += sprintf(ans, "%s ", sec); 1943 } 1944 1945 static int 1946 ptp_ocp_summary_show(struct seq_file *s, void *data) 1947 { 1948 struct device *dev = s->private; 1949 struct ptp_system_timestamp sts; 1950 u32 sma_in, sma_out, ctrl, val; 1951 struct ts_reg __iomem *ts_reg; 1952 struct timespec64 ts; 1953 struct ptp_ocp *bp; 1954 const char *src; 1955 bool on, map; 1956 char *buf; 1957 1958 buf = (char *)__get_free_page(GFP_KERNEL); 1959 if (!buf) 1960 return -ENOMEM; 1961 1962 bp = dev_get_drvdata(dev); 1963 sma_in = ioread32(&bp->sma->gpio1); 1964 sma_out = ioread32(&bp->sma->gpio2); 1965 1966 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp)); 1967 1968 sma1_show(dev, NULL, buf); 1969 seq_printf(s, " sma1: %s", buf); 1970 1971 sma2_show(dev, NULL, buf); 1972 seq_printf(s, " sma2: %s", buf); 1973 1974 sma3_show(dev, NULL, buf); 1975 seq_printf(s, " sma3: %s", buf); 1976 1977 sma4_show(dev, NULL, buf); 1978 seq_printf(s, " sma4: %s", buf); 1979 1980 if (bp->ts0) { 1981 ts_reg = bp->ts0->mem; 1982 on = ioread32(&ts_reg->enable); 1983 src = "GNSS"; 1984 seq_printf(s, "%7s: %s, src: %s\n", "TS0", 1985 on ? " ON" : "OFF", src); 1986 } 1987 1988 if (bp->ts1) { 1989 ts_reg = bp->ts1->mem; 1990 on = ioread32(&ts_reg->enable); 1991 src = gpio_map(sma_in, 2, "sma1", "sma2", "----"); 1992 seq_printf(s, "%7s: %s, src: %s\n", "TS1", 1993 on ? " ON" : "OFF", src); 1994 } 1995 1996 if (bp->ts2) { 1997 ts_reg = bp->ts2->mem; 1998 on = ioread32(&ts_reg->enable); 1999 src = gpio_map(sma_in, 3, "sma1", "sma2", "----"); 2000 seq_printf(s, "%7s: %s, src: %s\n", "TS2", 2001 on ? " ON" : "OFF", src); 2002 } 2003 2004 if (bp->pps) { 2005 ts_reg = bp->pps->mem; 2006 src = "PHC"; 2007 on = ioread32(&ts_reg->enable); 2008 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP); 2009 seq_printf(s, "%7s: %s, src: %s\n", "TS3", 2010 on & map ? " ON" : "OFF", src); 2011 2012 map = !!(bp->pps_req_map & OCP_REQ_PPS); 2013 seq_printf(s, "%7s: %s, src: %s\n", "PPS", 2014 on & map ? " ON" : "OFF", src); 2015 } 2016 2017 if (bp->irig_out) { 2018 ctrl = ioread32(&bp->irig_out->ctrl); 2019 on = ctrl & IRIG_M_CTRL_ENABLE; 2020 val = ioread32(&bp->irig_out->status); 2021 gpio_multi_map(buf, sma_out, 4, "sma3", "sma4", "----"); 2022 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG", 2023 on ? " ON" : "OFF", val, (ctrl >> 16), buf); 2024 } 2025 2026 if (bp->irig_in) { 2027 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE; 2028 val = ioread32(&bp->irig_in->status); 2029 src = gpio_map(sma_in, 4, "sma1", "sma2", "----"); 2030 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in", 2031 on ? " ON" : "OFF", val, src); 2032 } 2033 2034 if (bp->dcf_out) { 2035 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE; 2036 val = ioread32(&bp->dcf_out->status); 2037 gpio_multi_map(buf, sma_out, 5, "sma3", "sma4", "----"); 2038 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF", 2039 on ? " ON" : "OFF", val, buf); 2040 } 2041 2042 if (bp->dcf_in) { 2043 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE; 2044 val = ioread32(&bp->dcf_in->status); 2045 src = gpio_map(sma_in, 5, "sma1", "sma2", "----"); 2046 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in", 2047 on ? " ON" : "OFF", val, src); 2048 } 2049 2050 if (bp->nmea_out) { 2051 on = ioread32(&bp->nmea_out->ctrl) & 1; 2052 val = ioread32(&bp->nmea_out->status); 2053 seq_printf(s, "%7s: %s, error: %d\n", "NMEA", 2054 on ? " ON" : "OFF", val); 2055 } 2056 2057 /* compute src for PPS1, used below. */ 2058 if (bp->pps_select) { 2059 val = ioread32(&bp->pps_select->gpio1); 2060 if (val & 0x01) 2061 src = gpio_map(sma_in, 0, "sma1", "sma2", "----"); 2062 else if (val & 0x02) 2063 src = "MAC"; 2064 else if (val & 0x04) 2065 src = "GNSS"; 2066 else 2067 src = "----"; 2068 } else { 2069 src = "?"; 2070 } 2071 2072 /* assumes automatic switchover/selection */ 2073 val = ioread32(&bp->reg->select); 2074 switch (val >> 16) { 2075 case 0: 2076 sprintf(buf, "----"); 2077 break; 2078 case 2: 2079 sprintf(buf, "IRIG"); 2080 break; 2081 case 3: 2082 sprintf(buf, "%s via PPS1", src); 2083 break; 2084 case 6: 2085 sprintf(buf, "DCF"); 2086 break; 2087 default: 2088 strcpy(buf, "unknown"); 2089 break; 2090 } 2091 val = ioread32(&bp->reg->status); 2092 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf, 2093 val & OCP_STATUS_IN_SYNC ? "sync" : "unsynced"); 2094 2095 /* reuses PPS1 src from earlier */ 2096 seq_printf(s, "MAC PPS1 src: %s\n", src); 2097 2098 src = gpio_map(sma_in, 1, "sma1", "sma2", "GNSS2"); 2099 seq_printf(s, "MAC PPS2 src: %s\n", src); 2100 2101 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) { 2102 struct timespec64 sys_ts; 2103 s64 pre_ns, post_ns, ns; 2104 2105 pre_ns = timespec64_to_ns(&sts.pre_ts); 2106 post_ns = timespec64_to_ns(&sts.post_ts); 2107 ns = (pre_ns + post_ns) / 2; 2108 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC; 2109 sys_ts = ns_to_timespec64(ns); 2110 2111 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC", 2112 ts.tv_sec, ts.tv_nsec, &ts); 2113 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS", 2114 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts, 2115 bp->utc_tai_offset); 2116 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "", 2117 timespec64_to_ns(&ts) - ns, 2118 post_ns - pre_ns); 2119 } 2120 2121 free_page((unsigned long)buf); 2122 return 0; 2123 } 2124 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary); 2125 2126 static struct dentry *ptp_ocp_debugfs_root; 2127 2128 static void 2129 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp) 2130 { 2131 struct dentry *d; 2132 2133 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root); 2134 bp->debug_root = d; 2135 debugfs_create_file("summary", 0444, bp->debug_root, 2136 &bp->dev, &ptp_ocp_summary_fops); 2137 } 2138 2139 static void 2140 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp) 2141 { 2142 debugfs_remove_recursive(bp->debug_root); 2143 } 2144 2145 static void 2146 ptp_ocp_debugfs_init(void) 2147 { 2148 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL); 2149 } 2150 2151 static void 2152 ptp_ocp_debugfs_fini(void) 2153 { 2154 debugfs_remove_recursive(ptp_ocp_debugfs_root); 2155 } 2156 2157 static void 2158 ptp_ocp_dev_release(struct device *dev) 2159 { 2160 struct ptp_ocp *bp = dev_get_drvdata(dev); 2161 2162 mutex_lock(&ptp_ocp_lock); 2163 idr_remove(&ptp_ocp_idr, bp->id); 2164 mutex_unlock(&ptp_ocp_lock); 2165 } 2166 2167 static int 2168 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) 2169 { 2170 int err; 2171 2172 mutex_lock(&ptp_ocp_lock); 2173 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); 2174 mutex_unlock(&ptp_ocp_lock); 2175 if (err < 0) { 2176 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); 2177 return err; 2178 } 2179 bp->id = err; 2180 2181 bp->ptp_info = ptp_ocp_clock_info; 2182 spin_lock_init(&bp->lock); 2183 bp->gnss_port = -1; 2184 bp->gnss2_port = -1; 2185 bp->mac_port = -1; 2186 bp->nmea_port = -1; 2187 bp->pdev = pdev; 2188 2189 device_initialize(&bp->dev); 2190 dev_set_name(&bp->dev, "ocp%d", bp->id); 2191 bp->dev.class = &timecard_class; 2192 bp->dev.parent = &pdev->dev; 2193 bp->dev.release = ptp_ocp_dev_release; 2194 dev_set_drvdata(&bp->dev, bp); 2195 2196 err = device_add(&bp->dev); 2197 if (err) { 2198 dev_err(&bp->dev, "device add failed: %d\n", err); 2199 goto out; 2200 } 2201 2202 pci_set_drvdata(pdev, bp); 2203 2204 return 0; 2205 2206 out: 2207 ptp_ocp_dev_release(&bp->dev); 2208 put_device(&bp->dev); 2209 return err; 2210 } 2211 2212 static void 2213 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) 2214 { 2215 struct device *dev = &bp->dev; 2216 2217 if (sysfs_create_link(&dev->kobj, &child->kobj, link)) 2218 dev_err(dev, "%s symlink failed\n", link); 2219 } 2220 2221 static void 2222 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) 2223 { 2224 struct device *dev, *child; 2225 2226 dev = &bp->pdev->dev; 2227 2228 child = device_find_child_by_name(dev, name); 2229 if (!child) { 2230 dev_err(dev, "Could not find device %s\n", name); 2231 return; 2232 } 2233 2234 ptp_ocp_symlink(bp, child, link); 2235 put_device(child); 2236 } 2237 2238 static int 2239 ptp_ocp_complete(struct ptp_ocp *bp) 2240 { 2241 struct pps_device *pps; 2242 char buf[32]; 2243 2244 if (bp->gnss_port != -1) { 2245 sprintf(buf, "ttyS%d", bp->gnss_port); 2246 ptp_ocp_link_child(bp, buf, "ttyGNSS"); 2247 } 2248 if (bp->gnss2_port != -1) { 2249 sprintf(buf, "ttyS%d", bp->gnss2_port); 2250 ptp_ocp_link_child(bp, buf, "ttyGNSS2"); 2251 } 2252 if (bp->mac_port != -1) { 2253 sprintf(buf, "ttyS%d", bp->mac_port); 2254 ptp_ocp_link_child(bp, buf, "ttyMAC"); 2255 } 2256 if (bp->nmea_port != -1) { 2257 sprintf(buf, "ttyS%d", bp->nmea_port); 2258 ptp_ocp_link_child(bp, buf, "ttyNMEA"); 2259 } 2260 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); 2261 ptp_ocp_link_child(bp, buf, "ptp"); 2262 2263 pps = pps_lookup_dev(bp->ptp); 2264 if (pps) 2265 ptp_ocp_symlink(bp, pps->dev, "pps"); 2266 2267 if (device_add_groups(&bp->dev, timecard_groups)) 2268 pr_err("device add groups failed\n"); 2269 2270 ptp_ocp_debugfs_add_device(bp); 2271 2272 return 0; 2273 } 2274 2275 static void 2276 ptp_ocp_phc_info(struct ptp_ocp *bp) 2277 { 2278 struct timespec64 ts; 2279 u32 version, select; 2280 bool sync; 2281 2282 version = ioread32(&bp->reg->version); 2283 select = ioread32(&bp->reg->select); 2284 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", 2285 version >> 24, (version >> 16) & 0xff, version & 0xffff, 2286 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16), 2287 ptp_clock_index(bp->ptp)); 2288 2289 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 2290 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) 2291 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n", 2292 ts.tv_sec, ts.tv_nsec, 2293 sync ? "in-sync" : "UNSYNCED"); 2294 } 2295 2296 static void 2297 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud) 2298 { 2299 if (port != -1) 2300 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud); 2301 } 2302 2303 static void 2304 ptp_ocp_info(struct ptp_ocp *bp) 2305 { 2306 static int nmea_baud[] = { 2307 1200, 2400, 4800, 9600, 19200, 38400, 2308 57600, 115200, 230400, 460800, 921600, 2309 1000000, 2000000 2310 }; 2311 struct device *dev = &bp->pdev->dev; 2312 u32 reg; 2313 2314 ptp_ocp_phc_info(bp); 2315 if (bp->tod) 2316 ptp_ocp_tod_info(bp); 2317 2318 if (bp->image) { 2319 u32 ver = ioread32(&bp->image->version); 2320 2321 dev_info(dev, "version %x\n", ver); 2322 if (ver & 0xffff) 2323 dev_info(dev, "regular image, version %d\n", 2324 ver & 0xffff); 2325 else 2326 dev_info(dev, "golden image, version %d\n", 2327 ver >> 16); 2328 } 2329 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port, 115200); 2330 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port, 115200); 2331 ptp_ocp_serial_info(dev, "MAC", bp->mac_port, 57600); 2332 if (bp->nmea_out && bp->nmea_port != -1) { 2333 int baud = -1; 2334 2335 reg = ioread32(&bp->nmea_out->uart_baud); 2336 if (reg < ARRAY_SIZE(nmea_baud)) 2337 baud = nmea_baud[reg]; 2338 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port, baud); 2339 } 2340 } 2341 2342 static void 2343 ptp_ocp_detach_sysfs(struct ptp_ocp *bp) 2344 { 2345 struct device *dev = &bp->dev; 2346 2347 sysfs_remove_link(&dev->kobj, "ttyGNSS"); 2348 sysfs_remove_link(&dev->kobj, "ttyMAC"); 2349 sysfs_remove_link(&dev->kobj, "ptp"); 2350 sysfs_remove_link(&dev->kobj, "pps"); 2351 device_remove_groups(dev, timecard_groups); 2352 } 2353 2354 static void 2355 ptp_ocp_detach(struct ptp_ocp *bp) 2356 { 2357 ptp_ocp_debugfs_remove_device(bp); 2358 ptp_ocp_detach_sysfs(bp); 2359 if (timer_pending(&bp->watchdog)) 2360 del_timer_sync(&bp->watchdog); 2361 if (bp->ts0) 2362 ptp_ocp_unregister_ext(bp->ts0); 2363 if (bp->ts1) 2364 ptp_ocp_unregister_ext(bp->ts1); 2365 if (bp->ts2) 2366 ptp_ocp_unregister_ext(bp->ts2); 2367 if (bp->pps) 2368 ptp_ocp_unregister_ext(bp->pps); 2369 if (bp->gnss_port != -1) 2370 serial8250_unregister_port(bp->gnss_port); 2371 if (bp->gnss2_port != -1) 2372 serial8250_unregister_port(bp->gnss2_port); 2373 if (bp->mac_port != -1) 2374 serial8250_unregister_port(bp->mac_port); 2375 if (bp->nmea_port != -1) 2376 serial8250_unregister_port(bp->nmea_port); 2377 if (bp->spi_flash) 2378 platform_device_unregister(bp->spi_flash); 2379 if (bp->i2c_ctrl) 2380 platform_device_unregister(bp->i2c_ctrl); 2381 if (bp->i2c_clk) 2382 clk_hw_unregister_fixed_rate(bp->i2c_clk); 2383 if (bp->n_irqs) 2384 pci_free_irq_vectors(bp->pdev); 2385 if (bp->ptp) 2386 ptp_clock_unregister(bp->ptp); 2387 device_unregister(&bp->dev); 2388 } 2389 2390 static int 2391 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2392 { 2393 struct devlink *devlink; 2394 struct ptp_ocp *bp; 2395 int err; 2396 2397 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); 2398 if (!devlink) { 2399 dev_err(&pdev->dev, "devlink_alloc failed\n"); 2400 return -ENOMEM; 2401 } 2402 2403 err = devlink_register(devlink); 2404 if (err) 2405 goto out_free; 2406 2407 err = pci_enable_device(pdev); 2408 if (err) { 2409 dev_err(&pdev->dev, "pci_enable_device\n"); 2410 goto out_unregister; 2411 } 2412 2413 bp = devlink_priv(devlink); 2414 err = ptp_ocp_device_init(bp, pdev); 2415 if (err) 2416 goto out_disable; 2417 2418 /* compat mode. 2419 * Older FPGA firmware only returns 2 irq's. 2420 * allow this - if not all of the IRQ's are returned, skip the 2421 * extra devices and just register the clock. 2422 */ 2423 err = pci_alloc_irq_vectors(pdev, 1, 11, PCI_IRQ_MSI | PCI_IRQ_MSIX); 2424 if (err < 0) { 2425 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); 2426 goto out; 2427 } 2428 bp->n_irqs = err; 2429 pci_set_master(pdev); 2430 2431 err = ptp_ocp_register_resources(bp, id->driver_data); 2432 if (err) 2433 goto out; 2434 2435 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); 2436 if (IS_ERR(bp->ptp)) { 2437 err = PTR_ERR(bp->ptp); 2438 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); 2439 bp->ptp = NULL; 2440 goto out; 2441 } 2442 2443 err = ptp_ocp_complete(bp); 2444 if (err) 2445 goto out; 2446 2447 ptp_ocp_info(bp); 2448 2449 return 0; 2450 2451 out: 2452 ptp_ocp_detach(bp); 2453 pci_set_drvdata(pdev, NULL); 2454 out_disable: 2455 pci_disable_device(pdev); 2456 out_unregister: 2457 devlink_unregister(devlink); 2458 out_free: 2459 devlink_free(devlink); 2460 2461 return err; 2462 } 2463 2464 static void 2465 ptp_ocp_remove(struct pci_dev *pdev) 2466 { 2467 struct ptp_ocp *bp = pci_get_drvdata(pdev); 2468 struct devlink *devlink = priv_to_devlink(bp); 2469 2470 ptp_ocp_detach(bp); 2471 pci_set_drvdata(pdev, NULL); 2472 pci_disable_device(pdev); 2473 2474 devlink_unregister(devlink); 2475 devlink_free(devlink); 2476 } 2477 2478 static struct pci_driver ptp_ocp_driver = { 2479 .name = KBUILD_MODNAME, 2480 .id_table = ptp_ocp_pcidev_id, 2481 .probe = ptp_ocp_probe, 2482 .remove = ptp_ocp_remove, 2483 }; 2484 2485 static int 2486 ptp_ocp_i2c_notifier_call(struct notifier_block *nb, 2487 unsigned long action, void *data) 2488 { 2489 struct device *dev, *child = data; 2490 struct ptp_ocp *bp; 2491 bool add; 2492 2493 switch (action) { 2494 case BUS_NOTIFY_ADD_DEVICE: 2495 case BUS_NOTIFY_DEL_DEVICE: 2496 add = action == BUS_NOTIFY_ADD_DEVICE; 2497 break; 2498 default: 2499 return 0; 2500 } 2501 2502 if (!i2c_verify_adapter(child)) 2503 return 0; 2504 2505 dev = child; 2506 while ((dev = dev->parent)) 2507 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 2508 goto found; 2509 return 0; 2510 2511 found: 2512 bp = dev_get_drvdata(dev); 2513 if (add) 2514 ptp_ocp_symlink(bp, child, "i2c"); 2515 else 2516 sysfs_remove_link(&bp->dev.kobj, "i2c"); 2517 2518 return 0; 2519 } 2520 2521 static struct notifier_block ptp_ocp_i2c_notifier = { 2522 .notifier_call = ptp_ocp_i2c_notifier_call, 2523 }; 2524 2525 static int __init 2526 ptp_ocp_init(void) 2527 { 2528 const char *what; 2529 int err; 2530 2531 ptp_ocp_debugfs_init(); 2532 2533 what = "timecard class"; 2534 err = class_register(&timecard_class); 2535 if (err) 2536 goto out; 2537 2538 what = "i2c notifier"; 2539 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2540 if (err) 2541 goto out_notifier; 2542 2543 what = "ptp_ocp driver"; 2544 err = pci_register_driver(&ptp_ocp_driver); 2545 if (err) 2546 goto out_register; 2547 2548 return 0; 2549 2550 out_register: 2551 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2552 out_notifier: 2553 class_unregister(&timecard_class); 2554 out: 2555 ptp_ocp_debugfs_fini(); 2556 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); 2557 return err; 2558 } 2559 2560 static void __exit 2561 ptp_ocp_fini(void) 2562 { 2563 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 2564 pci_unregister_driver(&ptp_ocp_driver); 2565 class_unregister(&timecard_class); 2566 ptp_ocp_debugfs_fini(); 2567 } 2568 2569 module_init(ptp_ocp_init); 2570 module_exit(ptp_ocp_fini); 2571 2572 MODULE_DESCRIPTION("OpenCompute TimeCard driver"); 2573 MODULE_LICENSE("GPL v2"); 2574