1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2020 Facebook */ 3 4 #include <linux/err.h> 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/init.h> 8 #include <linux/pci.h> 9 #include <linux/serial_8250.h> 10 #include <linux/clkdev.h> 11 #include <linux/clk-provider.h> 12 #include <linux/platform_device.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/spi/spi.h> 15 #include <linux/spi/xilinx_spi.h> 16 #include <net/devlink.h> 17 #include <linux/i2c.h> 18 #include <linux/mtd/mtd.h> 19 20 #ifndef PCI_VENDOR_ID_FACEBOOK 21 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b 22 #endif 23 24 #ifndef PCI_DEVICE_ID_FACEBOOK_TIMECARD 25 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400 26 #endif 27 28 static struct class timecard_class = { 29 .owner = THIS_MODULE, 30 .name = "timecard", 31 }; 32 33 struct ocp_reg { 34 u32 ctrl; 35 u32 status; 36 u32 select; 37 u32 version; 38 u32 time_ns; 39 u32 time_sec; 40 u32 __pad0[2]; 41 u32 adjust_ns; 42 u32 adjust_sec; 43 u32 __pad1[2]; 44 u32 offset_ns; 45 u32 offset_window_ns; 46 u32 __pad2[2]; 47 u32 drift_ns; 48 u32 drift_window_ns; 49 u32 __pad3[6]; 50 u32 servo_offset_p; 51 u32 servo_offset_i; 52 u32 servo_drift_p; 53 u32 servo_drift_i; 54 }; 55 56 #define OCP_CTRL_ENABLE BIT(0) 57 #define OCP_CTRL_ADJUST_TIME BIT(1) 58 #define OCP_CTRL_ADJUST_OFFSET BIT(2) 59 #define OCP_CTRL_ADJUST_DRIFT BIT(3) 60 #define OCP_CTRL_ADJUST_SERVO BIT(8) 61 #define OCP_CTRL_READ_TIME_REQ BIT(30) 62 #define OCP_CTRL_READ_TIME_DONE BIT(31) 63 64 #define OCP_STATUS_IN_SYNC BIT(0) 65 #define OCP_STATUS_IN_HOLDOVER BIT(1) 66 67 #define OCP_SELECT_CLK_NONE 0 68 #define OCP_SELECT_CLK_REG 0xfe 69 70 struct tod_reg { 71 u32 ctrl; 72 u32 status; 73 u32 uart_polarity; 74 u32 version; 75 u32 correction_sec; 76 u32 __pad0[3]; 77 u32 uart_baud; 78 u32 __pad1[3]; 79 u32 utc_status; 80 u32 leap; 81 }; 82 83 #define TOD_CTRL_PROTOCOL BIT(28) 84 #define TOD_CTRL_DISABLE_FMT_A BIT(17) 85 #define TOD_CTRL_DISABLE_FMT_B BIT(16) 86 #define TOD_CTRL_ENABLE BIT(0) 87 #define TOD_CTRL_GNSS_MASK ((1U << 4) - 1) 88 #define TOD_CTRL_GNSS_SHIFT 24 89 90 #define TOD_STATUS_UTC_MASK 0xff 91 #define TOD_STATUS_UTC_VALID BIT(8) 92 #define TOD_STATUS_LEAP_VALID BIT(16) 93 94 struct ts_reg { 95 u32 enable; 96 u32 error; 97 u32 polarity; 98 u32 version; 99 u32 __pad0[4]; 100 u32 cable_delay; 101 u32 __pad1[3]; 102 u32 intr; 103 u32 intr_mask; 104 u32 event_count; 105 u32 __pad2[1]; 106 u32 ts_count; 107 u32 time_ns; 108 u32 time_sec; 109 u32 data_width; 110 u32 data; 111 }; 112 113 struct pps_reg { 114 u32 ctrl; 115 u32 status; 116 u32 __pad0[6]; 117 u32 cable_delay; 118 }; 119 120 #define PPS_STATUS_FILTER_ERR BIT(0) 121 #define PPS_STATUS_SUPERV_ERR BIT(1) 122 123 struct img_reg { 124 u32 version; 125 }; 126 127 struct ptp_ocp_flash_info { 128 const char *name; 129 int pci_offset; 130 int data_size; 131 void *data; 132 }; 133 134 struct ptp_ocp_i2c_info { 135 const char *name; 136 unsigned long fixed_rate; 137 size_t data_size; 138 void *data; 139 }; 140 141 struct ptp_ocp_ext_info { 142 const char *name; 143 int index; 144 irqreturn_t (*irq_fcn)(int irq, void *priv); 145 int (*enable)(void *priv, bool enable); 146 }; 147 148 struct ptp_ocp_ext_src { 149 void __iomem *mem; 150 struct ptp_ocp *bp; 151 struct ptp_ocp_ext_info *info; 152 int irq_vec; 153 }; 154 155 struct ptp_ocp { 156 struct pci_dev *pdev; 157 struct device dev; 158 spinlock_t lock; 159 struct ocp_reg __iomem *reg; 160 struct tod_reg __iomem *tod; 161 struct pps_reg __iomem *pps_to_ext; 162 struct pps_reg __iomem *pps_to_clk; 163 struct ptp_ocp_ext_src *pps; 164 struct ptp_ocp_ext_src *ts0; 165 struct ptp_ocp_ext_src *ts1; 166 struct img_reg __iomem *image; 167 struct ptp_clock *ptp; 168 struct ptp_clock_info ptp_info; 169 struct platform_device *i2c_ctrl; 170 struct platform_device *spi_flash; 171 struct clk_hw *i2c_clk; 172 struct timer_list watchdog; 173 time64_t gnss_lost; 174 int id; 175 int n_irqs; 176 int gnss_port; 177 int mac_port; /* miniature atomic clock */ 178 u8 serial[6]; 179 int flash_start; 180 bool has_serial; 181 }; 182 183 struct ocp_resource { 184 unsigned long offset; 185 int size; 186 int irq_vec; 187 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r); 188 void *extra; 189 unsigned long bp_offset; 190 }; 191 192 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r); 193 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r); 194 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r); 195 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r); 196 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r); 197 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r); 198 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv); 199 static int ptp_ocp_ts_enable(void *priv, bool enable); 200 201 #define bp_assign_entry(bp, res, val) ({ \ 202 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \ 203 *(typeof(val) *)addr = val; \ 204 }) 205 206 #define OCP_RES_LOCATION(member) \ 207 .bp_offset = offsetof(struct ptp_ocp, member) 208 209 #define OCP_MEM_RESOURCE(member) \ 210 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem 211 212 #define OCP_SERIAL_RESOURCE(member) \ 213 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial 214 215 #define OCP_I2C_RESOURCE(member) \ 216 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c 217 218 #define OCP_SPI_RESOURCE(member) \ 219 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi 220 221 #define OCP_EXT_RESOURCE(member) \ 222 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext 223 224 /* This is the MSI vector mapping used. 225 * 0: N/C 226 * 1: TS0 227 * 2: TS1 228 * 3: GPS 229 * 4: GPS2 (n/c) 230 * 5: MAC 231 * 6: SPI IMU (inertial measurement unit) 232 * 7: I2C oscillator 233 * 8: HWICAP 234 * 9: SPI Flash 235 */ 236 237 static struct ocp_resource ocp_fb_resource[] = { 238 { 239 OCP_MEM_RESOURCE(reg), 240 .offset = 0x01000000, .size = 0x10000, 241 }, 242 { 243 OCP_EXT_RESOURCE(ts0), 244 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1, 245 .extra = &(struct ptp_ocp_ext_info) { 246 .name = "ts0", .index = 0, 247 .irq_fcn = ptp_ocp_ts_irq, 248 .enable = ptp_ocp_ts_enable, 249 }, 250 }, 251 { 252 OCP_EXT_RESOURCE(ts1), 253 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2, 254 .extra = &(struct ptp_ocp_ext_info) { 255 .name = "ts1", .index = 1, 256 .irq_fcn = ptp_ocp_ts_irq, 257 .enable = ptp_ocp_ts_enable, 258 }, 259 }, 260 { 261 OCP_MEM_RESOURCE(pps_to_ext), 262 .offset = 0x01030000, .size = 0x10000, 263 }, 264 { 265 OCP_MEM_RESOURCE(pps_to_clk), 266 .offset = 0x01040000, .size = 0x10000, 267 }, 268 { 269 OCP_MEM_RESOURCE(tod), 270 .offset = 0x01050000, .size = 0x10000, 271 }, 272 { 273 OCP_MEM_RESOURCE(image), 274 .offset = 0x00020000, .size = 0x1000, 275 }, 276 { 277 OCP_I2C_RESOURCE(i2c_ctrl), 278 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7, 279 .extra = &(struct ptp_ocp_i2c_info) { 280 .name = "xiic-i2c", 281 .fixed_rate = 50000000, 282 }, 283 }, 284 { 285 OCP_SERIAL_RESOURCE(gnss_port), 286 .offset = 0x00160000 + 0x1000, .irq_vec = 3, 287 }, 288 { 289 OCP_SERIAL_RESOURCE(mac_port), 290 .offset = 0x00180000 + 0x1000, .irq_vec = 5, 291 }, 292 { 293 OCP_SPI_RESOURCE(spi_flash), 294 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9, 295 .extra = &(struct ptp_ocp_flash_info) { 296 .name = "xilinx_spi", .pci_offset = 0, 297 .data_size = sizeof(struct xspi_platform_data), 298 .data = &(struct xspi_platform_data) { 299 .num_chipselect = 1, 300 .bits_per_word = 8, 301 .num_devices = 1, 302 .devices = &(struct spi_board_info) { 303 .modalias = "spi-nor", 304 }, 305 }, 306 }, 307 }, 308 { 309 .setup = ptp_ocp_fb_board_init, 310 }, 311 { } 312 }; 313 314 static const struct pci_device_id ptp_ocp_pcidev_id[] = { 315 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) }, 316 { 0 } 317 }; 318 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id); 319 320 static DEFINE_MUTEX(ptp_ocp_lock); 321 static DEFINE_IDR(ptp_ocp_idr); 322 323 static struct { 324 const char *name; 325 int value; 326 } ptp_ocp_clock[] = { 327 { .name = "NONE", .value = 0 }, 328 { .name = "TOD", .value = 1 }, 329 { .name = "IRIG", .value = 2 }, 330 { .name = "PPS", .value = 3 }, 331 { .name = "PTP", .value = 4 }, 332 { .name = "RTC", .value = 5 }, 333 { .name = "DCF", .value = 6 }, 334 { .name = "REGS", .value = 0xfe }, 335 { .name = "EXT", .value = 0xff }, 336 }; 337 338 static const char * 339 ptp_ocp_clock_name_from_val(int val) 340 { 341 int i; 342 343 for (i = 0; i < ARRAY_SIZE(ptp_ocp_clock); i++) 344 if (ptp_ocp_clock[i].value == val) 345 return ptp_ocp_clock[i].name; 346 return NULL; 347 } 348 349 static int 350 ptp_ocp_clock_val_from_name(const char *name) 351 { 352 const char *clk; 353 int i; 354 355 for (i = 0; i < ARRAY_SIZE(ptp_ocp_clock); i++) { 356 clk = ptp_ocp_clock[i].name; 357 if (!strncasecmp(name, clk, strlen(clk))) 358 return ptp_ocp_clock[i].value; 359 } 360 return -EINVAL; 361 } 362 363 static int 364 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts, 365 struct ptp_system_timestamp *sts) 366 { 367 u32 ctrl, time_sec, time_ns; 368 int i; 369 370 ctrl = ioread32(&bp->reg->ctrl); 371 ctrl |= OCP_CTRL_READ_TIME_REQ; 372 373 ptp_read_system_prets(sts); 374 iowrite32(ctrl, &bp->reg->ctrl); 375 376 for (i = 0; i < 100; i++) { 377 ctrl = ioread32(&bp->reg->ctrl); 378 if (ctrl & OCP_CTRL_READ_TIME_DONE) 379 break; 380 } 381 ptp_read_system_postts(sts); 382 383 time_ns = ioread32(&bp->reg->time_ns); 384 time_sec = ioread32(&bp->reg->time_sec); 385 386 ts->tv_sec = time_sec; 387 ts->tv_nsec = time_ns; 388 389 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT; 390 } 391 392 static int 393 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts, 394 struct ptp_system_timestamp *sts) 395 { 396 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 397 unsigned long flags; 398 int err; 399 400 spin_lock_irqsave(&bp->lock, flags); 401 err = __ptp_ocp_gettime_locked(bp, ts, sts); 402 spin_unlock_irqrestore(&bp->lock, flags); 403 404 return err; 405 } 406 407 static void 408 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts) 409 { 410 u32 ctrl, time_sec, time_ns; 411 u32 select; 412 413 time_ns = ts->tv_nsec; 414 time_sec = ts->tv_sec; 415 416 select = ioread32(&bp->reg->select); 417 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 418 419 iowrite32(time_ns, &bp->reg->adjust_ns); 420 iowrite32(time_sec, &bp->reg->adjust_sec); 421 422 ctrl = ioread32(&bp->reg->ctrl); 423 ctrl |= OCP_CTRL_ADJUST_TIME; 424 iowrite32(ctrl, &bp->reg->ctrl); 425 426 /* restore clock selection */ 427 iowrite32(select >> 16, &bp->reg->select); 428 } 429 430 static int 431 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts) 432 { 433 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 434 unsigned long flags; 435 436 if (ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC) 437 return 0; 438 439 spin_lock_irqsave(&bp->lock, flags); 440 __ptp_ocp_settime_locked(bp, ts); 441 spin_unlock_irqrestore(&bp->lock, flags); 442 443 return 0; 444 } 445 446 static int 447 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns) 448 { 449 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 450 struct timespec64 ts; 451 unsigned long flags; 452 int err; 453 454 if (ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC) 455 return 0; 456 457 spin_lock_irqsave(&bp->lock, flags); 458 err = __ptp_ocp_gettime_locked(bp, &ts, NULL); 459 if (likely(!err)) { 460 timespec64_add_ns(&ts, delta_ns); 461 __ptp_ocp_settime_locked(bp, &ts); 462 } 463 spin_unlock_irqrestore(&bp->lock, flags); 464 465 return err; 466 } 467 468 static int 469 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) 470 { 471 if (scaled_ppm == 0) 472 return 0; 473 474 return -EOPNOTSUPP; 475 } 476 477 static int 478 ptp_ocp_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) 479 { 480 return -EOPNOTSUPP; 481 } 482 483 static int 484 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq, 485 int on) 486 { 487 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info); 488 struct ptp_ocp_ext_src *ext = NULL; 489 int err; 490 491 switch (rq->type) { 492 case PTP_CLK_REQ_EXTTS: 493 switch (rq->extts.index) { 494 case 0: 495 ext = bp->ts0; 496 break; 497 case 1: 498 ext = bp->ts1; 499 break; 500 } 501 break; 502 case PTP_CLK_REQ_PPS: 503 ext = bp->pps; 504 break; 505 default: 506 return -EOPNOTSUPP; 507 } 508 509 err = -ENXIO; 510 if (ext) 511 err = ext->info->enable(ext, on); 512 513 return err; 514 } 515 516 static const struct ptp_clock_info ptp_ocp_clock_info = { 517 .owner = THIS_MODULE, 518 .name = KBUILD_MODNAME, 519 .max_adj = 100000000, 520 .gettimex64 = ptp_ocp_gettimex, 521 .settime64 = ptp_ocp_settime, 522 .adjtime = ptp_ocp_adjtime, 523 .adjfine = ptp_ocp_null_adjfine, 524 .adjphase = ptp_ocp_adjphase, 525 .enable = ptp_ocp_enable, 526 .pps = true, 527 .n_ext_ts = 2, 528 }; 529 530 static void 531 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp) 532 { 533 u32 ctrl, select; 534 535 select = ioread32(&bp->reg->select); 536 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select); 537 538 iowrite32(0, &bp->reg->drift_ns); 539 540 ctrl = ioread32(&bp->reg->ctrl); 541 ctrl |= OCP_CTRL_ADJUST_DRIFT; 542 iowrite32(ctrl, &bp->reg->ctrl); 543 544 /* restore clock selection */ 545 iowrite32(select >> 16, &bp->reg->select); 546 } 547 548 static void 549 ptp_ocp_watchdog(struct timer_list *t) 550 { 551 struct ptp_ocp *bp = from_timer(bp, t, watchdog); 552 unsigned long flags; 553 u32 status; 554 555 status = ioread32(&bp->pps_to_clk->status); 556 557 if (status & PPS_STATUS_SUPERV_ERR) { 558 iowrite32(status, &bp->pps_to_clk->status); 559 if (!bp->gnss_lost) { 560 spin_lock_irqsave(&bp->lock, flags); 561 __ptp_ocp_clear_drift_locked(bp); 562 spin_unlock_irqrestore(&bp->lock, flags); 563 bp->gnss_lost = ktime_get_real_seconds(); 564 } 565 566 } else if (bp->gnss_lost) { 567 bp->gnss_lost = 0; 568 } 569 570 mod_timer(&bp->watchdog, jiffies + HZ); 571 } 572 573 static int 574 ptp_ocp_init_clock(struct ptp_ocp *bp) 575 { 576 struct timespec64 ts; 577 bool sync; 578 u32 ctrl; 579 580 /* make sure clock is enabled */ 581 ctrl = ioread32(&bp->reg->ctrl); 582 ctrl |= OCP_CTRL_ENABLE; 583 iowrite32(ctrl, &bp->reg->ctrl); 584 585 /* NO DRIFT Correction */ 586 /* offset_p:i 1/8, offset_i: 1/16, drift_p: 0, drift_i: 0 */ 587 iowrite32(0x2000, &bp->reg->servo_offset_p); 588 iowrite32(0x1000, &bp->reg->servo_offset_i); 589 iowrite32(0, &bp->reg->servo_drift_p); 590 iowrite32(0, &bp->reg->servo_drift_i); 591 592 /* latch servo values */ 593 ctrl |= OCP_CTRL_ADJUST_SERVO; 594 iowrite32(ctrl, &bp->reg->ctrl); 595 596 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) { 597 dev_err(&bp->pdev->dev, "clock not enabled\n"); 598 return -ENODEV; 599 } 600 601 sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC; 602 if (!sync) { 603 ktime_get_real_ts64(&ts); 604 ptp_ocp_settime(&bp->ptp_info, &ts); 605 } 606 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL)) 607 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n", 608 ts.tv_sec, ts.tv_nsec, 609 sync ? "in-sync" : "UNSYNCED"); 610 611 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0); 612 mod_timer(&bp->watchdog, jiffies + HZ); 613 614 return 0; 615 } 616 617 static void 618 ptp_ocp_tod_info(struct ptp_ocp *bp) 619 { 620 static const char * const proto_name[] = { 621 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none", 622 "UBX", "UBX_UTC", "UBX_LS", "UBX_none" 623 }; 624 static const char * const gnss_name[] = { 625 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU", 626 }; 627 u32 version, ctrl, reg; 628 int idx; 629 630 version = ioread32(&bp->tod->version); 631 dev_info(&bp->pdev->dev, "TOD Version %d.%d.%d\n", 632 version >> 24, (version >> 16) & 0xff, version & 0xffff); 633 634 ctrl = ioread32(&bp->tod->ctrl); 635 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE; 636 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B); 637 iowrite32(ctrl, &bp->tod->ctrl); 638 639 ctrl = ioread32(&bp->tod->ctrl); 640 idx = ctrl & TOD_CTRL_PROTOCOL ? 4 : 0; 641 idx += (ctrl >> 16) & 3; 642 dev_info(&bp->pdev->dev, "control: %x\n", ctrl); 643 dev_info(&bp->pdev->dev, "TOD Protocol %s %s\n", proto_name[idx], 644 ctrl & TOD_CTRL_ENABLE ? "enabled" : ""); 645 646 idx = (ctrl >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK; 647 if (idx < ARRAY_SIZE(gnss_name)) 648 dev_info(&bp->pdev->dev, "GNSS %s\n", gnss_name[idx]); 649 650 reg = ioread32(&bp->tod->status); 651 dev_info(&bp->pdev->dev, "status: %x\n", reg); 652 653 reg = ioread32(&bp->tod->correction_sec); 654 dev_info(&bp->pdev->dev, "correction: %d\n", reg); 655 656 reg = ioread32(&bp->tod->utc_status); 657 dev_info(&bp->pdev->dev, "utc_status: %x\n", reg); 658 dev_info(&bp->pdev->dev, "utc_offset: %d valid:%d leap_valid:%d\n", 659 reg & TOD_STATUS_UTC_MASK, reg & TOD_STATUS_UTC_VALID ? 1 : 0, 660 reg & TOD_STATUS_LEAP_VALID ? 1 : 0); 661 } 662 663 static int 664 ptp_ocp_firstchild(struct device *dev, void *data) 665 { 666 return 1; 667 } 668 669 static int 670 ptp_ocp_read_i2c(struct i2c_adapter *adap, u8 addr, u8 reg, u8 sz, u8 *data) 671 { 672 struct i2c_msg msgs[2] = { 673 { 674 .addr = addr, 675 .len = 1, 676 .buf = ®, 677 }, 678 { 679 .addr = addr, 680 .flags = I2C_M_RD, 681 .len = 2, 682 .buf = data, 683 }, 684 }; 685 int err; 686 u8 len; 687 688 /* xiic-i2c for some stupid reason only does 2 byte reads. */ 689 while (sz) { 690 len = min_t(u8, sz, 2); 691 msgs[1].len = len; 692 err = i2c_transfer(adap, msgs, 2); 693 if (err != msgs[1].len) 694 return err; 695 msgs[1].buf += len; 696 reg += len; 697 sz -= len; 698 } 699 return 0; 700 } 701 702 static void 703 ptp_ocp_get_serial_number(struct ptp_ocp *bp) 704 { 705 struct i2c_adapter *adap; 706 struct device *dev; 707 int err; 708 709 dev = device_find_child(&bp->i2c_ctrl->dev, NULL, ptp_ocp_firstchild); 710 if (!dev) { 711 dev_err(&bp->pdev->dev, "Can't find I2C adapter\n"); 712 return; 713 } 714 715 adap = i2c_verify_adapter(dev); 716 if (!adap) { 717 dev_err(&bp->pdev->dev, "device '%s' isn't an I2C adapter\n", 718 dev_name(dev)); 719 goto out; 720 } 721 722 err = ptp_ocp_read_i2c(adap, 0x58, 0x9A, 6, bp->serial); 723 if (err) { 724 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", err); 725 goto out; 726 } 727 728 bp->has_serial = true; 729 730 out: 731 put_device(dev); 732 } 733 734 static void 735 ptp_ocp_info(struct ptp_ocp *bp) 736 { 737 u32 version, select; 738 739 version = ioread32(&bp->reg->version); 740 select = ioread32(&bp->reg->select); 741 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n", 742 version >> 24, (version >> 16) & 0xff, version & 0xffff, 743 ptp_ocp_clock_name_from_val(select >> 16), 744 ptp_clock_index(bp->ptp)); 745 746 if (bp->tod) 747 ptp_ocp_tod_info(bp); 748 } 749 750 static struct device * 751 ptp_ocp_find_flash(struct ptp_ocp *bp) 752 { 753 struct device *dev, *last; 754 755 last = NULL; 756 dev = &bp->spi_flash->dev; 757 758 while ((dev = device_find_child(dev, NULL, ptp_ocp_firstchild))) { 759 if (!strcmp("mtd", dev_bus_name(dev))) 760 break; 761 put_device(last); 762 last = dev; 763 } 764 put_device(last); 765 766 return dev; 767 } 768 769 static int 770 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev, 771 const struct firmware *fw) 772 { 773 struct mtd_info *mtd = dev_get_drvdata(dev); 774 struct ptp_ocp *bp = devlink_priv(devlink); 775 size_t off, len, resid, wrote; 776 struct erase_info erase; 777 size_t base, blksz; 778 int err = 0; 779 780 off = 0; 781 base = bp->flash_start; 782 blksz = 4096; 783 resid = fw->size; 784 785 while (resid) { 786 devlink_flash_update_status_notify(devlink, "Flashing", 787 NULL, off, fw->size); 788 789 len = min_t(size_t, resid, blksz); 790 erase.addr = base + off; 791 erase.len = blksz; 792 793 err = mtd_erase(mtd, &erase); 794 if (err) 795 goto out; 796 797 err = mtd_write(mtd, base + off, len, &wrote, &fw->data[off]); 798 if (err) 799 goto out; 800 801 off += blksz; 802 resid -= len; 803 } 804 out: 805 return err; 806 } 807 808 static int 809 ptp_ocp_devlink_flash_update(struct devlink *devlink, 810 struct devlink_flash_update_params *params, 811 struct netlink_ext_ack *extack) 812 { 813 struct ptp_ocp *bp = devlink_priv(devlink); 814 struct device *dev; 815 const char *msg; 816 int err; 817 818 dev = ptp_ocp_find_flash(bp); 819 if (!dev) { 820 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n"); 821 return -ENODEV; 822 } 823 824 devlink_flash_update_status_notify(devlink, "Preparing to flash", 825 NULL, 0, 0); 826 827 err = ptp_ocp_devlink_flash(devlink, dev, params->fw); 828 829 msg = err ? "Flash error" : "Flash complete"; 830 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0); 831 832 put_device(dev); 833 return err; 834 } 835 836 static int 837 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req, 838 struct netlink_ext_ack *extack) 839 { 840 struct ptp_ocp *bp = devlink_priv(devlink); 841 char buf[32]; 842 int err; 843 844 err = devlink_info_driver_name_put(req, KBUILD_MODNAME); 845 if (err) 846 return err; 847 848 if (bp->image) { 849 u32 ver = ioread32(&bp->image->version); 850 851 if (ver & 0xffff) { 852 sprintf(buf, "%d", ver); 853 err = devlink_info_version_running_put(req, 854 "fw", 855 buf); 856 } else { 857 sprintf(buf, "%d", ver >> 16); 858 err = devlink_info_version_running_put(req, 859 "loader", 860 buf); 861 } 862 if (err) 863 return err; 864 } 865 866 if (!bp->has_serial) 867 ptp_ocp_get_serial_number(bp); 868 869 if (bp->has_serial) { 870 sprintf(buf, "%pM", bp->serial); 871 err = devlink_info_serial_number_put(req, buf); 872 if (err) 873 return err; 874 } 875 876 return 0; 877 } 878 879 static const struct devlink_ops ptp_ocp_devlink_ops = { 880 .flash_update = ptp_ocp_devlink_flash_update, 881 .info_get = ptp_ocp_devlink_info_get, 882 }; 883 884 static void __iomem * 885 __ptp_ocp_get_mem(struct ptp_ocp *bp, unsigned long start, int size) 886 { 887 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp"); 888 889 return devm_ioremap_resource(&bp->pdev->dev, &res); 890 } 891 892 static void __iomem * 893 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r) 894 { 895 unsigned long start; 896 897 start = pci_resource_start(bp->pdev, 0) + r->offset; 898 return __ptp_ocp_get_mem(bp, start, r->size); 899 } 900 901 static void 902 ptp_ocp_set_irq_resource(struct resource *res, int irq) 903 { 904 struct resource r = DEFINE_RES_IRQ(irq); 905 *res = r; 906 } 907 908 static void 909 ptp_ocp_set_mem_resource(struct resource *res, unsigned long start, int size) 910 { 911 struct resource r = DEFINE_RES_MEM(start, size); 912 *res = r; 913 } 914 915 static int 916 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r) 917 { 918 struct ptp_ocp_flash_info *info; 919 struct pci_dev *pdev = bp->pdev; 920 struct platform_device *p; 921 struct resource res[2]; 922 unsigned long start; 923 int id; 924 925 /* XXX hack to work around old FPGA */ 926 if (bp->n_irqs < 10) { 927 dev_err(&bp->pdev->dev, "FPGA does not have SPI devices\n"); 928 return 0; 929 } 930 931 if (r->irq_vec > bp->n_irqs) { 932 dev_err(&bp->pdev->dev, "spi device irq %d out of range\n", 933 r->irq_vec); 934 return 0; 935 } 936 937 start = pci_resource_start(pdev, 0) + r->offset; 938 ptp_ocp_set_mem_resource(&res[0], start, r->size); 939 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 940 941 info = r->extra; 942 id = pci_dev_id(pdev) << 1; 943 id += info->pci_offset; 944 945 p = platform_device_register_resndata(&pdev->dev, info->name, id, 946 res, 2, info->data, 947 info->data_size); 948 if (IS_ERR(p)) 949 return PTR_ERR(p); 950 951 bp_assign_entry(bp, r, p); 952 953 return 0; 954 } 955 956 static struct platform_device * 957 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id) 958 { 959 struct ptp_ocp_i2c_info *info; 960 struct resource res[2]; 961 unsigned long start; 962 963 info = r->extra; 964 start = pci_resource_start(pdev, 0) + r->offset; 965 ptp_ocp_set_mem_resource(&res[0], start, r->size); 966 ptp_ocp_set_irq_resource(&res[1], pci_irq_vector(pdev, r->irq_vec)); 967 968 return platform_device_register_resndata(&pdev->dev, info->name, 969 id, res, 2, 970 info->data, info->data_size); 971 } 972 973 static int 974 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r) 975 { 976 struct pci_dev *pdev = bp->pdev; 977 struct ptp_ocp_i2c_info *info; 978 struct platform_device *p; 979 struct clk_hw *clk; 980 char buf[32]; 981 int id; 982 983 if (r->irq_vec > bp->n_irqs) { 984 dev_err(&bp->pdev->dev, "i2c device irq %d out of range\n", 985 r->irq_vec); 986 return 0; 987 } 988 989 info = r->extra; 990 id = pci_dev_id(bp->pdev); 991 992 sprintf(buf, "AXI.%d", id); 993 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0, 994 info->fixed_rate); 995 if (IS_ERR(clk)) 996 return PTR_ERR(clk); 997 bp->i2c_clk = clk; 998 999 sprintf(buf, "%s.%d", info->name, id); 1000 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf); 1001 p = ptp_ocp_i2c_bus(bp->pdev, r, id); 1002 if (IS_ERR(p)) 1003 return PTR_ERR(p); 1004 1005 bp_assign_entry(bp, r, p); 1006 1007 return 0; 1008 } 1009 1010 static irqreturn_t 1011 ptp_ocp_ts_irq(int irq, void *priv) 1012 { 1013 struct ptp_ocp_ext_src *ext = priv; 1014 struct ts_reg __iomem *reg = ext->mem; 1015 struct ptp_clock_event ev; 1016 u32 sec, nsec; 1017 1018 /* XXX should fix API - this converts s/ns -> ts -> s/ns */ 1019 sec = ioread32(®->time_sec); 1020 nsec = ioread32(®->time_ns); 1021 1022 ev.type = PTP_CLOCK_EXTTS; 1023 ev.index = ext->info->index; 1024 ev.timestamp = sec * 1000000000ULL + nsec; 1025 1026 ptp_clock_event(ext->bp->ptp, &ev); 1027 1028 iowrite32(1, ®->intr); /* write 1 to ack */ 1029 1030 return IRQ_HANDLED; 1031 } 1032 1033 static int 1034 ptp_ocp_ts_enable(void *priv, bool enable) 1035 { 1036 struct ptp_ocp_ext_src *ext = priv; 1037 struct ts_reg __iomem *reg = ext->mem; 1038 1039 if (enable) { 1040 iowrite32(1, ®->enable); 1041 iowrite32(1, ®->intr_mask); 1042 iowrite32(1, ®->intr); 1043 } else { 1044 iowrite32(0, ®->intr_mask); 1045 iowrite32(0, ®->enable); 1046 } 1047 1048 return 0; 1049 } 1050 1051 static void 1052 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext) 1053 { 1054 ext->info->enable(ext, false); 1055 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext); 1056 kfree(ext); 1057 } 1058 1059 static int 1060 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r) 1061 { 1062 struct pci_dev *pdev = bp->pdev; 1063 struct ptp_ocp_ext_src *ext; 1064 int err; 1065 1066 ext = kzalloc(sizeof(*ext), GFP_KERNEL); 1067 if (!ext) 1068 return -ENOMEM; 1069 1070 err = -EINVAL; 1071 ext->mem = ptp_ocp_get_mem(bp, r); 1072 if (!ext->mem) 1073 goto out; 1074 1075 ext->bp = bp; 1076 ext->info = r->extra; 1077 ext->irq_vec = r->irq_vec; 1078 1079 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL, 1080 ext, "ocp%d.%s", bp->id, ext->info->name); 1081 if (err) { 1082 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec); 1083 goto out; 1084 } 1085 1086 bp_assign_entry(bp, r, ext); 1087 1088 return 0; 1089 1090 out: 1091 kfree(ext); 1092 return err; 1093 } 1094 1095 static int 1096 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r) 1097 { 1098 struct pci_dev *pdev = bp->pdev; 1099 struct uart_8250_port uart; 1100 1101 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets 1102 * the serial port device claim and release the pci resource. 1103 */ 1104 memset(&uart, 0, sizeof(uart)); 1105 uart.port.dev = &pdev->dev; 1106 uart.port.iotype = UPIO_MEM; 1107 uart.port.regshift = 2; 1108 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset; 1109 uart.port.irq = pci_irq_vector(pdev, r->irq_vec); 1110 uart.port.uartclk = 50000000; 1111 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP; 1112 uart.port.type = PORT_16550A; 1113 1114 return serial8250_register_8250_port(&uart); 1115 } 1116 1117 static int 1118 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r) 1119 { 1120 int port; 1121 1122 if (r->irq_vec > bp->n_irqs) { 1123 dev_err(&bp->pdev->dev, "serial device irq %d out of range\n", 1124 r->irq_vec); 1125 return 0; 1126 } 1127 1128 port = ptp_ocp_serial_line(bp, r); 1129 if (port < 0) 1130 return port; 1131 1132 bp_assign_entry(bp, r, port); 1133 1134 return 0; 1135 } 1136 1137 static int 1138 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r) 1139 { 1140 void __iomem *mem; 1141 1142 mem = ptp_ocp_get_mem(bp, r); 1143 if (!mem) 1144 return -EINVAL; 1145 1146 bp_assign_entry(bp, r, mem); 1147 1148 return 0; 1149 } 1150 1151 /* FB specific board initializers; last "resource" registered. */ 1152 static int 1153 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r) 1154 { 1155 bp->flash_start = 1024 * 4096; 1156 1157 return ptp_ocp_init_clock(bp); 1158 } 1159 1160 static int 1161 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data) 1162 { 1163 struct ocp_resource *r, *table; 1164 int err = 0; 1165 1166 table = (struct ocp_resource *)driver_data; 1167 for (r = table; r->setup; r++) { 1168 err = r->setup(bp, r); 1169 if (err) 1170 break; 1171 } 1172 return err; 1173 } 1174 1175 static ssize_t 1176 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf) 1177 { 1178 struct ptp_ocp *bp = dev_get_drvdata(dev); 1179 1180 if (!bp->has_serial) 1181 ptp_ocp_get_serial_number(bp); 1182 1183 return sysfs_emit(buf, "%pM\n", bp->serial); 1184 } 1185 static DEVICE_ATTR_RO(serialnum); 1186 1187 static ssize_t 1188 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf) 1189 { 1190 struct ptp_ocp *bp = dev_get_drvdata(dev); 1191 ssize_t ret; 1192 1193 if (bp->gnss_lost) 1194 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost); 1195 else 1196 ret = sysfs_emit(buf, "SYNC\n"); 1197 1198 return ret; 1199 } 1200 static DEVICE_ATTR_RO(gnss_sync); 1201 1202 static ssize_t 1203 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf) 1204 { 1205 struct ptp_ocp *bp = dev_get_drvdata(dev); 1206 const char *p; 1207 u32 select; 1208 1209 select = ioread32(&bp->reg->select); 1210 p = ptp_ocp_clock_name_from_val(select >> 16); 1211 1212 return sysfs_emit(buf, "%s\n", p); 1213 } 1214 1215 static ssize_t 1216 clock_source_store(struct device *dev, struct device_attribute *attr, 1217 const char *buf, size_t count) 1218 { 1219 struct ptp_ocp *bp = dev_get_drvdata(dev); 1220 unsigned long flags; 1221 int val; 1222 1223 val = ptp_ocp_clock_val_from_name(buf); 1224 if (val < 0) 1225 return val; 1226 1227 spin_lock_irqsave(&bp->lock, flags); 1228 iowrite32(val, &bp->reg->select); 1229 spin_unlock_irqrestore(&bp->lock, flags); 1230 1231 return count; 1232 } 1233 static DEVICE_ATTR_RW(clock_source); 1234 1235 static ssize_t 1236 available_clock_sources_show(struct device *dev, 1237 struct device_attribute *attr, char *buf) 1238 { 1239 const char *clk; 1240 ssize_t count; 1241 int i; 1242 1243 count = 0; 1244 for (i = 0; i < ARRAY_SIZE(ptp_ocp_clock); i++) { 1245 clk = ptp_ocp_clock[i].name; 1246 count += sysfs_emit_at(buf, count, "%s ", clk); 1247 } 1248 if (count) 1249 count--; 1250 count += sysfs_emit_at(buf, count, "\n"); 1251 return count; 1252 } 1253 static DEVICE_ATTR_RO(available_clock_sources); 1254 1255 static struct attribute *timecard_attrs[] = { 1256 &dev_attr_serialnum.attr, 1257 &dev_attr_gnss_sync.attr, 1258 &dev_attr_clock_source.attr, 1259 &dev_attr_available_clock_sources.attr, 1260 NULL, 1261 }; 1262 ATTRIBUTE_GROUPS(timecard); 1263 1264 static void 1265 ptp_ocp_dev_release(struct device *dev) 1266 { 1267 struct ptp_ocp *bp = dev_get_drvdata(dev); 1268 1269 mutex_lock(&ptp_ocp_lock); 1270 idr_remove(&ptp_ocp_idr, bp->id); 1271 mutex_unlock(&ptp_ocp_lock); 1272 } 1273 1274 static int 1275 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev) 1276 { 1277 int err; 1278 1279 mutex_lock(&ptp_ocp_lock); 1280 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL); 1281 mutex_unlock(&ptp_ocp_lock); 1282 if (err < 0) { 1283 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err); 1284 return err; 1285 } 1286 bp->id = err; 1287 1288 bp->ptp_info = ptp_ocp_clock_info; 1289 spin_lock_init(&bp->lock); 1290 bp->gnss_port = -1; 1291 bp->mac_port = -1; 1292 bp->pdev = pdev; 1293 1294 device_initialize(&bp->dev); 1295 dev_set_name(&bp->dev, "ocp%d", bp->id); 1296 bp->dev.class = &timecard_class; 1297 bp->dev.parent = &pdev->dev; 1298 bp->dev.release = ptp_ocp_dev_release; 1299 dev_set_drvdata(&bp->dev, bp); 1300 1301 err = device_add(&bp->dev); 1302 if (err) { 1303 dev_err(&bp->dev, "device add failed: %d\n", err); 1304 goto out; 1305 } 1306 1307 pci_set_drvdata(pdev, bp); 1308 1309 return 0; 1310 1311 out: 1312 ptp_ocp_dev_release(&bp->dev); 1313 put_device(&bp->dev); 1314 return err; 1315 } 1316 1317 static void 1318 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link) 1319 { 1320 struct device *dev = &bp->dev; 1321 1322 if (sysfs_create_link(&dev->kobj, &child->kobj, link)) 1323 dev_err(dev, "%s symlink failed\n", link); 1324 } 1325 1326 static void 1327 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link) 1328 { 1329 struct device *dev, *child; 1330 1331 dev = &bp->pdev->dev; 1332 1333 child = device_find_child_by_name(dev, name); 1334 if (!child) { 1335 dev_err(dev, "Could not find device %s\n", name); 1336 return; 1337 } 1338 1339 ptp_ocp_symlink(bp, child, link); 1340 put_device(child); 1341 } 1342 1343 static int 1344 ptp_ocp_complete(struct ptp_ocp *bp) 1345 { 1346 struct pps_device *pps; 1347 char buf[32]; 1348 1349 if (bp->gnss_port != -1) { 1350 sprintf(buf, "ttyS%d", bp->gnss_port); 1351 ptp_ocp_link_child(bp, buf, "ttyGNSS"); 1352 } 1353 if (bp->mac_port != -1) { 1354 sprintf(buf, "ttyS%d", bp->mac_port); 1355 ptp_ocp_link_child(bp, buf, "ttyMAC"); 1356 } 1357 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp)); 1358 ptp_ocp_link_child(bp, buf, "ptp"); 1359 1360 pps = pps_lookup_dev(bp->ptp); 1361 if (pps) 1362 ptp_ocp_symlink(bp, pps->dev, "pps"); 1363 1364 if (device_add_groups(&bp->dev, timecard_groups)) 1365 pr_err("device add groups failed\n"); 1366 1367 return 0; 1368 } 1369 1370 static void 1371 ptp_ocp_resource_summary(struct ptp_ocp *bp) 1372 { 1373 struct device *dev = &bp->pdev->dev; 1374 1375 if (bp->image) { 1376 u32 ver = ioread32(&bp->image->version); 1377 1378 dev_info(dev, "version %x\n", ver); 1379 if (ver & 0xffff) 1380 dev_info(dev, "regular image, version %d\n", 1381 ver & 0xffff); 1382 else 1383 dev_info(dev, "golden image, version %d\n", 1384 ver >> 16); 1385 } 1386 if (bp->gnss_port != -1) 1387 dev_info(dev, "GNSS @ /dev/ttyS%d 115200\n", bp->gnss_port); 1388 if (bp->mac_port != -1) 1389 dev_info(dev, "MAC @ /dev/ttyS%d 57600\n", bp->mac_port); 1390 } 1391 1392 static void 1393 ptp_ocp_detach_sysfs(struct ptp_ocp *bp) 1394 { 1395 struct device *dev = &bp->dev; 1396 1397 sysfs_remove_link(&dev->kobj, "ttyGNSS"); 1398 sysfs_remove_link(&dev->kobj, "ttyMAC"); 1399 sysfs_remove_link(&dev->kobj, "ptp"); 1400 sysfs_remove_link(&dev->kobj, "pps"); 1401 device_remove_groups(dev, timecard_groups); 1402 } 1403 1404 static void 1405 ptp_ocp_detach(struct ptp_ocp *bp) 1406 { 1407 ptp_ocp_detach_sysfs(bp); 1408 if (timer_pending(&bp->watchdog)) 1409 del_timer_sync(&bp->watchdog); 1410 if (bp->ts0) 1411 ptp_ocp_unregister_ext(bp->ts0); 1412 if (bp->ts1) 1413 ptp_ocp_unregister_ext(bp->ts1); 1414 if (bp->pps) 1415 ptp_ocp_unregister_ext(bp->pps); 1416 if (bp->gnss_port != -1) 1417 serial8250_unregister_port(bp->gnss_port); 1418 if (bp->mac_port != -1) 1419 serial8250_unregister_port(bp->mac_port); 1420 if (bp->spi_flash) 1421 platform_device_unregister(bp->spi_flash); 1422 if (bp->i2c_ctrl) 1423 platform_device_unregister(bp->i2c_ctrl); 1424 if (bp->i2c_clk) 1425 clk_hw_unregister_fixed_rate(bp->i2c_clk); 1426 if (bp->n_irqs) 1427 pci_free_irq_vectors(bp->pdev); 1428 if (bp->ptp) 1429 ptp_clock_unregister(bp->ptp); 1430 device_unregister(&bp->dev); 1431 } 1432 1433 static int 1434 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1435 { 1436 struct devlink *devlink; 1437 struct ptp_ocp *bp; 1438 int err; 1439 1440 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev); 1441 if (!devlink) { 1442 dev_err(&pdev->dev, "devlink_alloc failed\n"); 1443 return -ENOMEM; 1444 } 1445 1446 err = devlink_register(devlink); 1447 if (err) 1448 goto out_free; 1449 1450 err = pci_enable_device(pdev); 1451 if (err) { 1452 dev_err(&pdev->dev, "pci_enable_device\n"); 1453 goto out_unregister; 1454 } 1455 1456 bp = devlink_priv(devlink); 1457 err = ptp_ocp_device_init(bp, pdev); 1458 if (err) 1459 goto out_disable; 1460 1461 /* compat mode. 1462 * Older FPGA firmware only returns 2 irq's. 1463 * allow this - if not all of the IRQ's are returned, skip the 1464 * extra devices and just register the clock. 1465 */ 1466 err = pci_alloc_irq_vectors(pdev, 1, 10, PCI_IRQ_MSI | PCI_IRQ_MSIX); 1467 if (err < 0) { 1468 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err); 1469 goto out; 1470 } 1471 bp->n_irqs = err; 1472 pci_set_master(pdev); 1473 1474 err = ptp_ocp_register_resources(bp, id->driver_data); 1475 if (err) 1476 goto out; 1477 1478 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev); 1479 if (IS_ERR(bp->ptp)) { 1480 err = PTR_ERR(bp->ptp); 1481 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err); 1482 bp->ptp = NULL; 1483 goto out; 1484 } 1485 1486 err = ptp_ocp_complete(bp); 1487 if (err) 1488 goto out; 1489 1490 ptp_ocp_info(bp); 1491 ptp_ocp_resource_summary(bp); 1492 1493 return 0; 1494 1495 out: 1496 ptp_ocp_detach(bp); 1497 pci_set_drvdata(pdev, NULL); 1498 out_disable: 1499 pci_disable_device(pdev); 1500 out_unregister: 1501 devlink_unregister(devlink); 1502 out_free: 1503 devlink_free(devlink); 1504 1505 return err; 1506 } 1507 1508 static void 1509 ptp_ocp_remove(struct pci_dev *pdev) 1510 { 1511 struct ptp_ocp *bp = pci_get_drvdata(pdev); 1512 struct devlink *devlink = priv_to_devlink(bp); 1513 1514 ptp_ocp_detach(bp); 1515 pci_set_drvdata(pdev, NULL); 1516 pci_disable_device(pdev); 1517 1518 devlink_unregister(devlink); 1519 devlink_free(devlink); 1520 } 1521 1522 static struct pci_driver ptp_ocp_driver = { 1523 .name = KBUILD_MODNAME, 1524 .id_table = ptp_ocp_pcidev_id, 1525 .probe = ptp_ocp_probe, 1526 .remove = ptp_ocp_remove, 1527 }; 1528 1529 static int 1530 ptp_ocp_i2c_notifier_call(struct notifier_block *nb, 1531 unsigned long action, void *data) 1532 { 1533 struct device *dev, *child = data; 1534 struct ptp_ocp *bp; 1535 bool add; 1536 1537 switch (action) { 1538 case BUS_NOTIFY_ADD_DEVICE: 1539 case BUS_NOTIFY_DEL_DEVICE: 1540 add = action == BUS_NOTIFY_ADD_DEVICE; 1541 break; 1542 default: 1543 return 0; 1544 } 1545 1546 if (!i2c_verify_adapter(child)) 1547 return 0; 1548 1549 dev = child; 1550 while ((dev = dev->parent)) 1551 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME)) 1552 goto found; 1553 return 0; 1554 1555 found: 1556 bp = dev_get_drvdata(dev); 1557 if (add) 1558 ptp_ocp_symlink(bp, child, "i2c"); 1559 else 1560 sysfs_remove_link(&bp->dev.kobj, "i2c"); 1561 1562 return 0; 1563 } 1564 1565 static struct notifier_block ptp_ocp_i2c_notifier = { 1566 .notifier_call = ptp_ocp_i2c_notifier_call, 1567 }; 1568 1569 static int __init 1570 ptp_ocp_init(void) 1571 { 1572 const char *what; 1573 int err; 1574 1575 what = "timecard class"; 1576 err = class_register(&timecard_class); 1577 if (err) 1578 goto out; 1579 1580 what = "i2c notifier"; 1581 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 1582 if (err) 1583 goto out_notifier; 1584 1585 what = "ptp_ocp driver"; 1586 err = pci_register_driver(&ptp_ocp_driver); 1587 if (err) 1588 goto out_register; 1589 1590 return 0; 1591 1592 out_register: 1593 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 1594 out_notifier: 1595 class_unregister(&timecard_class); 1596 out: 1597 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err); 1598 return err; 1599 } 1600 1601 static void __exit 1602 ptp_ocp_fini(void) 1603 { 1604 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier); 1605 pci_unregister_driver(&ptp_ocp_driver); 1606 class_unregister(&timecard_class); 1607 } 1608 1609 module_init(ptp_ocp_init); 1610 module_exit(ptp_ocp_fini); 1611 1612 MODULE_DESCRIPTION("OpenCompute TimeCard driver"); 1613 MODULE_LICENSE("GPL v2"); 1614