1*1802d0beSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 241d32cfcSBaolin Wang /* 341d32cfcSBaolin Wang * Driver header file for pin controller driver 441d32cfcSBaolin Wang * Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com 541d32cfcSBaolin Wang */ 641d32cfcSBaolin Wang 741d32cfcSBaolin Wang #ifndef __PINCTRL_SPRD_H__ 841d32cfcSBaolin Wang #define __PINCTRL_SPRD_H__ 941d32cfcSBaolin Wang 1041d32cfcSBaolin Wang struct platform_device; 1141d32cfcSBaolin Wang 1241d32cfcSBaolin Wang #define NUM_OFFSET (20) 1341d32cfcSBaolin Wang #define TYPE_OFFSET (16) 1441d32cfcSBaolin Wang #define BIT_OFFSET (8) 1541d32cfcSBaolin Wang #define WIDTH_OFFSET (4) 1641d32cfcSBaolin Wang 1741d32cfcSBaolin Wang #define SPRD_PIN_INFO(num, type, offset, width, reg) \ 1841d32cfcSBaolin Wang (((num) & 0xFFF) << NUM_OFFSET | \ 1941d32cfcSBaolin Wang ((type) & 0xF) << TYPE_OFFSET | \ 2041d32cfcSBaolin Wang ((offset) & 0xFF) << BIT_OFFSET | \ 2141d32cfcSBaolin Wang ((width) & 0xF) << WIDTH_OFFSET | \ 2241d32cfcSBaolin Wang ((reg) & 0xF)) 2341d32cfcSBaolin Wang 2441d32cfcSBaolin Wang #define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin) 2541d32cfcSBaolin Wang 2641d32cfcSBaolin Wang #define SPRD_PINCTRL_PIN_DATA(a, b) \ 2741d32cfcSBaolin Wang { \ 2841d32cfcSBaolin Wang .name = b, \ 2941d32cfcSBaolin Wang .num = (((a) >> NUM_OFFSET) & 0xfff), \ 3041d32cfcSBaolin Wang .type = (((a) >> TYPE_OFFSET) & 0xf), \ 3141d32cfcSBaolin Wang .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \ 3241d32cfcSBaolin Wang .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \ 3341d32cfcSBaolin Wang .reg = ((a) & 0xf) \ 3441d32cfcSBaolin Wang } 3541d32cfcSBaolin Wang 3641d32cfcSBaolin Wang enum pin_type { 3741d32cfcSBaolin Wang GLOBAL_CTRL_PIN, 3841d32cfcSBaolin Wang COMMON_PIN, 3941d32cfcSBaolin Wang MISC_PIN, 4041d32cfcSBaolin Wang }; 4141d32cfcSBaolin Wang 4241d32cfcSBaolin Wang struct sprd_pins_info { 4341d32cfcSBaolin Wang const char *name; 4441d32cfcSBaolin Wang unsigned int num; 4541d32cfcSBaolin Wang enum pin_type type; 4641d32cfcSBaolin Wang 4741d32cfcSBaolin Wang /* for global control pins configuration */ 4841d32cfcSBaolin Wang unsigned long bit_offset; 4941d32cfcSBaolin Wang unsigned long bit_width; 5041d32cfcSBaolin Wang unsigned int reg; 5141d32cfcSBaolin Wang }; 5241d32cfcSBaolin Wang 5341d32cfcSBaolin Wang int sprd_pinctrl_core_probe(struct platform_device *pdev, 5441d32cfcSBaolin Wang struct sprd_pins_info *sprd_soc_pin_info, 5541d32cfcSBaolin Wang int pins_cnt); 5641d32cfcSBaolin Wang int sprd_pinctrl_remove(struct platform_device *pdev); 5741d32cfcSBaolin Wang void sprd_pinctrl_shutdown(struct platform_device *pdev); 5841d32cfcSBaolin Wang 5941d32cfcSBaolin Wang #endif /* __PINCTRL_SPRD_H__ */ 60