1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/io.h> 12 #include <linux/interrupt.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/pinconf-generic.h> 17 #include <linux/pinctrl/pinconf.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/spinlock.h> 21 22 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 23 24 #include "../core.h" 25 #include "../pinconf.h" 26 #include "../pinmux.h" 27 28 #define DRV_NAME "pinctrl-rzg2l" 29 30 /* 31 * Use 16 lower bits [15:0] for pin identifier 32 * Use 16 higher bits [31:16] for pin mux function 33 */ 34 #define MUX_PIN_ID_MASK GENMASK(15, 0) 35 #define MUX_FUNC_MASK GENMASK(31, 16) 36 #define MUX_FUNC_OFFS 16 37 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 38 39 /* PIN capabilities */ 40 #define PIN_CFG_IOLH_A BIT(0) 41 #define PIN_CFG_IOLH_B BIT(1) 42 #define PIN_CFG_SR BIT(2) 43 #define PIN_CFG_IEN BIT(3) 44 #define PIN_CFG_PUPD BIT(4) 45 #define PIN_CFG_IO_VMC_SD0 BIT(5) 46 #define PIN_CFG_IO_VMC_SD1 BIT(6) 47 #define PIN_CFG_IO_VMC_QSPI BIT(7) 48 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 49 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 50 #define PIN_CFG_FILONOFF BIT(10) 51 #define PIN_CFG_FILNUM BIT(11) 52 #define PIN_CFG_FILCLKSEL BIT(12) 53 54 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ 55 PIN_CFG_SR | \ 56 PIN_CFG_PUPD | \ 57 PIN_CFG_FILONOFF | \ 58 PIN_CFG_FILNUM | \ 59 PIN_CFG_FILCLKSEL) 60 61 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 62 PIN_CFG_FILONOFF | \ 63 PIN_CFG_FILNUM | \ 64 PIN_CFG_FILCLKSEL) 65 66 /* 67 * n indicates number of pins in the port, a is the register index 68 * and f is pin configuration capabilities supported. 69 */ 70 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 71 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 72 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) 73 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) 74 75 /* 76 * BIT(31) indicates dedicated pin, p is the register index while 77 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 78 * (b * 8) and f is the pin configuration capabilities supported. 79 */ 80 #define RZG2L_SINGLE_PIN BIT(31) 81 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 82 ((p) << 24) | ((b) << 20) | (f)) 83 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) 84 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 85 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) 86 87 #define P(n) (0x0000 + 0x10 + (n)) 88 #define PM(n) (0x0100 + 0x20 + (n) * 2) 89 #define PMC(n) (0x0200 + 0x10 + (n)) 90 #define PFC(n) (0x0400 + 0x40 + (n) * 4) 91 #define PIN(n) (0x0800 + 0x10 + (n)) 92 #define IOLH(n) (0x1000 + (n) * 8) 93 #define IEN(n) (0x1800 + (n) * 8) 94 #define ISEL(n) (0x2c80 + (n) * 8) 95 #define PWPR (0x3014) 96 #define SD_CH(n) (0x3000 + (n) * 4) 97 #define QSPI (0x3008) 98 99 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 100 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 101 102 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 103 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 104 105 #define PM_MASK 0x03 106 #define PVDD_MASK 0x01 107 #define PFC_MASK 0x07 108 #define IEN_MASK 0x01 109 #define IOLH_MASK 0x03 110 111 #define PM_INPUT 0x1 112 #define PM_OUTPUT 0x2 113 114 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 115 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) 116 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 117 118 #define RZG2L_TINT_MAX_INTERRUPT 32 119 #define RZG2L_TINT_IRQ_START_INDEX 9 120 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 121 122 struct rzg2l_dedicated_configs { 123 const char *name; 124 u32 config; 125 }; 126 127 struct rzg2l_pinctrl_data { 128 const char * const *port_pins; 129 const u32 *port_pin_configs; 130 struct rzg2l_dedicated_configs *dedicated_pins; 131 unsigned int n_port_pins; 132 unsigned int n_dedicated_pins; 133 }; 134 135 struct rzg2l_pinctrl { 136 struct pinctrl_dev *pctl; 137 struct pinctrl_desc desc; 138 struct pinctrl_pin_desc *pins; 139 140 const struct rzg2l_pinctrl_data *data; 141 void __iomem *base; 142 struct device *dev; 143 struct clk *clk; 144 145 struct gpio_chip gpio_chip; 146 struct pinctrl_gpio_range gpio_range; 147 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 148 spinlock_t bitmap_lock; 149 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 150 151 spinlock_t lock; 152 }; 153 154 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; 155 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; 156 157 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 158 u8 port, u8 pin, u8 func) 159 { 160 unsigned long flags; 161 u32 reg; 162 163 spin_lock_irqsave(&pctrl->lock, flags); 164 165 /* Set pin to 'Non-use (Hi-Z input protection)' */ 166 reg = readw(pctrl->base + PM(port)); 167 reg &= ~(PM_MASK << (pin * 2)); 168 writew(reg, pctrl->base + PM(port)); 169 170 /* Temporarily switch to GPIO mode with PMC register */ 171 reg = readb(pctrl->base + PMC(port)); 172 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); 173 174 /* Set the PWPR register to allow PFC register to write */ 175 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 176 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ 177 178 /* Select Pin function mode with PFC register */ 179 reg = readl(pctrl->base + PFC(port)); 180 reg &= ~(PFC_MASK << (pin * 4)); 181 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); 182 183 /* Set the PWPR register to be write-protected */ 184 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 185 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ 186 187 /* Switch to Peripheral pin function with PMC register */ 188 reg = readb(pctrl->base + PMC(port)); 189 writeb(reg | BIT(pin), pctrl->base + PMC(port)); 190 191 spin_unlock_irqrestore(&pctrl->lock, flags); 192 }; 193 194 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 195 unsigned int func_selector, 196 unsigned int group_selector) 197 { 198 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 199 struct function_desc *func; 200 unsigned int i, *psel_val; 201 struct group_desc *group; 202 int *pins; 203 204 func = pinmux_generic_get_function(pctldev, func_selector); 205 if (!func) 206 return -EINVAL; 207 group = pinctrl_generic_get_group(pctldev, group_selector); 208 if (!group) 209 return -EINVAL; 210 211 psel_val = func->data; 212 pins = group->pins; 213 214 for (i = 0; i < group->num_pins; i++) { 215 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 216 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), 217 psel_val[i]); 218 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), 219 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 220 } 221 222 return 0; 223 }; 224 225 static int rzg2l_map_add_config(struct pinctrl_map *map, 226 const char *group_or_pin, 227 enum pinctrl_map_type type, 228 unsigned long *configs, 229 unsigned int num_configs) 230 { 231 unsigned long *cfgs; 232 233 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 234 GFP_KERNEL); 235 if (!cfgs) 236 return -ENOMEM; 237 238 map->type = type; 239 map->data.configs.group_or_pin = group_or_pin; 240 map->data.configs.configs = cfgs; 241 map->data.configs.num_configs = num_configs; 242 243 return 0; 244 } 245 246 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 247 struct device_node *np, 248 struct pinctrl_map **map, 249 unsigned int *num_maps, 250 unsigned int *index) 251 { 252 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 253 struct pinctrl_map *maps = *map; 254 unsigned int nmaps = *num_maps; 255 unsigned long *configs = NULL; 256 unsigned int *pins, *psel_val; 257 unsigned int num_pinmux = 0; 258 unsigned int idx = *index; 259 unsigned int num_pins, i; 260 unsigned int num_configs; 261 struct property *pinmux; 262 struct property *prop; 263 int ret, gsel, fsel; 264 const char **pin_fn; 265 const char *pin; 266 267 pinmux = of_find_property(np, "pinmux", NULL); 268 if (pinmux) 269 num_pinmux = pinmux->length / sizeof(u32); 270 271 ret = of_property_count_strings(np, "pins"); 272 if (ret == -EINVAL) { 273 num_pins = 0; 274 } else if (ret < 0) { 275 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 276 return ret; 277 } else { 278 num_pins = ret; 279 } 280 281 if (!num_pinmux && !num_pins) 282 return 0; 283 284 if (num_pinmux && num_pins) { 285 dev_err(pctrl->dev, 286 "DT node must contain either a pinmux or pins and not both\n"); 287 return -EINVAL; 288 } 289 290 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 291 if (ret < 0) 292 return ret; 293 294 if (num_pins && !num_configs) { 295 dev_err(pctrl->dev, "DT node must contain a config\n"); 296 ret = -ENODEV; 297 goto done; 298 } 299 300 if (num_pinmux) 301 nmaps += 1; 302 303 if (num_pins) 304 nmaps += num_pins; 305 306 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 307 if (!maps) { 308 ret = -ENOMEM; 309 goto done; 310 } 311 312 *map = maps; 313 *num_maps = nmaps; 314 if (num_pins) { 315 of_property_for_each_string(np, "pins", prop, pin) { 316 ret = rzg2l_map_add_config(&maps[idx], pin, 317 PIN_MAP_TYPE_CONFIGS_PIN, 318 configs, num_configs); 319 if (ret < 0) 320 goto done; 321 322 idx++; 323 } 324 ret = 0; 325 goto done; 326 } 327 328 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 329 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 330 GFP_KERNEL); 331 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 332 if (!pins || !psel_val || !pin_fn) { 333 ret = -ENOMEM; 334 goto done; 335 } 336 337 /* Collect pin locations and mux settings from DT properties */ 338 for (i = 0; i < num_pinmux; ++i) { 339 u32 value; 340 341 ret = of_property_read_u32_index(np, "pinmux", i, &value); 342 if (ret) 343 goto done; 344 pins[i] = value & MUX_PIN_ID_MASK; 345 psel_val[i] = MUX_FUNC(value); 346 } 347 348 /* Register a single pin group listing all the pins we read from DT */ 349 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL); 350 if (gsel < 0) { 351 ret = gsel; 352 goto done; 353 } 354 355 /* 356 * Register a single group function where the 'data' is an array PSEL 357 * register values read from DT. 358 */ 359 pin_fn[0] = np->name; 360 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1, 361 psel_val); 362 if (fsel < 0) { 363 ret = fsel; 364 goto remove_group; 365 } 366 367 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 368 maps[idx].data.mux.group = np->name; 369 maps[idx].data.mux.function = np->name; 370 idx++; 371 372 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 373 ret = 0; 374 goto done; 375 376 remove_group: 377 pinctrl_generic_remove_group(pctldev, gsel); 378 done: 379 *index = idx; 380 kfree(configs); 381 return ret; 382 } 383 384 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 385 struct pinctrl_map *map, 386 unsigned int num_maps) 387 { 388 unsigned int i; 389 390 if (!map) 391 return; 392 393 for (i = 0; i < num_maps; ++i) { 394 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 395 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 396 kfree(map[i].data.configs.configs); 397 } 398 kfree(map); 399 } 400 401 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 402 struct device_node *np, 403 struct pinctrl_map **map, 404 unsigned int *num_maps) 405 { 406 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 407 struct device_node *child; 408 unsigned int index; 409 int ret; 410 411 *map = NULL; 412 *num_maps = 0; 413 index = 0; 414 415 for_each_child_of_node(np, child) { 416 ret = rzg2l_dt_subnode_to_map(pctldev, child, map, 417 num_maps, &index); 418 if (ret < 0) { 419 of_node_put(child); 420 goto done; 421 } 422 } 423 424 if (*num_maps == 0) { 425 ret = rzg2l_dt_subnode_to_map(pctldev, np, map, 426 num_maps, &index); 427 if (ret < 0) 428 goto done; 429 } 430 431 if (*num_maps) 432 return 0; 433 434 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 435 ret = -EINVAL; 436 437 done: 438 if (ret < 0) 439 rzg2l_dt_free_map(pctldev, *map, *num_maps); 440 441 return ret; 442 } 443 444 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 445 u32 cfg, u32 port, u8 bit) 446 { 447 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 448 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); 449 u32 data; 450 451 if (bit >= pincount || port >= pctrl->data->n_port_pins) 452 return -EINVAL; 453 454 data = pctrl->data->port_pin_configs[port]; 455 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) 456 return -EINVAL; 457 458 return 0; 459 } 460 461 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 462 u8 bit, u32 mask) 463 { 464 void __iomem *addr = pctrl->base + offset; 465 466 /* handle _L/_H for 32-bit register read/write */ 467 if (bit >= 4) { 468 bit -= 4; 469 addr += 4; 470 } 471 472 return (readl(addr) >> (bit * 8)) & mask; 473 } 474 475 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 476 u8 bit, u32 mask, u32 val) 477 { 478 void __iomem *addr = pctrl->base + offset; 479 unsigned long flags; 480 u32 reg; 481 482 /* handle _L/_H for 32-bit register read/write */ 483 if (bit >= 4) { 484 bit -= 4; 485 addr += 4; 486 } 487 488 spin_lock_irqsave(&pctrl->lock, flags); 489 reg = readl(addr) & ~(mask << (bit * 8)); 490 writel(reg | (val << (bit * 8)), addr); 491 spin_unlock_irqrestore(&pctrl->lock, flags); 492 } 493 494 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 495 unsigned int _pin, 496 unsigned long *config) 497 { 498 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 499 enum pin_config_param param = pinconf_to_config_param(*config); 500 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 501 unsigned int *pin_data = pin->drv_data; 502 unsigned int arg = 0; 503 unsigned long flags; 504 void __iomem *addr; 505 u32 port_offset; 506 u32 cfg = 0; 507 u8 bit = 0; 508 509 if (!pin_data) 510 return -EINVAL; 511 512 if (*pin_data & RZG2L_SINGLE_PIN) { 513 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 514 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 515 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 516 } else { 517 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 518 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 519 bit = RZG2L_PIN_ID_TO_PIN(_pin); 520 521 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 522 return -EINVAL; 523 } 524 525 switch (param) { 526 case PIN_CONFIG_INPUT_ENABLE: 527 if (!(cfg & PIN_CFG_IEN)) 528 return -EINVAL; 529 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); 530 break; 531 532 case PIN_CONFIG_POWER_SOURCE: { 533 u32 pwr_reg = 0x0; 534 535 if (cfg & PIN_CFG_IO_VMC_SD0) 536 pwr_reg = SD_CH(0); 537 else if (cfg & PIN_CFG_IO_VMC_SD1) 538 pwr_reg = SD_CH(1); 539 else if (cfg & PIN_CFG_IO_VMC_QSPI) 540 pwr_reg = QSPI; 541 else 542 return -EINVAL; 543 544 spin_lock_irqsave(&pctrl->lock, flags); 545 addr = pctrl->base + pwr_reg; 546 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; 547 spin_unlock_irqrestore(&pctrl->lock, flags); 548 break; 549 } 550 551 case PIN_CONFIG_DRIVE_STRENGTH: { 552 unsigned int index; 553 554 if (!(cfg & PIN_CFG_IOLH_A)) 555 return -EINVAL; 556 557 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 558 arg = iolh_groupa_mA[index]; 559 break; 560 } 561 562 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 563 unsigned int index; 564 565 if (!(cfg & PIN_CFG_IOLH_B)) 566 return -EINVAL; 567 568 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 569 arg = iolh_groupb_oi[index]; 570 break; 571 } 572 573 default: 574 return -ENOTSUPP; 575 } 576 577 *config = pinconf_to_config_packed(param, arg); 578 579 return 0; 580 }; 581 582 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 583 unsigned int _pin, 584 unsigned long *_configs, 585 unsigned int num_configs) 586 { 587 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 588 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 589 unsigned int *pin_data = pin->drv_data; 590 enum pin_config_param param; 591 unsigned long flags; 592 void __iomem *addr; 593 u32 port_offset; 594 unsigned int i; 595 u32 cfg = 0; 596 u8 bit = 0; 597 598 if (!pin_data) 599 return -EINVAL; 600 601 if (*pin_data & RZG2L_SINGLE_PIN) { 602 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 603 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 604 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 605 } else { 606 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 607 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 608 bit = RZG2L_PIN_ID_TO_PIN(_pin); 609 610 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 611 return -EINVAL; 612 } 613 614 for (i = 0; i < num_configs; i++) { 615 param = pinconf_to_config_param(_configs[i]); 616 switch (param) { 617 case PIN_CONFIG_INPUT_ENABLE: { 618 unsigned int arg = 619 pinconf_to_config_argument(_configs[i]); 620 621 if (!(cfg & PIN_CFG_IEN)) 622 return -EINVAL; 623 624 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); 625 break; 626 } 627 628 case PIN_CONFIG_POWER_SOURCE: { 629 unsigned int mV = pinconf_to_config_argument(_configs[i]); 630 u32 pwr_reg = 0x0; 631 632 if (mV != 1800 && mV != 3300) 633 return -EINVAL; 634 635 if (cfg & PIN_CFG_IO_VMC_SD0) 636 pwr_reg = SD_CH(0); 637 else if (cfg & PIN_CFG_IO_VMC_SD1) 638 pwr_reg = SD_CH(1); 639 else if (cfg & PIN_CFG_IO_VMC_QSPI) 640 pwr_reg = QSPI; 641 else 642 return -EINVAL; 643 644 addr = pctrl->base + pwr_reg; 645 spin_lock_irqsave(&pctrl->lock, flags); 646 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); 647 spin_unlock_irqrestore(&pctrl->lock, flags); 648 break; 649 } 650 651 case PIN_CONFIG_DRIVE_STRENGTH: { 652 unsigned int arg = pinconf_to_config_argument(_configs[i]); 653 unsigned int index; 654 655 if (!(cfg & PIN_CFG_IOLH_A)) 656 return -EINVAL; 657 658 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { 659 if (arg == iolh_groupa_mA[index]) 660 break; 661 } 662 if (index >= ARRAY_SIZE(iolh_groupa_mA)) 663 return -EINVAL; 664 665 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 666 break; 667 } 668 669 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 670 unsigned int arg = pinconf_to_config_argument(_configs[i]); 671 unsigned int index; 672 673 if (!(cfg & PIN_CFG_IOLH_B)) 674 return -EINVAL; 675 676 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { 677 if (arg == iolh_groupb_oi[index]) 678 break; 679 } 680 if (index >= ARRAY_SIZE(iolh_groupb_oi)) 681 return -EINVAL; 682 683 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 684 break; 685 } 686 687 default: 688 return -EOPNOTSUPP; 689 } 690 } 691 692 return 0; 693 } 694 695 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 696 unsigned int group, 697 unsigned long *configs, 698 unsigned int num_configs) 699 { 700 const unsigned int *pins; 701 unsigned int i, npins; 702 int ret; 703 704 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 705 if (ret) 706 return ret; 707 708 for (i = 0; i < npins; i++) { 709 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 710 num_configs); 711 if (ret) 712 return ret; 713 } 714 715 return 0; 716 }; 717 718 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 719 unsigned int group, 720 unsigned long *config) 721 { 722 const unsigned int *pins; 723 unsigned int i, npins, prev_config = 0; 724 int ret; 725 726 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 727 if (ret) 728 return ret; 729 730 for (i = 0; i < npins; i++) { 731 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 732 if (ret) 733 return ret; 734 735 /* Check config matching between to pin */ 736 if (i && prev_config != *config) 737 return -EOPNOTSUPP; 738 739 prev_config = *config; 740 } 741 742 return 0; 743 }; 744 745 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 746 .get_groups_count = pinctrl_generic_get_group_count, 747 .get_group_name = pinctrl_generic_get_group_name, 748 .get_group_pins = pinctrl_generic_get_group_pins, 749 .dt_node_to_map = rzg2l_dt_node_to_map, 750 .dt_free_map = rzg2l_dt_free_map, 751 }; 752 753 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 754 .get_functions_count = pinmux_generic_get_function_count, 755 .get_function_name = pinmux_generic_get_function_name, 756 .get_function_groups = pinmux_generic_get_function_groups, 757 .set_mux = rzg2l_pinctrl_set_mux, 758 .strict = true, 759 }; 760 761 static const struct pinconf_ops rzg2l_pinctrl_confops = { 762 .is_generic = true, 763 .pin_config_get = rzg2l_pinctrl_pinconf_get, 764 .pin_config_set = rzg2l_pinctrl_pinconf_set, 765 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 766 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 767 .pin_config_config_dbg_show = pinconf_generic_dump_config, 768 }; 769 770 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 771 { 772 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 773 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 774 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 775 unsigned long flags; 776 u8 reg8; 777 int ret; 778 779 ret = pinctrl_gpio_request(chip->base + offset); 780 if (ret) 781 return ret; 782 783 spin_lock_irqsave(&pctrl->lock, flags); 784 785 /* Select GPIO mode in PMC Register */ 786 reg8 = readb(pctrl->base + PMC(port)); 787 reg8 &= ~BIT(bit); 788 writeb(reg8, pctrl->base + PMC(port)); 789 790 spin_unlock_irqrestore(&pctrl->lock, flags); 791 792 return 0; 793 } 794 795 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, 796 u8 bit, bool output) 797 { 798 unsigned long flags; 799 u16 reg16; 800 801 spin_lock_irqsave(&pctrl->lock, flags); 802 803 reg16 = readw(pctrl->base + PM(port)); 804 reg16 &= ~(PM_MASK << (bit * 2)); 805 806 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 807 writew(reg16, pctrl->base + PM(port)); 808 809 spin_unlock_irqrestore(&pctrl->lock, flags); 810 } 811 812 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 813 { 814 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 815 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 816 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 817 818 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { 819 u16 reg16; 820 821 reg16 = readw(pctrl->base + PM(port)); 822 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 823 if (reg16 == PM_OUTPUT) 824 return GPIO_LINE_DIRECTION_OUT; 825 } 826 827 return GPIO_LINE_DIRECTION_IN; 828 } 829 830 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 831 unsigned int offset) 832 { 833 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 834 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 835 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 836 837 rzg2l_gpio_set_direction(pctrl, port, bit, false); 838 839 return 0; 840 } 841 842 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 843 int value) 844 { 845 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 846 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 847 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 848 unsigned long flags; 849 u8 reg8; 850 851 spin_lock_irqsave(&pctrl->lock, flags); 852 853 reg8 = readb(pctrl->base + P(port)); 854 855 if (value) 856 writeb(reg8 | BIT(bit), pctrl->base + P(port)); 857 else 858 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); 859 860 spin_unlock_irqrestore(&pctrl->lock, flags); 861 } 862 863 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 864 unsigned int offset, int value) 865 { 866 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 867 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 868 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 869 870 rzg2l_gpio_set(chip, offset, value); 871 rzg2l_gpio_set_direction(pctrl, port, bit, true); 872 873 return 0; 874 } 875 876 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 877 { 878 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 879 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 880 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 881 u16 reg16; 882 883 reg16 = readw(pctrl->base + PM(port)); 884 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 885 886 if (reg16 == PM_INPUT) 887 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); 888 else if (reg16 == PM_OUTPUT) 889 return !!(readb(pctrl->base + P(port)) & BIT(bit)); 890 else 891 return -EINVAL; 892 } 893 894 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 895 { 896 unsigned int virq; 897 898 pinctrl_gpio_free(chip->base + offset); 899 900 virq = irq_find_mapping(chip->irq.domain, offset); 901 if (virq) 902 irq_dispose_mapping(virq); 903 904 /* 905 * Set the GPIO as an input to ensure that the next GPIO request won't 906 * drive the GPIO pin as an output. 907 */ 908 rzg2l_gpio_direction_input(chip, offset); 909 } 910 911 static const char * const rzg2l_gpio_names[] = { 912 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 913 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 914 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 915 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 916 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 917 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 918 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 919 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 920 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 921 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 922 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 923 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 924 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 925 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 926 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 927 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 928 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 929 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 930 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 931 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 932 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 933 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 934 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 935 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 936 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 937 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 938 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 939 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 940 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 941 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 942 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 943 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 944 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 945 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 946 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 947 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 948 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 949 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 950 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 951 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 952 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 953 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 954 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 955 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 956 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 957 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 958 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 959 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 960 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 961 }; 962 963 static const u32 rzg2l_gpio_configs[] = { 964 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 965 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 966 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 967 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 968 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 969 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 970 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 971 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 972 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 973 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 974 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 975 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 976 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 977 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 978 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 979 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 980 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 981 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 982 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 983 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 984 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 985 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 986 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 987 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 988 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 989 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 990 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 991 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 992 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 993 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 994 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 995 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 996 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 997 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 998 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 999 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1000 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1001 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1002 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1003 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1004 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1005 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1006 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1007 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1008 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1009 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1010 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1011 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1012 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1013 }; 1014 1015 static const u32 r9a07g043_gpio_configs[] = { 1016 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1017 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1018 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1019 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1020 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1021 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1022 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1023 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1024 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1025 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1026 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1027 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1028 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1029 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1030 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1031 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1032 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1033 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1034 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1035 }; 1036 1037 static struct { 1038 struct rzg2l_dedicated_configs common[35]; 1039 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1040 } rzg2l_dedicated_pins = { 1041 .common = { 1042 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1043 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1044 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1045 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1046 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1047 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1048 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1049 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1050 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1051 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1052 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1053 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1054 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1055 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1056 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1057 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1058 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1059 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1060 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1061 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1062 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1063 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1064 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1065 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1066 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1067 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1068 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1069 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1070 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1071 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1072 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1073 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1074 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1075 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1076 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1077 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1078 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1079 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1080 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1081 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1082 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1083 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1084 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1085 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1086 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1087 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1088 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1089 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1090 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1091 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1092 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1093 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1094 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1095 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1096 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1097 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1098 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1099 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1100 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1101 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1102 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1103 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1104 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1105 }, 1106 .rzg2l_pins = { 1107 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1108 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1109 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1110 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1111 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1112 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1113 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1114 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1115 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1116 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1117 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1118 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1119 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1120 } 1121 }; 1122 1123 static int rzg2l_gpio_get_gpioint(unsigned int virq) 1124 { 1125 unsigned int gpioint; 1126 unsigned int i; 1127 u32 port, bit; 1128 1129 port = virq / 8; 1130 bit = virq % 8; 1131 1132 if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || 1133 bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) 1134 return -EINVAL; 1135 1136 gpioint = bit; 1137 for (i = 0; i < port; i++) 1138 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); 1139 1140 return gpioint; 1141 } 1142 1143 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1144 { 1145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1146 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1147 unsigned int hwirq = irqd_to_hwirq(d); 1148 unsigned long flags; 1149 void __iomem *addr; 1150 u32 port; 1151 u8 bit; 1152 1153 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1154 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1155 1156 addr = pctrl->base + ISEL(port); 1157 if (bit >= 4) { 1158 bit -= 4; 1159 addr += 4; 1160 } 1161 1162 spin_lock_irqsave(&pctrl->lock, flags); 1163 writel(readl(addr) & ~BIT(bit * 8), addr); 1164 spin_unlock_irqrestore(&pctrl->lock, flags); 1165 1166 gpiochip_disable_irq(gc, hwirq); 1167 irq_chip_disable_parent(d); 1168 } 1169 1170 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1171 { 1172 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1173 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1174 unsigned int hwirq = irqd_to_hwirq(d); 1175 unsigned long flags; 1176 void __iomem *addr; 1177 u32 port; 1178 u8 bit; 1179 1180 gpiochip_enable_irq(gc, hwirq); 1181 1182 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1183 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1184 1185 addr = pctrl->base + ISEL(port); 1186 if (bit >= 4) { 1187 bit -= 4; 1188 addr += 4; 1189 } 1190 1191 spin_lock_irqsave(&pctrl->lock, flags); 1192 writel(readl(addr) | BIT(bit * 8), addr); 1193 spin_unlock_irqrestore(&pctrl->lock, flags); 1194 1195 irq_chip_enable_parent(d); 1196 } 1197 1198 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1199 { 1200 return irq_chip_set_type_parent(d, type); 1201 } 1202 1203 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1204 { 1205 irq_chip_eoi_parent(d); 1206 } 1207 1208 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1209 { 1210 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1211 1212 seq_printf(p, dev_name(gc->parent)); 1213 } 1214 1215 static const struct irq_chip rzg2l_gpio_irqchip = { 1216 .name = "rzg2l-gpio", 1217 .irq_disable = rzg2l_gpio_irq_disable, 1218 .irq_enable = rzg2l_gpio_irq_enable, 1219 .irq_mask = irq_chip_mask_parent, 1220 .irq_unmask = irq_chip_unmask_parent, 1221 .irq_set_type = rzg2l_gpio_irq_set_type, 1222 .irq_eoi = rzg2l_gpio_irqc_eoi, 1223 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1224 .flags = IRQCHIP_IMMUTABLE, 1225 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1226 }; 1227 1228 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1229 unsigned int child, 1230 unsigned int child_type, 1231 unsigned int *parent, 1232 unsigned int *parent_type) 1233 { 1234 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1235 unsigned long flags; 1236 int gpioint, irq; 1237 1238 gpioint = rzg2l_gpio_get_gpioint(child); 1239 if (gpioint < 0) 1240 return gpioint; 1241 1242 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1243 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1244 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1245 if (irq < 0) 1246 return -ENOSPC; 1247 pctrl->hwirq[irq] = child; 1248 irq += RZG2L_TINT_IRQ_START_INDEX; 1249 1250 /* All these interrupts are level high in the CPU */ 1251 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1252 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1253 return 0; 1254 } 1255 1256 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1257 union gpio_irq_fwspec *gfwspec, 1258 unsigned int parent_hwirq, 1259 unsigned int parent_type) 1260 { 1261 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1262 1263 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1264 fwspec->param_count = 2; 1265 fwspec->param[0] = parent_hwirq; 1266 fwspec->param[1] = parent_type; 1267 1268 return 0; 1269 } 1270 1271 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1272 unsigned int nr_irqs) 1273 { 1274 struct irq_data *d; 1275 1276 d = irq_domain_get_irq_data(domain, virq); 1277 if (d) { 1278 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1279 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1280 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1281 unsigned long flags; 1282 unsigned int i; 1283 1284 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1285 if (pctrl->hwirq[i] == hwirq) { 1286 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1287 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1288 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1289 pctrl->hwirq[i] = 0; 1290 break; 1291 } 1292 } 1293 } 1294 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1295 } 1296 1297 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1298 unsigned long *valid_mask, 1299 unsigned int ngpios) 1300 { 1301 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1302 struct gpio_chip *chip = &pctrl->gpio_chip; 1303 unsigned int offset; 1304 1305 /* Forbid unused lines to be mapped as IRQs */ 1306 for (offset = 0; offset < chip->ngpio; offset++) { 1307 u32 port, bit; 1308 1309 port = offset / 8; 1310 bit = offset % 8; 1311 1312 if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || 1313 bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) 1314 clear_bit(offset, valid_mask); 1315 } 1316 } 1317 1318 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1319 { 1320 struct device_node *np = pctrl->dev->of_node; 1321 struct gpio_chip *chip = &pctrl->gpio_chip; 1322 const char *name = dev_name(pctrl->dev); 1323 struct irq_domain *parent_domain; 1324 struct of_phandle_args of_args; 1325 struct device_node *parent_np; 1326 struct gpio_irq_chip *girq; 1327 int ret; 1328 1329 parent_np = of_irq_find_parent(np); 1330 if (!parent_np) 1331 return -ENXIO; 1332 1333 parent_domain = irq_find_host(parent_np); 1334 of_node_put(parent_np); 1335 if (!parent_domain) 1336 return -EPROBE_DEFER; 1337 1338 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1339 if (ret) { 1340 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1341 return ret; 1342 } 1343 1344 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1345 of_args.args[2] != pctrl->data->n_port_pins) { 1346 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1347 return -EINVAL; 1348 } 1349 1350 chip->names = pctrl->data->port_pins; 1351 chip->request = rzg2l_gpio_request; 1352 chip->free = rzg2l_gpio_free; 1353 chip->get_direction = rzg2l_gpio_get_direction; 1354 chip->direction_input = rzg2l_gpio_direction_input; 1355 chip->direction_output = rzg2l_gpio_direction_output; 1356 chip->get = rzg2l_gpio_get; 1357 chip->set = rzg2l_gpio_set; 1358 chip->label = name; 1359 chip->parent = pctrl->dev; 1360 chip->owner = THIS_MODULE; 1361 chip->base = -1; 1362 chip->ngpio = of_args.args[2]; 1363 1364 girq = &chip->irq; 1365 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1366 girq->fwnode = of_node_to_fwnode(np); 1367 girq->parent_domain = parent_domain; 1368 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1369 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1370 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1371 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1372 1373 pctrl->gpio_range.id = 0; 1374 pctrl->gpio_range.pin_base = 0; 1375 pctrl->gpio_range.base = 0; 1376 pctrl->gpio_range.npins = chip->ngpio; 1377 pctrl->gpio_range.name = chip->label; 1378 pctrl->gpio_range.gc = chip; 1379 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1380 if (ret) { 1381 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1382 return ret; 1383 } 1384 1385 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1386 1387 return 0; 1388 } 1389 1390 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1391 { 1392 struct pinctrl_pin_desc *pins; 1393 unsigned int i, j; 1394 u32 *pin_data; 1395 int ret; 1396 1397 pctrl->desc.name = DRV_NAME; 1398 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1399 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1400 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1401 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1402 pctrl->desc.owner = THIS_MODULE; 1403 1404 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1405 if (!pins) 1406 return -ENOMEM; 1407 1408 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1409 sizeof(*pin_data), GFP_KERNEL); 1410 if (!pin_data) 1411 return -ENOMEM; 1412 1413 pctrl->pins = pins; 1414 pctrl->desc.pins = pins; 1415 1416 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1417 pins[i].number = i; 1418 pins[i].name = pctrl->data->port_pins[i]; 1419 if (i && !(i % RZG2L_PINS_PER_PORT)) 1420 j++; 1421 pin_data[i] = pctrl->data->port_pin_configs[j]; 1422 pins[i].drv_data = &pin_data[i]; 1423 } 1424 1425 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1426 unsigned int index = pctrl->data->n_port_pins + i; 1427 1428 pins[index].number = index; 1429 pins[index].name = pctrl->data->dedicated_pins[i].name; 1430 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1431 pins[index].drv_data = &pin_data[index]; 1432 } 1433 1434 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1435 &pctrl->pctl); 1436 if (ret) { 1437 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1438 return ret; 1439 } 1440 1441 ret = pinctrl_enable(pctrl->pctl); 1442 if (ret) { 1443 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1444 return ret; 1445 } 1446 1447 ret = rzg2l_gpio_register(pctrl); 1448 if (ret) { 1449 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1450 return ret; 1451 } 1452 1453 return 0; 1454 } 1455 1456 static void rzg2l_pinctrl_clk_disable(void *data) 1457 { 1458 clk_disable_unprepare(data); 1459 } 1460 1461 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1462 { 1463 struct rzg2l_pinctrl *pctrl; 1464 int ret; 1465 1466 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1467 if (!pctrl) 1468 return -ENOMEM; 1469 1470 pctrl->dev = &pdev->dev; 1471 1472 pctrl->data = of_device_get_match_data(&pdev->dev); 1473 if (!pctrl->data) 1474 return -EINVAL; 1475 1476 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1477 if (IS_ERR(pctrl->base)) 1478 return PTR_ERR(pctrl->base); 1479 1480 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1481 if (IS_ERR(pctrl->clk)) { 1482 ret = PTR_ERR(pctrl->clk); 1483 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1484 return ret; 1485 } 1486 1487 spin_lock_init(&pctrl->lock); 1488 spin_lock_init(&pctrl->bitmap_lock); 1489 1490 platform_set_drvdata(pdev, pctrl); 1491 1492 ret = clk_prepare_enable(pctrl->clk); 1493 if (ret) { 1494 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1495 return ret; 1496 } 1497 1498 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, 1499 pctrl->clk); 1500 if (ret) { 1501 dev_err(pctrl->dev, 1502 "failed to register GPIO clk disable action, %i\n", 1503 ret); 1504 return ret; 1505 } 1506 1507 ret = rzg2l_pinctrl_register(pctrl); 1508 if (ret) 1509 return ret; 1510 1511 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1512 return 0; 1513 } 1514 1515 static struct rzg2l_pinctrl_data r9a07g043_data = { 1516 .port_pins = rzg2l_gpio_names, 1517 .port_pin_configs = r9a07g043_gpio_configs, 1518 .dedicated_pins = rzg2l_dedicated_pins.common, 1519 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1520 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1521 }; 1522 1523 static struct rzg2l_pinctrl_data r9a07g044_data = { 1524 .port_pins = rzg2l_gpio_names, 1525 .port_pin_configs = rzg2l_gpio_configs, 1526 .dedicated_pins = rzg2l_dedicated_pins.common, 1527 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), 1528 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1529 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1530 }; 1531 1532 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1533 { 1534 .compatible = "renesas,r9a07g043-pinctrl", 1535 .data = &r9a07g043_data, 1536 }, 1537 { 1538 .compatible = "renesas,r9a07g044-pinctrl", 1539 .data = &r9a07g044_data, 1540 }, 1541 { /* sentinel */ } 1542 }; 1543 1544 static struct platform_driver rzg2l_pinctrl_driver = { 1545 .driver = { 1546 .name = DRV_NAME, 1547 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1548 }, 1549 .probe = rzg2l_pinctrl_probe, 1550 }; 1551 1552 static int __init rzg2l_pinctrl_init(void) 1553 { 1554 return platform_driver_register(&rzg2l_pinctrl_driver); 1555 } 1556 core_initcall(rzg2l_pinctrl_init); 1557 1558 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1559 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1560 MODULE_LICENSE("GPL v2"); 1561