1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Core pinctrl/GPIO driver for Intel GPIO controllers 4 * 5 * Copyright (C) 2015, Intel Corporation 6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #ifndef PINCTRL_INTEL_H 11 #define PINCTRL_INTEL_H 12 13 #include <linux/gpio/driver.h> 14 #include <linux/irq.h> 15 #include <linux/pm.h> 16 #include <linux/spinlock_types.h> 17 18 struct pinctrl_pin_desc; 19 struct platform_device; 20 struct device; 21 22 /** 23 * struct intel_pingroup - Description about group of pins 24 * @name: Name of the groups 25 * @pins: All pins in this group 26 * @npins: Number of pins in this groups 27 * @mode: Native mode in which the group is muxed out @pins. Used if @modes 28 * is %NULL. 29 * @modes: If not %NULL this will hold mode for each pin in @pins 30 */ 31 struct intel_pingroup { 32 const char *name; 33 const unsigned int *pins; 34 size_t npins; 35 unsigned short mode; 36 const unsigned int *modes; 37 }; 38 39 /** 40 * struct intel_function - Description about a function 41 * @name: Name of the function 42 * @groups: An array of groups for this function 43 * @ngroups: Number of groups in @groups 44 */ 45 struct intel_function { 46 const char *name; 47 const char * const *groups; 48 size_t ngroups; 49 }; 50 51 /** 52 * struct intel_padgroup - Hardware pad group information 53 * @reg_num: GPI_IS register number 54 * @base: Starting pin of this group 55 * @size: Size of this group (maximum is 32). 56 * @gpio_base: Starting GPIO base of this group 57 * @padown_num: PAD_OWN register number (assigned by the core driver) 58 * 59 * If pad groups of a community are not the same size, use this structure 60 * to specify them. 61 */ 62 struct intel_padgroup { 63 unsigned int reg_num; 64 unsigned int base; 65 unsigned int size; 66 int gpio_base; 67 unsigned int padown_num; 68 }; 69 70 /** 71 * enum - Special treatment for GPIO base in pad group 72 * 73 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created 74 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number 75 */ 76 enum { 77 INTEL_GPIO_BASE_NOMAP = -1, 78 INTEL_GPIO_BASE_MATCH = 0, 79 }; 80 81 /** 82 * struct intel_community - Intel pin community description 83 * @barno: MMIO BAR number where registers for this community reside 84 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 85 * then there is no support for owner. 86 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then 87 * locking is not supported. 88 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it 89 * is assumed that the host owns the pin (rather than 90 * ACPI). 91 * @is_offset: Register offset of GPI_IS from @regs. 92 * @ie_offset: Register offset of GPI_IE from @regs. 93 * @features: Additional features supported by the hardware 94 * @pin_base: Starting pin of pins in this community 95 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, 96 * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. 97 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at 98 * minimum. Use %0 if the number of registers can be 99 * determined by the size of the group. 100 * @npins: Number of pins in this community 101 * @gpps: Pad groups if the controller has variable size pad groups 102 * @ngpps: Number of pad groups in this community 103 * @pad_map: Optional non-linear mapping of the pads 104 * @regs: Community specific common registers (reserved for core driver) 105 * @pad_regs: Community specific pad registers (reserved for core driver) 106 * 107 * Most Intel GPIO host controllers this driver supports each pad group is 108 * of equal size (except the last one). In that case the driver can just 109 * fill in @gpp_size field and let the core driver to handle the rest. If 110 * the controller has pad groups of variable size the client driver can 111 * pass custom @gpps and @ngpps instead. 112 */ 113 struct intel_community { 114 unsigned int barno; 115 unsigned int padown_offset; 116 unsigned int padcfglock_offset; 117 unsigned int hostown_offset; 118 unsigned int is_offset; 119 unsigned int ie_offset; 120 unsigned int features; 121 unsigned int pin_base; 122 unsigned int gpp_size; 123 unsigned int gpp_num_padown_regs; 124 size_t npins; 125 const struct intel_padgroup *gpps; 126 size_t ngpps; 127 const unsigned int *pad_map; 128 /* Reserved for the core driver */ 129 void __iomem *regs; 130 void __iomem *pad_regs; 131 }; 132 133 /* Additional features supported by the hardware */ 134 #define PINCTRL_FEATURE_DEBOUNCE BIT(0) 135 #define PINCTRL_FEATURE_1K_PD BIT(1) 136 137 /** 138 * PIN_GROUP - Declare a pin group 139 * @n: Name of the group 140 * @p: An array of pins this group consists 141 * @m: Mode which the pins are put when this group is active. Can be either 142 * a single integer or an array of integers in which case mode is per 143 * pin. 144 */ 145 #define PIN_GROUP(n, p, m) \ 146 { \ 147 .name = (n), \ 148 .pins = (p), \ 149 .npins = ARRAY_SIZE((p)), \ 150 .mode = __builtin_choose_expr( \ 151 __builtin_constant_p((m)), (m), 0), \ 152 .modes = __builtin_choose_expr( \ 153 __builtin_constant_p((m)), NULL, (m)), \ 154 } 155 156 #define FUNCTION(n, g) \ 157 { \ 158 .name = (n), \ 159 .groups = (g), \ 160 .ngroups = ARRAY_SIZE((g)), \ 161 } 162 163 /** 164 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration 165 * @uid: ACPI _UID for the probe driver use if needed 166 * @pins: Array if pins this pinctrl controls 167 * @npins: Number of pins in the array 168 * @groups: Array of pin groups 169 * @ngroups: Number of groups in the array 170 * @functions: Array of functions 171 * @nfunctions: Number of functions in the array 172 * @communities: Array of communities this pinctrl handles 173 * @ncommunities: Number of communities in the array 174 * 175 * The @communities is used as a template by the core driver. It will make 176 * copy of all communities and fill in rest of the information. 177 */ 178 struct intel_pinctrl_soc_data { 179 const char *uid; 180 const struct pinctrl_pin_desc *pins; 181 size_t npins; 182 const struct intel_pingroup *groups; 183 size_t ngroups; 184 const struct intel_function *functions; 185 size_t nfunctions; 186 const struct intel_community *communities; 187 size_t ncommunities; 188 }; 189 190 struct intel_pad_context; 191 struct intel_community_context; 192 193 /** 194 * struct intel_pinctrl_context - context to be saved during suspend-resume 195 * @pads: Opaque context per pad (driver dependent) 196 * @communities: Opaque context per community (driver dependent) 197 */ 198 struct intel_pinctrl_context { 199 struct intel_pad_context *pads; 200 struct intel_community_context *communities; 201 }; 202 203 /** 204 * struct intel_pinctrl - Intel pinctrl private structure 205 * @dev: Pointer to the device structure 206 * @lock: Lock to serialize register access 207 * @pctldesc: Pin controller description 208 * @pctldev: Pointer to the pin controller device 209 * @chip: GPIO chip in this pin controller 210 * @irqchip: IRQ chip in this pin controller 211 * @soc: SoC/PCH specific pin configuration data 212 * @communities: All communities in this pin controller 213 * @ncommunities: Number of communities in this pin controller 214 * @context: Configuration saved over system sleep 215 * @irq: pinctrl/GPIO chip irq number 216 */ 217 struct intel_pinctrl { 218 struct device *dev; 219 raw_spinlock_t lock; 220 struct pinctrl_desc pctldesc; 221 struct pinctrl_dev *pctldev; 222 struct gpio_chip chip; 223 struct irq_chip irqchip; 224 const struct intel_pinctrl_soc_data *soc; 225 struct intel_community *communities; 226 size_t ncommunities; 227 struct intel_pinctrl_context context; 228 int irq; 229 }; 230 231 int intel_pinctrl_probe_by_hid(struct platform_device *pdev); 232 int intel_pinctrl_probe_by_uid(struct platform_device *pdev); 233 234 #ifdef CONFIG_PM_SLEEP 235 int intel_pinctrl_suspend_noirq(struct device *dev); 236 int intel_pinctrl_resume_noirq(struct device *dev); 237 #endif 238 239 #define INTEL_PINCTRL_PM_OPS(_name) \ 240 const struct dev_pm_ops _name = { \ 241 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \ 242 intel_pinctrl_resume_noirq) \ 243 } 244 245 #endif /* PINCTRL_INTEL_H */ 246