1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 #include <linux/string_helpers.h> 22 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 28 #include "pinctrl-intel.h" 29 30 /* memory mapped register offsets */ 31 #define BYT_CONF0_REG 0x000 32 #define BYT_CONF1_REG 0x004 33 #define BYT_VAL_REG 0x008 34 #define BYT_DFT_REG 0x00c 35 #define BYT_INT_STAT_REG 0x800 36 #define BYT_DIRECT_IRQ_REG 0x980 37 #define BYT_DEBOUNCE_REG 0x9d0 38 39 /* BYT_CONF0_REG register bits */ 40 #define BYT_IODEN BIT(31) 41 #define BYT_DIRECT_IRQ_EN BIT(27) 42 #define BYT_TRIG_MASK GENMASK(26, 24) 43 #define BYT_TRIG_NEG BIT(26) 44 #define BYT_TRIG_POS BIT(25) 45 #define BYT_TRIG_LVL BIT(24) 46 #define BYT_DEBOUNCE_EN BIT(20) 47 #define BYT_GLITCH_FILTER_EN BIT(19) 48 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 49 #define BYT_GLITCH_F_FAST_CLK BIT(16) 50 #define BYT_PULL_STR_SHIFT 9 51 #define BYT_PULL_STR_MASK GENMASK(10, 9) 52 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 57 #define BYT_PULL_ASSIGN_DOWN BIT(8) 58 #define BYT_PULL_ASSIGN_UP BIT(7) 59 #define BYT_PIN_MUX GENMASK(2, 0) 60 61 /* BYT_VAL_REG register bits */ 62 #define BYT_DIR_MASK GENMASK(2, 1) 63 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 64 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 65 #define BYT_LEVEL BIT(0) 66 67 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 68 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 69 70 /* BYT_DEBOUNCE_REG bits */ 71 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 72 #define BYT_DEBOUNCE_PULSE_375US 1 73 #define BYT_DEBOUNCE_PULSE_750US 2 74 #define BYT_DEBOUNCE_PULSE_1500US 3 75 #define BYT_DEBOUNCE_PULSE_3MS 4 76 #define BYT_DEBOUNCE_PULSE_6MS 5 77 #define BYT_DEBOUNCE_PULSE_12MS 6 78 #define BYT_DEBOUNCE_PULSE_24MS 7 79 80 #define BYT_NGPIO_SCORE 102 81 #define BYT_NGPIO_NCORE 28 82 #define BYT_NGPIO_SUS 44 83 84 #define BYT_SCORE_ACPI_UID "1" 85 #define BYT_NCORE_ACPI_UID "2" 86 #define BYT_SUS_ACPI_UID "3" 87 88 /* 89 * This is the function value most pins have for GPIO muxing. If the value 90 * differs from the default one, it must be explicitly mentioned. Otherwise, the 91 * pin control implementation will set the muxing value to default GPIO if it 92 * does not find a match for the requested function. 93 */ 94 #define BYT_DEFAULT_GPIO_MUX 0 95 #define BYT_ALTER_GPIO_MUX 1 96 97 struct intel_pad_context { 98 u32 conf0; 99 u32 val; 100 }; 101 102 #define COMMUNITY(p, n, map) \ 103 { \ 104 .pin_base = (p), \ 105 .npins = (n), \ 106 .pad_map = (map),\ 107 } 108 109 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 110 static const struct pinctrl_pin_desc byt_score_pins[] = { 111 PINCTRL_PIN(0, "SATA_GP0"), 112 PINCTRL_PIN(1, "SATA_GP1"), 113 PINCTRL_PIN(2, "SATA_LED#"), 114 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 115 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 116 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 117 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 118 PINCTRL_PIN(7, "SD3_WP"), 119 PINCTRL_PIN(8, "HDA_RST"), 120 PINCTRL_PIN(9, "HDA_SYNC"), 121 PINCTRL_PIN(10, "HDA_CLK"), 122 PINCTRL_PIN(11, "HDA_SDO"), 123 PINCTRL_PIN(12, "HDA_SDI0"), 124 PINCTRL_PIN(13, "HDA_SDI1"), 125 PINCTRL_PIN(14, "GPIO_S0_SC14"), 126 PINCTRL_PIN(15, "GPIO_S0_SC15"), 127 PINCTRL_PIN(16, "MMC1_CLK"), 128 PINCTRL_PIN(17, "MMC1_D0"), 129 PINCTRL_PIN(18, "MMC1_D1"), 130 PINCTRL_PIN(19, "MMC1_D2"), 131 PINCTRL_PIN(20, "MMC1_D3"), 132 PINCTRL_PIN(21, "MMC1_D4"), 133 PINCTRL_PIN(22, "MMC1_D5"), 134 PINCTRL_PIN(23, "MMC1_D6"), 135 PINCTRL_PIN(24, "MMC1_D7"), 136 PINCTRL_PIN(25, "MMC1_CMD"), 137 PINCTRL_PIN(26, "MMC1_RST"), 138 PINCTRL_PIN(27, "SD2_CLK"), 139 PINCTRL_PIN(28, "SD2_D0"), 140 PINCTRL_PIN(29, "SD2_D1"), 141 PINCTRL_PIN(30, "SD2_D2"), 142 PINCTRL_PIN(31, "SD2_D3_CD"), 143 PINCTRL_PIN(32, "SD2_CMD"), 144 PINCTRL_PIN(33, "SD3_CLK"), 145 PINCTRL_PIN(34, "SD3_D0"), 146 PINCTRL_PIN(35, "SD3_D1"), 147 PINCTRL_PIN(36, "SD3_D2"), 148 PINCTRL_PIN(37, "SD3_D3"), 149 PINCTRL_PIN(38, "SD3_CD"), 150 PINCTRL_PIN(39, "SD3_CMD"), 151 PINCTRL_PIN(40, "SD3_1P8EN"), 152 PINCTRL_PIN(41, "SD3_PWREN#"), 153 PINCTRL_PIN(42, "ILB_LPC_AD0"), 154 PINCTRL_PIN(43, "ILB_LPC_AD1"), 155 PINCTRL_PIN(44, "ILB_LPC_AD2"), 156 PINCTRL_PIN(45, "ILB_LPC_AD3"), 157 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 158 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 159 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 160 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 161 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 162 PINCTRL_PIN(51, "PCU_SMB_DATA"), 163 PINCTRL_PIN(52, "PCU_SMB_CLK"), 164 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 165 PINCTRL_PIN(54, "ILB_8254_SPKR"), 166 PINCTRL_PIN(55, "GPIO_S0_SC55"), 167 PINCTRL_PIN(56, "GPIO_S0_SC56"), 168 PINCTRL_PIN(57, "GPIO_S0_SC57"), 169 PINCTRL_PIN(58, "GPIO_S0_SC58"), 170 PINCTRL_PIN(59, "GPIO_S0_SC59"), 171 PINCTRL_PIN(60, "GPIO_S0_SC60"), 172 PINCTRL_PIN(61, "GPIO_S0_SC61"), 173 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 174 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 175 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 176 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 177 PINCTRL_PIN(66, "SIO_SPI_CS"), 178 PINCTRL_PIN(67, "SIO_SPI_MISO"), 179 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 180 PINCTRL_PIN(69, "SIO_SPI_CLK"), 181 PINCTRL_PIN(70, "SIO_UART1_RXD"), 182 PINCTRL_PIN(71, "SIO_UART1_TXD"), 183 PINCTRL_PIN(72, "SIO_UART1_RTS"), 184 PINCTRL_PIN(73, "SIO_UART1_CTS"), 185 PINCTRL_PIN(74, "SIO_UART2_RXD"), 186 PINCTRL_PIN(75, "SIO_UART2_TXD"), 187 PINCTRL_PIN(76, "SIO_UART2_RTS"), 188 PINCTRL_PIN(77, "SIO_UART2_CTS"), 189 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 190 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 191 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 192 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 193 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 194 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 195 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 196 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 197 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 198 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 199 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 200 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 201 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 202 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 203 PINCTRL_PIN(92, "GPIO_S0_SC92"), 204 PINCTRL_PIN(93, "GPIO_S0_SC93"), 205 PINCTRL_PIN(94, "SIO_PWM0"), 206 PINCTRL_PIN(95, "SIO_PWM1"), 207 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 208 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 209 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 210 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 211 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 212 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 213 }; 214 215 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 216 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 217 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 218 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 219 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 220 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 221 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 222 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 223 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 224 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 225 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 226 97, 100, 227 }; 228 229 /* SCORE groups */ 230 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 231 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 232 233 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 234 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 235 236 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 237 238 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 239 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 240 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 241 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 242 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 243 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 244 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 245 246 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 247 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 248 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 249 250 static const unsigned int byt_score_sdcard_pins[] = { 251 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 252 }; 253 static const unsigned int byt_score_sdcard_mux_values[] = { 254 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 255 }; 256 257 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 258 259 static const unsigned int byt_score_emmc_pins[] = { 260 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 261 }; 262 263 static const unsigned int byt_score_ilb_lpc_pins[] = { 264 42, 43, 44, 45, 46, 47, 48, 49, 50, 265 }; 266 267 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 268 269 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 270 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 271 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 272 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 273 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 274 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 275 276 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 277 278 static const struct intel_pingroup byt_score_groups[] = { 279 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), 280 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), 281 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), 282 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), 283 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), 284 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), 285 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), 286 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), 287 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), 288 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), 289 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), 290 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), 291 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), 292 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), 293 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), 294 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 295 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), 296 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), 297 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), 298 PIN_GROUP("sata_grp", byt_score_sata_pins, 1), 299 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 300 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 301 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 302 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 303 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 304 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 305 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), 306 }; 307 308 static const char * const byt_score_uart_groups[] = { 309 "uart1_grp", "uart2_grp", 310 }; 311 static const char * const byt_score_pwm_groups[] = { 312 "pwm0_grp", "pwm1_grp", 313 }; 314 static const char * const byt_score_ssp_groups[] = { 315 "ssp0_grp", "ssp1_grp", "ssp2_grp", 316 }; 317 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 318 static const char * const byt_score_i2c_groups[] = { 319 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 320 "i2c6_grp", 321 }; 322 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 323 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 324 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 325 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 326 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 327 static const char * const byt_score_plt_clk_groups[] = { 328 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 329 "plt_clk4_grp", "plt_clk5_grp", 330 }; 331 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 332 static const char * const byt_score_gpio_groups[] = { 333 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 334 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 335 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 336 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 337 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 338 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 339 }; 340 341 static const struct intel_function byt_score_functions[] = { 342 FUNCTION("uart", byt_score_uart_groups), 343 FUNCTION("pwm", byt_score_pwm_groups), 344 FUNCTION("ssp", byt_score_ssp_groups), 345 FUNCTION("spi", byt_score_spi_groups), 346 FUNCTION("i2c", byt_score_i2c_groups), 347 FUNCTION("sdcard", byt_score_sdcard_groups), 348 FUNCTION("sdio", byt_score_sdio_groups), 349 FUNCTION("emmc", byt_score_emmc_groups), 350 FUNCTION("lpc", byt_score_lpc_groups), 351 FUNCTION("sata", byt_score_sata_groups), 352 FUNCTION("plt_clk", byt_score_plt_clk_groups), 353 FUNCTION("smbus", byt_score_smbus_groups), 354 FUNCTION("gpio", byt_score_gpio_groups), 355 }; 356 357 static const struct intel_community byt_score_communities[] = { 358 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 359 }; 360 361 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 362 .uid = BYT_SCORE_ACPI_UID, 363 .pins = byt_score_pins, 364 .npins = ARRAY_SIZE(byt_score_pins), 365 .groups = byt_score_groups, 366 .ngroups = ARRAY_SIZE(byt_score_groups), 367 .functions = byt_score_functions, 368 .nfunctions = ARRAY_SIZE(byt_score_functions), 369 .communities = byt_score_communities, 370 .ncommunities = ARRAY_SIZE(byt_score_communities), 371 }; 372 373 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 374 static const struct pinctrl_pin_desc byt_sus_pins[] = { 375 PINCTRL_PIN(0, "GPIO_S50"), 376 PINCTRL_PIN(1, "GPIO_S51"), 377 PINCTRL_PIN(2, "GPIO_S52"), 378 PINCTRL_PIN(3, "GPIO_S53"), 379 PINCTRL_PIN(4, "GPIO_S54"), 380 PINCTRL_PIN(5, "GPIO_S55"), 381 PINCTRL_PIN(6, "GPIO_S56"), 382 PINCTRL_PIN(7, "GPIO_S57"), 383 PINCTRL_PIN(8, "GPIO_S58"), 384 PINCTRL_PIN(9, "GPIO_S59"), 385 PINCTRL_PIN(10, "GPIO_S510"), 386 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 387 PINCTRL_PIN(12, "PMC_SUSCLK0"), 388 PINCTRL_PIN(13, "GPIO_S513"), 389 PINCTRL_PIN(14, "USB_ULPI_RST"), 390 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 391 PINCTRL_PIN(16, "PMC_PWRBTN"), 392 PINCTRL_PIN(17, "GPIO_S517"), 393 PINCTRL_PIN(18, "PMC_SUS_STAT"), 394 PINCTRL_PIN(19, "USB_OC0"), 395 PINCTRL_PIN(20, "USB_OC1"), 396 PINCTRL_PIN(21, "PCU_SPI_CS1"), 397 PINCTRL_PIN(22, "GPIO_S522"), 398 PINCTRL_PIN(23, "GPIO_S523"), 399 PINCTRL_PIN(24, "GPIO_S524"), 400 PINCTRL_PIN(25, "GPIO_S525"), 401 PINCTRL_PIN(26, "GPIO_S526"), 402 PINCTRL_PIN(27, "GPIO_S527"), 403 PINCTRL_PIN(28, "GPIO_S528"), 404 PINCTRL_PIN(29, "GPIO_S529"), 405 PINCTRL_PIN(30, "GPIO_S530"), 406 PINCTRL_PIN(31, "USB_ULPI_CLK"), 407 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 408 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 409 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 410 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 411 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 412 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 413 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 414 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 415 PINCTRL_PIN(40, "USB_ULPI_DIR"), 416 PINCTRL_PIN(41, "USB_ULPI_NXT"), 417 PINCTRL_PIN(42, "USB_ULPI_STP"), 418 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 419 }; 420 421 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 422 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 423 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 424 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 425 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 426 52, 53, 59, 40, 427 }; 428 429 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 430 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 431 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 432 433 static const unsigned int byt_sus_usb_ulpi_pins[] = { 434 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 435 }; 436 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 437 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 438 }; 439 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 440 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 441 }; 442 443 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 444 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 445 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 446 447 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 448 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 449 450 static const struct intel_pingroup byt_sus_groups[] = { 451 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 452 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 453 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 454 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 455 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 456 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 457 PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 458 PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 459 }; 460 461 static const char * const byt_sus_usb_groups[] = { 462 "usb_oc_grp", "usb_ulpi_grp", 463 }; 464 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 465 static const char * const byt_sus_pmu_clk_groups[] = { 466 "pmu_clk1_grp", "pmu_clk2_grp", 467 }; 468 static const char * const byt_sus_gpio_groups[] = { 469 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 470 "pmu_clk1_grp", "pmu_clk2_grp", 471 }; 472 473 static const struct intel_function byt_sus_functions[] = { 474 FUNCTION("usb", byt_sus_usb_groups), 475 FUNCTION("spi", byt_sus_spi_groups), 476 FUNCTION("gpio", byt_sus_gpio_groups), 477 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 478 }; 479 480 static const struct intel_community byt_sus_communities[] = { 481 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 482 }; 483 484 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 485 .uid = BYT_SUS_ACPI_UID, 486 .pins = byt_sus_pins, 487 .npins = ARRAY_SIZE(byt_sus_pins), 488 .groups = byt_sus_groups, 489 .ngroups = ARRAY_SIZE(byt_sus_groups), 490 .functions = byt_sus_functions, 491 .nfunctions = ARRAY_SIZE(byt_sus_functions), 492 .communities = byt_sus_communities, 493 .ncommunities = ARRAY_SIZE(byt_sus_communities), 494 }; 495 496 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 497 PINCTRL_PIN(0, "HV_DDI0_HPD"), 498 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 499 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 500 PINCTRL_PIN(3, "PANEL0_VDDEN"), 501 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 502 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 503 PINCTRL_PIN(6, "HV_DDI1_HPD"), 504 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 505 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 506 PINCTRL_PIN(9, "PANEL1_VDDEN"), 507 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 508 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 509 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 510 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 511 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 512 PINCTRL_PIN(15, "GP_CAMERASB00"), 513 PINCTRL_PIN(16, "GP_CAMERASB01"), 514 PINCTRL_PIN(17, "GP_CAMERASB02"), 515 PINCTRL_PIN(18, "GP_CAMERASB03"), 516 PINCTRL_PIN(19, "GP_CAMERASB04"), 517 PINCTRL_PIN(20, "GP_CAMERASB05"), 518 PINCTRL_PIN(21, "GP_CAMERASB06"), 519 PINCTRL_PIN(22, "GP_CAMERASB07"), 520 PINCTRL_PIN(23, "GP_CAMERASB08"), 521 PINCTRL_PIN(24, "GP_CAMERASB09"), 522 PINCTRL_PIN(25, "GP_CAMERASB10"), 523 PINCTRL_PIN(26, "GP_CAMERASB11"), 524 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 525 }; 526 527 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 528 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 529 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 530 3, 6, 10, 13, 2, 5, 9, 7, 531 }; 532 533 static const struct intel_community byt_ncore_communities[] = { 534 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 535 }; 536 537 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 538 .uid = BYT_NCORE_ACPI_UID, 539 .pins = byt_ncore_pins, 540 .npins = ARRAY_SIZE(byt_ncore_pins), 541 .communities = byt_ncore_communities, 542 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 543 }; 544 545 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 546 &byt_score_soc_data, 547 &byt_sus_soc_data, 548 &byt_ncore_soc_data, 549 NULL 550 }; 551 552 static DEFINE_RAW_SPINLOCK(byt_lock); 553 554 static struct intel_community *byt_get_community(struct intel_pinctrl *vg, 555 unsigned int pin) 556 { 557 struct intel_community *comm; 558 int i; 559 560 for (i = 0; i < vg->ncommunities; i++) { 561 comm = vg->communities + i; 562 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 563 return comm; 564 } 565 566 return NULL; 567 } 568 569 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 570 int reg) 571 { 572 struct intel_community *comm = byt_get_community(vg, offset); 573 u32 reg_offset; 574 575 if (!comm) 576 return NULL; 577 578 offset -= comm->pin_base; 579 switch (reg) { 580 case BYT_INT_STAT_REG: 581 reg_offset = (offset / 32) * 4; 582 break; 583 case BYT_DEBOUNCE_REG: 584 reg_offset = 0; 585 break; 586 default: 587 reg_offset = comm->pad_map[offset] * 16; 588 break; 589 } 590 591 return comm->pad_regs + reg_offset + reg; 592 } 593 594 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 595 { 596 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 597 598 return vg->soc->ngroups; 599 } 600 601 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 602 unsigned int selector) 603 { 604 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 605 606 return vg->soc->groups[selector].grp.name; 607 } 608 609 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 610 unsigned int selector, 611 const unsigned int **pins, 612 unsigned int *num_pins) 613 { 614 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 615 616 *pins = vg->soc->groups[selector].grp.pins; 617 *num_pins = vg->soc->groups[selector].grp.npins; 618 619 return 0; 620 } 621 622 static const struct pinctrl_ops byt_pinctrl_ops = { 623 .get_groups_count = byt_get_groups_count, 624 .get_group_name = byt_get_group_name, 625 .get_group_pins = byt_get_group_pins, 626 }; 627 628 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 629 { 630 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 631 632 return vg->soc->nfunctions; 633 } 634 635 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 636 unsigned int selector) 637 { 638 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 639 640 return vg->soc->functions[selector].func.name; 641 } 642 643 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 644 unsigned int selector, 645 const char * const **groups, 646 unsigned int *ngroups) 647 { 648 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 649 650 *groups = vg->soc->functions[selector].func.groups; 651 *ngroups = vg->soc->functions[selector].func.ngroups; 652 653 return 0; 654 } 655 656 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 657 const struct intel_pingroup group, 658 unsigned int func) 659 { 660 unsigned long flags; 661 int i; 662 663 raw_spin_lock_irqsave(&byt_lock, flags); 664 665 for (i = 0; i < group.grp.npins; i++) { 666 void __iomem *padcfg0; 667 u32 value; 668 669 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 670 if (!padcfg0) { 671 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 672 group.grp.name, i); 673 continue; 674 } 675 676 value = readl(padcfg0); 677 value &= ~BYT_PIN_MUX; 678 value |= func; 679 writel(value, padcfg0); 680 } 681 682 raw_spin_unlock_irqrestore(&byt_lock, flags); 683 } 684 685 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 686 const struct intel_pingroup group, 687 const unsigned int *func) 688 { 689 unsigned long flags; 690 int i; 691 692 raw_spin_lock_irqsave(&byt_lock, flags); 693 694 for (i = 0; i < group.grp.npins; i++) { 695 void __iomem *padcfg0; 696 u32 value; 697 698 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 699 if (!padcfg0) { 700 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 701 group.grp.name, i); 702 continue; 703 } 704 705 value = readl(padcfg0); 706 value &= ~BYT_PIN_MUX; 707 value |= func[i]; 708 writel(value, padcfg0); 709 } 710 711 raw_spin_unlock_irqrestore(&byt_lock, flags); 712 } 713 714 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 715 unsigned int group_selector) 716 { 717 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 718 const struct intel_function func = vg->soc->functions[func_selector]; 719 const struct intel_pingroup group = vg->soc->groups[group_selector]; 720 721 if (group.modes) 722 byt_set_group_mixed_mux(vg, group, group.modes); 723 else if (!strcmp(func.func.name, "gpio")) 724 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 725 else 726 byt_set_group_simple_mux(vg, group, group.mode); 727 728 return 0; 729 } 730 731 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 732 { 733 /* SCORE pin 92-93 */ 734 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 735 offset >= 92 && offset <= 93) 736 return BYT_ALTER_GPIO_MUX; 737 738 /* SUS pin 11-21 */ 739 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 740 offset >= 11 && offset <= 21) 741 return BYT_ALTER_GPIO_MUX; 742 743 return BYT_DEFAULT_GPIO_MUX; 744 } 745 746 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 747 { 748 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 749 unsigned long flags; 750 u32 value; 751 752 raw_spin_lock_irqsave(&byt_lock, flags); 753 value = readl(reg); 754 755 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 756 if (value & BYT_DIRECT_IRQ_EN) 757 /* nothing to do */ ; 758 else 759 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 760 761 writel(value, reg); 762 raw_spin_unlock_irqrestore(&byt_lock, flags); 763 } 764 765 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 766 struct pinctrl_gpio_range *range, 767 unsigned int offset) 768 { 769 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 770 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 771 u32 value, gpio_mux; 772 unsigned long flags; 773 774 raw_spin_lock_irqsave(&byt_lock, flags); 775 776 /* 777 * In most cases, func pin mux 000 means GPIO function. 778 * But, some pins may have func pin mux 001 represents 779 * GPIO function. 780 * 781 * Because there are devices out there where some pins were not 782 * configured correctly we allow changing the mux value from 783 * request (but print out warning about that). 784 */ 785 value = readl(reg) & BYT_PIN_MUX; 786 gpio_mux = byt_get_gpio_mux(vg, offset); 787 if (gpio_mux != value) { 788 value = readl(reg) & ~BYT_PIN_MUX; 789 value |= gpio_mux; 790 writel(value, reg); 791 792 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); 793 } 794 795 raw_spin_unlock_irqrestore(&byt_lock, flags); 796 797 pm_runtime_get(vg->dev); 798 799 return 0; 800 } 801 802 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 803 struct pinctrl_gpio_range *range, 804 unsigned int offset) 805 { 806 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 807 808 byt_gpio_clear_triggering(vg, offset); 809 pm_runtime_put(vg->dev); 810 } 811 812 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 813 unsigned int offset) 814 { 815 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 816 817 /* 818 * Before making any direction modifications, do a check if gpio is set 819 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 820 * sense, so let's at least inform the caller before they shoot 821 * themselves in the foot. 822 */ 823 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 824 dev_info_once(vg->dev, 825 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n", 826 offset); 827 } 828 829 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 830 struct pinctrl_gpio_range *range, 831 unsigned int offset, 832 bool input) 833 { 834 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 835 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 836 unsigned long flags; 837 u32 value; 838 839 raw_spin_lock_irqsave(&byt_lock, flags); 840 841 value = readl(val_reg); 842 value &= ~BYT_DIR_MASK; 843 if (input) 844 value |= BYT_OUTPUT_EN; 845 else 846 byt_gpio_direct_irq_check(vg, offset); 847 848 writel(value, val_reg); 849 850 raw_spin_unlock_irqrestore(&byt_lock, flags); 851 852 return 0; 853 } 854 855 static const struct pinmux_ops byt_pinmux_ops = { 856 .get_functions_count = byt_get_functions_count, 857 .get_function_name = byt_get_function_name, 858 .get_function_groups = byt_get_function_groups, 859 .set_mux = byt_set_mux, 860 .gpio_request_enable = byt_gpio_request_enable, 861 .gpio_disable_free = byt_gpio_disable_free, 862 .gpio_set_direction = byt_gpio_set_direction, 863 }; 864 865 static void byt_get_pull_strength(u32 reg, u16 *strength) 866 { 867 switch (reg & BYT_PULL_STR_MASK) { 868 case BYT_PULL_STR_2K: 869 *strength = 2000; 870 break; 871 case BYT_PULL_STR_10K: 872 *strength = 10000; 873 break; 874 case BYT_PULL_STR_20K: 875 *strength = 20000; 876 break; 877 case BYT_PULL_STR_40K: 878 *strength = 40000; 879 break; 880 } 881 } 882 883 static int byt_set_pull_strength(u32 *reg, u16 strength) 884 { 885 *reg &= ~BYT_PULL_STR_MASK; 886 887 switch (strength) { 888 case 2000: 889 *reg |= BYT_PULL_STR_2K; 890 break; 891 case 10000: 892 *reg |= BYT_PULL_STR_10K; 893 break; 894 case 20000: 895 *reg |= BYT_PULL_STR_20K; 896 break; 897 case 40000: 898 *reg |= BYT_PULL_STR_40K; 899 break; 900 default: 901 return -EINVAL; 902 } 903 904 return 0; 905 } 906 907 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 908 unsigned long *config) 909 { 910 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 911 enum pin_config_param param = pinconf_to_config_param(*config); 912 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 913 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 914 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 915 unsigned long flags; 916 u32 conf, pull, val, debounce; 917 u16 arg = 0; 918 919 raw_spin_lock_irqsave(&byt_lock, flags); 920 conf = readl(conf_reg); 921 pull = conf & BYT_PULL_ASSIGN_MASK; 922 val = readl(val_reg); 923 raw_spin_unlock_irqrestore(&byt_lock, flags); 924 925 switch (param) { 926 case PIN_CONFIG_BIAS_DISABLE: 927 if (pull) 928 return -EINVAL; 929 break; 930 case PIN_CONFIG_BIAS_PULL_DOWN: 931 /* Pull assignment is only applicable in input mode */ 932 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 933 return -EINVAL; 934 935 byt_get_pull_strength(conf, &arg); 936 937 break; 938 case PIN_CONFIG_BIAS_PULL_UP: 939 /* Pull assignment is only applicable in input mode */ 940 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 941 return -EINVAL; 942 943 byt_get_pull_strength(conf, &arg); 944 945 break; 946 case PIN_CONFIG_INPUT_DEBOUNCE: 947 if (!(conf & BYT_DEBOUNCE_EN)) 948 return -EINVAL; 949 950 raw_spin_lock_irqsave(&byt_lock, flags); 951 debounce = readl(db_reg); 952 raw_spin_unlock_irqrestore(&byt_lock, flags); 953 954 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 955 case BYT_DEBOUNCE_PULSE_375US: 956 arg = 375; 957 break; 958 case BYT_DEBOUNCE_PULSE_750US: 959 arg = 750; 960 break; 961 case BYT_DEBOUNCE_PULSE_1500US: 962 arg = 1500; 963 break; 964 case BYT_DEBOUNCE_PULSE_3MS: 965 arg = 3000; 966 break; 967 case BYT_DEBOUNCE_PULSE_6MS: 968 arg = 6000; 969 break; 970 case BYT_DEBOUNCE_PULSE_12MS: 971 arg = 12000; 972 break; 973 case BYT_DEBOUNCE_PULSE_24MS: 974 arg = 24000; 975 break; 976 default: 977 return -EINVAL; 978 } 979 980 break; 981 default: 982 return -ENOTSUPP; 983 } 984 985 *config = pinconf_to_config_packed(param, arg); 986 987 return 0; 988 } 989 990 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 991 unsigned int offset, 992 unsigned long *configs, 993 unsigned int num_configs) 994 { 995 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 996 unsigned int param, arg; 997 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 998 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 999 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 1000 unsigned long flags; 1001 u32 conf, val, debounce; 1002 int i, ret = 0; 1003 1004 raw_spin_lock_irqsave(&byt_lock, flags); 1005 1006 conf = readl(conf_reg); 1007 val = readl(val_reg); 1008 1009 for (i = 0; i < num_configs; i++) { 1010 param = pinconf_to_config_param(configs[i]); 1011 arg = pinconf_to_config_argument(configs[i]); 1012 1013 switch (param) { 1014 case PIN_CONFIG_BIAS_DISABLE: 1015 conf &= ~BYT_PULL_ASSIGN_MASK; 1016 break; 1017 case PIN_CONFIG_BIAS_PULL_DOWN: 1018 /* Set default strength value in case none is given */ 1019 if (arg == 1) 1020 arg = 2000; 1021 1022 /* 1023 * Pull assignment is only applicable in input mode. If 1024 * chip is not in input mode, set it and warn about it. 1025 */ 1026 if (val & BYT_INPUT_EN) { 1027 val &= ~BYT_INPUT_EN; 1028 writel(val, val_reg); 1029 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 1030 } 1031 1032 conf &= ~BYT_PULL_ASSIGN_MASK; 1033 conf |= BYT_PULL_ASSIGN_DOWN; 1034 ret = byt_set_pull_strength(&conf, arg); 1035 1036 break; 1037 case PIN_CONFIG_BIAS_PULL_UP: 1038 /* Set default strength value in case none is given */ 1039 if (arg == 1) 1040 arg = 2000; 1041 1042 /* 1043 * Pull assignment is only applicable in input mode. If 1044 * chip is not in input mode, set it and warn about it. 1045 */ 1046 if (val & BYT_INPUT_EN) { 1047 val &= ~BYT_INPUT_EN; 1048 writel(val, val_reg); 1049 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 1050 } 1051 1052 conf &= ~BYT_PULL_ASSIGN_MASK; 1053 conf |= BYT_PULL_ASSIGN_UP; 1054 ret = byt_set_pull_strength(&conf, arg); 1055 1056 break; 1057 case PIN_CONFIG_INPUT_DEBOUNCE: 1058 debounce = readl(db_reg); 1059 1060 if (arg) 1061 conf |= BYT_DEBOUNCE_EN; 1062 else 1063 conf &= ~BYT_DEBOUNCE_EN; 1064 1065 switch (arg) { 1066 case 375: 1067 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1068 debounce |= BYT_DEBOUNCE_PULSE_375US; 1069 break; 1070 case 750: 1071 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1072 debounce |= BYT_DEBOUNCE_PULSE_750US; 1073 break; 1074 case 1500: 1075 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1076 debounce |= BYT_DEBOUNCE_PULSE_1500US; 1077 break; 1078 case 3000: 1079 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1080 debounce |= BYT_DEBOUNCE_PULSE_3MS; 1081 break; 1082 case 6000: 1083 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1084 debounce |= BYT_DEBOUNCE_PULSE_6MS; 1085 break; 1086 case 12000: 1087 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1088 debounce |= BYT_DEBOUNCE_PULSE_12MS; 1089 break; 1090 case 24000: 1091 debounce &= ~BYT_DEBOUNCE_PULSE_MASK; 1092 debounce |= BYT_DEBOUNCE_PULSE_24MS; 1093 break; 1094 default: 1095 if (arg) 1096 ret = -EINVAL; 1097 break; 1098 } 1099 1100 if (!ret) 1101 writel(debounce, db_reg); 1102 break; 1103 default: 1104 ret = -ENOTSUPP; 1105 } 1106 1107 if (ret) 1108 break; 1109 } 1110 1111 if (!ret) 1112 writel(conf, conf_reg); 1113 1114 raw_spin_unlock_irqrestore(&byt_lock, flags); 1115 1116 return ret; 1117 } 1118 1119 static const struct pinconf_ops byt_pinconf_ops = { 1120 .is_generic = true, 1121 .pin_config_get = byt_pin_config_get, 1122 .pin_config_set = byt_pin_config_set, 1123 }; 1124 1125 static const struct pinctrl_desc byt_pinctrl_desc = { 1126 .pctlops = &byt_pinctrl_ops, 1127 .pmxops = &byt_pinmux_ops, 1128 .confops = &byt_pinconf_ops, 1129 .owner = THIS_MODULE, 1130 }; 1131 1132 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1133 { 1134 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1135 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1136 unsigned long flags; 1137 u32 val; 1138 1139 raw_spin_lock_irqsave(&byt_lock, flags); 1140 val = readl(reg); 1141 raw_spin_unlock_irqrestore(&byt_lock, flags); 1142 1143 return !!(val & BYT_LEVEL); 1144 } 1145 1146 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1147 { 1148 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1149 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1150 unsigned long flags; 1151 u32 old_val; 1152 1153 if (!reg) 1154 return; 1155 1156 raw_spin_lock_irqsave(&byt_lock, flags); 1157 old_val = readl(reg); 1158 if (value) 1159 writel(old_val | BYT_LEVEL, reg); 1160 else 1161 writel(old_val & ~BYT_LEVEL, reg); 1162 raw_spin_unlock_irqrestore(&byt_lock, flags); 1163 } 1164 1165 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1166 { 1167 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1168 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1169 unsigned long flags; 1170 u32 value; 1171 1172 if (!reg) 1173 return -EINVAL; 1174 1175 raw_spin_lock_irqsave(&byt_lock, flags); 1176 value = readl(reg); 1177 raw_spin_unlock_irqrestore(&byt_lock, flags); 1178 1179 if (!(value & BYT_OUTPUT_EN)) 1180 return GPIO_LINE_DIRECTION_OUT; 1181 if (!(value & BYT_INPUT_EN)) 1182 return GPIO_LINE_DIRECTION_IN; 1183 1184 return -EINVAL; 1185 } 1186 1187 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1188 { 1189 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1190 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1191 unsigned long flags; 1192 u32 reg; 1193 1194 raw_spin_lock_irqsave(&byt_lock, flags); 1195 1196 reg = readl(val_reg); 1197 reg &= ~BYT_DIR_MASK; 1198 reg |= BYT_OUTPUT_EN; 1199 writel(reg, val_reg); 1200 1201 raw_spin_unlock_irqrestore(&byt_lock, flags); 1202 return 0; 1203 } 1204 1205 /* 1206 * Note despite the temptation this MUST NOT be converted into a call to 1207 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1208 * MUST be done as a single BYT_VAL_REG register write. 1209 * See the commit message of the commit adding this comment for details. 1210 */ 1211 static int byt_gpio_direction_output(struct gpio_chip *chip, 1212 unsigned int offset, int value) 1213 { 1214 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1215 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1216 unsigned long flags; 1217 u32 reg; 1218 1219 raw_spin_lock_irqsave(&byt_lock, flags); 1220 1221 byt_gpio_direct_irq_check(vg, offset); 1222 1223 reg = readl(val_reg); 1224 reg &= ~BYT_DIR_MASK; 1225 if (value) 1226 reg |= BYT_LEVEL; 1227 else 1228 reg &= ~BYT_LEVEL; 1229 1230 writel(reg, val_reg); 1231 1232 raw_spin_unlock_irqrestore(&byt_lock, flags); 1233 return 0; 1234 } 1235 1236 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1237 { 1238 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1239 int i; 1240 u32 conf0, val; 1241 1242 for (i = 0; i < vg->soc->npins; i++) { 1243 const struct intel_community *comm; 1244 const char *pull_str = NULL; 1245 const char *pull = NULL; 1246 void __iomem *reg; 1247 unsigned long flags; 1248 const char *label; 1249 unsigned int pin; 1250 1251 raw_spin_lock_irqsave(&byt_lock, flags); 1252 pin = vg->soc->pins[i].number; 1253 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1254 if (!reg) { 1255 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin); 1256 raw_spin_unlock_irqrestore(&byt_lock, flags); 1257 continue; 1258 } 1259 conf0 = readl(reg); 1260 1261 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1262 if (!reg) { 1263 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin); 1264 raw_spin_unlock_irqrestore(&byt_lock, flags); 1265 continue; 1266 } 1267 val = readl(reg); 1268 raw_spin_unlock_irqrestore(&byt_lock, flags); 1269 1270 comm = byt_get_community(vg, pin); 1271 if (!comm) { 1272 seq_printf(s, "Pin %i: can't retrieve community\n", pin); 1273 continue; 1274 } 1275 label = gpiochip_is_requested(chip, i); 1276 if (!label) 1277 label = "Unrequested"; 1278 1279 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1280 case BYT_PULL_ASSIGN_UP: 1281 pull = "up"; 1282 break; 1283 case BYT_PULL_ASSIGN_DOWN: 1284 pull = "down"; 1285 break; 1286 } 1287 1288 switch (conf0 & BYT_PULL_STR_MASK) { 1289 case BYT_PULL_STR_2K: 1290 pull_str = "2k"; 1291 break; 1292 case BYT_PULL_STR_10K: 1293 pull_str = "10k"; 1294 break; 1295 case BYT_PULL_STR_20K: 1296 pull_str = "20k"; 1297 break; 1298 case BYT_PULL_STR_40K: 1299 pull_str = "40k"; 1300 break; 1301 } 1302 1303 seq_printf(s, 1304 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1305 pin, 1306 label, 1307 val & BYT_INPUT_EN ? " " : "in", 1308 val & BYT_OUTPUT_EN ? " " : "out", 1309 str_hi_lo(val & BYT_LEVEL), 1310 comm->pad_map[i], comm->pad_map[i] * 16, 1311 conf0 & 0x7, 1312 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1313 conf0 & BYT_TRIG_POS ? " rise" : " ", 1314 conf0 & BYT_TRIG_LVL ? " level" : " "); 1315 1316 if (pull && pull_str) 1317 seq_printf(s, " %-4s %-3s", pull, pull_str); 1318 else 1319 seq_puts(s, " "); 1320 1321 if (conf0 & BYT_IODEN) 1322 seq_puts(s, " open-drain"); 1323 1324 seq_puts(s, "\n"); 1325 } 1326 } 1327 1328 static const struct gpio_chip byt_gpio_chip = { 1329 .owner = THIS_MODULE, 1330 .request = gpiochip_generic_request, 1331 .free = gpiochip_generic_free, 1332 .get_direction = byt_gpio_get_direction, 1333 .direction_input = byt_gpio_direction_input, 1334 .direction_output = byt_gpio_direction_output, 1335 .get = byt_gpio_get, 1336 .set = byt_gpio_set, 1337 .set_config = gpiochip_generic_config, 1338 .dbg_show = byt_gpio_dbg_show, 1339 }; 1340 1341 static void byt_irq_ack(struct irq_data *d) 1342 { 1343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1344 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1345 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1346 void __iomem *reg; 1347 1348 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); 1349 if (!reg) 1350 return; 1351 1352 raw_spin_lock(&byt_lock); 1353 writel(BIT(hwirq % 32), reg); 1354 raw_spin_unlock(&byt_lock); 1355 } 1356 1357 static void byt_irq_mask(struct irq_data *d) 1358 { 1359 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1360 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1361 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1362 1363 byt_gpio_clear_triggering(vg, hwirq); 1364 gpiochip_disable_irq(gc, hwirq); 1365 } 1366 1367 static void byt_irq_unmask(struct irq_data *d) 1368 { 1369 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1370 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1371 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1372 unsigned long flags; 1373 void __iomem *reg; 1374 u32 value; 1375 1376 gpiochip_enable_irq(gc, hwirq); 1377 1378 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1379 if (!reg) 1380 return; 1381 1382 raw_spin_lock_irqsave(&byt_lock, flags); 1383 value = readl(reg); 1384 1385 switch (irqd_get_trigger_type(d)) { 1386 case IRQ_TYPE_LEVEL_HIGH: 1387 value |= BYT_TRIG_LVL; 1388 fallthrough; 1389 case IRQ_TYPE_EDGE_RISING: 1390 value |= BYT_TRIG_POS; 1391 break; 1392 case IRQ_TYPE_LEVEL_LOW: 1393 value |= BYT_TRIG_LVL; 1394 fallthrough; 1395 case IRQ_TYPE_EDGE_FALLING: 1396 value |= BYT_TRIG_NEG; 1397 break; 1398 case IRQ_TYPE_EDGE_BOTH: 1399 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1400 break; 1401 } 1402 1403 writel(value, reg); 1404 1405 raw_spin_unlock_irqrestore(&byt_lock, flags); 1406 } 1407 1408 static int byt_irq_type(struct irq_data *d, unsigned int type) 1409 { 1410 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1411 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1412 u32 value; 1413 unsigned long flags; 1414 void __iomem *reg; 1415 1416 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1417 if (!reg) 1418 return -EINVAL; 1419 1420 raw_spin_lock_irqsave(&byt_lock, flags); 1421 value = readl(reg); 1422 1423 WARN(value & BYT_DIRECT_IRQ_EN, 1424 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing"); 1425 1426 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1427 * are used to indicate high and low level triggering 1428 */ 1429 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1430 BYT_TRIG_LVL); 1431 /* Enable glitch filtering */ 1432 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1433 BYT_GLITCH_F_FAST_CLK; 1434 1435 writel(value, reg); 1436 1437 if (type & IRQ_TYPE_EDGE_BOTH) 1438 irq_set_handler_locked(d, handle_edge_irq); 1439 else if (type & IRQ_TYPE_LEVEL_MASK) 1440 irq_set_handler_locked(d, handle_level_irq); 1441 1442 raw_spin_unlock_irqrestore(&byt_lock, flags); 1443 1444 return 0; 1445 } 1446 1447 static const struct irq_chip byt_gpio_irq_chip = { 1448 .name = "BYT-GPIO", 1449 .irq_ack = byt_irq_ack, 1450 .irq_mask = byt_irq_mask, 1451 .irq_unmask = byt_irq_unmask, 1452 .irq_set_type = byt_irq_type, 1453 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 1454 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1455 }; 1456 1457 static void byt_gpio_irq_handler(struct irq_desc *desc) 1458 { 1459 struct irq_data *data = irq_desc_get_irq_data(desc); 1460 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1461 struct irq_chip *chip = irq_data_get_irq_chip(data); 1462 u32 base, pin; 1463 void __iomem *reg; 1464 unsigned long pending; 1465 1466 /* check from GPIO controller which pin triggered the interrupt */ 1467 for (base = 0; base < vg->chip.ngpio; base += 32) { 1468 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1469 1470 if (!reg) { 1471 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1472 continue; 1473 } 1474 1475 raw_spin_lock(&byt_lock); 1476 pending = readl(reg); 1477 raw_spin_unlock(&byt_lock); 1478 for_each_set_bit(pin, &pending, 32) 1479 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1480 } 1481 chip->irq_eoi(data); 1482 } 1483 1484 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) 1485 { 1486 int direct_irq, ioapic_direct_irq_base; 1487 u8 *match, direct_irq_mux[16]; 1488 u32 trig; 1489 1490 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, 1491 sizeof(direct_irq_mux)); 1492 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); 1493 if (!match) { 1494 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); 1495 return false; 1496 } 1497 1498 direct_irq = match - direct_irq_mux; 1499 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ 1500 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; 1501 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, 1502 direct_irq, direct_irq + ioapic_direct_irq_base); 1503 1504 /* 1505 * Testing has shown that the way direct IRQs work is that the combination of the 1506 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ 1507 * trigger block, which normally sets the status flag in the IRQ status reg at 1508 * 0x800, to one of the IO-APIC pins according to the mux registers. 1509 * 1510 * This means that: 1511 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block 1512 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly 1513 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, 1514 * selecting edge mode operation then on the first edge the IO-APIC pin goes 1515 * high, but since no write-to-clear write will be done to the IRQ status reg 1516 * at 0x800, the detected edge condition will never get cleared. 1517 */ 1518 trig = conf0 & BYT_TRIG_MASK; 1519 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && 1520 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { 1521 dev_warn(vg->dev, 1522 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n", 1523 pin, conf0); 1524 return false; 1525 } 1526 1527 return true; 1528 } 1529 1530 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1531 unsigned long *valid_mask, 1532 unsigned int ngpios) 1533 { 1534 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1535 void __iomem *reg; 1536 u32 value; 1537 int i; 1538 1539 /* 1540 * Clear interrupt triggers for all pins that are GPIOs and 1541 * do not use direct IRQ mode. This will prevent spurious 1542 * interrupts from misconfigured pins. 1543 */ 1544 for (i = 0; i < vg->soc->npins; i++) { 1545 unsigned int pin = vg->soc->pins[i].number; 1546 1547 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1548 if (!reg) { 1549 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); 1550 continue; 1551 } 1552 1553 value = readl(reg); 1554 if (value & BYT_DIRECT_IRQ_EN) { 1555 if (byt_direct_irq_sanity_check(vg, i, value)) { 1556 clear_bit(i, valid_mask); 1557 } else { 1558 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | 1559 BYT_TRIG_NEG | BYT_TRIG_LVL); 1560 writel(value, reg); 1561 } 1562 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1563 byt_gpio_clear_triggering(vg, i); 1564 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1565 } 1566 } 1567 } 1568 1569 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1570 { 1571 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1572 void __iomem *reg; 1573 u32 base, value; 1574 1575 /* clear interrupt status trigger registers */ 1576 for (base = 0; base < vg->soc->npins; base += 32) { 1577 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1578 1579 if (!reg) { 1580 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1581 continue; 1582 } 1583 1584 writel(0xffffffff, reg); 1585 /* make sure trigger bits are cleared, if not then a pin 1586 might be misconfigured in bios */ 1587 value = readl(reg); 1588 if (value) 1589 dev_err(vg->dev, 1590 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n", 1591 base / 32, value); 1592 } 1593 1594 return 0; 1595 } 1596 1597 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 1598 { 1599 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1600 struct device *dev = vg->dev; 1601 int ret; 1602 1603 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1604 if (ret) 1605 dev_err(dev, "failed to add GPIO pin range\n"); 1606 1607 return ret; 1608 } 1609 1610 static int byt_gpio_probe(struct intel_pinctrl *vg) 1611 { 1612 struct platform_device *pdev = to_platform_device(vg->dev); 1613 struct gpio_chip *gc; 1614 int irq, ret; 1615 1616 /* Set up gpio chip */ 1617 vg->chip = byt_gpio_chip; 1618 gc = &vg->chip; 1619 gc->label = dev_name(vg->dev); 1620 gc->base = -1; 1621 gc->can_sleep = false; 1622 gc->add_pin_ranges = byt_gpio_add_pin_ranges; 1623 gc->parent = vg->dev; 1624 gc->ngpio = vg->soc->npins; 1625 1626 #ifdef CONFIG_PM_SLEEP 1627 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1628 GFP_KERNEL); 1629 if (!vg->context.pads) 1630 return -ENOMEM; 1631 #endif 1632 1633 /* set up interrupts */ 1634 irq = platform_get_irq_optional(pdev, 0); 1635 if (irq > 0) { 1636 struct gpio_irq_chip *girq; 1637 1638 girq = &gc->irq; 1639 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); 1640 girq->init_hw = byt_gpio_irq_init_hw; 1641 girq->init_valid_mask = byt_init_irq_valid_mask; 1642 girq->parent_handler = byt_gpio_irq_handler; 1643 girq->num_parents = 1; 1644 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1645 sizeof(*girq->parents), GFP_KERNEL); 1646 if (!girq->parents) 1647 return -ENOMEM; 1648 girq->parents[0] = irq; 1649 girq->default_type = IRQ_TYPE_NONE; 1650 girq->handler = handle_bad_irq; 1651 } 1652 1653 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1654 if (ret) { 1655 dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1656 return ret; 1657 } 1658 1659 return ret; 1660 } 1661 1662 static int byt_set_soc_data(struct intel_pinctrl *vg, 1663 const struct intel_pinctrl_soc_data *soc) 1664 { 1665 struct platform_device *pdev = to_platform_device(vg->dev); 1666 int i; 1667 1668 vg->soc = soc; 1669 1670 vg->ncommunities = vg->soc->ncommunities; 1671 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, 1672 sizeof(*vg->communities), GFP_KERNEL); 1673 if (!vg->communities) 1674 return -ENOMEM; 1675 1676 for (i = 0; i < vg->soc->ncommunities; i++) { 1677 struct intel_community *comm = vg->communities + i; 1678 1679 *comm = vg->soc->communities[i]; 1680 1681 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1682 if (IS_ERR(comm->pad_regs)) 1683 return PTR_ERR(comm->pad_regs); 1684 } 1685 1686 return 0; 1687 } 1688 1689 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1690 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1691 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1692 { } 1693 }; 1694 1695 static int byt_pinctrl_probe(struct platform_device *pdev) 1696 { 1697 const struct intel_pinctrl_soc_data *soc_data; 1698 struct device *dev = &pdev->dev; 1699 struct intel_pinctrl *vg; 1700 int ret; 1701 1702 soc_data = intel_pinctrl_get_soc_data(pdev); 1703 if (IS_ERR(soc_data)) 1704 return PTR_ERR(soc_data); 1705 1706 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1707 if (!vg) 1708 return -ENOMEM; 1709 1710 vg->dev = dev; 1711 ret = byt_set_soc_data(vg, soc_data); 1712 if (ret) { 1713 dev_err(dev, "failed to set soc data\n"); 1714 return ret; 1715 } 1716 1717 vg->pctldesc = byt_pinctrl_desc; 1718 vg->pctldesc.name = dev_name(dev); 1719 vg->pctldesc.pins = vg->soc->pins; 1720 vg->pctldesc.npins = vg->soc->npins; 1721 1722 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1723 if (IS_ERR(vg->pctldev)) { 1724 dev_err(dev, "failed to register pinctrl driver\n"); 1725 return PTR_ERR(vg->pctldev); 1726 } 1727 1728 ret = byt_gpio_probe(vg); 1729 if (ret) 1730 return ret; 1731 1732 platform_set_drvdata(pdev, vg); 1733 pm_runtime_enable(dev); 1734 1735 return 0; 1736 } 1737 1738 #ifdef CONFIG_PM_SLEEP 1739 static int byt_gpio_suspend(struct device *dev) 1740 { 1741 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1742 unsigned long flags; 1743 int i; 1744 1745 raw_spin_lock_irqsave(&byt_lock, flags); 1746 1747 for (i = 0; i < vg->soc->npins; i++) { 1748 void __iomem *reg; 1749 u32 value; 1750 unsigned int pin = vg->soc->pins[i].number; 1751 1752 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1753 if (!reg) { 1754 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1755 continue; 1756 } 1757 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1758 vg->context.pads[i].conf0 = value; 1759 1760 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1761 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1762 vg->context.pads[i].val = value; 1763 } 1764 1765 raw_spin_unlock_irqrestore(&byt_lock, flags); 1766 return 0; 1767 } 1768 1769 static int byt_gpio_resume(struct device *dev) 1770 { 1771 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1772 unsigned long flags; 1773 int i; 1774 1775 raw_spin_lock_irqsave(&byt_lock, flags); 1776 1777 for (i = 0; i < vg->soc->npins; i++) { 1778 void __iomem *reg; 1779 u32 value; 1780 unsigned int pin = vg->soc->pins[i].number; 1781 1782 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1783 if (!reg) { 1784 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1785 continue; 1786 } 1787 value = readl(reg); 1788 if ((value & BYT_CONF0_RESTORE_MASK) != 1789 vg->context.pads[i].conf0) { 1790 value &= ~BYT_CONF0_RESTORE_MASK; 1791 value |= vg->context.pads[i].conf0; 1792 writel(value, reg); 1793 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); 1794 } 1795 1796 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1797 value = readl(reg); 1798 if ((value & BYT_VAL_RESTORE_MASK) != 1799 vg->context.pads[i].val) { 1800 u32 v; 1801 1802 v = value & ~BYT_VAL_RESTORE_MASK; 1803 v |= vg->context.pads[i].val; 1804 if (v != value) { 1805 writel(v, reg); 1806 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); 1807 } 1808 } 1809 } 1810 1811 raw_spin_unlock_irqrestore(&byt_lock, flags); 1812 return 0; 1813 } 1814 #endif 1815 1816 #ifdef CONFIG_PM 1817 static int byt_gpio_runtime_suspend(struct device *dev) 1818 { 1819 return 0; 1820 } 1821 1822 static int byt_gpio_runtime_resume(struct device *dev) 1823 { 1824 return 0; 1825 } 1826 #endif 1827 1828 static const struct dev_pm_ops byt_gpio_pm_ops = { 1829 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1830 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1831 NULL) 1832 }; 1833 1834 static struct platform_driver byt_gpio_driver = { 1835 .probe = byt_pinctrl_probe, 1836 .driver = { 1837 .name = "byt_gpio", 1838 .pm = &byt_gpio_pm_ops, 1839 .acpi_match_table = byt_gpio_acpi_match, 1840 .suppress_bind_attrs = true, 1841 }, 1842 }; 1843 1844 static int __init byt_gpio_init(void) 1845 { 1846 return platform_driver_register(&byt_gpio_driver); 1847 } 1848 subsys_initcall(byt_gpio_init); 1849