1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Pinctrl GPIO driver for Intel Baytrail 4 * 5 * Copyright (c) 2012-2013, Intel Corporation 6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/seq_file.h> 21 #include <linux/string_helpers.h> 22 23 #include <linux/pinctrl/pinctrl.h> 24 #include <linux/pinctrl/pinmux.h> 25 #include <linux/pinctrl/pinconf.h> 26 #include <linux/pinctrl/pinconf-generic.h> 27 28 #include "pinctrl-intel.h" 29 30 /* memory mapped register offsets */ 31 #define BYT_CONF0_REG 0x000 32 #define BYT_CONF1_REG 0x004 33 #define BYT_VAL_REG 0x008 34 #define BYT_DFT_REG 0x00c 35 #define BYT_INT_STAT_REG 0x800 36 #define BYT_DIRECT_IRQ_REG 0x980 37 #define BYT_DEBOUNCE_REG 0x9d0 38 39 /* BYT_CONF0_REG register bits */ 40 #define BYT_IODEN BIT(31) 41 #define BYT_DIRECT_IRQ_EN BIT(27) 42 #define BYT_TRIG_MASK GENMASK(26, 24) 43 #define BYT_TRIG_NEG BIT(26) 44 #define BYT_TRIG_POS BIT(25) 45 #define BYT_TRIG_LVL BIT(24) 46 #define BYT_DEBOUNCE_EN BIT(20) 47 #define BYT_GLITCH_FILTER_EN BIT(19) 48 #define BYT_GLITCH_F_SLOW_CLK BIT(17) 49 #define BYT_GLITCH_F_FAST_CLK BIT(16) 50 #define BYT_PULL_STR_SHIFT 9 51 #define BYT_PULL_STR_MASK GENMASK(10, 9) 52 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT) 53 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT) 54 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT) 55 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT) 56 #define BYT_PULL_ASSIGN_MASK GENMASK(8, 7) 57 #define BYT_PULL_ASSIGN_DOWN BIT(8) 58 #define BYT_PULL_ASSIGN_UP BIT(7) 59 #define BYT_PIN_MUX GENMASK(2, 0) 60 61 /* BYT_VAL_REG register bits */ 62 #define BYT_DIR_MASK GENMASK(2, 1) 63 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/ 64 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/ 65 #define BYT_LEVEL BIT(0) 66 67 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | BYT_PIN_MUX) 68 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL) 69 70 /* BYT_DEBOUNCE_REG bits */ 71 #define BYT_DEBOUNCE_PULSE_MASK GENMASK(2, 0) 72 #define BYT_DEBOUNCE_PULSE_375US 1 73 #define BYT_DEBOUNCE_PULSE_750US 2 74 #define BYT_DEBOUNCE_PULSE_1500US 3 75 #define BYT_DEBOUNCE_PULSE_3MS 4 76 #define BYT_DEBOUNCE_PULSE_6MS 5 77 #define BYT_DEBOUNCE_PULSE_12MS 6 78 #define BYT_DEBOUNCE_PULSE_24MS 7 79 80 #define BYT_NGPIO_SCORE 102 81 #define BYT_NGPIO_NCORE 28 82 #define BYT_NGPIO_SUS 44 83 84 #define BYT_SCORE_ACPI_UID "1" 85 #define BYT_NCORE_ACPI_UID "2" 86 #define BYT_SUS_ACPI_UID "3" 87 88 /* 89 * This is the function value most pins have for GPIO muxing. If the value 90 * differs from the default one, it must be explicitly mentioned. Otherwise, the 91 * pin control implementation will set the muxing value to default GPIO if it 92 * does not find a match for the requested function. 93 */ 94 #define BYT_DEFAULT_GPIO_MUX 0 95 #define BYT_ALTER_GPIO_MUX 1 96 97 struct intel_pad_context { 98 u32 conf0; 99 u32 val; 100 }; 101 102 #define COMMUNITY(p, n, map) \ 103 { \ 104 .pin_base = (p), \ 105 .npins = (n), \ 106 .pad_map = (map),\ 107 } 108 109 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */ 110 static const struct pinctrl_pin_desc byt_score_pins[] = { 111 PINCTRL_PIN(0, "SATA_GP0"), 112 PINCTRL_PIN(1, "SATA_GP1"), 113 PINCTRL_PIN(2, "SATA_LED#"), 114 PINCTRL_PIN(3, "PCIE_CLKREQ0"), 115 PINCTRL_PIN(4, "PCIE_CLKREQ1"), 116 PINCTRL_PIN(5, "PCIE_CLKREQ2"), 117 PINCTRL_PIN(6, "PCIE_CLKREQ3"), 118 PINCTRL_PIN(7, "SD3_WP"), 119 PINCTRL_PIN(8, "HDA_RST"), 120 PINCTRL_PIN(9, "HDA_SYNC"), 121 PINCTRL_PIN(10, "HDA_CLK"), 122 PINCTRL_PIN(11, "HDA_SDO"), 123 PINCTRL_PIN(12, "HDA_SDI0"), 124 PINCTRL_PIN(13, "HDA_SDI1"), 125 PINCTRL_PIN(14, "GPIO_S0_SC14"), 126 PINCTRL_PIN(15, "GPIO_S0_SC15"), 127 PINCTRL_PIN(16, "MMC1_CLK"), 128 PINCTRL_PIN(17, "MMC1_D0"), 129 PINCTRL_PIN(18, "MMC1_D1"), 130 PINCTRL_PIN(19, "MMC1_D2"), 131 PINCTRL_PIN(20, "MMC1_D3"), 132 PINCTRL_PIN(21, "MMC1_D4"), 133 PINCTRL_PIN(22, "MMC1_D5"), 134 PINCTRL_PIN(23, "MMC1_D6"), 135 PINCTRL_PIN(24, "MMC1_D7"), 136 PINCTRL_PIN(25, "MMC1_CMD"), 137 PINCTRL_PIN(26, "MMC1_RST"), 138 PINCTRL_PIN(27, "SD2_CLK"), 139 PINCTRL_PIN(28, "SD2_D0"), 140 PINCTRL_PIN(29, "SD2_D1"), 141 PINCTRL_PIN(30, "SD2_D2"), 142 PINCTRL_PIN(31, "SD2_D3_CD"), 143 PINCTRL_PIN(32, "SD2_CMD"), 144 PINCTRL_PIN(33, "SD3_CLK"), 145 PINCTRL_PIN(34, "SD3_D0"), 146 PINCTRL_PIN(35, "SD3_D1"), 147 PINCTRL_PIN(36, "SD3_D2"), 148 PINCTRL_PIN(37, "SD3_D3"), 149 PINCTRL_PIN(38, "SD3_CD"), 150 PINCTRL_PIN(39, "SD3_CMD"), 151 PINCTRL_PIN(40, "SD3_1P8EN"), 152 PINCTRL_PIN(41, "SD3_PWREN#"), 153 PINCTRL_PIN(42, "ILB_LPC_AD0"), 154 PINCTRL_PIN(43, "ILB_LPC_AD1"), 155 PINCTRL_PIN(44, "ILB_LPC_AD2"), 156 PINCTRL_PIN(45, "ILB_LPC_AD3"), 157 PINCTRL_PIN(46, "ILB_LPC_FRAME"), 158 PINCTRL_PIN(47, "ILB_LPC_CLK0"), 159 PINCTRL_PIN(48, "ILB_LPC_CLK1"), 160 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"), 161 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"), 162 PINCTRL_PIN(51, "PCU_SMB_DATA"), 163 PINCTRL_PIN(52, "PCU_SMB_CLK"), 164 PINCTRL_PIN(53, "PCU_SMB_ALERT"), 165 PINCTRL_PIN(54, "ILB_8254_SPKR"), 166 PINCTRL_PIN(55, "GPIO_S0_SC55"), 167 PINCTRL_PIN(56, "GPIO_S0_SC56"), 168 PINCTRL_PIN(57, "GPIO_S0_SC57"), 169 PINCTRL_PIN(58, "GPIO_S0_SC58"), 170 PINCTRL_PIN(59, "GPIO_S0_SC59"), 171 PINCTRL_PIN(60, "GPIO_S0_SC60"), 172 PINCTRL_PIN(61, "GPIO_S0_SC61"), 173 PINCTRL_PIN(62, "LPE_I2S2_CLK"), 174 PINCTRL_PIN(63, "LPE_I2S2_FRM"), 175 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"), 176 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"), 177 PINCTRL_PIN(66, "SIO_SPI_CS"), 178 PINCTRL_PIN(67, "SIO_SPI_MISO"), 179 PINCTRL_PIN(68, "SIO_SPI_MOSI"), 180 PINCTRL_PIN(69, "SIO_SPI_CLK"), 181 PINCTRL_PIN(70, "SIO_UART1_RXD"), 182 PINCTRL_PIN(71, "SIO_UART1_TXD"), 183 PINCTRL_PIN(72, "SIO_UART1_RTS"), 184 PINCTRL_PIN(73, "SIO_UART1_CTS"), 185 PINCTRL_PIN(74, "SIO_UART2_RXD"), 186 PINCTRL_PIN(75, "SIO_UART2_TXD"), 187 PINCTRL_PIN(76, "SIO_UART2_RTS"), 188 PINCTRL_PIN(77, "SIO_UART2_CTS"), 189 PINCTRL_PIN(78, "SIO_I2C0_DATA"), 190 PINCTRL_PIN(79, "SIO_I2C0_CLK"), 191 PINCTRL_PIN(80, "SIO_I2C1_DATA"), 192 PINCTRL_PIN(81, "SIO_I2C1_CLK"), 193 PINCTRL_PIN(82, "SIO_I2C2_DATA"), 194 PINCTRL_PIN(83, "SIO_I2C2_CLK"), 195 PINCTRL_PIN(84, "SIO_I2C3_DATA"), 196 PINCTRL_PIN(85, "SIO_I2C3_CLK"), 197 PINCTRL_PIN(86, "SIO_I2C4_DATA"), 198 PINCTRL_PIN(87, "SIO_I2C4_CLK"), 199 PINCTRL_PIN(88, "SIO_I2C5_DATA"), 200 PINCTRL_PIN(89, "SIO_I2C5_CLK"), 201 PINCTRL_PIN(90, "SIO_I2C6_DATA"), 202 PINCTRL_PIN(91, "SIO_I2C6_CLK"), 203 PINCTRL_PIN(92, "GPIO_S0_SC92"), 204 PINCTRL_PIN(93, "GPIO_S0_SC93"), 205 PINCTRL_PIN(94, "SIO_PWM0"), 206 PINCTRL_PIN(95, "SIO_PWM1"), 207 PINCTRL_PIN(96, "PMC_PLT_CLK0"), 208 PINCTRL_PIN(97, "PMC_PLT_CLK1"), 209 PINCTRL_PIN(98, "PMC_PLT_CLK2"), 210 PINCTRL_PIN(99, "PMC_PLT_CLK3"), 211 PINCTRL_PIN(100, "PMC_PLT_CLK4"), 212 PINCTRL_PIN(101, "PMC_PLT_CLK5"), 213 }; 214 215 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = { 216 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, 217 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, 218 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, 219 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, 220 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, 221 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, 222 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, 223 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, 224 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, 225 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, 226 97, 100, 227 }; 228 229 /* SCORE groups */ 230 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 }; 231 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 }; 232 233 static const unsigned int byt_score_pwm0_pins[] = { 94 }; 234 static const unsigned int byt_score_pwm1_pins[] = { 95 }; 235 236 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 }; 237 238 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 }; 239 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 }; 240 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 }; 241 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 }; 242 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 }; 243 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 }; 244 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 }; 245 246 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 }; 247 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 }; 248 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 }; 249 250 static const unsigned int byt_score_sdcard_pins[] = { 251 7, 33, 34, 35, 36, 37, 38, 39, 40, 41, 252 }; 253 static const unsigned int byt_score_sdcard_mux_values[] = { 254 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 255 }; 256 257 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 }; 258 259 static const unsigned int byt_score_emmc_pins[] = { 260 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 261 }; 262 263 static const unsigned int byt_score_ilb_lpc_pins[] = { 264 42, 43, 44, 45, 46, 47, 48, 49, 50, 265 }; 266 267 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 }; 268 269 static const unsigned int byt_score_plt_clk0_pins[] = { 96 }; 270 static const unsigned int byt_score_plt_clk1_pins[] = { 97 }; 271 static const unsigned int byt_score_plt_clk2_pins[] = { 98 }; 272 static const unsigned int byt_score_plt_clk3_pins[] = { 99 }; 273 static const unsigned int byt_score_plt_clk4_pins[] = { 100 }; 274 static const unsigned int byt_score_plt_clk5_pins[] = { 101 }; 275 276 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 }; 277 278 static const struct intel_pingroup byt_score_groups[] = { 279 PIN_GROUP("uart1_grp", byt_score_uart1_pins, 1), 280 PIN_GROUP("uart2_grp", byt_score_uart2_pins, 1), 281 PIN_GROUP("pwm0_grp", byt_score_pwm0_pins, 1), 282 PIN_GROUP("pwm1_grp", byt_score_pwm1_pins, 1), 283 PIN_GROUP("ssp2_grp", byt_score_ssp2_pins, 1), 284 PIN_GROUP("sio_spi_grp", byt_score_sio_spi_pins, 1), 285 PIN_GROUP("i2c5_grp", byt_score_i2c5_pins, 1), 286 PIN_GROUP("i2c6_grp", byt_score_i2c6_pins, 1), 287 PIN_GROUP("i2c4_grp", byt_score_i2c4_pins, 1), 288 PIN_GROUP("i2c3_grp", byt_score_i2c3_pins, 1), 289 PIN_GROUP("i2c2_grp", byt_score_i2c2_pins, 1), 290 PIN_GROUP("i2c1_grp", byt_score_i2c1_pins, 1), 291 PIN_GROUP("i2c0_grp", byt_score_i2c0_pins, 1), 292 PIN_GROUP("ssp0_grp", byt_score_ssp0_pins, 1), 293 PIN_GROUP("ssp1_grp", byt_score_ssp1_pins, 1), 294 PIN_GROUP("sdcard_grp", byt_score_sdcard_pins, byt_score_sdcard_mux_values), 295 PIN_GROUP("sdio_grp", byt_score_sdio_pins, 1), 296 PIN_GROUP("emmc_grp", byt_score_emmc_pins, 1), 297 PIN_GROUP("lpc_grp", byt_score_ilb_lpc_pins, 1), 298 PIN_GROUP("sata_grp", byt_score_sata_pins, 1), 299 PIN_GROUP("plt_clk0_grp", byt_score_plt_clk0_pins, 1), 300 PIN_GROUP("plt_clk1_grp", byt_score_plt_clk1_pins, 1), 301 PIN_GROUP("plt_clk2_grp", byt_score_plt_clk2_pins, 1), 302 PIN_GROUP("plt_clk3_grp", byt_score_plt_clk3_pins, 1), 303 PIN_GROUP("plt_clk4_grp", byt_score_plt_clk4_pins, 1), 304 PIN_GROUP("plt_clk5_grp", byt_score_plt_clk5_pins, 1), 305 PIN_GROUP("smbus_grp", byt_score_smbus_pins, 1), 306 }; 307 308 static const char * const byt_score_uart_groups[] = { 309 "uart1_grp", "uart2_grp", 310 }; 311 static const char * const byt_score_pwm_groups[] = { 312 "pwm0_grp", "pwm1_grp", 313 }; 314 static const char * const byt_score_ssp_groups[] = { 315 "ssp0_grp", "ssp1_grp", "ssp2_grp", 316 }; 317 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" }; 318 static const char * const byt_score_i2c_groups[] = { 319 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", 320 "i2c6_grp", 321 }; 322 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" }; 323 static const char * const byt_score_sdio_groups[] = { "sdio_grp" }; 324 static const char * const byt_score_emmc_groups[] = { "emmc_grp" }; 325 static const char * const byt_score_lpc_groups[] = { "lpc_grp" }; 326 static const char * const byt_score_sata_groups[] = { "sata_grp" }; 327 static const char * const byt_score_plt_clk_groups[] = { 328 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 329 "plt_clk4_grp", "plt_clk5_grp", 330 }; 331 static const char * const byt_score_smbus_groups[] = { "smbus_grp" }; 332 static const char * const byt_score_gpio_groups[] = { 333 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp", 334 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp", 335 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp", 336 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp", 337 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp", 338 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp", 339 }; 340 341 static const struct intel_function byt_score_functions[] = { 342 FUNCTION("uart", byt_score_uart_groups), 343 FUNCTION("pwm", byt_score_pwm_groups), 344 FUNCTION("ssp", byt_score_ssp_groups), 345 FUNCTION("spi", byt_score_spi_groups), 346 FUNCTION("i2c", byt_score_i2c_groups), 347 FUNCTION("sdcard", byt_score_sdcard_groups), 348 FUNCTION("sdio", byt_score_sdio_groups), 349 FUNCTION("emmc", byt_score_emmc_groups), 350 FUNCTION("lpc", byt_score_lpc_groups), 351 FUNCTION("sata", byt_score_sata_groups), 352 FUNCTION("plt_clk", byt_score_plt_clk_groups), 353 FUNCTION("smbus", byt_score_smbus_groups), 354 FUNCTION("gpio", byt_score_gpio_groups), 355 }; 356 357 static const struct intel_community byt_score_communities[] = { 358 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), 359 }; 360 361 static const struct intel_pinctrl_soc_data byt_score_soc_data = { 362 .uid = BYT_SCORE_ACPI_UID, 363 .pins = byt_score_pins, 364 .npins = ARRAY_SIZE(byt_score_pins), 365 .groups = byt_score_groups, 366 .ngroups = ARRAY_SIZE(byt_score_groups), 367 .functions = byt_score_functions, 368 .nfunctions = ARRAY_SIZE(byt_score_functions), 369 .communities = byt_score_communities, 370 .ncommunities = ARRAY_SIZE(byt_score_communities), 371 }; 372 373 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */ 374 static const struct pinctrl_pin_desc byt_sus_pins[] = { 375 PINCTRL_PIN(0, "GPIO_S50"), 376 PINCTRL_PIN(1, "GPIO_S51"), 377 PINCTRL_PIN(2, "GPIO_S52"), 378 PINCTRL_PIN(3, "GPIO_S53"), 379 PINCTRL_PIN(4, "GPIO_S54"), 380 PINCTRL_PIN(5, "GPIO_S55"), 381 PINCTRL_PIN(6, "GPIO_S56"), 382 PINCTRL_PIN(7, "GPIO_S57"), 383 PINCTRL_PIN(8, "GPIO_S58"), 384 PINCTRL_PIN(9, "GPIO_S59"), 385 PINCTRL_PIN(10, "GPIO_S510"), 386 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"), 387 PINCTRL_PIN(12, "PMC_SUSCLK0"), 388 PINCTRL_PIN(13, "GPIO_S513"), 389 PINCTRL_PIN(14, "USB_ULPI_RST"), 390 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"), 391 PINCTRL_PIN(16, "PMC_PWRBTN"), 392 PINCTRL_PIN(17, "GPIO_S517"), 393 PINCTRL_PIN(18, "PMC_SUS_STAT"), 394 PINCTRL_PIN(19, "USB_OC0"), 395 PINCTRL_PIN(20, "USB_OC1"), 396 PINCTRL_PIN(21, "PCU_SPI_CS1"), 397 PINCTRL_PIN(22, "GPIO_S522"), 398 PINCTRL_PIN(23, "GPIO_S523"), 399 PINCTRL_PIN(24, "GPIO_S524"), 400 PINCTRL_PIN(25, "GPIO_S525"), 401 PINCTRL_PIN(26, "GPIO_S526"), 402 PINCTRL_PIN(27, "GPIO_S527"), 403 PINCTRL_PIN(28, "GPIO_S528"), 404 PINCTRL_PIN(29, "GPIO_S529"), 405 PINCTRL_PIN(30, "GPIO_S530"), 406 PINCTRL_PIN(31, "USB_ULPI_CLK"), 407 PINCTRL_PIN(32, "USB_ULPI_DATA0"), 408 PINCTRL_PIN(33, "USB_ULPI_DATA1"), 409 PINCTRL_PIN(34, "USB_ULPI_DATA2"), 410 PINCTRL_PIN(35, "USB_ULPI_DATA3"), 411 PINCTRL_PIN(36, "USB_ULPI_DATA4"), 412 PINCTRL_PIN(37, "USB_ULPI_DATA5"), 413 PINCTRL_PIN(38, "USB_ULPI_DATA6"), 414 PINCTRL_PIN(39, "USB_ULPI_DATA7"), 415 PINCTRL_PIN(40, "USB_ULPI_DIR"), 416 PINCTRL_PIN(41, "USB_ULPI_NXT"), 417 PINCTRL_PIN(42, "USB_ULPI_STP"), 418 PINCTRL_PIN(43, "USB_ULPI_REFCLK"), 419 }; 420 421 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = { 422 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 423 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 424 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, 425 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 426 52, 53, 59, 40, 427 }; 428 429 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 }; 430 static const unsigned int byt_sus_usb_over_current_mode_values[] = { 0, 0 }; 431 static const unsigned int byt_sus_usb_over_current_gpio_mode_values[] = { 1, 1 }; 432 433 static const unsigned int byt_sus_usb_ulpi_pins[] = { 434 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 435 }; 436 static const unsigned int byt_sus_usb_ulpi_mode_values[] = { 437 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 438 }; 439 static const unsigned int byt_sus_usb_ulpi_gpio_mode_values[] = { 440 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 441 }; 442 443 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 }; 444 static const unsigned int byt_sus_pcu_spi_mode_values[] = { 0 }; 445 static const unsigned int byt_sus_pcu_spi_gpio_mode_values[] = { 1 }; 446 447 static const unsigned int byt_sus_pmu_clk1_pins[] = { 5 }; 448 static const unsigned int byt_sus_pmu_clk2_pins[] = { 6 }; 449 450 static const struct intel_pingroup byt_sus_groups[] = { 451 PIN_GROUP("usb_oc_grp", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_mode_values), 452 PIN_GROUP("usb_ulpi_grp", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mode_values), 453 PIN_GROUP("pcu_spi_grp", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mode_values), 454 PIN_GROUP("usb_oc_grp_gpio", byt_sus_usb_over_current_pins, byt_sus_usb_over_current_gpio_mode_values), 455 PIN_GROUP("usb_ulpi_grp_gpio", byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_gpio_mode_values), 456 PIN_GROUP("pcu_spi_grp_gpio", byt_sus_pcu_spi_pins, byt_sus_pcu_spi_gpio_mode_values), 457 PIN_GROUP("pmu_clk1_grp", byt_sus_pmu_clk1_pins, 1), 458 PIN_GROUP("pmu_clk2_grp", byt_sus_pmu_clk2_pins, 1), 459 }; 460 461 static const char * const byt_sus_usb_groups[] = { 462 "usb_oc_grp", "usb_ulpi_grp", 463 }; 464 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" }; 465 static const char * const byt_sus_pmu_clk_groups[] = { 466 "pmu_clk1_grp", "pmu_clk2_grp", 467 }; 468 static const char * const byt_sus_gpio_groups[] = { 469 "usb_oc_grp_gpio", "usb_ulpi_grp_gpio", "pcu_spi_grp_gpio", 470 "pmu_clk1_grp", "pmu_clk2_grp", 471 }; 472 473 static const struct intel_function byt_sus_functions[] = { 474 FUNCTION("usb", byt_sus_usb_groups), 475 FUNCTION("spi", byt_sus_spi_groups), 476 FUNCTION("gpio", byt_sus_gpio_groups), 477 FUNCTION("pmu_clk", byt_sus_pmu_clk_groups), 478 }; 479 480 static const struct intel_community byt_sus_communities[] = { 481 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), 482 }; 483 484 static const struct intel_pinctrl_soc_data byt_sus_soc_data = { 485 .uid = BYT_SUS_ACPI_UID, 486 .pins = byt_sus_pins, 487 .npins = ARRAY_SIZE(byt_sus_pins), 488 .groups = byt_sus_groups, 489 .ngroups = ARRAY_SIZE(byt_sus_groups), 490 .functions = byt_sus_functions, 491 .nfunctions = ARRAY_SIZE(byt_sus_functions), 492 .communities = byt_sus_communities, 493 .ncommunities = ARRAY_SIZE(byt_sus_communities), 494 }; 495 496 static const struct pinctrl_pin_desc byt_ncore_pins[] = { 497 PINCTRL_PIN(0, "HV_DDI0_HPD"), 498 PINCTRL_PIN(1, "HV_DDI0_DDC_SDA"), 499 PINCTRL_PIN(2, "HV_DDI0_DDC_SCL"), 500 PINCTRL_PIN(3, "PANEL0_VDDEN"), 501 PINCTRL_PIN(4, "PANEL0_BKLTEN"), 502 PINCTRL_PIN(5, "PANEL0_BKLTCTL"), 503 PINCTRL_PIN(6, "HV_DDI1_HPD"), 504 PINCTRL_PIN(7, "HV_DDI1_DDC_SDA"), 505 PINCTRL_PIN(8, "HV_DDI1_DDC_SCL"), 506 PINCTRL_PIN(9, "PANEL1_VDDEN"), 507 PINCTRL_PIN(10, "PANEL1_BKLTEN"), 508 PINCTRL_PIN(11, "PANEL1_BKLTCTL"), 509 PINCTRL_PIN(12, "GP_INTD_DSI_TE1"), 510 PINCTRL_PIN(13, "HV_DDI2_DDC_SDA"), 511 PINCTRL_PIN(14, "HV_DDI2_DDC_SCL"), 512 PINCTRL_PIN(15, "GP_CAMERASB00"), 513 PINCTRL_PIN(16, "GP_CAMERASB01"), 514 PINCTRL_PIN(17, "GP_CAMERASB02"), 515 PINCTRL_PIN(18, "GP_CAMERASB03"), 516 PINCTRL_PIN(19, "GP_CAMERASB04"), 517 PINCTRL_PIN(20, "GP_CAMERASB05"), 518 PINCTRL_PIN(21, "GP_CAMERASB06"), 519 PINCTRL_PIN(22, "GP_CAMERASB07"), 520 PINCTRL_PIN(23, "GP_CAMERASB08"), 521 PINCTRL_PIN(24, "GP_CAMERASB09"), 522 PINCTRL_PIN(25, "GP_CAMERASB10"), 523 PINCTRL_PIN(26, "GP_CAMERASB11"), 524 PINCTRL_PIN(27, "GP_INTD_DSI_TE2"), 525 }; 526 527 static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 528 19, 18, 17, 20, 21, 22, 24, 25, 23, 16, 529 14, 15, 12, 26, 27, 1, 4, 8, 11, 0, 530 3, 6, 10, 13, 2, 5, 9, 7, 531 }; 532 533 static const struct intel_community byt_ncore_communities[] = { 534 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), 535 }; 536 537 static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { 538 .uid = BYT_NCORE_ACPI_UID, 539 .pins = byt_ncore_pins, 540 .npins = ARRAY_SIZE(byt_ncore_pins), 541 .communities = byt_ncore_communities, 542 .ncommunities = ARRAY_SIZE(byt_ncore_communities), 543 }; 544 545 static const struct intel_pinctrl_soc_data *byt_soc_data[] = { 546 &byt_score_soc_data, 547 &byt_sus_soc_data, 548 &byt_ncore_soc_data, 549 NULL 550 }; 551 552 static DEFINE_RAW_SPINLOCK(byt_lock); 553 554 static struct intel_community *byt_get_community(struct intel_pinctrl *vg, 555 unsigned int pin) 556 { 557 struct intel_community *comm; 558 int i; 559 560 for (i = 0; i < vg->ncommunities; i++) { 561 comm = vg->communities + i; 562 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) 563 return comm; 564 } 565 566 return NULL; 567 } 568 569 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset, 570 int reg) 571 { 572 struct intel_community *comm = byt_get_community(vg, offset); 573 u32 reg_offset; 574 575 if (!comm) 576 return NULL; 577 578 offset -= comm->pin_base; 579 switch (reg) { 580 case BYT_INT_STAT_REG: 581 reg_offset = (offset / 32) * 4; 582 break; 583 case BYT_DEBOUNCE_REG: 584 reg_offset = 0; 585 break; 586 default: 587 reg_offset = comm->pad_map[offset] * 16; 588 break; 589 } 590 591 return comm->pad_regs + reg_offset + reg; 592 } 593 594 static int byt_get_groups_count(struct pinctrl_dev *pctldev) 595 { 596 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 597 598 return vg->soc->ngroups; 599 } 600 601 static const char *byt_get_group_name(struct pinctrl_dev *pctldev, 602 unsigned int selector) 603 { 604 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 605 606 return vg->soc->groups[selector].grp.name; 607 } 608 609 static int byt_get_group_pins(struct pinctrl_dev *pctldev, 610 unsigned int selector, 611 const unsigned int **pins, 612 unsigned int *num_pins) 613 { 614 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 615 616 *pins = vg->soc->groups[selector].grp.pins; 617 *num_pins = vg->soc->groups[selector].grp.npins; 618 619 return 0; 620 } 621 622 static const struct pinctrl_ops byt_pinctrl_ops = { 623 .get_groups_count = byt_get_groups_count, 624 .get_group_name = byt_get_group_name, 625 .get_group_pins = byt_get_group_pins, 626 }; 627 628 static int byt_get_functions_count(struct pinctrl_dev *pctldev) 629 { 630 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 631 632 return vg->soc->nfunctions; 633 } 634 635 static const char *byt_get_function_name(struct pinctrl_dev *pctldev, 636 unsigned int selector) 637 { 638 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 639 640 return vg->soc->functions[selector].func.name; 641 } 642 643 static int byt_get_function_groups(struct pinctrl_dev *pctldev, 644 unsigned int selector, 645 const char * const **groups, 646 unsigned int *ngroups) 647 { 648 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 649 650 *groups = vg->soc->functions[selector].func.groups; 651 *ngroups = vg->soc->functions[selector].func.ngroups; 652 653 return 0; 654 } 655 656 static void byt_set_group_simple_mux(struct intel_pinctrl *vg, 657 const struct intel_pingroup group, 658 unsigned int func) 659 { 660 unsigned long flags; 661 int i; 662 663 raw_spin_lock_irqsave(&byt_lock, flags); 664 665 for (i = 0; i < group.grp.npins; i++) { 666 void __iomem *padcfg0; 667 u32 value; 668 669 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 670 if (!padcfg0) { 671 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 672 group.grp.name, i); 673 continue; 674 } 675 676 value = readl(padcfg0); 677 value &= ~BYT_PIN_MUX; 678 value |= func; 679 writel(value, padcfg0); 680 } 681 682 raw_spin_unlock_irqrestore(&byt_lock, flags); 683 } 684 685 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg, 686 const struct intel_pingroup group, 687 const unsigned int *func) 688 { 689 unsigned long flags; 690 int i; 691 692 raw_spin_lock_irqsave(&byt_lock, flags); 693 694 for (i = 0; i < group.grp.npins; i++) { 695 void __iomem *padcfg0; 696 u32 value; 697 698 padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG); 699 if (!padcfg0) { 700 dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n", 701 group.grp.name, i); 702 continue; 703 } 704 705 value = readl(padcfg0); 706 value &= ~BYT_PIN_MUX; 707 value |= func[i]; 708 writel(value, padcfg0); 709 } 710 711 raw_spin_unlock_irqrestore(&byt_lock, flags); 712 } 713 714 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, 715 unsigned int group_selector) 716 { 717 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev); 718 const struct intel_function func = vg->soc->functions[func_selector]; 719 const struct intel_pingroup group = vg->soc->groups[group_selector]; 720 721 if (group.modes) 722 byt_set_group_mixed_mux(vg, group, group.modes); 723 else if (!strcmp(func.func.name, "gpio")) 724 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX); 725 else 726 byt_set_group_simple_mux(vg, group, group.mode); 727 728 return 0; 729 } 730 731 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset) 732 { 733 /* SCORE pin 92-93 */ 734 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) && 735 offset >= 92 && offset <= 93) 736 return BYT_ALTER_GPIO_MUX; 737 738 /* SUS pin 11-21 */ 739 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) && 740 offset >= 11 && offset <= 21) 741 return BYT_ALTER_GPIO_MUX; 742 743 return BYT_DEFAULT_GPIO_MUX; 744 } 745 746 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset) 747 { 748 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 749 unsigned long flags; 750 u32 value; 751 752 raw_spin_lock_irqsave(&byt_lock, flags); 753 value = readl(reg); 754 755 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */ 756 if (!(value & BYT_DIRECT_IRQ_EN)) 757 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL); 758 759 writel(value, reg); 760 raw_spin_unlock_irqrestore(&byt_lock, flags); 761 } 762 763 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev, 764 struct pinctrl_gpio_range *range, 765 unsigned int offset) 766 { 767 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 768 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 769 u32 value, gpio_mux; 770 unsigned long flags; 771 772 raw_spin_lock_irqsave(&byt_lock, flags); 773 774 /* 775 * In most cases, func pin mux 000 means GPIO function. 776 * But, some pins may have func pin mux 001 represents 777 * GPIO function. 778 * 779 * Because there are devices out there where some pins were not 780 * configured correctly we allow changing the mux value from 781 * request (but print out warning about that). 782 */ 783 value = readl(reg) & BYT_PIN_MUX; 784 gpio_mux = byt_get_gpio_mux(vg, offset); 785 if (gpio_mux != value) { 786 value = readl(reg) & ~BYT_PIN_MUX; 787 value |= gpio_mux; 788 writel(value, reg); 789 790 dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset); 791 } 792 793 raw_spin_unlock_irqrestore(&byt_lock, flags); 794 795 pm_runtime_get(vg->dev); 796 797 return 0; 798 } 799 800 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev, 801 struct pinctrl_gpio_range *range, 802 unsigned int offset) 803 { 804 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 805 806 byt_gpio_clear_triggering(vg, offset); 807 pm_runtime_put(vg->dev); 808 } 809 810 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg, 811 unsigned int offset) 812 { 813 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 814 815 /* 816 * Before making any direction modifications, do a check if gpio is set 817 * for direct IRQ. On Bay Trail, setting GPIO to output does not make 818 * sense, so let's at least inform the caller before they shoot 819 * themselves in the foot. 820 */ 821 if (readl(conf_reg) & BYT_DIRECT_IRQ_EN) 822 dev_info_once(vg->dev, 823 "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n", 824 offset); 825 } 826 827 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev, 828 struct pinctrl_gpio_range *range, 829 unsigned int offset, 830 bool input) 831 { 832 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 833 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 834 unsigned long flags; 835 u32 value; 836 837 raw_spin_lock_irqsave(&byt_lock, flags); 838 839 value = readl(val_reg); 840 value &= ~BYT_DIR_MASK; 841 if (input) 842 value |= BYT_OUTPUT_EN; 843 else 844 byt_gpio_direct_irq_check(vg, offset); 845 846 writel(value, val_reg); 847 848 raw_spin_unlock_irqrestore(&byt_lock, flags); 849 850 return 0; 851 } 852 853 static const struct pinmux_ops byt_pinmux_ops = { 854 .get_functions_count = byt_get_functions_count, 855 .get_function_name = byt_get_function_name, 856 .get_function_groups = byt_get_function_groups, 857 .set_mux = byt_set_mux, 858 .gpio_request_enable = byt_gpio_request_enable, 859 .gpio_disable_free = byt_gpio_disable_free, 860 .gpio_set_direction = byt_gpio_set_direction, 861 }; 862 863 static void byt_get_pull_strength(u32 reg, u16 *strength) 864 { 865 switch (reg & BYT_PULL_STR_MASK) { 866 case BYT_PULL_STR_2K: 867 *strength = 2000; 868 break; 869 case BYT_PULL_STR_10K: 870 *strength = 10000; 871 break; 872 case BYT_PULL_STR_20K: 873 *strength = 20000; 874 break; 875 case BYT_PULL_STR_40K: 876 *strength = 40000; 877 break; 878 } 879 } 880 881 static int byt_set_pull_strength(u32 *reg, u16 strength) 882 { 883 *reg &= ~BYT_PULL_STR_MASK; 884 885 switch (strength) { 886 case 2000: 887 *reg |= BYT_PULL_STR_2K; 888 break; 889 case 10000: 890 *reg |= BYT_PULL_STR_10K; 891 break; 892 case 20000: 893 *reg |= BYT_PULL_STR_20K; 894 break; 895 case 40000: 896 *reg |= BYT_PULL_STR_40K; 897 break; 898 default: 899 return -EINVAL; 900 } 901 902 return 0; 903 } 904 905 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset, 906 unsigned long *config) 907 { 908 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 909 enum pin_config_param param = pinconf_to_config_param(*config); 910 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 911 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 912 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 913 unsigned long flags; 914 u32 conf, pull, val, debounce; 915 u16 arg = 0; 916 917 raw_spin_lock_irqsave(&byt_lock, flags); 918 conf = readl(conf_reg); 919 pull = conf & BYT_PULL_ASSIGN_MASK; 920 val = readl(val_reg); 921 raw_spin_unlock_irqrestore(&byt_lock, flags); 922 923 switch (param) { 924 case PIN_CONFIG_BIAS_DISABLE: 925 if (pull) 926 return -EINVAL; 927 break; 928 case PIN_CONFIG_BIAS_PULL_DOWN: 929 /* Pull assignment is only applicable in input mode */ 930 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN) 931 return -EINVAL; 932 933 byt_get_pull_strength(conf, &arg); 934 935 break; 936 case PIN_CONFIG_BIAS_PULL_UP: 937 /* Pull assignment is only applicable in input mode */ 938 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP) 939 return -EINVAL; 940 941 byt_get_pull_strength(conf, &arg); 942 943 break; 944 case PIN_CONFIG_INPUT_DEBOUNCE: 945 if (!(conf & BYT_DEBOUNCE_EN)) 946 return -EINVAL; 947 948 raw_spin_lock_irqsave(&byt_lock, flags); 949 debounce = readl(db_reg); 950 raw_spin_unlock_irqrestore(&byt_lock, flags); 951 952 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) { 953 case BYT_DEBOUNCE_PULSE_375US: 954 arg = 375; 955 break; 956 case BYT_DEBOUNCE_PULSE_750US: 957 arg = 750; 958 break; 959 case BYT_DEBOUNCE_PULSE_1500US: 960 arg = 1500; 961 break; 962 case BYT_DEBOUNCE_PULSE_3MS: 963 arg = 3000; 964 break; 965 case BYT_DEBOUNCE_PULSE_6MS: 966 arg = 6000; 967 break; 968 case BYT_DEBOUNCE_PULSE_12MS: 969 arg = 12000; 970 break; 971 case BYT_DEBOUNCE_PULSE_24MS: 972 arg = 24000; 973 break; 974 default: 975 return -EINVAL; 976 } 977 978 break; 979 default: 980 return -ENOTSUPP; 981 } 982 983 *config = pinconf_to_config_packed(param, arg); 984 985 return 0; 986 } 987 988 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev, 989 unsigned int offset, 990 unsigned long *configs, 991 unsigned int num_configs) 992 { 993 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev); 994 unsigned int param, arg; 995 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG); 996 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 997 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG); 998 u32 conf, val, db_pulse, debounce; 999 unsigned long flags; 1000 int i, ret = 0; 1001 1002 raw_spin_lock_irqsave(&byt_lock, flags); 1003 1004 conf = readl(conf_reg); 1005 val = readl(val_reg); 1006 1007 for (i = 0; i < num_configs; i++) { 1008 param = pinconf_to_config_param(configs[i]); 1009 arg = pinconf_to_config_argument(configs[i]); 1010 1011 switch (param) { 1012 case PIN_CONFIG_BIAS_DISABLE: 1013 conf &= ~BYT_PULL_ASSIGN_MASK; 1014 break; 1015 case PIN_CONFIG_BIAS_PULL_DOWN: 1016 /* Set default strength value in case none is given */ 1017 if (arg == 1) 1018 arg = 2000; 1019 1020 /* 1021 * Pull assignment is only applicable in input mode. If 1022 * chip is not in input mode, set it and warn about it. 1023 */ 1024 if (val & BYT_INPUT_EN) { 1025 val &= ~BYT_INPUT_EN; 1026 writel(val, val_reg); 1027 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 1028 } 1029 1030 conf &= ~BYT_PULL_ASSIGN_MASK; 1031 conf |= BYT_PULL_ASSIGN_DOWN; 1032 ret = byt_set_pull_strength(&conf, arg); 1033 1034 break; 1035 case PIN_CONFIG_BIAS_PULL_UP: 1036 /* Set default strength value in case none is given */ 1037 if (arg == 1) 1038 arg = 2000; 1039 1040 /* 1041 * Pull assignment is only applicable in input mode. If 1042 * chip is not in input mode, set it and warn about it. 1043 */ 1044 if (val & BYT_INPUT_EN) { 1045 val &= ~BYT_INPUT_EN; 1046 writel(val, val_reg); 1047 dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset); 1048 } 1049 1050 conf &= ~BYT_PULL_ASSIGN_MASK; 1051 conf |= BYT_PULL_ASSIGN_UP; 1052 ret = byt_set_pull_strength(&conf, arg); 1053 1054 break; 1055 case PIN_CONFIG_INPUT_DEBOUNCE: 1056 if (arg) 1057 conf |= BYT_DEBOUNCE_EN; 1058 else 1059 conf &= ~BYT_DEBOUNCE_EN; 1060 1061 switch (arg) { 1062 case 375: 1063 db_pulse = BYT_DEBOUNCE_PULSE_375US; 1064 break; 1065 case 750: 1066 db_pulse = BYT_DEBOUNCE_PULSE_750US; 1067 break; 1068 case 1500: 1069 db_pulse = BYT_DEBOUNCE_PULSE_1500US; 1070 break; 1071 case 3000: 1072 db_pulse = BYT_DEBOUNCE_PULSE_3MS; 1073 break; 1074 case 6000: 1075 db_pulse = BYT_DEBOUNCE_PULSE_6MS; 1076 break; 1077 case 12000: 1078 db_pulse = BYT_DEBOUNCE_PULSE_12MS; 1079 break; 1080 case 24000: 1081 db_pulse = BYT_DEBOUNCE_PULSE_24MS; 1082 break; 1083 default: 1084 if (arg) 1085 ret = -EINVAL; 1086 break; 1087 } 1088 1089 if (ret) 1090 break; 1091 1092 debounce = readl(db_reg); 1093 debounce = (debounce & ~BYT_DEBOUNCE_PULSE_MASK) | db_pulse; 1094 writel(debounce, db_reg); 1095 1096 break; 1097 default: 1098 ret = -ENOTSUPP; 1099 } 1100 1101 if (ret) 1102 break; 1103 } 1104 1105 if (!ret) 1106 writel(conf, conf_reg); 1107 1108 raw_spin_unlock_irqrestore(&byt_lock, flags); 1109 1110 return ret; 1111 } 1112 1113 static const struct pinconf_ops byt_pinconf_ops = { 1114 .is_generic = true, 1115 .pin_config_get = byt_pin_config_get, 1116 .pin_config_set = byt_pin_config_set, 1117 }; 1118 1119 static const struct pinctrl_desc byt_pinctrl_desc = { 1120 .pctlops = &byt_pinctrl_ops, 1121 .pmxops = &byt_pinmux_ops, 1122 .confops = &byt_pinconf_ops, 1123 .owner = THIS_MODULE, 1124 }; 1125 1126 static int byt_gpio_get(struct gpio_chip *chip, unsigned int offset) 1127 { 1128 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1129 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1130 unsigned long flags; 1131 u32 val; 1132 1133 raw_spin_lock_irqsave(&byt_lock, flags); 1134 val = readl(reg); 1135 raw_spin_unlock_irqrestore(&byt_lock, flags); 1136 1137 return !!(val & BYT_LEVEL); 1138 } 1139 1140 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1141 { 1142 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1143 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1144 unsigned long flags; 1145 u32 old_val; 1146 1147 if (!reg) 1148 return; 1149 1150 raw_spin_lock_irqsave(&byt_lock, flags); 1151 old_val = readl(reg); 1152 if (value) 1153 writel(old_val | BYT_LEVEL, reg); 1154 else 1155 writel(old_val & ~BYT_LEVEL, reg); 1156 raw_spin_unlock_irqrestore(&byt_lock, flags); 1157 } 1158 1159 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1160 { 1161 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1162 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1163 unsigned long flags; 1164 u32 value; 1165 1166 if (!reg) 1167 return -EINVAL; 1168 1169 raw_spin_lock_irqsave(&byt_lock, flags); 1170 value = readl(reg); 1171 raw_spin_unlock_irqrestore(&byt_lock, flags); 1172 1173 if (!(value & BYT_OUTPUT_EN)) 1174 return GPIO_LINE_DIRECTION_OUT; 1175 if (!(value & BYT_INPUT_EN)) 1176 return GPIO_LINE_DIRECTION_IN; 1177 1178 return -EINVAL; 1179 } 1180 1181 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1182 { 1183 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1184 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1185 unsigned long flags; 1186 u32 reg; 1187 1188 raw_spin_lock_irqsave(&byt_lock, flags); 1189 1190 reg = readl(val_reg); 1191 reg &= ~BYT_DIR_MASK; 1192 reg |= BYT_OUTPUT_EN; 1193 writel(reg, val_reg); 1194 1195 raw_spin_unlock_irqrestore(&byt_lock, flags); 1196 return 0; 1197 } 1198 1199 /* 1200 * Note despite the temptation this MUST NOT be converted into a call to 1201 * pinctrl_gpio_direction_output() + byt_gpio_set() that does not work this 1202 * MUST be done as a single BYT_VAL_REG register write. 1203 * See the commit message of the commit adding this comment for details. 1204 */ 1205 static int byt_gpio_direction_output(struct gpio_chip *chip, 1206 unsigned int offset, int value) 1207 { 1208 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1209 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG); 1210 unsigned long flags; 1211 u32 reg; 1212 1213 raw_spin_lock_irqsave(&byt_lock, flags); 1214 1215 byt_gpio_direct_irq_check(vg, offset); 1216 1217 reg = readl(val_reg); 1218 reg &= ~BYT_DIR_MASK; 1219 if (value) 1220 reg |= BYT_LEVEL; 1221 else 1222 reg &= ~BYT_LEVEL; 1223 1224 writel(reg, val_reg); 1225 1226 raw_spin_unlock_irqrestore(&byt_lock, flags); 1227 return 0; 1228 } 1229 1230 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 1231 { 1232 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1233 int i; 1234 u32 conf0, val; 1235 1236 for (i = 0; i < vg->soc->npins; i++) { 1237 const struct intel_community *comm; 1238 void __iomem *conf_reg, *val_reg; 1239 const char *pull_str = NULL; 1240 const char *pull = NULL; 1241 unsigned long flags; 1242 const char *label; 1243 unsigned int pin; 1244 1245 pin = vg->soc->pins[i].number; 1246 1247 conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1248 if (!conf_reg) { 1249 seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin); 1250 continue; 1251 } 1252 1253 val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1254 if (!val_reg) { 1255 seq_printf(s, "Pin %i: can't retrieve VAL\n", pin); 1256 continue; 1257 } 1258 1259 raw_spin_lock_irqsave(&byt_lock, flags); 1260 conf0 = readl(conf_reg); 1261 val = readl(val_reg); 1262 raw_spin_unlock_irqrestore(&byt_lock, flags); 1263 1264 comm = byt_get_community(vg, pin); 1265 if (!comm) { 1266 seq_printf(s, "Pin %i: can't retrieve community\n", pin); 1267 continue; 1268 } 1269 label = gpiochip_is_requested(chip, i); 1270 if (!label) 1271 label = "Unrequested"; 1272 1273 switch (conf0 & BYT_PULL_ASSIGN_MASK) { 1274 case BYT_PULL_ASSIGN_UP: 1275 pull = "up"; 1276 break; 1277 case BYT_PULL_ASSIGN_DOWN: 1278 pull = "down"; 1279 break; 1280 } 1281 1282 switch (conf0 & BYT_PULL_STR_MASK) { 1283 case BYT_PULL_STR_2K: 1284 pull_str = "2k"; 1285 break; 1286 case BYT_PULL_STR_10K: 1287 pull_str = "10k"; 1288 break; 1289 case BYT_PULL_STR_20K: 1290 pull_str = "20k"; 1291 break; 1292 case BYT_PULL_STR_40K: 1293 pull_str = "40k"; 1294 break; 1295 } 1296 1297 seq_printf(s, 1298 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s", 1299 pin, 1300 label, 1301 val & BYT_INPUT_EN ? " " : "in", 1302 val & BYT_OUTPUT_EN ? " " : "out", 1303 str_hi_lo(val & BYT_LEVEL), 1304 comm->pad_map[i], comm->pad_map[i] * 16, 1305 conf0 & 0x7, 1306 conf0 & BYT_TRIG_NEG ? " fall" : " ", 1307 conf0 & BYT_TRIG_POS ? " rise" : " ", 1308 conf0 & BYT_TRIG_LVL ? " level" : " "); 1309 1310 if (pull && pull_str) 1311 seq_printf(s, " %-4s %-3s", pull, pull_str); 1312 else 1313 seq_puts(s, " "); 1314 1315 if (conf0 & BYT_IODEN) 1316 seq_puts(s, " open-drain"); 1317 1318 seq_puts(s, "\n"); 1319 } 1320 } 1321 1322 static const struct gpio_chip byt_gpio_chip = { 1323 .owner = THIS_MODULE, 1324 .request = gpiochip_generic_request, 1325 .free = gpiochip_generic_free, 1326 .get_direction = byt_gpio_get_direction, 1327 .direction_input = byt_gpio_direction_input, 1328 .direction_output = byt_gpio_direction_output, 1329 .get = byt_gpio_get, 1330 .set = byt_gpio_set, 1331 .set_config = gpiochip_generic_config, 1332 .dbg_show = byt_gpio_dbg_show, 1333 }; 1334 1335 static void byt_irq_ack(struct irq_data *d) 1336 { 1337 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1338 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1339 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1340 void __iomem *reg; 1341 1342 reg = byt_gpio_reg(vg, hwirq, BYT_INT_STAT_REG); 1343 if (!reg) 1344 return; 1345 1346 raw_spin_lock(&byt_lock); 1347 writel(BIT(hwirq % 32), reg); 1348 raw_spin_unlock(&byt_lock); 1349 } 1350 1351 static void byt_irq_mask(struct irq_data *d) 1352 { 1353 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1354 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1355 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1356 1357 byt_gpio_clear_triggering(vg, hwirq); 1358 gpiochip_disable_irq(gc, hwirq); 1359 } 1360 1361 static void byt_irq_unmask(struct irq_data *d) 1362 { 1363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1364 struct intel_pinctrl *vg = gpiochip_get_data(gc); 1365 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1366 unsigned long flags; 1367 void __iomem *reg; 1368 u32 value; 1369 1370 gpiochip_enable_irq(gc, hwirq); 1371 1372 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1373 if (!reg) 1374 return; 1375 1376 raw_spin_lock_irqsave(&byt_lock, flags); 1377 value = readl(reg); 1378 1379 switch (irqd_get_trigger_type(d)) { 1380 case IRQ_TYPE_LEVEL_HIGH: 1381 value |= BYT_TRIG_LVL; 1382 fallthrough; 1383 case IRQ_TYPE_EDGE_RISING: 1384 value |= BYT_TRIG_POS; 1385 break; 1386 case IRQ_TYPE_LEVEL_LOW: 1387 value |= BYT_TRIG_LVL; 1388 fallthrough; 1389 case IRQ_TYPE_EDGE_FALLING: 1390 value |= BYT_TRIG_NEG; 1391 break; 1392 case IRQ_TYPE_EDGE_BOTH: 1393 value |= (BYT_TRIG_NEG | BYT_TRIG_POS); 1394 break; 1395 } 1396 1397 writel(value, reg); 1398 1399 raw_spin_unlock_irqrestore(&byt_lock, flags); 1400 } 1401 1402 static int byt_irq_type(struct irq_data *d, unsigned int type) 1403 { 1404 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d)); 1405 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1406 u32 value; 1407 unsigned long flags; 1408 void __iomem *reg; 1409 1410 reg = byt_gpio_reg(vg, hwirq, BYT_CONF0_REG); 1411 if (!reg) 1412 return -EINVAL; 1413 1414 raw_spin_lock_irqsave(&byt_lock, flags); 1415 value = readl(reg); 1416 1417 WARN(value & BYT_DIRECT_IRQ_EN, 1418 "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing"); 1419 1420 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits 1421 * are used to indicate high and low level triggering 1422 */ 1423 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG | 1424 BYT_TRIG_LVL); 1425 /* Enable glitch filtering */ 1426 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK | 1427 BYT_GLITCH_F_FAST_CLK; 1428 1429 writel(value, reg); 1430 1431 if (type & IRQ_TYPE_EDGE_BOTH) 1432 irq_set_handler_locked(d, handle_edge_irq); 1433 else if (type & IRQ_TYPE_LEVEL_MASK) 1434 irq_set_handler_locked(d, handle_level_irq); 1435 1436 raw_spin_unlock_irqrestore(&byt_lock, flags); 1437 1438 return 0; 1439 } 1440 1441 static const struct irq_chip byt_gpio_irq_chip = { 1442 .name = "BYT-GPIO", 1443 .irq_ack = byt_irq_ack, 1444 .irq_mask = byt_irq_mask, 1445 .irq_unmask = byt_irq_unmask, 1446 .irq_set_type = byt_irq_type, 1447 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 1448 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1449 }; 1450 1451 static void byt_gpio_irq_handler(struct irq_desc *desc) 1452 { 1453 struct irq_data *data = irq_desc_get_irq_data(desc); 1454 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc)); 1455 struct irq_chip *chip = irq_data_get_irq_chip(data); 1456 u32 base, pin; 1457 void __iomem *reg; 1458 unsigned long pending; 1459 1460 /* check from GPIO controller which pin triggered the interrupt */ 1461 for (base = 0; base < vg->chip.ngpio; base += 32) { 1462 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1463 1464 if (!reg) { 1465 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1466 continue; 1467 } 1468 1469 raw_spin_lock(&byt_lock); 1470 pending = readl(reg); 1471 raw_spin_unlock(&byt_lock); 1472 for_each_set_bit(pin, &pending, 32) 1473 generic_handle_domain_irq(vg->chip.irq.domain, base + pin); 1474 } 1475 chip->irq_eoi(data); 1476 } 1477 1478 static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 conf0) 1479 { 1480 int direct_irq, ioapic_direct_irq_base; 1481 u8 *match, direct_irq_mux[16]; 1482 u32 trig; 1483 1484 memcpy_fromio(direct_irq_mux, vg->communities->pad_regs + BYT_DIRECT_IRQ_REG, 1485 sizeof(direct_irq_mux)); 1486 match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux)); 1487 if (!match) { 1488 dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin); 1489 return false; 1490 } 1491 1492 direct_irq = match - direct_irq_mux; 1493 /* Base IO-APIC pin numbers come from atom-e3800-family-datasheet.pdf */ 1494 ioapic_direct_irq_base = (vg->communities->npins == BYT_NGPIO_SCORE) ? 51 : 67; 1495 dev_dbg(vg->dev, "Pin %i: uses direct IRQ %d (IO-APIC %d)\n", pin, 1496 direct_irq, direct_irq + ioapic_direct_irq_base); 1497 1498 /* 1499 * Testing has shown that the way direct IRQs work is that the combination of the 1500 * direct-irq-en flag and the direct IRQ mux connect the output of the GPIO's IRQ 1501 * trigger block, which normally sets the status flag in the IRQ status reg at 1502 * 0x800, to one of the IO-APIC pins according to the mux registers. 1503 * 1504 * This means that: 1505 * 1. The TRIG_MASK bits must be set to configure the GPIO's IRQ trigger block 1506 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly 1507 * passed (1:1 or inverted) to the IO-APIC pin, if TRIG_LVL is not set, 1508 * selecting edge mode operation then on the first edge the IO-APIC pin goes 1509 * high, but since no write-to-clear write will be done to the IRQ status reg 1510 * at 0x800, the detected edge condition will never get cleared. 1511 */ 1512 trig = conf0 & BYT_TRIG_MASK; 1513 if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) && 1514 trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) { 1515 dev_warn(vg->dev, 1516 FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n", 1517 pin, conf0); 1518 return false; 1519 } 1520 1521 return true; 1522 } 1523 1524 static void byt_init_irq_valid_mask(struct gpio_chip *chip, 1525 unsigned long *valid_mask, 1526 unsigned int ngpios) 1527 { 1528 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1529 void __iomem *reg; 1530 u32 value; 1531 int i; 1532 1533 /* 1534 * Clear interrupt triggers for all pins that are GPIOs and 1535 * do not use direct IRQ mode. This will prevent spurious 1536 * interrupts from misconfigured pins. 1537 */ 1538 for (i = 0; i < vg->soc->npins; i++) { 1539 unsigned int pin = vg->soc->pins[i].number; 1540 1541 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1542 if (!reg) { 1543 dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i); 1544 continue; 1545 } 1546 1547 value = readl(reg); 1548 if (value & BYT_DIRECT_IRQ_EN) { 1549 if (byt_direct_irq_sanity_check(vg, i, value)) { 1550 clear_bit(i, valid_mask); 1551 } else { 1552 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | 1553 BYT_TRIG_NEG | BYT_TRIG_LVL); 1554 writel(value, reg); 1555 } 1556 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) { 1557 byt_gpio_clear_triggering(vg, i); 1558 dev_dbg(vg->dev, "disabling GPIO %d\n", i); 1559 } 1560 } 1561 } 1562 1563 static int byt_gpio_irq_init_hw(struct gpio_chip *chip) 1564 { 1565 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1566 void __iomem *reg; 1567 u32 base, value; 1568 1569 /* clear interrupt status trigger registers */ 1570 for (base = 0; base < vg->soc->npins; base += 32) { 1571 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG); 1572 1573 if (!reg) { 1574 dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base); 1575 continue; 1576 } 1577 1578 writel(0xffffffff, reg); 1579 /* make sure trigger bits are cleared, if not then a pin 1580 might be misconfigured in bios */ 1581 value = readl(reg); 1582 if (value) 1583 dev_err(vg->dev, 1584 "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n", 1585 base / 32, value); 1586 } 1587 1588 return 0; 1589 } 1590 1591 static int byt_gpio_add_pin_ranges(struct gpio_chip *chip) 1592 { 1593 struct intel_pinctrl *vg = gpiochip_get_data(chip); 1594 struct device *dev = vg->dev; 1595 int ret; 1596 1597 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins); 1598 if (ret) 1599 dev_err(dev, "failed to add GPIO pin range\n"); 1600 1601 return ret; 1602 } 1603 1604 static int byt_gpio_probe(struct intel_pinctrl *vg) 1605 { 1606 struct platform_device *pdev = to_platform_device(vg->dev); 1607 struct gpio_chip *gc; 1608 int irq, ret; 1609 1610 /* Set up gpio chip */ 1611 vg->chip = byt_gpio_chip; 1612 gc = &vg->chip; 1613 gc->label = dev_name(vg->dev); 1614 gc->base = -1; 1615 gc->can_sleep = false; 1616 gc->add_pin_ranges = byt_gpio_add_pin_ranges; 1617 gc->parent = vg->dev; 1618 gc->ngpio = vg->soc->npins; 1619 1620 #ifdef CONFIG_PM_SLEEP 1621 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads), 1622 GFP_KERNEL); 1623 if (!vg->context.pads) 1624 return -ENOMEM; 1625 #endif 1626 1627 /* set up interrupts */ 1628 irq = platform_get_irq_optional(pdev, 0); 1629 if (irq > 0) { 1630 struct gpio_irq_chip *girq; 1631 1632 girq = &gc->irq; 1633 gpio_irq_chip_set_chip(girq, &byt_gpio_irq_chip); 1634 girq->init_hw = byt_gpio_irq_init_hw; 1635 girq->init_valid_mask = byt_init_irq_valid_mask; 1636 girq->parent_handler = byt_gpio_irq_handler; 1637 girq->num_parents = 1; 1638 girq->parents = devm_kcalloc(vg->dev, girq->num_parents, 1639 sizeof(*girq->parents), GFP_KERNEL); 1640 if (!girq->parents) 1641 return -ENOMEM; 1642 girq->parents[0] = irq; 1643 girq->default_type = IRQ_TYPE_NONE; 1644 girq->handler = handle_bad_irq; 1645 } 1646 1647 ret = devm_gpiochip_add_data(vg->dev, gc, vg); 1648 if (ret) { 1649 dev_err(vg->dev, "failed adding byt-gpio chip\n"); 1650 return ret; 1651 } 1652 1653 return ret; 1654 } 1655 1656 static int byt_set_soc_data(struct intel_pinctrl *vg, 1657 const struct intel_pinctrl_soc_data *soc) 1658 { 1659 struct platform_device *pdev = to_platform_device(vg->dev); 1660 int i; 1661 1662 vg->soc = soc; 1663 1664 vg->ncommunities = vg->soc->ncommunities; 1665 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities, 1666 sizeof(*vg->communities), GFP_KERNEL); 1667 if (!vg->communities) 1668 return -ENOMEM; 1669 1670 for (i = 0; i < vg->soc->ncommunities; i++) { 1671 struct intel_community *comm = vg->communities + i; 1672 1673 *comm = vg->soc->communities[i]; 1674 1675 comm->pad_regs = devm_platform_ioremap_resource(pdev, 0); 1676 if (IS_ERR(comm->pad_regs)) 1677 return PTR_ERR(comm->pad_regs); 1678 } 1679 1680 return 0; 1681 } 1682 1683 static const struct acpi_device_id byt_gpio_acpi_match[] = { 1684 { "INT33B2", (kernel_ulong_t)byt_soc_data }, 1685 { "INT33FC", (kernel_ulong_t)byt_soc_data }, 1686 { } 1687 }; 1688 1689 static int byt_pinctrl_probe(struct platform_device *pdev) 1690 { 1691 const struct intel_pinctrl_soc_data *soc_data; 1692 struct device *dev = &pdev->dev; 1693 struct intel_pinctrl *vg; 1694 int ret; 1695 1696 soc_data = intel_pinctrl_get_soc_data(pdev); 1697 if (IS_ERR(soc_data)) 1698 return PTR_ERR(soc_data); 1699 1700 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); 1701 if (!vg) 1702 return -ENOMEM; 1703 1704 vg->dev = dev; 1705 ret = byt_set_soc_data(vg, soc_data); 1706 if (ret) { 1707 dev_err(dev, "failed to set soc data\n"); 1708 return ret; 1709 } 1710 1711 vg->pctldesc = byt_pinctrl_desc; 1712 vg->pctldesc.name = dev_name(dev); 1713 vg->pctldesc.pins = vg->soc->pins; 1714 vg->pctldesc.npins = vg->soc->npins; 1715 1716 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg); 1717 if (IS_ERR(vg->pctldev)) { 1718 dev_err(dev, "failed to register pinctrl driver\n"); 1719 return PTR_ERR(vg->pctldev); 1720 } 1721 1722 ret = byt_gpio_probe(vg); 1723 if (ret) 1724 return ret; 1725 1726 platform_set_drvdata(pdev, vg); 1727 pm_runtime_enable(dev); 1728 1729 return 0; 1730 } 1731 1732 #ifdef CONFIG_PM_SLEEP 1733 static int byt_gpio_suspend(struct device *dev) 1734 { 1735 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1736 unsigned long flags; 1737 int i; 1738 1739 raw_spin_lock_irqsave(&byt_lock, flags); 1740 1741 for (i = 0; i < vg->soc->npins; i++) { 1742 void __iomem *reg; 1743 u32 value; 1744 unsigned int pin = vg->soc->pins[i].number; 1745 1746 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1747 if (!reg) { 1748 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1749 continue; 1750 } 1751 value = readl(reg) & BYT_CONF0_RESTORE_MASK; 1752 vg->context.pads[i].conf0 = value; 1753 1754 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1755 if (!reg) { 1756 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1757 continue; 1758 } 1759 value = readl(reg) & BYT_VAL_RESTORE_MASK; 1760 vg->context.pads[i].val = value; 1761 } 1762 1763 raw_spin_unlock_irqrestore(&byt_lock, flags); 1764 return 0; 1765 } 1766 1767 static int byt_gpio_resume(struct device *dev) 1768 { 1769 struct intel_pinctrl *vg = dev_get_drvdata(dev); 1770 unsigned long flags; 1771 int i; 1772 1773 raw_spin_lock_irqsave(&byt_lock, flags); 1774 1775 for (i = 0; i < vg->soc->npins; i++) { 1776 void __iomem *reg; 1777 u32 value; 1778 unsigned int pin = vg->soc->pins[i].number; 1779 1780 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG); 1781 if (!reg) { 1782 dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i); 1783 continue; 1784 } 1785 value = readl(reg); 1786 if ((value & BYT_CONF0_RESTORE_MASK) != 1787 vg->context.pads[i].conf0) { 1788 value &= ~BYT_CONF0_RESTORE_MASK; 1789 value |= vg->context.pads[i].conf0; 1790 writel(value, reg); 1791 dev_info(dev, "restored pin %d CONF0 %#08x", i, value); 1792 } 1793 1794 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG); 1795 if (!reg) { 1796 dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i); 1797 continue; 1798 } 1799 value = readl(reg); 1800 if ((value & BYT_VAL_RESTORE_MASK) != 1801 vg->context.pads[i].val) { 1802 u32 v; 1803 1804 v = value & ~BYT_VAL_RESTORE_MASK; 1805 v |= vg->context.pads[i].val; 1806 if (v != value) { 1807 writel(v, reg); 1808 dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v); 1809 } 1810 } 1811 } 1812 1813 raw_spin_unlock_irqrestore(&byt_lock, flags); 1814 return 0; 1815 } 1816 #endif 1817 1818 #ifdef CONFIG_PM 1819 static int byt_gpio_runtime_suspend(struct device *dev) 1820 { 1821 return 0; 1822 } 1823 1824 static int byt_gpio_runtime_resume(struct device *dev) 1825 { 1826 return 0; 1827 } 1828 #endif 1829 1830 static const struct dev_pm_ops byt_gpio_pm_ops = { 1831 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume) 1832 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume, 1833 NULL) 1834 }; 1835 1836 static struct platform_driver byt_gpio_driver = { 1837 .probe = byt_pinctrl_probe, 1838 .driver = { 1839 .name = "byt_gpio", 1840 .pm = &byt_gpio_pm_ops, 1841 .acpi_match_table = byt_gpio_acpi_match, 1842 .suppress_bind_attrs = true, 1843 }, 1844 }; 1845 1846 static int __init byt_gpio_init(void) 1847 { 1848 return platform_driver_register(&byt_gpio_driver); 1849 } 1850 subsys_initcall(byt_gpio_init); 1851