1*c2b39decSFabio Estevam // SPDX-License-Identifier: GPL-2.0 2*c2b39decSFabio Estevam // 3*c2b39decSFabio Estevam // Freescale imx6sl pinctrl driver 4*c2b39decSFabio Estevam // 5*c2b39decSFabio Estevam // Author: Shawn Guo <shawn.guo@linaro.org> 6*c2b39decSFabio Estevam // Copyright (C) 2013 Freescale Semiconductor, Inc. 7edad3b2aSLinus Walleij 8edad3b2aSLinus Walleij #include <linux/err.h> 9edad3b2aSLinus Walleij #include <linux/init.h> 10edad3b2aSLinus Walleij #include <linux/io.h> 11edad3b2aSLinus Walleij #include <linux/of.h> 12edad3b2aSLinus Walleij #include <linux/of_device.h> 13edad3b2aSLinus Walleij #include <linux/pinctrl/pinctrl.h> 14edad3b2aSLinus Walleij 15edad3b2aSLinus Walleij #include "pinctrl-imx.h" 16edad3b2aSLinus Walleij 17edad3b2aSLinus Walleij enum imx6sl_pads { 18edad3b2aSLinus Walleij MX6SL_PAD_RESERVE0 = 0, 19edad3b2aSLinus Walleij MX6SL_PAD_RESERVE1 = 1, 20edad3b2aSLinus Walleij MX6SL_PAD_RESERVE2 = 2, 21edad3b2aSLinus Walleij MX6SL_PAD_RESERVE3 = 3, 22edad3b2aSLinus Walleij MX6SL_PAD_RESERVE4 = 4, 23edad3b2aSLinus Walleij MX6SL_PAD_RESERVE5 = 5, 24edad3b2aSLinus Walleij MX6SL_PAD_RESERVE6 = 6, 25edad3b2aSLinus Walleij MX6SL_PAD_RESERVE7 = 7, 26edad3b2aSLinus Walleij MX6SL_PAD_RESERVE8 = 8, 27edad3b2aSLinus Walleij MX6SL_PAD_RESERVE9 = 9, 28edad3b2aSLinus Walleij MX6SL_PAD_RESERVE10 = 10, 29edad3b2aSLinus Walleij MX6SL_PAD_RESERVE11 = 11, 30edad3b2aSLinus Walleij MX6SL_PAD_RESERVE12 = 12, 31edad3b2aSLinus Walleij MX6SL_PAD_RESERVE13 = 13, 32edad3b2aSLinus Walleij MX6SL_PAD_RESERVE14 = 14, 33edad3b2aSLinus Walleij MX6SL_PAD_RESERVE15 = 15, 34edad3b2aSLinus Walleij MX6SL_PAD_RESERVE16 = 16, 35edad3b2aSLinus Walleij MX6SL_PAD_RESERVE17 = 17, 36edad3b2aSLinus Walleij MX6SL_PAD_RESERVE18 = 18, 37edad3b2aSLinus Walleij MX6SL_PAD_AUD_MCLK = 19, 38edad3b2aSLinus Walleij MX6SL_PAD_AUD_RXC = 20, 39edad3b2aSLinus Walleij MX6SL_PAD_AUD_RXD = 21, 40edad3b2aSLinus Walleij MX6SL_PAD_AUD_RXFS = 22, 41edad3b2aSLinus Walleij MX6SL_PAD_AUD_TXC = 23, 42edad3b2aSLinus Walleij MX6SL_PAD_AUD_TXD = 24, 43edad3b2aSLinus Walleij MX6SL_PAD_AUD_TXFS = 25, 44edad3b2aSLinus Walleij MX6SL_PAD_ECSPI1_MISO = 26, 45edad3b2aSLinus Walleij MX6SL_PAD_ECSPI1_MOSI = 27, 46edad3b2aSLinus Walleij MX6SL_PAD_ECSPI1_SCLK = 28, 47edad3b2aSLinus Walleij MX6SL_PAD_ECSPI1_SS0 = 29, 48edad3b2aSLinus Walleij MX6SL_PAD_ECSPI2_MISO = 30, 49edad3b2aSLinus Walleij MX6SL_PAD_ECSPI2_MOSI = 31, 50edad3b2aSLinus Walleij MX6SL_PAD_ECSPI2_SCLK = 32, 51edad3b2aSLinus Walleij MX6SL_PAD_ECSPI2_SS0 = 33, 52edad3b2aSLinus Walleij MX6SL_PAD_EPDC_BDR0 = 34, 53edad3b2aSLinus Walleij MX6SL_PAD_EPDC_BDR1 = 35, 54edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D0 = 36, 55edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D1 = 37, 56edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D10 = 38, 57edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D11 = 39, 58edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D12 = 40, 59edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D13 = 41, 60edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D14 = 42, 61edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D15 = 43, 62edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D2 = 44, 63edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D3 = 45, 64edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D4 = 46, 65edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D5 = 47, 66edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D6 = 48, 67edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D7 = 49, 68edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D8 = 50, 69edad3b2aSLinus Walleij MX6SL_PAD_EPDC_D9 = 51, 70edad3b2aSLinus Walleij MX6SL_PAD_EPDC_GDCLK = 52, 71edad3b2aSLinus Walleij MX6SL_PAD_EPDC_GDOE = 53, 72edad3b2aSLinus Walleij MX6SL_PAD_EPDC_GDRL = 54, 73edad3b2aSLinus Walleij MX6SL_PAD_EPDC_GDSP = 55, 74edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRCOM = 56, 75edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRCTRL0 = 57, 76edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRCTRL1 = 58, 77edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRCTRL2 = 59, 78edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRCTRL3 = 60, 79edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRINT = 61, 80edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRSTAT = 62, 81edad3b2aSLinus Walleij MX6SL_PAD_EPDC_PWRWAKEUP = 63, 82edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDCE0 = 64, 83edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDCE1 = 65, 84edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDCE2 = 66, 85edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDCE3 = 67, 86edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDCLK = 68, 87edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDLE = 69, 88edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDOE = 70, 89edad3b2aSLinus Walleij MX6SL_PAD_EPDC_SDSHR = 71, 90edad3b2aSLinus Walleij MX6SL_PAD_EPDC_VCOM0 = 72, 91edad3b2aSLinus Walleij MX6SL_PAD_EPDC_VCOM1 = 73, 92edad3b2aSLinus Walleij MX6SL_PAD_FEC_CRS_DV = 74, 93edad3b2aSLinus Walleij MX6SL_PAD_FEC_MDC = 75, 94edad3b2aSLinus Walleij MX6SL_PAD_FEC_MDIO = 76, 95edad3b2aSLinus Walleij MX6SL_PAD_FEC_REF_CLK = 77, 96edad3b2aSLinus Walleij MX6SL_PAD_FEC_RX_ER = 78, 97edad3b2aSLinus Walleij MX6SL_PAD_FEC_RXD0 = 79, 98edad3b2aSLinus Walleij MX6SL_PAD_FEC_RXD1 = 80, 99edad3b2aSLinus Walleij MX6SL_PAD_FEC_TX_CLK = 81, 100edad3b2aSLinus Walleij MX6SL_PAD_FEC_TX_EN = 82, 101edad3b2aSLinus Walleij MX6SL_PAD_FEC_TXD0 = 83, 102edad3b2aSLinus Walleij MX6SL_PAD_FEC_TXD1 = 84, 103edad3b2aSLinus Walleij MX6SL_PAD_HSIC_DAT = 85, 104edad3b2aSLinus Walleij MX6SL_PAD_HSIC_STROBE = 86, 105edad3b2aSLinus Walleij MX6SL_PAD_I2C1_SCL = 87, 106edad3b2aSLinus Walleij MX6SL_PAD_I2C1_SDA = 88, 107edad3b2aSLinus Walleij MX6SL_PAD_I2C2_SCL = 89, 108edad3b2aSLinus Walleij MX6SL_PAD_I2C2_SDA = 90, 109edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL0 = 91, 110edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL1 = 92, 111edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL2 = 93, 112edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL3 = 94, 113edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL4 = 95, 114edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL5 = 96, 115edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL6 = 97, 116edad3b2aSLinus Walleij MX6SL_PAD_KEY_COL7 = 98, 117edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW0 = 99, 118edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW1 = 100, 119edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW2 = 101, 120edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW3 = 102, 121edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW4 = 103, 122edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW5 = 104, 123edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW6 = 105, 124edad3b2aSLinus Walleij MX6SL_PAD_KEY_ROW7 = 106, 125edad3b2aSLinus Walleij MX6SL_PAD_LCD_CLK = 107, 126edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT0 = 108, 127edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT1 = 109, 128edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT10 = 110, 129edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT11 = 111, 130edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT12 = 112, 131edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT13 = 113, 132edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT14 = 114, 133edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT15 = 115, 134edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT16 = 116, 135edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT17 = 117, 136edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT18 = 118, 137edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT19 = 119, 138edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT2 = 120, 139edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT20 = 121, 140edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT21 = 122, 141edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT22 = 123, 142edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT23 = 124, 143edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT3 = 125, 144edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT4 = 126, 145edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT5 = 127, 146edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT6 = 128, 147edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT7 = 129, 148edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT8 = 130, 149edad3b2aSLinus Walleij MX6SL_PAD_LCD_DAT9 = 131, 150edad3b2aSLinus Walleij MX6SL_PAD_LCD_ENABLE = 132, 151edad3b2aSLinus Walleij MX6SL_PAD_LCD_HSYNC = 133, 152edad3b2aSLinus Walleij MX6SL_PAD_LCD_RESET = 134, 153edad3b2aSLinus Walleij MX6SL_PAD_LCD_VSYNC = 135, 154edad3b2aSLinus Walleij MX6SL_PAD_PWM1 = 136, 155edad3b2aSLinus Walleij MX6SL_PAD_REF_CLK_24M = 137, 156edad3b2aSLinus Walleij MX6SL_PAD_REF_CLK_32K = 138, 157edad3b2aSLinus Walleij MX6SL_PAD_SD1_CLK = 139, 158edad3b2aSLinus Walleij MX6SL_PAD_SD1_CMD = 140, 159edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT0 = 141, 160edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT1 = 142, 161edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT2 = 143, 162edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT3 = 144, 163edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT4 = 145, 164edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT5 = 146, 165edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT6 = 147, 166edad3b2aSLinus Walleij MX6SL_PAD_SD1_DAT7 = 148, 167edad3b2aSLinus Walleij MX6SL_PAD_SD2_CLK = 149, 168edad3b2aSLinus Walleij MX6SL_PAD_SD2_CMD = 150, 169edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT0 = 151, 170edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT1 = 152, 171edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT2 = 153, 172edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT3 = 154, 173edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT4 = 155, 174edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT5 = 156, 175edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT6 = 157, 176edad3b2aSLinus Walleij MX6SL_PAD_SD2_DAT7 = 158, 177edad3b2aSLinus Walleij MX6SL_PAD_SD2_RST = 159, 178edad3b2aSLinus Walleij MX6SL_PAD_SD3_CLK = 160, 179edad3b2aSLinus Walleij MX6SL_PAD_SD3_CMD = 161, 180edad3b2aSLinus Walleij MX6SL_PAD_SD3_DAT0 = 162, 181edad3b2aSLinus Walleij MX6SL_PAD_SD3_DAT1 = 163, 182edad3b2aSLinus Walleij MX6SL_PAD_SD3_DAT2 = 164, 183edad3b2aSLinus Walleij MX6SL_PAD_SD3_DAT3 = 165, 184edad3b2aSLinus Walleij MX6SL_PAD_UART1_RXD = 166, 185edad3b2aSLinus Walleij MX6SL_PAD_UART1_TXD = 167, 186edad3b2aSLinus Walleij MX6SL_PAD_WDOG_B = 168, 187edad3b2aSLinus Walleij }; 188edad3b2aSLinus Walleij 189edad3b2aSLinus Walleij /* Pad names for the pinmux subsystem */ 190edad3b2aSLinus Walleij static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = { 191edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE0), 192edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE1), 193edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE2), 194edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE3), 195edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE4), 196edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE5), 197edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE6), 198edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE7), 199edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE8), 200edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE9), 201edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE10), 202edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE11), 203edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE12), 204edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE13), 205edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE14), 206edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE15), 207edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE16), 208edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE17), 209edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_RESERVE18), 210edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_MCLK), 211edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXC), 212edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXD), 213edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_RXFS), 214edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXC), 215edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXD), 216edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_AUD_TXFS), 217edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MISO), 218edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_MOSI), 219edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SCLK), 220edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI1_SS0), 221edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MISO), 222edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_MOSI), 223edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SCLK), 224edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_ECSPI2_SS0), 225edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR0), 226edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_BDR1), 227edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D0), 228edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D1), 229edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D10), 230edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D11), 231edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D12), 232edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D13), 233edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D14), 234edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D15), 235edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D2), 236edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D3), 237edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D4), 238edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D5), 239edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D6), 240edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D7), 241edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D8), 242edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_D9), 243edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDCLK), 244edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDOE), 245edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDRL), 246edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_GDSP), 247edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCOM), 248edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL0), 249edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL1), 250edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL2), 251edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRCTRL3), 252edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRINT), 253edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRSTAT), 254edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_PWRWAKEUP), 255edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE0), 256edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE1), 257edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE2), 258edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCE3), 259edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDCLK), 260edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDLE), 261edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDOE), 262edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_SDSHR), 263edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM0), 264edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_EPDC_VCOM1), 265edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_CRS_DV), 266edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDC), 267edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_MDIO), 268edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_REF_CLK), 269edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RX_ER), 270edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD0), 271edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_RXD1), 272edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_CLK), 273edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TX_EN), 274edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD0), 275edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_FEC_TXD1), 276edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_DAT), 277edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_HSIC_STROBE), 278edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SCL), 279edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_I2C1_SDA), 280edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SCL), 281edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_I2C2_SDA), 282edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL0), 283edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL1), 284edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL2), 285edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL3), 286edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL4), 287edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL5), 288edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL6), 289edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_COL7), 290edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW0), 291edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW1), 292edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW2), 293edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW3), 294edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW4), 295edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW5), 296edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW6), 297edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_KEY_ROW7), 298edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_CLK), 299edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT0), 300edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT1), 301edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT10), 302edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT11), 303edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT12), 304edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT13), 305edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT14), 306edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT15), 307edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT16), 308edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT17), 309edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT18), 310edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT19), 311edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT2), 312edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT20), 313edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT21), 314edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT22), 315edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT23), 316edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT3), 317edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT4), 318edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT5), 319edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT6), 320edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT7), 321edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT8), 322edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_DAT9), 323edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_ENABLE), 324edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_HSYNC), 325edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_RESET), 326edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_LCD_VSYNC), 327edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_PWM1), 328edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_24M), 329edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_REF_CLK_32K), 330edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CLK), 331edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_CMD), 332edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT0), 333edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT1), 334edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT2), 335edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT3), 336edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT4), 337edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT5), 338edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT6), 339edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD1_DAT7), 340edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CLK), 341edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_CMD), 342edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT0), 343edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT1), 344edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT2), 345edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT3), 346edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT4), 347edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT5), 348edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT6), 349edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_DAT7), 350edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD2_RST), 351edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CLK), 352edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_CMD), 353edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT0), 354edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT1), 355edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT2), 356edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_SD3_DAT3), 357edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_UART1_RXD), 358edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_UART1_TXD), 359edad3b2aSLinus Walleij IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B), 360edad3b2aSLinus Walleij }; 361edad3b2aSLinus Walleij 3627c017687SStefan Agner static const struct imx_pinctrl_soc_info imx6sl_pinctrl_info = { 363edad3b2aSLinus Walleij .pins = imx6sl_pinctrl_pads, 364edad3b2aSLinus Walleij .npins = ARRAY_SIZE(imx6sl_pinctrl_pads), 3658626ada8SPhilipp Zabel .gpr_compatible = "fsl,imx6sl-iomuxc-gpr", 366edad3b2aSLinus Walleij }; 367edad3b2aSLinus Walleij 368edad3b2aSLinus Walleij static const struct of_device_id imx6sl_pinctrl_of_match[] = { 369edad3b2aSLinus Walleij { .compatible = "fsl,imx6sl-iomuxc", }, 370edad3b2aSLinus Walleij { /* sentinel */ } 371edad3b2aSLinus Walleij }; 372edad3b2aSLinus Walleij 373edad3b2aSLinus Walleij static int imx6sl_pinctrl_probe(struct platform_device *pdev) 374edad3b2aSLinus Walleij { 375edad3b2aSLinus Walleij return imx_pinctrl_probe(pdev, &imx6sl_pinctrl_info); 376edad3b2aSLinus Walleij } 377edad3b2aSLinus Walleij 378edad3b2aSLinus Walleij static struct platform_driver imx6sl_pinctrl_driver = { 379edad3b2aSLinus Walleij .driver = { 380edad3b2aSLinus Walleij .name = "imx6sl-pinctrl", 381edad3b2aSLinus Walleij .of_match_table = imx6sl_pinctrl_of_match, 382edad3b2aSLinus Walleij }, 383edad3b2aSLinus Walleij .probe = imx6sl_pinctrl_probe, 384edad3b2aSLinus Walleij }; 385edad3b2aSLinus Walleij 386edad3b2aSLinus Walleij static int __init imx6sl_pinctrl_init(void) 387edad3b2aSLinus Walleij { 388edad3b2aSLinus Walleij return platform_driver_register(&imx6sl_pinctrl_driver); 389edad3b2aSLinus Walleij } 390edad3b2aSLinus Walleij arch_initcall(imx6sl_pinctrl_init); 391