1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments CPSW Port's PHY Interface Mode selection Driver 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * 7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com> 8 */ 9 10 #include <linux/platform_device.h> 11 #include <linux/module.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_net.h> 16 #include <linux/phy.h> 17 #include <linux/phy/phy.h> 18 #include <linux/regmap.h> 19 20 /* AM33xx SoC specific definitions for the CONTROL port */ 21 #define AM33XX_GMII_SEL_MODE_MII 0 22 #define AM33XX_GMII_SEL_MODE_RMII 1 23 #define AM33XX_GMII_SEL_MODE_RGMII 2 24 25 /* J72xx SoC specific definitions for the CONTROL port */ 26 #define J72XX_GMII_SEL_MODE_SGMII 3 27 #define J72XX_GMII_SEL_MODE_QSGMII 4 28 #define J72XX_GMII_SEL_MODE_QSGMII_SUB 6 29 30 #define PHY_GMII_PORT(n) BIT((n) - 1) 31 32 enum { 33 PHY_GMII_SEL_PORT_MODE = 0, 34 PHY_GMII_SEL_RGMII_ID_MODE, 35 PHY_GMII_SEL_RMII_IO_CLK_EN, 36 PHY_GMII_SEL_LAST, 37 }; 38 39 struct phy_gmii_sel_phy_priv { 40 struct phy_gmii_sel_priv *priv; 41 u32 id; 42 struct phy *if_phy; 43 int rmii_clock_external; 44 int phy_if_mode; 45 struct regmap_field *fields[PHY_GMII_SEL_LAST]; 46 }; 47 48 struct phy_gmii_sel_soc_data { 49 u32 num_ports; 50 u32 features; 51 const struct reg_field (*regfields)[PHY_GMII_SEL_LAST]; 52 bool use_of_data; 53 u64 extra_modes; 54 u32 num_qsgmii_main_ports; 55 }; 56 57 struct phy_gmii_sel_priv { 58 struct device *dev; 59 const struct phy_gmii_sel_soc_data *soc_data; 60 struct regmap *regmap; 61 struct phy_provider *phy_provider; 62 struct phy_gmii_sel_phy_priv *if_phys; 63 u32 num_ports; 64 u32 reg_offset; 65 u32 qsgmii_main_ports; 66 }; 67 68 static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode) 69 { 70 struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy); 71 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data; 72 struct device *dev = if_phy->priv->dev; 73 struct regmap_field *regfield; 74 int ret, rgmii_id = 0; 75 u32 gmii_sel_mode = 0; 76 77 if (mode != PHY_MODE_ETHERNET) 78 return -EINVAL; 79 80 switch (submode) { 81 case PHY_INTERFACE_MODE_RMII: 82 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII; 83 break; 84 85 case PHY_INTERFACE_MODE_RGMII: 86 case PHY_INTERFACE_MODE_RGMII_RXID: 87 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII; 88 break; 89 90 case PHY_INTERFACE_MODE_RGMII_ID: 91 case PHY_INTERFACE_MODE_RGMII_TXID: 92 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII; 93 rgmii_id = 1; 94 break; 95 96 case PHY_INTERFACE_MODE_MII: 97 case PHY_INTERFACE_MODE_GMII: 98 gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII; 99 break; 100 101 case PHY_INTERFACE_MODE_QSGMII: 102 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII))) 103 goto unsupported; 104 if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1)) 105 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII; 106 else 107 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB; 108 break; 109 110 case PHY_INTERFACE_MODE_SGMII: 111 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII))) 112 goto unsupported; 113 else 114 gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII; 115 break; 116 117 default: 118 goto unsupported; 119 } 120 121 if_phy->phy_if_mode = submode; 122 123 dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n", 124 __func__, if_phy->id, submode, rgmii_id, 125 if_phy->rmii_clock_external); 126 127 regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE]; 128 ret = regmap_field_write(regfield, gmii_sel_mode); 129 if (ret) { 130 dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret); 131 return ret; 132 } 133 134 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) && 135 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) { 136 regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]; 137 ret = regmap_field_write(regfield, rgmii_id); 138 if (ret) 139 return ret; 140 } 141 142 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && 143 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) { 144 regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]; 145 ret = regmap_field_write(regfield, 146 if_phy->rmii_clock_external); 147 } 148 149 return 0; 150 151 unsupported: 152 dev_warn(dev, "port%u: unsupported mode: \"%s\"\n", 153 if_phy->id, phy_modes(submode)); 154 return -EINVAL; 155 } 156 157 static const 158 struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = { 159 { 160 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1), 161 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4), 162 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6), 163 }, 164 { 165 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3), 166 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5), 167 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7), 168 }, 169 }; 170 171 static const 172 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = { 173 .num_ports = 2, 174 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) | 175 BIT(PHY_GMII_SEL_RMII_IO_CLK_EN), 176 .regfields = phy_gmii_sel_fields_am33xx, 177 }; 178 179 static const 180 struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = { 181 { 182 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1), 183 }, 184 { 185 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5), 186 }, 187 }; 188 189 static const 190 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = { 191 .num_ports = 2, 192 .regfields = phy_gmii_sel_fields_dra7, 193 }; 194 195 static const 196 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = { 197 .num_ports = 2, 198 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE), 199 .regfields = phy_gmii_sel_fields_am33xx, 200 }; 201 202 static const 203 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = { 204 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2), }, 205 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2), }, 206 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2), }, 207 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2), }, 208 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2), }, 209 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2), }, 210 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2), }, 211 { [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2), }, 212 }; 213 214 static const 215 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = { 216 .use_of_data = true, 217 .regfields = phy_gmii_sel_fields_am654, 218 }; 219 220 static const 221 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = { 222 .use_of_data = true, 223 .regfields = phy_gmii_sel_fields_am654, 224 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 225 .num_ports = 4, 226 .num_qsgmii_main_ports = 1, 227 }; 228 229 static const 230 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = { 231 .use_of_data = true, 232 .regfields = phy_gmii_sel_fields_am654, 233 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 234 .num_ports = 8, 235 .num_qsgmii_main_ports = 2, 236 }; 237 238 static const struct of_device_id phy_gmii_sel_id_table[] = { 239 { 240 .compatible = "ti,am3352-phy-gmii-sel", 241 .data = &phy_gmii_sel_soc_am33xx, 242 }, 243 { 244 .compatible = "ti,dra7xx-phy-gmii-sel", 245 .data = &phy_gmii_sel_soc_dra7, 246 }, 247 { 248 .compatible = "ti,am43xx-phy-gmii-sel", 249 .data = &phy_gmii_sel_soc_am33xx, 250 }, 251 { 252 .compatible = "ti,dm814-phy-gmii-sel", 253 .data = &phy_gmii_sel_soc_dm814, 254 }, 255 { 256 .compatible = "ti,am654-phy-gmii-sel", 257 .data = &phy_gmii_sel_soc_am654, 258 }, 259 { 260 .compatible = "ti,j7200-cpsw5g-phy-gmii-sel", 261 .data = &phy_gmii_sel_cpsw5g_soc_j7200, 262 }, 263 { 264 .compatible = "ti,j721e-cpsw9g-phy-gmii-sel", 265 .data = &phy_gmii_sel_cpsw9g_soc_j721e, 266 }, 267 {} 268 }; 269 MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table); 270 271 static const struct phy_ops phy_gmii_sel_ops = { 272 .set_mode = phy_gmii_sel_mode, 273 .owner = THIS_MODULE, 274 }; 275 276 static struct phy *phy_gmii_sel_of_xlate(struct device *dev, 277 struct of_phandle_args *args) 278 { 279 struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev); 280 int phy_id = args->args[0]; 281 282 if (args->args_count < 1) 283 return ERR_PTR(-EINVAL); 284 if (!priv || !priv->if_phys) 285 return ERR_PTR(-ENODEV); 286 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) && 287 args->args_count < 2) 288 return ERR_PTR(-EINVAL); 289 if (phy_id > priv->num_ports) 290 return ERR_PTR(-EINVAL); 291 if (phy_id != priv->if_phys[phy_id - 1].id) 292 return ERR_PTR(-EINVAL); 293 294 phy_id--; 295 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) 296 priv->if_phys[phy_id].rmii_clock_external = args->args[1]; 297 dev_dbg(dev, "%s id:%u ext:%d\n", __func__, 298 priv->if_phys[phy_id].id, args->args[1]); 299 300 return priv->if_phys[phy_id].if_phy; 301 } 302 303 static int phy_gmii_init_phy(struct phy_gmii_sel_priv *priv, int port, 304 struct phy_gmii_sel_phy_priv *if_phy) 305 { 306 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data; 307 struct device *dev = priv->dev; 308 const struct reg_field *fields; 309 struct regmap_field *regfield; 310 struct reg_field field; 311 int ret; 312 313 if_phy->id = port; 314 if_phy->priv = priv; 315 316 fields = soc_data->regfields[port - 1]; 317 field = *fields++; 318 field.reg += priv->reg_offset; 319 dev_dbg(dev, "%s field %x %d %d\n", __func__, 320 field.reg, field.msb, field.lsb); 321 322 regfield = devm_regmap_field_alloc(dev, priv->regmap, field); 323 if (IS_ERR(regfield)) 324 return PTR_ERR(regfield); 325 if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield; 326 327 field = *fields++; 328 field.reg += priv->reg_offset; 329 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE)) { 330 regfield = devm_regmap_field_alloc(dev, 331 priv->regmap, 332 field); 333 if (IS_ERR(regfield)) 334 return PTR_ERR(regfield); 335 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield; 336 dev_dbg(dev, "%s field %x %d %d\n", __func__, 337 field.reg, field.msb, field.lsb); 338 } 339 340 field = *fields; 341 field.reg += priv->reg_offset; 342 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) { 343 regfield = devm_regmap_field_alloc(dev, 344 priv->regmap, 345 field); 346 if (IS_ERR(regfield)) 347 return PTR_ERR(regfield); 348 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield; 349 dev_dbg(dev, "%s field %x %d %d\n", __func__, 350 field.reg, field.msb, field.lsb); 351 } 352 353 if_phy->if_phy = devm_phy_create(dev, 354 priv->dev->of_node, 355 &phy_gmii_sel_ops); 356 if (IS_ERR(if_phy->if_phy)) { 357 ret = PTR_ERR(if_phy->if_phy); 358 dev_err(dev, "Failed to create phy%d %d\n", port, ret); 359 return ret; 360 } 361 phy_set_drvdata(if_phy->if_phy, if_phy); 362 363 return 0; 364 } 365 366 static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv) 367 { 368 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data; 369 struct phy_gmii_sel_phy_priv *if_phys; 370 struct device *dev = priv->dev; 371 int i, ret; 372 373 if (soc_data->use_of_data) { 374 const __be32 *offset; 375 u64 size; 376 377 offset = of_get_address(dev->of_node, 0, &size, NULL); 378 if (!offset) 379 return -EINVAL; 380 priv->num_ports = size / sizeof(u32); 381 if (!priv->num_ports) 382 return -EINVAL; 383 priv->reg_offset = __be32_to_cpu(*offset); 384 } 385 386 if_phys = devm_kcalloc(dev, priv->num_ports, 387 sizeof(*if_phys), GFP_KERNEL); 388 if (!if_phys) 389 return -ENOMEM; 390 dev_dbg(dev, "%s %d\n", __func__, priv->num_ports); 391 392 for (i = 0; i < priv->num_ports; i++) { 393 ret = phy_gmii_init_phy(priv, i + 1, &if_phys[i]); 394 if (ret) 395 return ret; 396 } 397 398 priv->if_phys = if_phys; 399 return 0; 400 } 401 402 static int phy_gmii_sel_probe(struct platform_device *pdev) 403 { 404 struct device *dev = &pdev->dev; 405 const struct phy_gmii_sel_soc_data *soc_data; 406 struct device_node *node = dev->of_node; 407 const struct of_device_id *of_id; 408 struct phy_gmii_sel_priv *priv; 409 u32 main_ports = 1; 410 int ret; 411 u32 i; 412 413 of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node); 414 if (!of_id) 415 return -EINVAL; 416 417 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 418 if (!priv) 419 return -ENOMEM; 420 421 priv->dev = &pdev->dev; 422 priv->soc_data = of_id->data; 423 soc_data = priv->soc_data; 424 priv->num_ports = priv->soc_data->num_ports; 425 priv->qsgmii_main_ports = 0; 426 427 /* 428 * Based on the compatible, try to read the appropriate number of 429 * QSGMII main ports from the "ti,qsgmii-main-ports" property from 430 * the device-tree node. 431 */ 432 for (i = 0; i < soc_data->num_qsgmii_main_ports; i++) { 433 of_property_read_u32_index(node, "ti,qsgmii-main-ports", i, &main_ports); 434 /* 435 * Ensure that main_ports is within bounds. 436 */ 437 if (main_ports < 1 || main_ports > soc_data->num_ports) { 438 dev_err(dev, "Invalid qsgmii main port provided\n"); 439 return -EINVAL; 440 } 441 priv->qsgmii_main_ports |= PHY_GMII_PORT(main_ports); 442 } 443 444 priv->regmap = syscon_node_to_regmap(node->parent); 445 if (IS_ERR(priv->regmap)) { 446 ret = PTR_ERR(priv->regmap); 447 dev_err(dev, "Failed to get syscon %d\n", ret); 448 return ret; 449 } 450 451 ret = phy_gmii_sel_init_ports(priv); 452 if (ret) 453 return ret; 454 455 dev_set_drvdata(&pdev->dev, priv); 456 457 priv->phy_provider = 458 devm_of_phy_provider_register(dev, 459 phy_gmii_sel_of_xlate); 460 if (IS_ERR(priv->phy_provider)) { 461 ret = PTR_ERR(priv->phy_provider); 462 dev_err(dev, "Failed to create phy provider %d\n", ret); 463 return ret; 464 } 465 466 return 0; 467 } 468 469 static struct platform_driver phy_gmii_sel_driver = { 470 .probe = phy_gmii_sel_probe, 471 .driver = { 472 .name = "phy-gmii-sel", 473 .of_match_table = phy_gmii_sel_id_table, 474 }, 475 }; 476 module_platform_driver(phy_gmii_sel_driver); 477 478 MODULE_LICENSE("GPL v2"); 479 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 480 MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver"); 481