1f1b2d06dSAlim Akhtar // SPDX-License-Identifier: GPL-2.0-only 2f1b2d06dSAlim Akhtar /* 3f1b2d06dSAlim Akhtar * UFS PHY driver data for FSD SoC 4f1b2d06dSAlim Akhtar * 5f1b2d06dSAlim Akhtar * Copyright (C) 2022 Samsung Electronics Co., Ltd. 6f1b2d06dSAlim Akhtar * 7f1b2d06dSAlim Akhtar */ 8f1b2d06dSAlim Akhtar #include "phy-samsung-ufs.h" 9f1b2d06dSAlim Akhtar 10f1b2d06dSAlim Akhtar #define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724 11f1b2d06dSAlim Akhtar #define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 12f1b2d06dSAlim Akhtar #define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 13f1b2d06dSAlim Akhtar #define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e 14f1b2d06dSAlim Akhtar 15f1b2d06dSAlim Akhtar static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = { 16f1b2d06dSAlim Akhtar PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), 17f1b2d06dSAlim Akhtar PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), 18f1b2d06dSAlim Akhtar PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), 19f1b2d06dSAlim Akhtar PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY), 20f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), 21f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), 22f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), 23f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), 24f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), 25f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), 26f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), 27f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), 28f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), 29f1b2d06dSAlim Akhtar PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), 30f1b2d06dSAlim Akhtar END_UFS_PHY_CFG 31f1b2d06dSAlim Akhtar }; 32f1b2d06dSAlim Akhtar 33f1b2d06dSAlim Akhtar /* Calibration for HS mode series A/B */ 34f1b2d06dSAlim Akhtar static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = { 35f1b2d06dSAlim Akhtar END_UFS_PHY_CFG 36f1b2d06dSAlim Akhtar }; 37f1b2d06dSAlim Akhtar 38f1b2d06dSAlim Akhtar /* Calibration for HS mode series A/B atfer PMC */ 39f1b2d06dSAlim Akhtar static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = { 40f1b2d06dSAlim Akhtar END_UFS_PHY_CFG 41f1b2d06dSAlim Akhtar }; 42f1b2d06dSAlim Akhtar 43f1b2d06dSAlim Akhtar static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = { 44f1b2d06dSAlim Akhtar [CFG_PRE_INIT] = fsd_pre_init_cfg, 45f1b2d06dSAlim Akhtar [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg, 46f1b2d06dSAlim Akhtar [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg, 47f1b2d06dSAlim Akhtar }; 48f1b2d06dSAlim Akhtar 49*8d5bb683SChanho Park static const char * const fsd_ufs_phy_clks[] = { 50*8d5bb683SChanho Park "ref_clk", 51*8d5bb683SChanho Park }; 52*8d5bb683SChanho Park 53f1b2d06dSAlim Akhtar const struct samsung_ufs_phy_drvdata fsd_ufs_phy = { 54f1b2d06dSAlim Akhtar .cfgs = fsd_ufs_phy_cfgs, 55f1b2d06dSAlim Akhtar .isol = { 56f1b2d06dSAlim Akhtar .offset = FSD_EMBEDDED_COMBO_PHY_CTRL, 57f1b2d06dSAlim Akhtar .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK, 58f1b2d06dSAlim Akhtar .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN, 59f1b2d06dSAlim Akhtar }, 60*8d5bb683SChanho Park .clk_list = fsd_ufs_phy_clks, 61*8d5bb683SChanho Park .num_clks = ARRAY_SIZE(fsd_ufs_phy_clks), 62f1b2d06dSAlim Akhtar .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, 63f1b2d06dSAlim Akhtar }; 64