1d6451924SChanho Park // SPDX-License-Identifier: GPL-2.0-only 2d6451924SChanho Park /* 3d6451924SChanho Park * UFS PHY driver data for Samsung EXYNOSAUTO v9 SoC 4d6451924SChanho Park * 5d6451924SChanho Park * Copyright (C) 2021 Samsung Electronics Co., Ltd. 6d6451924SChanho Park */ 7d6451924SChanho Park 8d6451924SChanho Park #include "phy-samsung-ufs.h" 9d6451924SChanho Park 10d6451924SChanho Park #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 11d6451924SChanho Park #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 12d6451924SChanho Park #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 13e313216bSAlim Akhtar #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e 14d6451924SChanho Park 15d6451924SChanho Park #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ 16d6451924SChanho Park PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) 17d6451924SChanho Park 18d6451924SChanho Park /* Calibration for phy initialization */ 19d6451924SChanho Park static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = { 20d6451924SChanho Park PHY_COMN_REG_CFG(0x023, 0x80, PWR_MODE_ANY), 21d6451924SChanho Park PHY_COMN_REG_CFG(0x01d, 0x10, PWR_MODE_ANY), 22d6451924SChanho Park 23d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x044, 0xb5, PWR_MODE_ANY), 24d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x43, PWR_MODE_ANY), 25d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x05b, 0x20, PWR_MODE_ANY), 26d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x05e, 0xc0, PWR_MODE_ANY), 27d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x038, 0x12, PWR_MODE_ANY), 28d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x059, 0x58, PWR_MODE_ANY), 29d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x06c, 0x18, PWR_MODE_ANY), 30d6451924SChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x06d, 0x02, PWR_MODE_ANY), 31d6451924SChanho Park 32d6451924SChanho Park PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY), 33d6451924SChanho Park PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY), 34d6451924SChanho Park 35f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY), 36f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY), 37d6451924SChanho Park 38d6451924SChanho Park END_UFS_PHY_CFG, 39d6451924SChanho Park }; 40d6451924SChanho Park 41d6451924SChanho Park /* Calibration for HS mode series A/B */ 42d6451924SChanho Park static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = { 43f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY), 44f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY), 45f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY), 46d6451924SChanho Park 47f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B), 48f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B | 49d6451924SChanho Park PWR_MODE_HS_G3_SER_B), 50f7fdc4dbSChanho Park PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B), 51d6451924SChanho Park 52d6451924SChanho Park END_UFS_PHY_CFG, 53d6451924SChanho Park }; 54d6451924SChanho Park 55d6451924SChanho Park static const struct samsung_ufs_phy_cfg *exynosautov9_ufs_phy_cfgs[CFG_TAG_MAX] = { 56d6451924SChanho Park [CFG_PRE_INIT] = exynosautov9_pre_init_cfg, 57d6451924SChanho Park [CFG_PRE_PWR_HS] = exynosautov9_pre_pwr_hs_cfg, 58d6451924SChanho Park }; 59d6451924SChanho Park 60*8d5bb683SChanho Park static const char * const exynosautov9_ufs_phy_clks[] = { 61*8d5bb683SChanho Park "ref_clk", 62*8d5bb683SChanho Park }; 63*8d5bb683SChanho Park 64d6451924SChanho Park const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { 65558801e8SChanho Park .cfgs = exynosautov9_ufs_phy_cfgs, 66d6451924SChanho Park .isol = { 67d6451924SChanho Park .offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL, 68d6451924SChanho Park .mask = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK, 69d6451924SChanho Park .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, 70d6451924SChanho Park }, 71*8d5bb683SChanho Park .clk_list = exynosautov9_ufs_phy_clks, 72*8d5bb683SChanho Park .num_clks = ARRAY_SIZE(exynosautov9_ufs_phy_clks), 73e313216bSAlim Akhtar .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, 74d6451924SChanho Park }; 75