1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/phy/phy.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * mask of lanes for which this register is written 47 * for cases when second lane needs different values 48 */ 49 u8 lane_mask; 50 }; 51 52 #define QMP_PHY_INIT_CFG(o, v) \ 53 { \ 54 .offset = o, \ 55 .val = v, \ 56 .lane_mask = 0xff, \ 57 } 58 59 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 60 { \ 61 .offset = o, \ 62 .val = v, \ 63 .lane_mask = l, \ 64 } 65 66 /* set of registers with offsets different per-PHY */ 67 enum qphy_reg_layout { 68 /* PCS registers */ 69 QPHY_SW_RESET, 70 QPHY_START_CTRL, 71 QPHY_PCS_STATUS, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 /* Keep last to ensure regs_layout arrays are properly initialized */ 74 QPHY_LAYOUT_SIZE 75 }; 76 77 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 78 [QPHY_SW_RESET] = 0x00, 79 [QPHY_START_CTRL] = 0x44, 80 [QPHY_PCS_STATUS] = 0x14, 81 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 82 }; 83 84 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 85 [QPHY_SW_RESET] = 0x00, 86 [QPHY_START_CTRL] = 0x08, 87 [QPHY_PCS_STATUS] = 0x174, 88 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 89 }; 90 91 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 92 [QPHY_SW_RESET] = 0x00, 93 [QPHY_START_CTRL] = 0x08, 94 [QPHY_PCS_STATUS] = 0x174, 95 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 96 }; 97 98 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 99 [QPHY_SW_RESET] = 0x00, 100 [QPHY_START_CTRL] = 0x08, 101 [QPHY_PCS_STATUS] = 0x2ac, 102 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 103 }; 104 105 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x44, 108 [QPHY_PCS_STATUS] = 0x14, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 110 }; 111 112 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 155 }; 156 157 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 159 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 162 }; 163 164 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 179 }; 180 181 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 192 }; 193 194 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 195 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 241 }; 242 243 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 244 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 246 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 247 }; 248 249 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 280 }; 281 282 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 290 }; 291 292 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 302 }; 303 304 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 305 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 306 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 307 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 308 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 310 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 311 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 313 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 314 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 315 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 317 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 318 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 319 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 320 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 321 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 322 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 323 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 325 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 331 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 332 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 333 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 334 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 335 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 336 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 341 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 344 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 345 }; 346 347 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 348 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 349 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 350 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 351 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 352 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 353 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 354 }; 355 356 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 357 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 358 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 359 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 360 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 361 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 362 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 363 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 368 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 378 }; 379 380 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 381 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 438 }; 439 440 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 441 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 442 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 445 }; 446 447 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 478 }; 479 480 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 505 }; 506 507 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 550 }; 551 552 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 553 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 554 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 555 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 556 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 557 }; 558 559 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 576 }; 577 578 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 580 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 586 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 594 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 598 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 600 }; 601 602 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 608 }; 609 610 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 611 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 612 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 613 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 656 }; 657 658 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 715 }; 716 717 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 718 }; 719 720 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 728 }; 729 730 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 773 }; 774 775 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 776 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 777 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 778 }; 779 780 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 817 }; 818 819 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 825 }; 826 827 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 835 }; 836 837 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 879 }; 880 881 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 883 }; 884 885 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 886 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 887 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 888 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 889 }; 890 891 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 894 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 895 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 896 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 897 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 898 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 899 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 900 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 901 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 902 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 903 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 922 }; 923 924 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 931 }; 932 933 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 934 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 935 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 936 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 937 }; 938 939 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 940 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 941 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 942 }; 943 944 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 945 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 946 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 948 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 949 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 950 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 951 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 952 }; 953 954 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 957 }; 958 959 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 960 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 961 }; 962 963 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 968 }; 969 970 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 973 }; 974 975 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 978 }; 979 980 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1020 }; 1021 1022 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1023 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1028 }; 1029 1030 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1031 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1056 }; 1057 1058 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1059 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1060 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1061 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1062 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1063 }; 1064 1065 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1066 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1067 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1068 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1069 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1070 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1071 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1072 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1073 }; 1074 1075 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1118 }; 1119 1120 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1121 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1126 }; 1127 1128 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1151 }; 1152 1153 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1154 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1155 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1156 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1157 }; 1158 1159 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1160 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1162 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1163 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1164 }; 1165 1166 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1167 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1180 }; 1181 1182 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1183 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1211 }; 1212 1213 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1214 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1218 }; 1219 1220 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1221 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1245 1246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1247 1248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1249 1250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1258 1259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1268 }; 1269 1270 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1271 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1272 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1273 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1274 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1275 }; 1276 1277 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1278 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1279 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1280 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1281 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1282 }; 1283 1284 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1285 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1286 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1287 }; 1288 1289 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1310 }; 1311 1312 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1313 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1314 }; 1315 1316 struct qmp_phy_cfg_tables { 1317 const struct qmp_phy_init_tbl *serdes; 1318 int serdes_num; 1319 const struct qmp_phy_init_tbl *tx; 1320 int tx_num; 1321 const struct qmp_phy_init_tbl *rx; 1322 int rx_num; 1323 const struct qmp_phy_init_tbl *pcs; 1324 int pcs_num; 1325 const struct qmp_phy_init_tbl *pcs_misc; 1326 int pcs_misc_num; 1327 }; 1328 1329 /* struct qmp_phy_cfg - per-PHY initialization config */ 1330 struct qmp_phy_cfg { 1331 int lanes; 1332 1333 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1334 const struct qmp_phy_cfg_tables tables; 1335 /* 1336 * Additional init sequences for PHY blocks, providing additional 1337 * register programming. They are used for providing separate sequences 1338 * for the Root Complex and End Point use cases. 1339 * 1340 * If EP mode is not supported, both tables can be left unset. 1341 */ 1342 const struct qmp_phy_cfg_tables *tables_rc; 1343 const struct qmp_phy_cfg_tables *tables_ep; 1344 1345 /* clock ids to be requested */ 1346 const char * const *clk_list; 1347 int num_clks; 1348 /* resets to be requested */ 1349 const char * const *reset_list; 1350 int num_resets; 1351 /* regulators to be requested */ 1352 const char * const *vreg_list; 1353 int num_vregs; 1354 1355 /* array of registers with different offsets */ 1356 const unsigned int *regs; 1357 1358 unsigned int start_ctrl; 1359 unsigned int pwrdn_ctrl; 1360 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1361 unsigned int phy_status; 1362 1363 /* true, if PHY needs delay after POWER_DOWN */ 1364 bool has_pwrdn_delay; 1365 /* power_down delay in usec */ 1366 int pwrdn_delay_min; 1367 int pwrdn_delay_max; 1368 1369 /* QMP PHY pipe clock interface rate */ 1370 unsigned long pipe_clock_rate; 1371 }; 1372 1373 /** 1374 * struct qmp_phy - per-lane phy descriptor 1375 * 1376 * @phy: generic phy 1377 * @cfg: phy specific configuration 1378 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1379 * @tx: iomapped memory space for lane's tx 1380 * @rx: iomapped memory space for lane's rx 1381 * @pcs: iomapped memory space for lane's pcs 1382 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1383 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1384 * @pcs_misc: iomapped memory space for lane's pcs_misc 1385 * @pipe_clk: pipe clock 1386 * @qmp: QMP phy to which this lane belongs 1387 * @mode: currently selected PHY mode 1388 */ 1389 struct qmp_phy { 1390 struct phy *phy; 1391 const struct qmp_phy_cfg *cfg; 1392 void __iomem *serdes; 1393 void __iomem *tx; 1394 void __iomem *rx; 1395 void __iomem *pcs; 1396 void __iomem *tx2; 1397 void __iomem *rx2; 1398 void __iomem *pcs_misc; 1399 struct clk *pipe_clk; 1400 struct qcom_qmp *qmp; 1401 int mode; 1402 }; 1403 1404 /** 1405 * struct qcom_qmp - structure holding QMP phy block attributes 1406 * 1407 * @dev: device 1408 * 1409 * @clks: array of clocks required by phy 1410 * @resets: array of resets required by phy 1411 * @vregs: regulator supplies bulk data 1412 * 1413 * @phys: array of per-lane phy descriptors 1414 */ 1415 struct qcom_qmp { 1416 struct device *dev; 1417 1418 struct clk_bulk_data *clks; 1419 struct reset_control_bulk_data *resets; 1420 struct regulator_bulk_data *vregs; 1421 1422 struct qmp_phy **phys; 1423 }; 1424 1425 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1426 { 1427 u32 reg; 1428 1429 reg = readl(base + offset); 1430 reg |= val; 1431 writel(reg, base + offset); 1432 1433 /* ensure that above write is through */ 1434 readl(base + offset); 1435 } 1436 1437 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1438 { 1439 u32 reg; 1440 1441 reg = readl(base + offset); 1442 reg &= ~val; 1443 writel(reg, base + offset); 1444 1445 /* ensure that above write is through */ 1446 readl(base + offset); 1447 } 1448 1449 /* list of clocks required by phy */ 1450 static const char * const ipq8074_pciephy_clk_l[] = { 1451 "aux", "cfg_ahb", 1452 }; 1453 1454 static const char * const msm8996_phy_clk_l[] = { 1455 "aux", "cfg_ahb", "ref", 1456 }; 1457 1458 1459 static const char * const sdm845_pciephy_clk_l[] = { 1460 "aux", "cfg_ahb", "ref", "refgen", 1461 }; 1462 1463 /* list of regulators */ 1464 static const char * const qmp_phy_vreg_l[] = { 1465 "vdda-phy", "vdda-pll", 1466 }; 1467 1468 /* list of resets */ 1469 static const char * const ipq8074_pciephy_reset_l[] = { 1470 "phy", "common", 1471 }; 1472 1473 static const char * const sdm845_pciephy_reset_l[] = { 1474 "phy", 1475 }; 1476 1477 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1478 .lanes = 1, 1479 1480 .tables = { 1481 .serdes = ipq8074_pcie_serdes_tbl, 1482 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1483 .tx = ipq8074_pcie_tx_tbl, 1484 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1485 .rx = ipq8074_pcie_rx_tbl, 1486 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1487 .pcs = ipq8074_pcie_pcs_tbl, 1488 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1489 }, 1490 .clk_list = ipq8074_pciephy_clk_l, 1491 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1492 .reset_list = ipq8074_pciephy_reset_l, 1493 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1494 .vreg_list = NULL, 1495 .num_vregs = 0, 1496 .regs = pciephy_regs_layout, 1497 1498 .start_ctrl = SERDES_START | PCS_START, 1499 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1500 .phy_status = PHYSTATUS, 1501 1502 .has_pwrdn_delay = true, 1503 .pwrdn_delay_min = 995, /* us */ 1504 .pwrdn_delay_max = 1005, /* us */ 1505 }; 1506 1507 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1508 .lanes = 1, 1509 1510 .tables = { 1511 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1512 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1513 .tx = ipq8074_pcie_gen3_tx_tbl, 1514 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1515 .rx = ipq8074_pcie_gen3_rx_tbl, 1516 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1517 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1518 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1519 }, 1520 .clk_list = ipq8074_pciephy_clk_l, 1521 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1522 .reset_list = ipq8074_pciephy_reset_l, 1523 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1524 .vreg_list = NULL, 1525 .num_vregs = 0, 1526 .regs = ipq_pciephy_gen3_regs_layout, 1527 1528 .start_ctrl = SERDES_START | PCS_START, 1529 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1530 1531 .has_pwrdn_delay = true, 1532 .pwrdn_delay_min = 995, /* us */ 1533 .pwrdn_delay_max = 1005, /* us */ 1534 1535 .pipe_clock_rate = 250000000, 1536 }; 1537 1538 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1539 .lanes = 1, 1540 1541 .tables = { 1542 .serdes = ipq6018_pcie_serdes_tbl, 1543 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1544 .tx = ipq6018_pcie_tx_tbl, 1545 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1546 .rx = ipq6018_pcie_rx_tbl, 1547 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1548 .pcs = ipq6018_pcie_pcs_tbl, 1549 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1550 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1551 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1552 }, 1553 .clk_list = ipq8074_pciephy_clk_l, 1554 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1555 .reset_list = ipq8074_pciephy_reset_l, 1556 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1557 .vreg_list = NULL, 1558 .num_vregs = 0, 1559 .regs = ipq_pciephy_gen3_regs_layout, 1560 1561 .start_ctrl = SERDES_START | PCS_START, 1562 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1563 1564 .has_pwrdn_delay = true, 1565 .pwrdn_delay_min = 995, /* us */ 1566 .pwrdn_delay_max = 1005, /* us */ 1567 }; 1568 1569 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1570 .lanes = 1, 1571 1572 .tables = { 1573 .serdes = sdm845_qmp_pcie_serdes_tbl, 1574 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1575 .tx = sdm845_qmp_pcie_tx_tbl, 1576 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1577 .rx = sdm845_qmp_pcie_rx_tbl, 1578 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1579 .pcs = sdm845_qmp_pcie_pcs_tbl, 1580 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1581 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1582 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1583 }, 1584 .clk_list = sdm845_pciephy_clk_l, 1585 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1586 .reset_list = sdm845_pciephy_reset_l, 1587 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1588 .vreg_list = qmp_phy_vreg_l, 1589 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1590 .regs = sdm845_qmp_pciephy_regs_layout, 1591 1592 .start_ctrl = PCS_START | SERDES_START, 1593 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1594 .phy_status = PHYSTATUS, 1595 1596 .has_pwrdn_delay = true, 1597 .pwrdn_delay_min = 995, /* us */ 1598 .pwrdn_delay_max = 1005, /* us */ 1599 }; 1600 1601 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1602 .lanes = 1, 1603 1604 .tables = { 1605 .serdes = sdm845_qhp_pcie_serdes_tbl, 1606 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1607 .tx = sdm845_qhp_pcie_tx_tbl, 1608 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1609 .rx = sdm845_qhp_pcie_rx_tbl, 1610 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1611 .pcs = sdm845_qhp_pcie_pcs_tbl, 1612 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1613 }, 1614 .clk_list = sdm845_pciephy_clk_l, 1615 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1616 .reset_list = sdm845_pciephy_reset_l, 1617 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1618 .vreg_list = qmp_phy_vreg_l, 1619 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1620 .regs = sdm845_qhp_pciephy_regs_layout, 1621 1622 .start_ctrl = PCS_START | SERDES_START, 1623 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1624 .phy_status = PHYSTATUS, 1625 1626 .has_pwrdn_delay = true, 1627 .pwrdn_delay_min = 995, /* us */ 1628 .pwrdn_delay_max = 1005, /* us */ 1629 }; 1630 1631 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1632 .lanes = 1, 1633 1634 .tables = { 1635 .serdes = sm8250_qmp_pcie_serdes_tbl, 1636 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1637 .tx = sm8250_qmp_pcie_tx_tbl, 1638 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1639 .rx = sm8250_qmp_pcie_rx_tbl, 1640 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1641 .pcs = sm8250_qmp_pcie_pcs_tbl, 1642 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1643 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1644 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1645 }, 1646 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1647 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1648 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1649 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1650 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1651 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1652 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1653 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1654 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1655 }, 1656 .clk_list = sdm845_pciephy_clk_l, 1657 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1658 .reset_list = sdm845_pciephy_reset_l, 1659 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1660 .vreg_list = qmp_phy_vreg_l, 1661 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1662 .regs = sm8250_pcie_regs_layout, 1663 1664 .start_ctrl = PCS_START | SERDES_START, 1665 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1666 .phy_status = PHYSTATUS, 1667 1668 .has_pwrdn_delay = true, 1669 .pwrdn_delay_min = 995, /* us */ 1670 .pwrdn_delay_max = 1005, /* us */ 1671 }; 1672 1673 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1674 .lanes = 2, 1675 1676 .tables = { 1677 .serdes = sm8250_qmp_pcie_serdes_tbl, 1678 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1679 .tx = sm8250_qmp_pcie_tx_tbl, 1680 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1681 .rx = sm8250_qmp_pcie_rx_tbl, 1682 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1683 .pcs = sm8250_qmp_pcie_pcs_tbl, 1684 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1685 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1686 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1687 }, 1688 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1689 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1690 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1691 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1692 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1693 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1694 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1695 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1696 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1697 }, 1698 .clk_list = sdm845_pciephy_clk_l, 1699 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1700 .reset_list = sdm845_pciephy_reset_l, 1701 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1702 .vreg_list = qmp_phy_vreg_l, 1703 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1704 .regs = sm8250_pcie_regs_layout, 1705 1706 .start_ctrl = PCS_START | SERDES_START, 1707 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1708 .phy_status = PHYSTATUS, 1709 1710 .has_pwrdn_delay = true, 1711 .pwrdn_delay_min = 995, /* us */ 1712 .pwrdn_delay_max = 1005, /* us */ 1713 }; 1714 1715 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1716 .lanes = 1, 1717 1718 .tables = { 1719 .serdes = msm8998_pcie_serdes_tbl, 1720 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1721 .tx = msm8998_pcie_tx_tbl, 1722 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1723 .rx = msm8998_pcie_rx_tbl, 1724 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1725 .pcs = msm8998_pcie_pcs_tbl, 1726 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1727 }, 1728 .clk_list = msm8996_phy_clk_l, 1729 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1730 .reset_list = ipq8074_pciephy_reset_l, 1731 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1732 .vreg_list = qmp_phy_vreg_l, 1733 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1734 .regs = pciephy_regs_layout, 1735 1736 .start_ctrl = SERDES_START | PCS_START, 1737 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1738 .phy_status = PHYSTATUS, 1739 }; 1740 1741 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1742 .lanes = 1, 1743 1744 .tables = { 1745 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1746 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1747 .tx = sc8180x_qmp_pcie_tx_tbl, 1748 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1749 .rx = sc8180x_qmp_pcie_rx_tbl, 1750 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1751 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1752 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1753 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1754 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1755 }, 1756 .clk_list = sdm845_pciephy_clk_l, 1757 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1758 .reset_list = sdm845_pciephy_reset_l, 1759 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1760 .vreg_list = qmp_phy_vreg_l, 1761 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1762 .regs = sm8250_pcie_regs_layout, 1763 1764 .start_ctrl = PCS_START | SERDES_START, 1765 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1766 1767 .has_pwrdn_delay = true, 1768 .pwrdn_delay_min = 995, /* us */ 1769 .pwrdn_delay_max = 1005, /* us */ 1770 }; 1771 1772 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1773 .lanes = 2, 1774 1775 .tables = { 1776 .serdes = sdx55_qmp_pcie_serdes_tbl, 1777 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1778 .tx = sdx55_qmp_pcie_tx_tbl, 1779 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1780 .rx = sdx55_qmp_pcie_rx_tbl, 1781 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1782 .pcs = sdx55_qmp_pcie_pcs_tbl, 1783 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1784 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1785 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1786 }, 1787 .clk_list = sdm845_pciephy_clk_l, 1788 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1789 .reset_list = sdm845_pciephy_reset_l, 1790 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1791 .vreg_list = qmp_phy_vreg_l, 1792 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1793 .regs = sm8250_pcie_regs_layout, 1794 1795 .start_ctrl = PCS_START | SERDES_START, 1796 .pwrdn_ctrl = SW_PWRDN, 1797 .phy_status = PHYSTATUS_4_20, 1798 1799 .has_pwrdn_delay = true, 1800 .pwrdn_delay_min = 995, /* us */ 1801 .pwrdn_delay_max = 1005, /* us */ 1802 }; 1803 1804 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1805 .lanes = 1, 1806 1807 .tables = { 1808 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1809 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1810 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1811 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1812 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1813 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1814 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1815 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1816 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1817 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1818 }, 1819 .clk_list = sdm845_pciephy_clk_l, 1820 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1821 .reset_list = sdm845_pciephy_reset_l, 1822 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1823 .vreg_list = qmp_phy_vreg_l, 1824 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1825 .regs = sm8250_pcie_regs_layout, 1826 1827 .start_ctrl = SERDES_START | PCS_START, 1828 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1829 .phy_status = PHYSTATUS, 1830 1831 .has_pwrdn_delay = true, 1832 .pwrdn_delay_min = 995, /* us */ 1833 .pwrdn_delay_max = 1005, /* us */ 1834 }; 1835 1836 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1837 .lanes = 2, 1838 1839 .tables = { 1840 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1841 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1842 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1843 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1844 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1845 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1846 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1847 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1848 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1849 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1850 }, 1851 1852 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1853 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 1854 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 1855 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 1856 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 1857 }, 1858 1859 .tables_ep = &(const struct qmp_phy_cfg_tables) { 1860 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 1861 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 1862 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 1863 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 1864 }, 1865 1866 .clk_list = sdm845_pciephy_clk_l, 1867 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1868 .reset_list = sdm845_pciephy_reset_l, 1869 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1870 .vreg_list = qmp_phy_vreg_l, 1871 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1872 .regs = sm8250_pcie_regs_layout, 1873 1874 .start_ctrl = SERDES_START | PCS_START, 1875 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1876 .phy_status = PHYSTATUS_4_20, 1877 1878 .has_pwrdn_delay = true, 1879 .pwrdn_delay_min = 995, /* us */ 1880 .pwrdn_delay_max = 1005, /* us */ 1881 }; 1882 1883 static void qmp_pcie_configure_lane(void __iomem *base, 1884 const struct qmp_phy_init_tbl tbl[], 1885 int num, 1886 u8 lane_mask) 1887 { 1888 int i; 1889 const struct qmp_phy_init_tbl *t = tbl; 1890 1891 if (!t) 1892 return; 1893 1894 for (i = 0; i < num; i++, t++) { 1895 if (!(t->lane_mask & lane_mask)) 1896 continue; 1897 1898 writel(t->val, base + t->offset); 1899 } 1900 } 1901 1902 static void qmp_pcie_configure(void __iomem *base, 1903 const struct qmp_phy_init_tbl tbl[], 1904 int num) 1905 { 1906 qmp_pcie_configure_lane(base, tbl, num, 0xff); 1907 } 1908 1909 static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1910 { 1911 void __iomem *serdes = qphy->serdes; 1912 1913 if (!tables) 1914 return; 1915 1916 qmp_pcie_configure(serdes, tables->serdes, tables->serdes_num); 1917 } 1918 1919 static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1920 { 1921 const struct qmp_phy_cfg *cfg = qphy->cfg; 1922 void __iomem *tx = qphy->tx; 1923 void __iomem *rx = qphy->rx; 1924 1925 if (!tables) 1926 return; 1927 1928 qmp_pcie_configure_lane(tx, tables->tx, tables->tx_num, 1); 1929 1930 if (cfg->lanes >= 2) 1931 qmp_pcie_configure_lane(qphy->tx2, tables->tx, tables->tx_num, 2); 1932 1933 qmp_pcie_configure_lane(rx, tables->rx, tables->rx_num, 1); 1934 if (cfg->lanes >= 2) 1935 qmp_pcie_configure_lane(qphy->rx2, tables->rx, tables->rx_num, 2); 1936 } 1937 1938 static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1939 { 1940 void __iomem *pcs = qphy->pcs; 1941 void __iomem *pcs_misc = qphy->pcs_misc; 1942 1943 if (!tables) 1944 return; 1945 1946 qmp_pcie_configure(pcs, tables->pcs, tables->pcs_num); 1947 qmp_pcie_configure(pcs_misc, tables->pcs_misc, tables->pcs_misc_num); 1948 } 1949 1950 static int qmp_pcie_init(struct phy *phy) 1951 { 1952 struct qmp_phy *qphy = phy_get_drvdata(phy); 1953 struct qcom_qmp *qmp = qphy->qmp; 1954 const struct qmp_phy_cfg *cfg = qphy->cfg; 1955 int ret; 1956 1957 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1958 if (ret) { 1959 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1960 return ret; 1961 } 1962 1963 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1964 if (ret) { 1965 dev_err(qmp->dev, "reset assert failed\n"); 1966 goto err_disable_regulators; 1967 } 1968 1969 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1970 if (ret) { 1971 dev_err(qmp->dev, "reset deassert failed\n"); 1972 goto err_disable_regulators; 1973 } 1974 1975 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1976 if (ret) 1977 goto err_assert_reset; 1978 1979 return 0; 1980 1981 err_assert_reset: 1982 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1983 err_disable_regulators: 1984 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1985 1986 return ret; 1987 } 1988 1989 static int qmp_pcie_exit(struct phy *phy) 1990 { 1991 struct qmp_phy *qphy = phy_get_drvdata(phy); 1992 struct qcom_qmp *qmp = qphy->qmp; 1993 const struct qmp_phy_cfg *cfg = qphy->cfg; 1994 1995 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1996 1997 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1998 1999 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2000 2001 return 0; 2002 } 2003 2004 static int qmp_pcie_power_on(struct phy *phy) 2005 { 2006 struct qmp_phy *qphy = phy_get_drvdata(phy); 2007 struct qcom_qmp *qmp = qphy->qmp; 2008 const struct qmp_phy_cfg *cfg = qphy->cfg; 2009 const struct qmp_phy_cfg_tables *mode_tables; 2010 void __iomem *pcs = qphy->pcs; 2011 void __iomem *status; 2012 unsigned int mask, val, ready; 2013 int ret; 2014 2015 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2016 cfg->pwrdn_ctrl); 2017 2018 if (qphy->mode == PHY_MODE_PCIE_RC) 2019 mode_tables = cfg->tables_rc; 2020 else 2021 mode_tables = cfg->tables_ep; 2022 2023 qmp_pcie_serdes_init(qphy, &cfg->tables); 2024 qmp_pcie_serdes_init(qphy, mode_tables); 2025 2026 ret = clk_prepare_enable(qphy->pipe_clk); 2027 if (ret) { 2028 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2029 return ret; 2030 } 2031 2032 /* Tx, Rx, and PCS configurations */ 2033 qmp_pcie_lanes_init(qphy, &cfg->tables); 2034 qmp_pcie_lanes_init(qphy, mode_tables); 2035 2036 qmp_pcie_pcs_init(qphy, &cfg->tables); 2037 qmp_pcie_pcs_init(qphy, mode_tables); 2038 2039 if (cfg->has_pwrdn_delay) 2040 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2041 2042 /* Pull PHY out of reset state */ 2043 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2044 2045 /* start SerDes and Phy-Coding-Sublayer */ 2046 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2047 2048 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2049 mask = cfg->phy_status; 2050 ready = 0; 2051 2052 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2053 PHY_INIT_COMPLETE_TIMEOUT); 2054 if (ret) { 2055 dev_err(qmp->dev, "phy initialization timed-out\n"); 2056 goto err_disable_pipe_clk; 2057 } 2058 2059 return 0; 2060 2061 err_disable_pipe_clk: 2062 clk_disable_unprepare(qphy->pipe_clk); 2063 2064 return ret; 2065 } 2066 2067 static int qmp_pcie_power_off(struct phy *phy) 2068 { 2069 struct qmp_phy *qphy = phy_get_drvdata(phy); 2070 const struct qmp_phy_cfg *cfg = qphy->cfg; 2071 2072 clk_disable_unprepare(qphy->pipe_clk); 2073 2074 /* PHY reset */ 2075 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2076 2077 /* stop SerDes and Phy-Coding-Sublayer */ 2078 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2079 2080 /* Put PHY into POWER DOWN state: active low */ 2081 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2082 cfg->pwrdn_ctrl); 2083 2084 return 0; 2085 } 2086 2087 static int qmp_pcie_enable(struct phy *phy) 2088 { 2089 int ret; 2090 2091 ret = qmp_pcie_init(phy); 2092 if (ret) 2093 return ret; 2094 2095 ret = qmp_pcie_power_on(phy); 2096 if (ret) 2097 qmp_pcie_exit(phy); 2098 2099 return ret; 2100 } 2101 2102 static int qmp_pcie_disable(struct phy *phy) 2103 { 2104 int ret; 2105 2106 ret = qmp_pcie_power_off(phy); 2107 if (ret) 2108 return ret; 2109 2110 return qmp_pcie_exit(phy); 2111 } 2112 2113 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2114 { 2115 struct qmp_phy *qphy = phy_get_drvdata(phy); 2116 2117 switch (submode) { 2118 case PHY_MODE_PCIE_RC: 2119 case PHY_MODE_PCIE_EP: 2120 qphy->mode = submode; 2121 break; 2122 default: 2123 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2124 return -EINVAL; 2125 } 2126 2127 return 0; 2128 } 2129 2130 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2131 { 2132 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2133 int num = cfg->num_vregs; 2134 int i; 2135 2136 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2137 if (!qmp->vregs) 2138 return -ENOMEM; 2139 2140 for (i = 0; i < num; i++) 2141 qmp->vregs[i].supply = cfg->vreg_list[i]; 2142 2143 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2144 } 2145 2146 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2147 { 2148 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2149 int i; 2150 int ret; 2151 2152 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2153 sizeof(*qmp->resets), GFP_KERNEL); 2154 if (!qmp->resets) 2155 return -ENOMEM; 2156 2157 for (i = 0; i < cfg->num_resets; i++) 2158 qmp->resets[i].id = cfg->reset_list[i]; 2159 2160 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2161 if (ret) 2162 return dev_err_probe(dev, ret, "failed to get resets\n"); 2163 2164 return 0; 2165 } 2166 2167 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2168 { 2169 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2170 int num = cfg->num_clks; 2171 int i; 2172 2173 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2174 if (!qmp->clks) 2175 return -ENOMEM; 2176 2177 for (i = 0; i < num; i++) 2178 qmp->clks[i].id = cfg->clk_list[i]; 2179 2180 return devm_clk_bulk_get(dev, num, qmp->clks); 2181 } 2182 2183 static void phy_clk_release_provider(void *res) 2184 { 2185 of_clk_del_provider(res); 2186 } 2187 2188 /* 2189 * Register a fixed rate pipe clock. 2190 * 2191 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2192 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2193 * by the PHY driver for its operations. 2194 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2195 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2196 * Below picture shows this relationship. 2197 * 2198 * +---------------+ 2199 * | PHY block |<<---------------------------------------+ 2200 * | | | 2201 * | +-------+ | +-----+ | 2202 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2203 * clk | +-------+ | +-----+ 2204 * +---------------+ 2205 */ 2206 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2207 { 2208 struct clk_fixed_rate *fixed; 2209 struct clk_init_data init = { }; 2210 int ret; 2211 2212 ret = of_property_read_string(np, "clock-output-names", &init.name); 2213 if (ret) { 2214 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2215 return ret; 2216 } 2217 2218 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2219 if (!fixed) 2220 return -ENOMEM; 2221 2222 init.ops = &clk_fixed_rate_ops; 2223 2224 /* 2225 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2226 * unless other frequency is specified in the PHY config. 2227 */ 2228 if (qmp->phys[0]->cfg->pipe_clock_rate) 2229 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2230 else 2231 fixed->fixed_rate = 125000000; 2232 2233 fixed->hw.init = &init; 2234 2235 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2236 if (ret) 2237 return ret; 2238 2239 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2240 if (ret) 2241 return ret; 2242 2243 /* 2244 * Roll a devm action because the clock provider is the child node, but 2245 * the child node is not actually a device. 2246 */ 2247 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2248 } 2249 2250 static const struct phy_ops qmp_pcie_ops = { 2251 .power_on = qmp_pcie_enable, 2252 .power_off = qmp_pcie_disable, 2253 .set_mode = qmp_pcie_set_mode, 2254 .owner = THIS_MODULE, 2255 }; 2256 2257 static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2258 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2259 { 2260 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2261 struct phy *generic_phy; 2262 struct qmp_phy *qphy; 2263 int ret; 2264 2265 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2266 if (!qphy) 2267 return -ENOMEM; 2268 2269 qphy->mode = PHY_MODE_PCIE_RC; 2270 2271 qphy->cfg = cfg; 2272 qphy->serdes = serdes; 2273 /* 2274 * Get memory resources for the PHY: 2275 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2276 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2277 * For single lane PHYs: pcs_misc (optional) -> 3. 2278 */ 2279 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2280 if (IS_ERR(qphy->tx)) 2281 return PTR_ERR(qphy->tx); 2282 2283 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2284 qphy->rx = qphy->tx; 2285 else 2286 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2287 if (IS_ERR(qphy->rx)) 2288 return PTR_ERR(qphy->rx); 2289 2290 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2291 if (IS_ERR(qphy->pcs)) 2292 return PTR_ERR(qphy->pcs); 2293 2294 if (cfg->lanes >= 2) { 2295 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2296 if (IS_ERR(qphy->tx2)) 2297 return PTR_ERR(qphy->tx2); 2298 2299 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2300 if (IS_ERR(qphy->rx2)) 2301 return PTR_ERR(qphy->rx2); 2302 2303 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2304 } else { 2305 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2306 } 2307 2308 if (IS_ERR(qphy->pcs_misc) && 2309 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2310 qphy->pcs_misc = qphy->pcs + 0x400; 2311 2312 if (IS_ERR(qphy->pcs_misc)) { 2313 if (cfg->tables.pcs_misc || 2314 (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2315 (cfg->tables_ep && cfg->tables_ep->pcs_misc)) 2316 return PTR_ERR(qphy->pcs_misc); 2317 } 2318 2319 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2320 if (IS_ERR(qphy->pipe_clk)) { 2321 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2322 "failed to get lane%d pipe clock\n", id); 2323 } 2324 2325 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2326 if (IS_ERR(generic_phy)) { 2327 ret = PTR_ERR(generic_phy); 2328 dev_err(dev, "failed to create qphy %d\n", ret); 2329 return ret; 2330 } 2331 2332 qphy->phy = generic_phy; 2333 qphy->qmp = qmp; 2334 qmp->phys[id] = qphy; 2335 phy_set_drvdata(generic_phy, qphy); 2336 2337 return 0; 2338 } 2339 2340 static const struct of_device_id qmp_pcie_of_match_table[] = { 2341 { 2342 .compatible = "qcom,msm8998-qmp-pcie-phy", 2343 .data = &msm8998_pciephy_cfg, 2344 }, { 2345 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2346 .data = &ipq8074_pciephy_cfg, 2347 }, { 2348 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2349 .data = &ipq8074_pciephy_gen3_cfg, 2350 }, { 2351 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2352 .data = &ipq6018_pciephy_cfg, 2353 }, { 2354 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2355 .data = &sc8180x_pciephy_cfg, 2356 }, { 2357 .compatible = "qcom,sdm845-qhp-pcie-phy", 2358 .data = &sdm845_qhp_pciephy_cfg, 2359 }, { 2360 .compatible = "qcom,sdm845-qmp-pcie-phy", 2361 .data = &sdm845_qmp_pciephy_cfg, 2362 }, { 2363 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2364 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2365 }, { 2366 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2367 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2368 }, { 2369 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2370 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2371 }, { 2372 .compatible = "qcom,sdx55-qmp-pcie-phy", 2373 .data = &sdx55_qmp_pciephy_cfg, 2374 }, { 2375 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2376 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2377 }, { 2378 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2379 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2380 }, 2381 { }, 2382 }; 2383 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2384 2385 static int qmp_pcie_probe(struct platform_device *pdev) 2386 { 2387 struct qcom_qmp *qmp; 2388 struct device *dev = &pdev->dev; 2389 struct device_node *child; 2390 struct phy_provider *phy_provider; 2391 void __iomem *serdes; 2392 const struct qmp_phy_cfg *cfg = NULL; 2393 int num, id; 2394 int ret; 2395 2396 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2397 if (!qmp) 2398 return -ENOMEM; 2399 2400 qmp->dev = dev; 2401 dev_set_drvdata(dev, qmp); 2402 2403 cfg = of_device_get_match_data(dev); 2404 if (!cfg) 2405 return -EINVAL; 2406 2407 serdes = devm_platform_ioremap_resource(pdev, 0); 2408 if (IS_ERR(serdes)) 2409 return PTR_ERR(serdes); 2410 2411 ret = qmp_pcie_clk_init(dev, cfg); 2412 if (ret) 2413 return ret; 2414 2415 ret = qmp_pcie_reset_init(dev, cfg); 2416 if (ret) 2417 return ret; 2418 2419 ret = qmp_pcie_vreg_init(dev, cfg); 2420 if (ret) 2421 return ret; 2422 2423 num = of_get_available_child_count(dev->of_node); 2424 /* do we have a rogue child node ? */ 2425 if (num > 1) 2426 return -EINVAL; 2427 2428 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2429 if (!qmp->phys) 2430 return -ENOMEM; 2431 2432 id = 0; 2433 for_each_available_child_of_node(dev->of_node, child) { 2434 /* Create per-lane phy */ 2435 ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2436 if (ret) { 2437 dev_err(dev, "failed to create lane%d phy, %d\n", 2438 id, ret); 2439 goto err_node_put; 2440 } 2441 2442 /* 2443 * Register the pipe clock provided by phy. 2444 * See function description to see details of this pipe clock. 2445 */ 2446 ret = phy_pipe_clk_register(qmp, child); 2447 if (ret) { 2448 dev_err(qmp->dev, 2449 "failed to register pipe clock source\n"); 2450 goto err_node_put; 2451 } 2452 2453 id++; 2454 } 2455 2456 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2457 2458 return PTR_ERR_OR_ZERO(phy_provider); 2459 2460 err_node_put: 2461 of_node_put(child); 2462 return ret; 2463 } 2464 2465 static struct platform_driver qmp_pcie_driver = { 2466 .probe = qmp_pcie_probe, 2467 .driver = { 2468 .name = "qcom-qmp-pcie-phy", 2469 .of_match_table = qmp_pcie_of_match_table, 2470 }, 2471 }; 2472 2473 module_platform_driver(qmp_pcie_driver); 2474 2475 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2476 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2477 MODULE_LICENSE("GPL v2"); 2478