1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/phy/phy.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * mask of lanes for which this register is written 47 * for cases when second lane needs different values 48 */ 49 u8 lane_mask; 50 }; 51 52 #define QMP_PHY_INIT_CFG(o, v) \ 53 { \ 54 .offset = o, \ 55 .val = v, \ 56 .lane_mask = 0xff, \ 57 } 58 59 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 60 { \ 61 .offset = o, \ 62 .val = v, \ 63 .lane_mask = l, \ 64 } 65 66 /* set of registers with offsets different per-PHY */ 67 enum qphy_reg_layout { 68 /* PCS registers */ 69 QPHY_SW_RESET, 70 QPHY_START_CTRL, 71 QPHY_PCS_STATUS, 72 QPHY_PCS_POWER_DOWN_CONTROL, 73 /* Keep last to ensure regs_layout arrays are properly initialized */ 74 QPHY_LAYOUT_SIZE 75 }; 76 77 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 78 [QPHY_SW_RESET] = 0x00, 79 [QPHY_START_CTRL] = 0x44, 80 [QPHY_PCS_STATUS] = 0x14, 81 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 82 }; 83 84 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 85 [QPHY_SW_RESET] = 0x00, 86 [QPHY_START_CTRL] = 0x08, 87 [QPHY_PCS_STATUS] = 0x174, 88 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 89 }; 90 91 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 92 [QPHY_SW_RESET] = 0x00, 93 [QPHY_START_CTRL] = 0x08, 94 [QPHY_PCS_STATUS] = 0x174, 95 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 96 }; 97 98 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 99 [QPHY_SW_RESET] = 0x00, 100 [QPHY_START_CTRL] = 0x08, 101 [QPHY_PCS_STATUS] = 0x2ac, 102 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 103 }; 104 105 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x44, 108 [QPHY_PCS_STATUS] = 0x14, 109 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 110 }; 111 112 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 113 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 114 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 155 }; 156 157 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 158 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 159 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 162 }; 163 164 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 166 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 179 }; 180 181 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 192 }; 193 194 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 195 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 196 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 241 }; 242 243 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 244 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 246 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 247 }; 248 249 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 280 }; 281 282 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 290 }; 291 292 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 302 }; 303 304 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 305 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 306 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 307 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 308 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 310 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 311 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 312 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 313 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 314 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 315 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 317 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 318 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 319 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 320 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 321 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 322 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 323 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 325 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 326 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 328 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 331 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 332 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 333 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 334 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 335 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 336 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 337 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 341 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 344 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 345 }; 346 347 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 348 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 349 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 350 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 351 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 352 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 353 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 354 }; 355 356 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 357 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 358 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 359 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 360 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 361 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 362 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 363 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 368 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 378 }; 379 380 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 381 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 382 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 383 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 438 }; 439 440 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 441 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 442 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 445 }; 446 447 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 448 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 449 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 478 }; 479 480 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 481 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 482 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 505 }; 506 507 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 550 }; 551 552 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 553 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 554 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 555 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 556 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 557 }; 558 559 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 576 }; 577 578 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 580 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 586 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 594 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 598 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 600 }; 601 602 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 608 }; 609 610 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 611 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 612 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 613 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 614 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 615 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 656 }; 657 658 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 715 }; 716 717 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 718 }; 719 720 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 728 }; 729 730 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 773 }; 774 775 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 776 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 777 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 778 }; 779 780 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 817 }; 818 819 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 825 }; 826 827 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 835 }; 836 837 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 838 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 839 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 840 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 841 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 842 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 879 }; 880 881 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 883 }; 884 885 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 886 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 887 }; 888 889 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 890 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 891 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 892 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 893 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 894 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 895 }; 896 897 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 902 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 903 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 904 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 905 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 906 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 916 }; 917 918 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 919 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 920 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 921 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 922 }; 923 924 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 925 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 926 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 927 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 928 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 929 }; 930 931 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 932 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 933 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 934 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 935 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 936 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 937 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 938 }; 939 940 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 941 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 942 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 943 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 944 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 945 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 946 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 947 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 948 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 949 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 950 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 951 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 952 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 958 }; 959 960 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 961 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 962 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 963 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 964 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 965 }; 966 967 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 968 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 969 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 970 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 971 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 972 }; 973 974 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 982 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 983 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1016 }; 1017 1018 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1020 }; 1021 1022 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1023 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1026 }; 1027 1028 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1059 }; 1060 1061 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1068 }; 1069 1070 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1071 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1072 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1073 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1074 }; 1075 1076 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1077 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1079 }; 1080 1081 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1085 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1086 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1087 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1088 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1089 }; 1090 1091 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1094 }; 1095 1096 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1097 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1098 }; 1099 1100 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1101 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1105 }; 1106 1107 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1108 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1109 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1110 }; 1111 1112 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1113 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1114 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1115 }; 1116 1117 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1118 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1119 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1120 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1121 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1122 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1123 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1124 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1125 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1126 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1157 }; 1158 1159 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1160 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1165 }; 1166 1167 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1168 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1169 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1174 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1175 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1176 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1177 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1179 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1180 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1181 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1182 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1183 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1184 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1185 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1191 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1192 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1193 }; 1194 1195 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1196 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1197 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1198 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1199 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1200 }; 1201 1202 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1203 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1204 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1205 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1206 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1207 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1208 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1209 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1210 }; 1211 1212 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1255 }; 1256 1257 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1258 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1263 }; 1264 1265 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1288 }; 1289 1290 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1291 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1292 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1293 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1294 }; 1295 1296 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1297 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1298 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1299 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1300 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1301 }; 1302 1303 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1317 }; 1318 1319 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1348 }; 1349 1350 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1351 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1355 }; 1356 1357 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1358 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1382 1383 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1384 1385 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1386 1387 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1389 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1390 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1391 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1392 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1393 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1394 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1395 1396 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1402 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1403 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1404 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1405 }; 1406 1407 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1408 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1409 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1410 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1411 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1412 }; 1413 1414 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1415 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1416 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1417 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1418 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1419 }; 1420 1421 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1422 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1423 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1424 }; 1425 1426 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1427 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1428 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1429 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1430 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1431 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1432 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1447 }; 1448 1449 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1450 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1451 }; 1452 1453 struct qmp_pcie_offsets { 1454 u16 serdes; 1455 u16 pcs; 1456 u16 pcs_misc; 1457 u16 tx; 1458 u16 rx; 1459 u16 tx2; 1460 u16 rx2; 1461 }; 1462 1463 struct qmp_phy_cfg_tbls { 1464 const struct qmp_phy_init_tbl *serdes; 1465 int serdes_num; 1466 const struct qmp_phy_init_tbl *tx; 1467 int tx_num; 1468 const struct qmp_phy_init_tbl *rx; 1469 int rx_num; 1470 const struct qmp_phy_init_tbl *pcs; 1471 int pcs_num; 1472 const struct qmp_phy_init_tbl *pcs_misc; 1473 int pcs_misc_num; 1474 }; 1475 1476 /* struct qmp_phy_cfg - per-PHY initialization config */ 1477 struct qmp_phy_cfg { 1478 int lanes; 1479 1480 const struct qmp_pcie_offsets *offsets; 1481 1482 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1483 const struct qmp_phy_cfg_tbls tbls; 1484 /* 1485 * Additional init sequences for PHY blocks, providing additional 1486 * register programming. They are used for providing separate sequences 1487 * for the Root Complex and End Point use cases. 1488 * 1489 * If EP mode is not supported, both tables can be left unset. 1490 */ 1491 const struct qmp_phy_cfg_tbls *tbls_rc; 1492 const struct qmp_phy_cfg_tbls *tbls_ep; 1493 1494 /* clock ids to be requested */ 1495 const char * const *clk_list; 1496 int num_clks; 1497 /* resets to be requested */ 1498 const char * const *reset_list; 1499 int num_resets; 1500 /* regulators to be requested */ 1501 const char * const *vreg_list; 1502 int num_vregs; 1503 1504 /* array of registers with different offsets */ 1505 const unsigned int *regs; 1506 1507 unsigned int pwrdn_ctrl; 1508 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1509 unsigned int phy_status; 1510 1511 bool skip_start_delay; 1512 1513 /* QMP PHY pipe clock interface rate */ 1514 unsigned long pipe_clock_rate; 1515 }; 1516 1517 struct qmp_pcie { 1518 struct device *dev; 1519 1520 const struct qmp_phy_cfg *cfg; 1521 1522 void __iomem *serdes; 1523 void __iomem *pcs; 1524 void __iomem *pcs_misc; 1525 void __iomem *tx; 1526 void __iomem *rx; 1527 void __iomem *tx2; 1528 void __iomem *rx2; 1529 1530 struct clk_bulk_data *clks; 1531 struct clk_bulk_data pipe_clks[2]; 1532 int num_pipe_clks; 1533 1534 struct reset_control_bulk_data *resets; 1535 struct regulator_bulk_data *vregs; 1536 1537 struct phy *phy; 1538 int mode; 1539 }; 1540 1541 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1542 { 1543 u32 reg; 1544 1545 reg = readl(base + offset); 1546 reg |= val; 1547 writel(reg, base + offset); 1548 1549 /* ensure that above write is through */ 1550 readl(base + offset); 1551 } 1552 1553 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1554 { 1555 u32 reg; 1556 1557 reg = readl(base + offset); 1558 reg &= ~val; 1559 writel(reg, base + offset); 1560 1561 /* ensure that above write is through */ 1562 readl(base + offset); 1563 } 1564 1565 /* list of clocks required by phy */ 1566 static const char * const ipq8074_pciephy_clk_l[] = { 1567 "aux", "cfg_ahb", 1568 }; 1569 1570 static const char * const msm8996_phy_clk_l[] = { 1571 "aux", "cfg_ahb", "ref", 1572 }; 1573 1574 static const char * const sc8280xp_pciephy_clk_l[] = { 1575 "aux", "cfg_ahb", "ref", "rchng", 1576 }; 1577 1578 static const char * const sdm845_pciephy_clk_l[] = { 1579 "aux", "cfg_ahb", "ref", "refgen", 1580 }; 1581 1582 /* list of regulators */ 1583 static const char * const qmp_phy_vreg_l[] = { 1584 "vdda-phy", "vdda-pll", 1585 }; 1586 1587 /* list of resets */ 1588 static const char * const ipq8074_pciephy_reset_l[] = { 1589 "phy", "common", 1590 }; 1591 1592 static const char * const sdm845_pciephy_reset_l[] = { 1593 "phy", 1594 }; 1595 1596 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 1597 .serdes = 0, 1598 .pcs = 0x0200, 1599 .pcs_misc = 0x0600, 1600 .tx = 0x0e00, 1601 .rx = 0x1000, 1602 .tx2 = 0x1600, 1603 .rx2 = 0x1800, 1604 }; 1605 1606 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1607 .lanes = 1, 1608 1609 .tbls = { 1610 .serdes = ipq8074_pcie_serdes_tbl, 1611 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1612 .tx = ipq8074_pcie_tx_tbl, 1613 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1614 .rx = ipq8074_pcie_rx_tbl, 1615 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1616 .pcs = ipq8074_pcie_pcs_tbl, 1617 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1618 }, 1619 .clk_list = ipq8074_pciephy_clk_l, 1620 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1621 .reset_list = ipq8074_pciephy_reset_l, 1622 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1623 .vreg_list = NULL, 1624 .num_vregs = 0, 1625 .regs = pciephy_regs_layout, 1626 1627 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1628 .phy_status = PHYSTATUS, 1629 }; 1630 1631 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1632 .lanes = 1, 1633 1634 .tbls = { 1635 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1636 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1637 .tx = ipq8074_pcie_gen3_tx_tbl, 1638 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1639 .rx = ipq8074_pcie_gen3_rx_tbl, 1640 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1641 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1642 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1643 }, 1644 .clk_list = ipq8074_pciephy_clk_l, 1645 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1646 .reset_list = ipq8074_pciephy_reset_l, 1647 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1648 .vreg_list = NULL, 1649 .num_vregs = 0, 1650 .regs = ipq_pciephy_gen3_regs_layout, 1651 1652 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1653 .phy_status = PHYSTATUS, 1654 1655 .pipe_clock_rate = 250000000, 1656 }; 1657 1658 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1659 .lanes = 1, 1660 1661 .tbls = { 1662 .serdes = ipq6018_pcie_serdes_tbl, 1663 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1664 .tx = ipq6018_pcie_tx_tbl, 1665 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1666 .rx = ipq6018_pcie_rx_tbl, 1667 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1668 .pcs = ipq6018_pcie_pcs_tbl, 1669 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1670 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1671 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1672 }, 1673 .clk_list = ipq8074_pciephy_clk_l, 1674 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1675 .reset_list = ipq8074_pciephy_reset_l, 1676 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1677 .vreg_list = NULL, 1678 .num_vregs = 0, 1679 .regs = ipq_pciephy_gen3_regs_layout, 1680 1681 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1682 .phy_status = PHYSTATUS, 1683 }; 1684 1685 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1686 .lanes = 1, 1687 1688 .tbls = { 1689 .serdes = sdm845_qmp_pcie_serdes_tbl, 1690 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1691 .tx = sdm845_qmp_pcie_tx_tbl, 1692 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1693 .rx = sdm845_qmp_pcie_rx_tbl, 1694 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1695 .pcs = sdm845_qmp_pcie_pcs_tbl, 1696 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1697 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1698 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1699 }, 1700 .clk_list = sdm845_pciephy_clk_l, 1701 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1702 .reset_list = sdm845_pciephy_reset_l, 1703 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1704 .vreg_list = qmp_phy_vreg_l, 1705 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1706 .regs = sdm845_qmp_pciephy_regs_layout, 1707 1708 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1709 .phy_status = PHYSTATUS, 1710 }; 1711 1712 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1713 .lanes = 1, 1714 1715 .tbls = { 1716 .serdes = sdm845_qhp_pcie_serdes_tbl, 1717 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1718 .tx = sdm845_qhp_pcie_tx_tbl, 1719 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1720 .rx = sdm845_qhp_pcie_rx_tbl, 1721 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1722 .pcs = sdm845_qhp_pcie_pcs_tbl, 1723 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1724 }, 1725 .clk_list = sdm845_pciephy_clk_l, 1726 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1727 .reset_list = sdm845_pciephy_reset_l, 1728 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1729 .vreg_list = qmp_phy_vreg_l, 1730 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1731 .regs = sdm845_qhp_pciephy_regs_layout, 1732 1733 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1734 .phy_status = PHYSTATUS, 1735 }; 1736 1737 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1738 .lanes = 1, 1739 1740 .tbls = { 1741 .serdes = sm8250_qmp_pcie_serdes_tbl, 1742 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1743 .tx = sm8250_qmp_pcie_tx_tbl, 1744 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1745 .rx = sm8250_qmp_pcie_rx_tbl, 1746 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1747 .pcs = sm8250_qmp_pcie_pcs_tbl, 1748 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1749 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1750 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1751 }, 1752 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1753 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1754 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1755 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1756 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1757 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1758 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1759 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1760 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1761 }, 1762 .clk_list = sdm845_pciephy_clk_l, 1763 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1764 .reset_list = sdm845_pciephy_reset_l, 1765 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1766 .vreg_list = qmp_phy_vreg_l, 1767 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1768 .regs = sm8250_pcie_regs_layout, 1769 1770 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1771 .phy_status = PHYSTATUS, 1772 }; 1773 1774 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1775 .lanes = 2, 1776 1777 .tbls = { 1778 .serdes = sm8250_qmp_pcie_serdes_tbl, 1779 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1780 .tx = sm8250_qmp_pcie_tx_tbl, 1781 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1782 .rx = sm8250_qmp_pcie_rx_tbl, 1783 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1784 .pcs = sm8250_qmp_pcie_pcs_tbl, 1785 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1786 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1787 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1788 }, 1789 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1790 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1791 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1792 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1793 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1794 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1795 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1796 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1797 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1798 }, 1799 .clk_list = sdm845_pciephy_clk_l, 1800 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1801 .reset_list = sdm845_pciephy_reset_l, 1802 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1803 .vreg_list = qmp_phy_vreg_l, 1804 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1805 .regs = sm8250_pcie_regs_layout, 1806 1807 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1808 .phy_status = PHYSTATUS, 1809 }; 1810 1811 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1812 .lanes = 1, 1813 1814 .tbls = { 1815 .serdes = msm8998_pcie_serdes_tbl, 1816 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1817 .tx = msm8998_pcie_tx_tbl, 1818 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1819 .rx = msm8998_pcie_rx_tbl, 1820 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1821 .pcs = msm8998_pcie_pcs_tbl, 1822 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1823 }, 1824 .clk_list = msm8996_phy_clk_l, 1825 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1826 .reset_list = ipq8074_pciephy_reset_l, 1827 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1828 .vreg_list = qmp_phy_vreg_l, 1829 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1830 .regs = pciephy_regs_layout, 1831 1832 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1833 .phy_status = PHYSTATUS, 1834 1835 .skip_start_delay = true, 1836 }; 1837 1838 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1839 .lanes = 1, 1840 1841 .tbls = { 1842 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1843 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1844 .tx = sc8180x_qmp_pcie_tx_tbl, 1845 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1846 .rx = sc8180x_qmp_pcie_rx_tbl, 1847 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1848 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1849 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1850 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1851 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1852 }, 1853 .clk_list = sdm845_pciephy_clk_l, 1854 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1855 .reset_list = sdm845_pciephy_reset_l, 1856 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1857 .vreg_list = qmp_phy_vreg_l, 1858 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1859 .regs = sm8250_pcie_regs_layout, 1860 1861 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1862 .phy_status = PHYSTATUS, 1863 }; 1864 1865 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 1866 .lanes = 1, 1867 1868 .offsets = &qmp_pcie_offsets_v5, 1869 1870 .tbls = { 1871 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1872 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1873 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 1874 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 1875 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 1876 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 1877 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 1878 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 1879 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 1880 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 1881 }, 1882 1883 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1884 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 1885 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 1886 }, 1887 1888 .clk_list = sc8280xp_pciephy_clk_l, 1889 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1890 .reset_list = sdm845_pciephy_reset_l, 1891 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1892 .vreg_list = qmp_phy_vreg_l, 1893 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1894 .regs = sm8250_pcie_regs_layout, 1895 1896 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1897 .phy_status = PHYSTATUS, 1898 }; 1899 1900 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 1901 .lanes = 2, 1902 1903 .offsets = &qmp_pcie_offsets_v5, 1904 1905 .tbls = { 1906 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1907 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1908 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1909 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1910 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1911 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1912 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1913 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1914 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1915 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1916 }, 1917 1918 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1919 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1920 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1921 }, 1922 1923 .clk_list = sc8280xp_pciephy_clk_l, 1924 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1925 .reset_list = sdm845_pciephy_reset_l, 1926 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1927 .vreg_list = qmp_phy_vreg_l, 1928 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1929 .regs = sm8250_pcie_regs_layout, 1930 1931 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1932 .phy_status = PHYSTATUS, 1933 }; 1934 1935 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1936 .lanes = 2, 1937 1938 .tbls = { 1939 .serdes = sdx55_qmp_pcie_serdes_tbl, 1940 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1941 .tx = sdx55_qmp_pcie_tx_tbl, 1942 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1943 .rx = sdx55_qmp_pcie_rx_tbl, 1944 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1945 .pcs = sdx55_qmp_pcie_pcs_tbl, 1946 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1947 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1948 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1949 }, 1950 .clk_list = sdm845_pciephy_clk_l, 1951 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1952 .reset_list = sdm845_pciephy_reset_l, 1953 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1954 .vreg_list = qmp_phy_vreg_l, 1955 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1956 .regs = sm8250_pcie_regs_layout, 1957 1958 .pwrdn_ctrl = SW_PWRDN, 1959 .phy_status = PHYSTATUS_4_20, 1960 }; 1961 1962 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1963 .lanes = 1, 1964 1965 .tbls = { 1966 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1967 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1968 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1969 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1970 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1971 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1972 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1973 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1974 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1975 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1976 }, 1977 .clk_list = sdm845_pciephy_clk_l, 1978 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1979 .reset_list = sdm845_pciephy_reset_l, 1980 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1981 .vreg_list = qmp_phy_vreg_l, 1982 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1983 .regs = sm8250_pcie_regs_layout, 1984 1985 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1986 .phy_status = PHYSTATUS, 1987 }; 1988 1989 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1990 .lanes = 2, 1991 1992 .tbls = { 1993 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1994 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1995 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1996 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1997 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1998 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1999 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2000 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2001 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2002 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 2003 }, 2004 2005 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2006 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 2007 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 2008 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 2009 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 2010 }, 2011 2012 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2013 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 2014 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 2015 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 2016 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 2017 }, 2018 2019 .clk_list = sdm845_pciephy_clk_l, 2020 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2021 .reset_list = sdm845_pciephy_reset_l, 2022 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2023 .vreg_list = qmp_phy_vreg_l, 2024 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2025 .regs = sm8250_pcie_regs_layout, 2026 2027 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2028 .phy_status = PHYSTATUS_4_20, 2029 }; 2030 2031 static void qmp_pcie_configure_lane(void __iomem *base, 2032 const struct qmp_phy_init_tbl tbl[], 2033 int num, 2034 u8 lane_mask) 2035 { 2036 int i; 2037 const struct qmp_phy_init_tbl *t = tbl; 2038 2039 if (!t) 2040 return; 2041 2042 for (i = 0; i < num; i++, t++) { 2043 if (!(t->lane_mask & lane_mask)) 2044 continue; 2045 2046 writel(t->val, base + t->offset); 2047 } 2048 } 2049 2050 static void qmp_pcie_configure(void __iomem *base, 2051 const struct qmp_phy_init_tbl tbl[], 2052 int num) 2053 { 2054 qmp_pcie_configure_lane(base, tbl, num, 0xff); 2055 } 2056 2057 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2058 { 2059 const struct qmp_phy_cfg *cfg = qmp->cfg; 2060 void __iomem *serdes = qmp->serdes; 2061 void __iomem *tx = qmp->tx; 2062 void __iomem *rx = qmp->rx; 2063 void __iomem *tx2 = qmp->tx2; 2064 void __iomem *rx2 = qmp->rx2; 2065 void __iomem *pcs = qmp->pcs; 2066 void __iomem *pcs_misc = qmp->pcs_misc; 2067 2068 if (!tbls) 2069 return; 2070 2071 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 2072 2073 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 2074 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 2075 2076 if (cfg->lanes >= 2) { 2077 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 2078 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 2079 } 2080 2081 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 2082 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 2083 } 2084 2085 static int qmp_pcie_init(struct phy *phy) 2086 { 2087 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2088 const struct qmp_phy_cfg *cfg = qmp->cfg; 2089 int ret; 2090 2091 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2092 if (ret) { 2093 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2094 return ret; 2095 } 2096 2097 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2098 if (ret) { 2099 dev_err(qmp->dev, "reset assert failed\n"); 2100 goto err_disable_regulators; 2101 } 2102 2103 usleep_range(200, 300); 2104 2105 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2106 if (ret) { 2107 dev_err(qmp->dev, "reset deassert failed\n"); 2108 goto err_disable_regulators; 2109 } 2110 2111 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2112 if (ret) 2113 goto err_assert_reset; 2114 2115 return 0; 2116 2117 err_assert_reset: 2118 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2119 err_disable_regulators: 2120 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2121 2122 return ret; 2123 } 2124 2125 static int qmp_pcie_exit(struct phy *phy) 2126 { 2127 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2128 const struct qmp_phy_cfg *cfg = qmp->cfg; 2129 2130 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2131 2132 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2133 2134 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2135 2136 return 0; 2137 } 2138 2139 static int qmp_pcie_power_on(struct phy *phy) 2140 { 2141 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2142 const struct qmp_phy_cfg *cfg = qmp->cfg; 2143 const struct qmp_phy_cfg_tbls *mode_tbls; 2144 void __iomem *pcs = qmp->pcs; 2145 void __iomem *status; 2146 unsigned int mask, val; 2147 int ret; 2148 2149 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2150 cfg->pwrdn_ctrl); 2151 2152 if (qmp->mode == PHY_MODE_PCIE_RC) 2153 mode_tbls = cfg->tbls_rc; 2154 else 2155 mode_tbls = cfg->tbls_ep; 2156 2157 qmp_pcie_init_registers(qmp, &cfg->tbls); 2158 qmp_pcie_init_registers(qmp, mode_tbls); 2159 2160 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 2161 if (ret) 2162 return ret; 2163 2164 /* Pull PHY out of reset state */ 2165 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2166 2167 /* start SerDes and Phy-Coding-Sublayer */ 2168 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2169 2170 if (!cfg->skip_start_delay) 2171 usleep_range(1000, 1200); 2172 2173 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2174 mask = cfg->phy_status; 2175 ret = readl_poll_timeout(status, val, !(val & mask), 200, 2176 PHY_INIT_COMPLETE_TIMEOUT); 2177 if (ret) { 2178 dev_err(qmp->dev, "phy initialization timed-out\n"); 2179 goto err_disable_pipe_clk; 2180 } 2181 2182 return 0; 2183 2184 err_disable_pipe_clk: 2185 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2186 2187 return ret; 2188 } 2189 2190 static int qmp_pcie_power_off(struct phy *phy) 2191 { 2192 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2193 const struct qmp_phy_cfg *cfg = qmp->cfg; 2194 2195 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2196 2197 /* PHY reset */ 2198 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2199 2200 /* stop SerDes and Phy-Coding-Sublayer */ 2201 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2202 SERDES_START | PCS_START); 2203 2204 /* Put PHY into POWER DOWN state: active low */ 2205 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2206 cfg->pwrdn_ctrl); 2207 2208 return 0; 2209 } 2210 2211 static int qmp_pcie_enable(struct phy *phy) 2212 { 2213 int ret; 2214 2215 ret = qmp_pcie_init(phy); 2216 if (ret) 2217 return ret; 2218 2219 ret = qmp_pcie_power_on(phy); 2220 if (ret) 2221 qmp_pcie_exit(phy); 2222 2223 return ret; 2224 } 2225 2226 static int qmp_pcie_disable(struct phy *phy) 2227 { 2228 int ret; 2229 2230 ret = qmp_pcie_power_off(phy); 2231 if (ret) 2232 return ret; 2233 2234 return qmp_pcie_exit(phy); 2235 } 2236 2237 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2238 { 2239 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2240 2241 switch (submode) { 2242 case PHY_MODE_PCIE_RC: 2243 case PHY_MODE_PCIE_EP: 2244 qmp->mode = submode; 2245 break; 2246 default: 2247 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2248 return -EINVAL; 2249 } 2250 2251 return 0; 2252 } 2253 2254 static const struct phy_ops qmp_pcie_phy_ops = { 2255 .power_on = qmp_pcie_enable, 2256 .power_off = qmp_pcie_disable, 2257 .set_mode = qmp_pcie_set_mode, 2258 .owner = THIS_MODULE, 2259 }; 2260 2261 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 2262 { 2263 const struct qmp_phy_cfg *cfg = qmp->cfg; 2264 struct device *dev = qmp->dev; 2265 int num = cfg->num_vregs; 2266 int i; 2267 2268 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2269 if (!qmp->vregs) 2270 return -ENOMEM; 2271 2272 for (i = 0; i < num; i++) 2273 qmp->vregs[i].supply = cfg->vreg_list[i]; 2274 2275 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2276 } 2277 2278 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 2279 { 2280 const struct qmp_phy_cfg *cfg = qmp->cfg; 2281 struct device *dev = qmp->dev; 2282 int i; 2283 int ret; 2284 2285 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2286 sizeof(*qmp->resets), GFP_KERNEL); 2287 if (!qmp->resets) 2288 return -ENOMEM; 2289 2290 for (i = 0; i < cfg->num_resets; i++) 2291 qmp->resets[i].id = cfg->reset_list[i]; 2292 2293 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2294 if (ret) 2295 return dev_err_probe(dev, ret, "failed to get resets\n"); 2296 2297 return 0; 2298 } 2299 2300 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 2301 { 2302 const struct qmp_phy_cfg *cfg = qmp->cfg; 2303 struct device *dev = qmp->dev; 2304 int num = cfg->num_clks; 2305 int i; 2306 2307 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2308 if (!qmp->clks) 2309 return -ENOMEM; 2310 2311 for (i = 0; i < num; i++) 2312 qmp->clks[i].id = cfg->clk_list[i]; 2313 2314 return devm_clk_bulk_get(dev, num, qmp->clks); 2315 } 2316 2317 static void phy_clk_release_provider(void *res) 2318 { 2319 of_clk_del_provider(res); 2320 } 2321 2322 /* 2323 * Register a fixed rate pipe clock. 2324 * 2325 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2326 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2327 * by the PHY driver for its operations. 2328 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2329 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2330 * Below picture shows this relationship. 2331 * 2332 * +---------------+ 2333 * | PHY block |<<---------------------------------------+ 2334 * | | | 2335 * | +-------+ | +-----+ | 2336 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2337 * clk | +-------+ | +-----+ 2338 * +---------------+ 2339 */ 2340 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2341 { 2342 struct clk_fixed_rate *fixed; 2343 struct clk_init_data init = { }; 2344 int ret; 2345 2346 ret = of_property_read_string(np, "clock-output-names", &init.name); 2347 if (ret) { 2348 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2349 return ret; 2350 } 2351 2352 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2353 if (!fixed) 2354 return -ENOMEM; 2355 2356 init.ops = &clk_fixed_rate_ops; 2357 2358 /* 2359 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2360 * unless other frequency is specified in the PHY config. 2361 */ 2362 if (qmp->cfg->pipe_clock_rate) 2363 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2364 else 2365 fixed->fixed_rate = 125000000; 2366 2367 fixed->hw.init = &init; 2368 2369 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2370 if (ret) 2371 return ret; 2372 2373 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2374 if (ret) 2375 return ret; 2376 2377 /* 2378 * Roll a devm action because the clock provider is the child node, but 2379 * the child node is not actually a device. 2380 */ 2381 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2382 } 2383 2384 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 2385 { 2386 struct platform_device *pdev = to_platform_device(qmp->dev); 2387 const struct qmp_phy_cfg *cfg = qmp->cfg; 2388 struct device *dev = qmp->dev; 2389 struct clk *clk; 2390 2391 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2392 if (IS_ERR(qmp->serdes)) 2393 return PTR_ERR(qmp->serdes); 2394 2395 /* 2396 * Get memory resources for the PHY: 2397 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2398 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2399 * For single lane PHYs: pcs_misc (optional) -> 3. 2400 */ 2401 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2402 if (IS_ERR(qmp->tx)) 2403 return PTR_ERR(qmp->tx); 2404 2405 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2406 qmp->rx = qmp->tx; 2407 else 2408 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2409 if (IS_ERR(qmp->rx)) 2410 return PTR_ERR(qmp->rx); 2411 2412 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2413 if (IS_ERR(qmp->pcs)) 2414 return PTR_ERR(qmp->pcs); 2415 2416 if (cfg->lanes >= 2) { 2417 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2418 if (IS_ERR(qmp->tx2)) 2419 return PTR_ERR(qmp->tx2); 2420 2421 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2422 if (IS_ERR(qmp->rx2)) 2423 return PTR_ERR(qmp->rx2); 2424 2425 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2426 } else { 2427 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2428 } 2429 2430 if (IS_ERR(qmp->pcs_misc) && 2431 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2432 qmp->pcs_misc = qmp->pcs + 0x400; 2433 2434 if (IS_ERR(qmp->pcs_misc)) { 2435 if (cfg->tbls.pcs_misc || 2436 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 2437 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 2438 return PTR_ERR(qmp->pcs_misc); 2439 } 2440 } 2441 2442 clk = devm_get_clk_from_child(dev, np, NULL); 2443 if (IS_ERR(clk)) { 2444 return dev_err_probe(dev, PTR_ERR(clk), 2445 "failed to get pipe clock\n"); 2446 } 2447 2448 qmp->num_pipe_clks = 1; 2449 qmp->pipe_clks[0].id = "pipe"; 2450 qmp->pipe_clks[0].clk = clk; 2451 2452 return 0; 2453 } 2454 2455 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 2456 { 2457 struct platform_device *pdev = to_platform_device(qmp->dev); 2458 const struct qmp_phy_cfg *cfg = qmp->cfg; 2459 const struct qmp_pcie_offsets *offs = cfg->offsets; 2460 struct device *dev = qmp->dev; 2461 void __iomem *base; 2462 int ret; 2463 2464 if (!offs) 2465 return -EINVAL; 2466 2467 base = devm_platform_ioremap_resource(pdev, 0); 2468 if (IS_ERR(base)) 2469 return PTR_ERR(base); 2470 2471 qmp->serdes = base + offs->serdes; 2472 qmp->pcs = base + offs->pcs; 2473 qmp->pcs_misc = base + offs->pcs_misc; 2474 qmp->tx = base + offs->tx; 2475 qmp->rx = base + offs->rx; 2476 2477 if (cfg->lanes >= 2) { 2478 qmp->tx2 = base + offs->tx2; 2479 qmp->rx2 = base + offs->rx2; 2480 } 2481 2482 qmp->num_pipe_clks = 2; 2483 qmp->pipe_clks[0].id = "pipe"; 2484 qmp->pipe_clks[1].id = "pipediv2"; 2485 2486 ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); 2487 if (ret) 2488 return ret; 2489 2490 return 0; 2491 } 2492 2493 static int qmp_pcie_probe(struct platform_device *pdev) 2494 { 2495 struct device *dev = &pdev->dev; 2496 struct phy_provider *phy_provider; 2497 struct device_node *np; 2498 struct qmp_pcie *qmp; 2499 int ret; 2500 2501 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2502 if (!qmp) 2503 return -ENOMEM; 2504 2505 qmp->dev = dev; 2506 2507 qmp->cfg = of_device_get_match_data(dev); 2508 if (!qmp->cfg) 2509 return -EINVAL; 2510 2511 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 2512 WARN_ON_ONCE(!qmp->cfg->phy_status); 2513 2514 ret = qmp_pcie_clk_init(qmp); 2515 if (ret) 2516 return ret; 2517 2518 ret = qmp_pcie_reset_init(qmp); 2519 if (ret) 2520 return ret; 2521 2522 ret = qmp_pcie_vreg_init(qmp); 2523 if (ret) 2524 return ret; 2525 2526 /* Check for legacy binding with child node. */ 2527 np = of_get_next_available_child(dev->of_node, NULL); 2528 if (np) { 2529 ret = qmp_pcie_parse_dt_legacy(qmp, np); 2530 } else { 2531 np = of_node_get(dev->of_node); 2532 ret = qmp_pcie_parse_dt(qmp); 2533 } 2534 if (ret) 2535 goto err_node_put; 2536 2537 ret = phy_pipe_clk_register(qmp, np); 2538 if (ret) 2539 goto err_node_put; 2540 2541 qmp->mode = PHY_MODE_PCIE_RC; 2542 2543 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 2544 if (IS_ERR(qmp->phy)) { 2545 ret = PTR_ERR(qmp->phy); 2546 dev_err(dev, "failed to create PHY: %d\n", ret); 2547 goto err_node_put; 2548 } 2549 2550 phy_set_drvdata(qmp->phy, qmp); 2551 2552 of_node_put(np); 2553 2554 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2555 2556 return PTR_ERR_OR_ZERO(phy_provider); 2557 2558 err_node_put: 2559 of_node_put(np); 2560 return ret; 2561 } 2562 2563 static const struct of_device_id qmp_pcie_of_match_table[] = { 2564 { 2565 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2566 .data = &ipq6018_pciephy_cfg, 2567 }, { 2568 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2569 .data = &ipq8074_pciephy_gen3_cfg, 2570 }, { 2571 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2572 .data = &ipq8074_pciephy_cfg, 2573 }, { 2574 .compatible = "qcom,msm8998-qmp-pcie-phy", 2575 .data = &msm8998_pciephy_cfg, 2576 }, { 2577 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2578 .data = &sc8180x_pciephy_cfg, 2579 }, { 2580 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 2581 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 2582 }, { 2583 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 2584 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 2585 }, { 2586 .compatible = "qcom,sdm845-qhp-pcie-phy", 2587 .data = &sdm845_qhp_pciephy_cfg, 2588 }, { 2589 .compatible = "qcom,sdm845-qmp-pcie-phy", 2590 .data = &sdm845_qmp_pciephy_cfg, 2591 }, { 2592 .compatible = "qcom,sdx55-qmp-pcie-phy", 2593 .data = &sdx55_qmp_pciephy_cfg, 2594 }, { 2595 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2596 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2597 }, { 2598 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2599 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2600 }, { 2601 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2602 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2603 }, { 2604 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2605 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2606 }, { 2607 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2608 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2609 }, 2610 { }, 2611 }; 2612 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2613 2614 static struct platform_driver qmp_pcie_driver = { 2615 .probe = qmp_pcie_probe, 2616 .driver = { 2617 .name = "qcom-qmp-pcie-phy", 2618 .of_match_table = qmp_pcie_of_match_table, 2619 }, 2620 }; 2621 2622 module_platform_driver(qmp_pcie_driver); 2623 2624 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2625 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2626 MODULE_LICENSE("GPL v2"); 2627