1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/phy/pcie.h> 19 #include <linux/phy/phy.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/reset.h> 24 #include <linux/slab.h> 25 26 #include <dt-bindings/phy/phy.h> 27 28 #include "phy-qcom-qmp.h" 29 30 /* QPHY_SW_RESET bit */ 31 #define SW_RESET BIT(0) 32 /* QPHY_POWER_DOWN_CONTROL */ 33 #define SW_PWRDN BIT(0) 34 #define REFCLK_DRV_DSBL BIT(1) 35 /* QPHY_START_CONTROL bits */ 36 #define SERDES_START BIT(0) 37 #define PCS_START BIT(1) 38 /* QPHY_PCS_STATUS bit */ 39 #define PHYSTATUS BIT(6) 40 #define PHYSTATUS_4_20 BIT(7) 41 42 #define PHY_INIT_COMPLETE_TIMEOUT 10000 43 44 struct qmp_phy_init_tbl { 45 unsigned int offset; 46 unsigned int val; 47 /* 48 * mask of lanes for which this register is written 49 * for cases when second lane needs different values 50 */ 51 u8 lane_mask; 52 }; 53 54 #define QMP_PHY_INIT_CFG(o, v) \ 55 { \ 56 .offset = o, \ 57 .val = v, \ 58 .lane_mask = 0xff, \ 59 } 60 61 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 62 { \ 63 .offset = o, \ 64 .val = v, \ 65 .lane_mask = l, \ 66 } 67 68 /* set of registers with offsets different per-PHY */ 69 enum qphy_reg_layout { 70 /* PCS registers */ 71 QPHY_SW_RESET, 72 QPHY_START_CTRL, 73 QPHY_PCS_STATUS, 74 QPHY_PCS_POWER_DOWN_CONTROL, 75 /* Keep last to ensure regs_layout arrays are properly initialized */ 76 QPHY_LAYOUT_SIZE 77 }; 78 79 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 80 [QPHY_SW_RESET] = 0x00, 81 [QPHY_START_CTRL] = 0x44, 82 [QPHY_PCS_STATUS] = 0x14, 83 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 84 }; 85 86 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 87 [QPHY_SW_RESET] = 0x00, 88 [QPHY_START_CTRL] = 0x08, 89 [QPHY_PCS_STATUS] = 0x174, 90 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 91 }; 92 93 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 94 [QPHY_SW_RESET] = 0x00, 95 [QPHY_START_CTRL] = 0x08, 96 [QPHY_PCS_STATUS] = 0x174, 97 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 98 }; 99 100 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 101 [QPHY_SW_RESET] = 0x00, 102 [QPHY_START_CTRL] = 0x08, 103 [QPHY_PCS_STATUS] = 0x2ac, 104 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 105 }; 106 107 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 108 [QPHY_SW_RESET] = 0x00, 109 [QPHY_START_CTRL] = 0x44, 110 [QPHY_PCS_STATUS] = 0x14, 111 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 112 }; 113 114 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 115 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 116 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 117 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 118 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 119 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 157 }; 158 159 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 160 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 161 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 162 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 163 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 164 }; 165 166 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 167 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 168 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 169 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 170 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 171 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 181 }; 182 183 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 194 }; 195 196 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 197 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 198 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 199 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 200 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 201 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 202 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 203 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 204 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 205 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 243 }; 244 245 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 246 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 247 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 248 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 249 }; 250 251 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 282 }; 283 284 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 288 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 289 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 292 }; 293 294 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 304 }; 305 306 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 307 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 308 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 309 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 310 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 311 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 312 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 313 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 314 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 316 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 317 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 318 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 319 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 320 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 321 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 322 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 323 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 324 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 325 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 326 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 328 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 329 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 330 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 331 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 332 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 333 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 334 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 335 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 336 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 337 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 338 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 341 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 344 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 346 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 347 }; 348 349 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 350 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 351 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 352 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 353 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 354 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 355 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 356 }; 357 358 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 359 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 360 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 361 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 362 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 363 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 364 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 365 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 366 }; 367 368 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 369 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 370 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 371 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 373 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 380 }; 381 382 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 383 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 384 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 385 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 386 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 387 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 388 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 389 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 390 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 391 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 392 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 393 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 440 }; 441 442 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 443 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 444 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 445 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 446 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 447 }; 448 449 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 450 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 451 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 452 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 453 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 454 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 480 }; 481 482 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 483 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 484 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 485 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 486 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 487 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 494 }; 495 496 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 510 }; 511 512 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 555 }; 556 557 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 558 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 559 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 560 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 561 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 562 }; 563 564 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 581 }; 582 583 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 585 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 591 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 599 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 603 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 605 }; 606 607 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 613 }; 614 615 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 616 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 617 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 618 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 619 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 620 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 661 }; 662 663 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 720 }; 721 722 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 723 }; 724 725 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 733 }; 734 735 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 778 }; 779 780 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 781 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 782 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 783 }; 784 785 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 822 }; 823 824 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 830 }; 831 832 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 840 }; 841 842 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = { 843 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00), 844 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9), 880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94), 882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 884 }; 885 886 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = { 887 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 888 }; 889 890 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = { 891 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 892 }; 893 894 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = { 895 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), 896 }; 897 898 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = { 899 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 900 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 901 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 902 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d), 903 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 904 }; 905 906 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = { 907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 925 }; 926 927 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = { 928 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 929 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 930 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 931 }; 932 933 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 934 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 935 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 936 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 937 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 938 }; 939 940 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = { 941 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1), 942 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2), 943 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5), 944 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 945 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 946 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 947 }; 948 949 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = { 950 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 951 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 952 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34), 954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 964 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 965 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 966 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 967 }; 968 969 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = { 970 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 971 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88), 972 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 973 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f), 974 }; 975 976 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 977 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), 978 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 979 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 980 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 981 }; 982 983 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 984 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 1025 }; 1026 1027 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 1029 }; 1030 1031 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 1032 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1035 }; 1036 1037 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 1038 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 1068 }; 1069 1070 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 1076 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 1077 }; 1078 1079 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1081 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 1083 }; 1084 1085 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 1086 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 1087 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 1088 }; 1089 1090 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 1091 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1092 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 1095 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 1096 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 1097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1098 }; 1099 1100 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1101 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1102 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 1103 }; 1104 1105 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 1106 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1107 }; 1108 1109 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 1110 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 1111 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 1112 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 1113 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1114 }; 1115 1116 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 1117 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 1118 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 1119 }; 1120 1121 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 1122 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 1123 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 1124 }; 1125 1126 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1127 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1128 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1143 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1144 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1145 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1166 }; 1167 1168 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1169 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1170 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1171 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1172 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1173 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1174 }; 1175 1176 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1177 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1178 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1179 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1180 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1181 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1182 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1183 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1184 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1185 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1186 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1187 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1188 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1189 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1190 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1191 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1192 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1193 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1194 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1195 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1196 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1197 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1198 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1199 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1200 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1201 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1202 }; 1203 1204 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1205 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1206 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1207 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1208 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1209 }; 1210 1211 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1212 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1213 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1214 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1215 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1216 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1217 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1218 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1219 }; 1220 1221 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1264 }; 1265 1266 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1267 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1272 }; 1273 1274 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1275 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1286 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1287 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1288 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1289 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1290 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1291 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1292 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1293 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1294 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1295 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1296 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1297 }; 1298 1299 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1300 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1301 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1302 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1303 }; 1304 1305 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1306 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1307 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1308 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1309 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1310 }; 1311 1312 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1326 }; 1327 1328 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1346 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1347 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1355 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1356 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1357 }; 1358 1359 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1364 }; 1365 1366 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1382 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1383 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1384 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1385 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1386 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1389 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1390 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1391 1392 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1393 1394 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1395 1396 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1402 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1403 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1404 1405 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1414 }; 1415 1416 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1417 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1418 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1419 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1420 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1421 }; 1422 1423 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1424 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1425 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1426 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1427 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1428 }; 1429 1430 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1431 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1432 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1433 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00), 1434 }; 1435 1436 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1448 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1449 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1450 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1451 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1452 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1455 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1456 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1457 }; 1458 1459 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1460 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1461 }; 1462 1463 struct qmp_pcie_offsets { 1464 u16 serdes; 1465 u16 pcs; 1466 u16 pcs_misc; 1467 u16 tx; 1468 u16 rx; 1469 u16 tx2; 1470 u16 rx2; 1471 }; 1472 1473 struct qmp_phy_cfg_tbls { 1474 const struct qmp_phy_init_tbl *serdes; 1475 int serdes_num; 1476 const struct qmp_phy_init_tbl *tx; 1477 int tx_num; 1478 const struct qmp_phy_init_tbl *rx; 1479 int rx_num; 1480 const struct qmp_phy_init_tbl *pcs; 1481 int pcs_num; 1482 const struct qmp_phy_init_tbl *pcs_misc; 1483 int pcs_misc_num; 1484 }; 1485 1486 /* struct qmp_phy_cfg - per-PHY initialization config */ 1487 struct qmp_phy_cfg { 1488 int lanes; 1489 1490 const struct qmp_pcie_offsets *offsets; 1491 1492 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1493 const struct qmp_phy_cfg_tbls tbls; 1494 /* 1495 * Additional init sequences for PHY blocks, providing additional 1496 * register programming. They are used for providing separate sequences 1497 * for the Root Complex and End Point use cases. 1498 * 1499 * If EP mode is not supported, both tables can be left unset. 1500 */ 1501 const struct qmp_phy_cfg_tbls *tbls_rc; 1502 const struct qmp_phy_cfg_tbls *tbls_ep; 1503 1504 const struct qmp_phy_init_tbl *serdes_4ln_tbl; 1505 int serdes_4ln_num; 1506 1507 /* clock ids to be requested */ 1508 const char * const *clk_list; 1509 int num_clks; 1510 /* resets to be requested */ 1511 const char * const *reset_list; 1512 int num_resets; 1513 /* regulators to be requested */ 1514 const char * const *vreg_list; 1515 int num_vregs; 1516 1517 /* array of registers with different offsets */ 1518 const unsigned int *regs; 1519 1520 unsigned int pwrdn_ctrl; 1521 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1522 unsigned int phy_status; 1523 1524 bool skip_start_delay; 1525 1526 /* QMP PHY pipe clock interface rate */ 1527 unsigned long pipe_clock_rate; 1528 }; 1529 1530 struct qmp_pcie { 1531 struct device *dev; 1532 1533 const struct qmp_phy_cfg *cfg; 1534 bool tcsr_4ln_config; 1535 1536 void __iomem *serdes; 1537 void __iomem *pcs; 1538 void __iomem *pcs_misc; 1539 void __iomem *tx; 1540 void __iomem *rx; 1541 void __iomem *tx2; 1542 void __iomem *rx2; 1543 1544 void __iomem *port_b; 1545 1546 struct clk_bulk_data *clks; 1547 struct clk_bulk_data pipe_clks[2]; 1548 int num_pipe_clks; 1549 1550 struct reset_control_bulk_data *resets; 1551 struct regulator_bulk_data *vregs; 1552 1553 struct phy *phy; 1554 int mode; 1555 }; 1556 1557 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1558 { 1559 u32 reg; 1560 1561 reg = readl(base + offset); 1562 reg |= val; 1563 writel(reg, base + offset); 1564 1565 /* ensure that above write is through */ 1566 readl(base + offset); 1567 } 1568 1569 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1570 { 1571 u32 reg; 1572 1573 reg = readl(base + offset); 1574 reg &= ~val; 1575 writel(reg, base + offset); 1576 1577 /* ensure that above write is through */ 1578 readl(base + offset); 1579 } 1580 1581 /* list of clocks required by phy */ 1582 static const char * const ipq8074_pciephy_clk_l[] = { 1583 "aux", "cfg_ahb", 1584 }; 1585 1586 static const char * const msm8996_phy_clk_l[] = { 1587 "aux", "cfg_ahb", "ref", 1588 }; 1589 1590 static const char * const sc8280xp_pciephy_clk_l[] = { 1591 "aux", "cfg_ahb", "ref", "rchng", 1592 }; 1593 1594 static const char * const sdm845_pciephy_clk_l[] = { 1595 "aux", "cfg_ahb", "ref", "refgen", 1596 }; 1597 1598 /* list of regulators */ 1599 static const char * const qmp_phy_vreg_l[] = { 1600 "vdda-phy", "vdda-pll", 1601 }; 1602 1603 /* list of resets */ 1604 static const char * const ipq8074_pciephy_reset_l[] = { 1605 "phy", "common", 1606 }; 1607 1608 static const char * const sdm845_pciephy_reset_l[] = { 1609 "phy", 1610 }; 1611 1612 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { 1613 .serdes = 0, 1614 .pcs = 0x0200, 1615 .pcs_misc = 0x0600, 1616 .tx = 0x0e00, 1617 .rx = 0x1000, 1618 .tx2 = 0x1600, 1619 .rx2 = 0x1800, 1620 }; 1621 1622 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1623 .lanes = 1, 1624 1625 .tbls = { 1626 .serdes = ipq8074_pcie_serdes_tbl, 1627 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1628 .tx = ipq8074_pcie_tx_tbl, 1629 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1630 .rx = ipq8074_pcie_rx_tbl, 1631 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1632 .pcs = ipq8074_pcie_pcs_tbl, 1633 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1634 }, 1635 .clk_list = ipq8074_pciephy_clk_l, 1636 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1637 .reset_list = ipq8074_pciephy_reset_l, 1638 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1639 .vreg_list = NULL, 1640 .num_vregs = 0, 1641 .regs = pciephy_regs_layout, 1642 1643 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1644 .phy_status = PHYSTATUS, 1645 }; 1646 1647 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1648 .lanes = 1, 1649 1650 .tbls = { 1651 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1652 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1653 .tx = ipq8074_pcie_gen3_tx_tbl, 1654 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1655 .rx = ipq8074_pcie_gen3_rx_tbl, 1656 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1657 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1658 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1659 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, 1660 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), 1661 }, 1662 .clk_list = ipq8074_pciephy_clk_l, 1663 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1664 .reset_list = ipq8074_pciephy_reset_l, 1665 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1666 .vreg_list = NULL, 1667 .num_vregs = 0, 1668 .regs = ipq_pciephy_gen3_regs_layout, 1669 1670 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1671 .phy_status = PHYSTATUS, 1672 1673 .pipe_clock_rate = 250000000, 1674 }; 1675 1676 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1677 .lanes = 1, 1678 1679 .tbls = { 1680 .serdes = ipq6018_pcie_serdes_tbl, 1681 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1682 .tx = ipq6018_pcie_tx_tbl, 1683 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1684 .rx = ipq6018_pcie_rx_tbl, 1685 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1686 .pcs = ipq6018_pcie_pcs_tbl, 1687 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1688 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1689 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1690 }, 1691 .clk_list = ipq8074_pciephy_clk_l, 1692 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1693 .reset_list = ipq8074_pciephy_reset_l, 1694 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1695 .vreg_list = NULL, 1696 .num_vregs = 0, 1697 .regs = ipq_pciephy_gen3_regs_layout, 1698 1699 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1700 .phy_status = PHYSTATUS, 1701 }; 1702 1703 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1704 .lanes = 1, 1705 1706 .tbls = { 1707 .serdes = sdm845_qmp_pcie_serdes_tbl, 1708 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1709 .tx = sdm845_qmp_pcie_tx_tbl, 1710 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1711 .rx = sdm845_qmp_pcie_rx_tbl, 1712 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1713 .pcs = sdm845_qmp_pcie_pcs_tbl, 1714 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1715 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1716 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1717 }, 1718 .clk_list = sdm845_pciephy_clk_l, 1719 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1720 .reset_list = sdm845_pciephy_reset_l, 1721 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1722 .vreg_list = qmp_phy_vreg_l, 1723 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1724 .regs = sdm845_qmp_pciephy_regs_layout, 1725 1726 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1727 .phy_status = PHYSTATUS, 1728 }; 1729 1730 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1731 .lanes = 1, 1732 1733 .tbls = { 1734 .serdes = sdm845_qhp_pcie_serdes_tbl, 1735 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1736 .tx = sdm845_qhp_pcie_tx_tbl, 1737 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1738 .rx = sdm845_qhp_pcie_rx_tbl, 1739 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1740 .pcs = sdm845_qhp_pcie_pcs_tbl, 1741 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1742 }, 1743 .clk_list = sdm845_pciephy_clk_l, 1744 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1745 .reset_list = sdm845_pciephy_reset_l, 1746 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1747 .vreg_list = qmp_phy_vreg_l, 1748 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1749 .regs = sdm845_qhp_pciephy_regs_layout, 1750 1751 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1752 .phy_status = PHYSTATUS, 1753 }; 1754 1755 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1756 .lanes = 1, 1757 1758 .tbls = { 1759 .serdes = sm8250_qmp_pcie_serdes_tbl, 1760 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1761 .tx = sm8250_qmp_pcie_tx_tbl, 1762 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1763 .rx = sm8250_qmp_pcie_rx_tbl, 1764 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1765 .pcs = sm8250_qmp_pcie_pcs_tbl, 1766 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1767 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1768 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1769 }, 1770 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1771 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1772 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1773 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1774 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1775 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1776 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1777 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1778 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1779 }, 1780 .clk_list = sdm845_pciephy_clk_l, 1781 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1782 .reset_list = sdm845_pciephy_reset_l, 1783 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1784 .vreg_list = qmp_phy_vreg_l, 1785 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1786 .regs = sm8250_pcie_regs_layout, 1787 1788 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1789 .phy_status = PHYSTATUS, 1790 }; 1791 1792 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1793 .lanes = 2, 1794 1795 .tbls = { 1796 .serdes = sm8250_qmp_pcie_serdes_tbl, 1797 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1798 .tx = sm8250_qmp_pcie_tx_tbl, 1799 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1800 .rx = sm8250_qmp_pcie_rx_tbl, 1801 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1802 .pcs = sm8250_qmp_pcie_pcs_tbl, 1803 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1804 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1805 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1806 }, 1807 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1808 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1809 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1810 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1811 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1812 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1813 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1814 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1815 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1816 }, 1817 .clk_list = sdm845_pciephy_clk_l, 1818 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1819 .reset_list = sdm845_pciephy_reset_l, 1820 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1821 .vreg_list = qmp_phy_vreg_l, 1822 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1823 .regs = sm8250_pcie_regs_layout, 1824 1825 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1826 .phy_status = PHYSTATUS, 1827 }; 1828 1829 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1830 .lanes = 1, 1831 1832 .tbls = { 1833 .serdes = msm8998_pcie_serdes_tbl, 1834 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1835 .tx = msm8998_pcie_tx_tbl, 1836 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1837 .rx = msm8998_pcie_rx_tbl, 1838 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1839 .pcs = msm8998_pcie_pcs_tbl, 1840 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1841 }, 1842 .clk_list = msm8996_phy_clk_l, 1843 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1844 .reset_list = ipq8074_pciephy_reset_l, 1845 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1846 .vreg_list = qmp_phy_vreg_l, 1847 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1848 .regs = pciephy_regs_layout, 1849 1850 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1851 .phy_status = PHYSTATUS, 1852 1853 .skip_start_delay = true, 1854 }; 1855 1856 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1857 .lanes = 1, 1858 1859 .tbls = { 1860 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1861 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1862 .tx = sc8180x_qmp_pcie_tx_tbl, 1863 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1864 .rx = sc8180x_qmp_pcie_rx_tbl, 1865 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1866 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1867 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1868 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1869 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1870 }, 1871 .clk_list = sdm845_pciephy_clk_l, 1872 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1873 .reset_list = sdm845_pciephy_reset_l, 1874 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1875 .vreg_list = qmp_phy_vreg_l, 1876 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1877 .regs = sm8250_pcie_regs_layout, 1878 1879 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1880 .phy_status = PHYSTATUS, 1881 }; 1882 1883 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { 1884 .lanes = 1, 1885 1886 .offsets = &qmp_pcie_offsets_v5, 1887 1888 .tbls = { 1889 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1890 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1891 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl, 1892 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl), 1893 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl, 1894 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl), 1895 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl, 1896 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl), 1897 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl, 1898 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl), 1899 }, 1900 1901 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1902 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl, 1903 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), 1904 }, 1905 1906 .clk_list = sc8280xp_pciephy_clk_l, 1907 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1908 .reset_list = sdm845_pciephy_reset_l, 1909 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1910 .vreg_list = qmp_phy_vreg_l, 1911 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1912 .regs = sm8250_pcie_regs_layout, 1913 1914 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1915 .phy_status = PHYSTATUS, 1916 }; 1917 1918 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { 1919 .lanes = 2, 1920 1921 .offsets = &qmp_pcie_offsets_v5, 1922 1923 .tbls = { 1924 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1925 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1926 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1927 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1928 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1929 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1930 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1931 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1932 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1933 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1934 }, 1935 1936 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1937 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1938 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1939 }, 1940 1941 .clk_list = sc8280xp_pciephy_clk_l, 1942 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1943 .reset_list = sdm845_pciephy_reset_l, 1944 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1945 .vreg_list = qmp_phy_vreg_l, 1946 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1947 .regs = sm8250_pcie_regs_layout, 1948 1949 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1950 .phy_status = PHYSTATUS, 1951 }; 1952 1953 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { 1954 .lanes = 4, 1955 1956 .offsets = &qmp_pcie_offsets_v5, 1957 1958 .tbls = { 1959 .serdes = sc8280xp_qmp_pcie_serdes_tbl, 1960 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl), 1961 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl, 1962 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl), 1963 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl, 1964 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl), 1965 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl, 1966 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl), 1967 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl, 1968 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl), 1969 }, 1970 1971 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 1972 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl, 1973 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), 1974 }, 1975 1976 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, 1977 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), 1978 1979 .clk_list = sc8280xp_pciephy_clk_l, 1980 .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), 1981 .reset_list = sdm845_pciephy_reset_l, 1982 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1983 .vreg_list = qmp_phy_vreg_l, 1984 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1985 .regs = sm8250_pcie_regs_layout, 1986 1987 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1988 .phy_status = PHYSTATUS, 1989 }; 1990 1991 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1992 .lanes = 2, 1993 1994 .tbls = { 1995 .serdes = sdx55_qmp_pcie_serdes_tbl, 1996 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1997 .tx = sdx55_qmp_pcie_tx_tbl, 1998 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1999 .rx = sdx55_qmp_pcie_rx_tbl, 2000 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 2001 .pcs = sdx55_qmp_pcie_pcs_tbl, 2002 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 2003 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 2004 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 2005 }, 2006 .clk_list = sdm845_pciephy_clk_l, 2007 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2008 .reset_list = sdm845_pciephy_reset_l, 2009 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2010 .vreg_list = qmp_phy_vreg_l, 2011 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2012 .regs = sm8250_pcie_regs_layout, 2013 2014 .pwrdn_ctrl = SW_PWRDN, 2015 .phy_status = PHYSTATUS_4_20, 2016 }; 2017 2018 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 2019 .lanes = 1, 2020 2021 .tbls = { 2022 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 2023 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 2024 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 2025 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 2026 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 2027 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 2028 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 2029 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 2030 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 2031 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 2032 }, 2033 .clk_list = sdm845_pciephy_clk_l, 2034 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2035 .reset_list = sdm845_pciephy_reset_l, 2036 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2037 .vreg_list = qmp_phy_vreg_l, 2038 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2039 .regs = sm8250_pcie_regs_layout, 2040 2041 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2042 .phy_status = PHYSTATUS, 2043 }; 2044 2045 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 2046 .lanes = 2, 2047 2048 .tbls = { 2049 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 2050 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 2051 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 2052 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 2053 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 2054 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 2055 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 2056 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 2057 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 2058 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 2059 }, 2060 2061 .tbls_rc = &(const struct qmp_phy_cfg_tbls) { 2062 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 2063 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 2064 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 2065 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 2066 }, 2067 2068 .tbls_ep = &(const struct qmp_phy_cfg_tbls) { 2069 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 2070 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 2071 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 2072 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 2073 }, 2074 2075 .clk_list = sdm845_pciephy_clk_l, 2076 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 2077 .reset_list = sdm845_pciephy_reset_l, 2078 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 2079 .vreg_list = qmp_phy_vreg_l, 2080 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2081 .regs = sm8250_pcie_regs_layout, 2082 2083 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 2084 .phy_status = PHYSTATUS_4_20, 2085 }; 2086 2087 static void qmp_pcie_configure_lane(void __iomem *base, 2088 const struct qmp_phy_init_tbl tbl[], 2089 int num, 2090 u8 lane_mask) 2091 { 2092 int i; 2093 const struct qmp_phy_init_tbl *t = tbl; 2094 2095 if (!t) 2096 return; 2097 2098 for (i = 0; i < num; i++, t++) { 2099 if (!(t->lane_mask & lane_mask)) 2100 continue; 2101 2102 writel(t->val, base + t->offset); 2103 } 2104 } 2105 2106 static void qmp_pcie_configure(void __iomem *base, 2107 const struct qmp_phy_init_tbl tbl[], 2108 int num) 2109 { 2110 qmp_pcie_configure_lane(base, tbl, num, 0xff); 2111 } 2112 2113 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2114 { 2115 const struct qmp_phy_cfg *cfg = qmp->cfg; 2116 const struct qmp_pcie_offsets *offs = cfg->offsets; 2117 void __iomem *tx3, *rx3, *tx4, *rx4; 2118 2119 tx3 = qmp->port_b + offs->tx; 2120 rx3 = qmp->port_b + offs->rx; 2121 tx4 = qmp->port_b + offs->tx2; 2122 rx4 = qmp->port_b + offs->rx2; 2123 2124 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1); 2125 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1); 2126 2127 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2); 2128 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2); 2129 } 2130 2131 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) 2132 { 2133 const struct qmp_phy_cfg *cfg = qmp->cfg; 2134 void __iomem *serdes = qmp->serdes; 2135 void __iomem *tx = qmp->tx; 2136 void __iomem *rx = qmp->rx; 2137 void __iomem *tx2 = qmp->tx2; 2138 void __iomem *rx2 = qmp->rx2; 2139 void __iomem *pcs = qmp->pcs; 2140 void __iomem *pcs_misc = qmp->pcs_misc; 2141 2142 if (!tbls) 2143 return; 2144 2145 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num); 2146 2147 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1); 2148 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1); 2149 2150 if (cfg->lanes >= 2) { 2151 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2); 2152 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2); 2153 } 2154 2155 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); 2156 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); 2157 2158 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2159 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); 2160 qmp_pcie_init_port_b(qmp, tbls); 2161 } 2162 } 2163 2164 static int qmp_pcie_init(struct phy *phy) 2165 { 2166 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2167 const struct qmp_phy_cfg *cfg = qmp->cfg; 2168 int ret; 2169 2170 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2171 if (ret) { 2172 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2173 return ret; 2174 } 2175 2176 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2177 if (ret) { 2178 dev_err(qmp->dev, "reset assert failed\n"); 2179 goto err_disable_regulators; 2180 } 2181 2182 usleep_range(200, 300); 2183 2184 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2185 if (ret) { 2186 dev_err(qmp->dev, "reset deassert failed\n"); 2187 goto err_disable_regulators; 2188 } 2189 2190 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2191 if (ret) 2192 goto err_assert_reset; 2193 2194 return 0; 2195 2196 err_assert_reset: 2197 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2198 err_disable_regulators: 2199 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2200 2201 return ret; 2202 } 2203 2204 static int qmp_pcie_exit(struct phy *phy) 2205 { 2206 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2207 const struct qmp_phy_cfg *cfg = qmp->cfg; 2208 2209 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2210 2211 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2212 2213 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2214 2215 return 0; 2216 } 2217 2218 static int qmp_pcie_power_on(struct phy *phy) 2219 { 2220 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2221 const struct qmp_phy_cfg *cfg = qmp->cfg; 2222 const struct qmp_phy_cfg_tbls *mode_tbls; 2223 void __iomem *pcs = qmp->pcs; 2224 void __iomem *status; 2225 unsigned int mask, val; 2226 int ret; 2227 2228 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2229 cfg->pwrdn_ctrl); 2230 2231 if (qmp->mode == PHY_MODE_PCIE_RC) 2232 mode_tbls = cfg->tbls_rc; 2233 else 2234 mode_tbls = cfg->tbls_ep; 2235 2236 qmp_pcie_init_registers(qmp, &cfg->tbls); 2237 qmp_pcie_init_registers(qmp, mode_tbls); 2238 2239 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); 2240 if (ret) 2241 return ret; 2242 2243 /* Pull PHY out of reset state */ 2244 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2245 2246 /* start SerDes and Phy-Coding-Sublayer */ 2247 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2248 2249 if (!cfg->skip_start_delay) 2250 usleep_range(1000, 1200); 2251 2252 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2253 mask = cfg->phy_status; 2254 ret = readl_poll_timeout(status, val, !(val & mask), 200, 2255 PHY_INIT_COMPLETE_TIMEOUT); 2256 if (ret) { 2257 dev_err(qmp->dev, "phy initialization timed-out\n"); 2258 goto err_disable_pipe_clk; 2259 } 2260 2261 return 0; 2262 2263 err_disable_pipe_clk: 2264 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2265 2266 return ret; 2267 } 2268 2269 static int qmp_pcie_power_off(struct phy *phy) 2270 { 2271 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2272 const struct qmp_phy_cfg *cfg = qmp->cfg; 2273 2274 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); 2275 2276 /* PHY reset */ 2277 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2278 2279 /* stop SerDes and Phy-Coding-Sublayer */ 2280 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2281 SERDES_START | PCS_START); 2282 2283 /* Put PHY into POWER DOWN state: active low */ 2284 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2285 cfg->pwrdn_ctrl); 2286 2287 return 0; 2288 } 2289 2290 static int qmp_pcie_enable(struct phy *phy) 2291 { 2292 int ret; 2293 2294 ret = qmp_pcie_init(phy); 2295 if (ret) 2296 return ret; 2297 2298 ret = qmp_pcie_power_on(phy); 2299 if (ret) 2300 qmp_pcie_exit(phy); 2301 2302 return ret; 2303 } 2304 2305 static int qmp_pcie_disable(struct phy *phy) 2306 { 2307 int ret; 2308 2309 ret = qmp_pcie_power_off(phy); 2310 if (ret) 2311 return ret; 2312 2313 return qmp_pcie_exit(phy); 2314 } 2315 2316 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2317 { 2318 struct qmp_pcie *qmp = phy_get_drvdata(phy); 2319 2320 switch (submode) { 2321 case PHY_MODE_PCIE_RC: 2322 case PHY_MODE_PCIE_EP: 2323 qmp->mode = submode; 2324 break; 2325 default: 2326 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2327 return -EINVAL; 2328 } 2329 2330 return 0; 2331 } 2332 2333 static const struct phy_ops qmp_pcie_phy_ops = { 2334 .power_on = qmp_pcie_enable, 2335 .power_off = qmp_pcie_disable, 2336 .set_mode = qmp_pcie_set_mode, 2337 .owner = THIS_MODULE, 2338 }; 2339 2340 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp) 2341 { 2342 const struct qmp_phy_cfg *cfg = qmp->cfg; 2343 struct device *dev = qmp->dev; 2344 int num = cfg->num_vregs; 2345 int i; 2346 2347 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2348 if (!qmp->vregs) 2349 return -ENOMEM; 2350 2351 for (i = 0; i < num; i++) 2352 qmp->vregs[i].supply = cfg->vreg_list[i]; 2353 2354 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2355 } 2356 2357 static int qmp_pcie_reset_init(struct qmp_pcie *qmp) 2358 { 2359 const struct qmp_phy_cfg *cfg = qmp->cfg; 2360 struct device *dev = qmp->dev; 2361 int i; 2362 int ret; 2363 2364 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2365 sizeof(*qmp->resets), GFP_KERNEL); 2366 if (!qmp->resets) 2367 return -ENOMEM; 2368 2369 for (i = 0; i < cfg->num_resets; i++) 2370 qmp->resets[i].id = cfg->reset_list[i]; 2371 2372 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2373 if (ret) 2374 return dev_err_probe(dev, ret, "failed to get resets\n"); 2375 2376 return 0; 2377 } 2378 2379 static int qmp_pcie_clk_init(struct qmp_pcie *qmp) 2380 { 2381 const struct qmp_phy_cfg *cfg = qmp->cfg; 2382 struct device *dev = qmp->dev; 2383 int num = cfg->num_clks; 2384 int i; 2385 2386 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2387 if (!qmp->clks) 2388 return -ENOMEM; 2389 2390 for (i = 0; i < num; i++) 2391 qmp->clks[i].id = cfg->clk_list[i]; 2392 2393 return devm_clk_bulk_get(dev, num, qmp->clks); 2394 } 2395 2396 static void phy_clk_release_provider(void *res) 2397 { 2398 of_clk_del_provider(res); 2399 } 2400 2401 /* 2402 * Register a fixed rate pipe clock. 2403 * 2404 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2405 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2406 * by the PHY driver for its operations. 2407 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2408 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2409 * Below picture shows this relationship. 2410 * 2411 * +---------------+ 2412 * | PHY block |<<---------------------------------------+ 2413 * | | | 2414 * | +-------+ | +-----+ | 2415 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2416 * clk | +-------+ | +-----+ 2417 * +---------------+ 2418 */ 2419 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) 2420 { 2421 struct clk_fixed_rate *fixed; 2422 struct clk_init_data init = { }; 2423 int ret; 2424 2425 ret = of_property_read_string(np, "clock-output-names", &init.name); 2426 if (ret) { 2427 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2428 return ret; 2429 } 2430 2431 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2432 if (!fixed) 2433 return -ENOMEM; 2434 2435 init.ops = &clk_fixed_rate_ops; 2436 2437 /* 2438 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2439 * unless other frequency is specified in the PHY config. 2440 */ 2441 if (qmp->cfg->pipe_clock_rate) 2442 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; 2443 else 2444 fixed->fixed_rate = 125000000; 2445 2446 fixed->hw.init = &init; 2447 2448 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2449 if (ret) 2450 return ret; 2451 2452 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2453 if (ret) 2454 return ret; 2455 2456 /* 2457 * Roll a devm action because the clock provider is the child node, but 2458 * the child node is not actually a device. 2459 */ 2460 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2461 } 2462 2463 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np) 2464 { 2465 struct platform_device *pdev = to_platform_device(qmp->dev); 2466 const struct qmp_phy_cfg *cfg = qmp->cfg; 2467 struct device *dev = qmp->dev; 2468 struct clk *clk; 2469 2470 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2471 if (IS_ERR(qmp->serdes)) 2472 return PTR_ERR(qmp->serdes); 2473 2474 /* 2475 * Get memory resources for the PHY: 2476 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2477 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2478 * For single lane PHYs: pcs_misc (optional) -> 3. 2479 */ 2480 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2481 if (IS_ERR(qmp->tx)) 2482 return PTR_ERR(qmp->tx); 2483 2484 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2485 qmp->rx = qmp->tx; 2486 else 2487 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2488 if (IS_ERR(qmp->rx)) 2489 return PTR_ERR(qmp->rx); 2490 2491 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2492 if (IS_ERR(qmp->pcs)) 2493 return PTR_ERR(qmp->pcs); 2494 2495 if (cfg->lanes >= 2) { 2496 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2497 if (IS_ERR(qmp->tx2)) 2498 return PTR_ERR(qmp->tx2); 2499 2500 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2501 if (IS_ERR(qmp->rx2)) 2502 return PTR_ERR(qmp->rx2); 2503 2504 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2505 } else { 2506 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2507 } 2508 2509 if (IS_ERR(qmp->pcs_misc) && 2510 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2511 qmp->pcs_misc = qmp->pcs + 0x400; 2512 2513 if (IS_ERR(qmp->pcs_misc)) { 2514 if (cfg->tbls.pcs_misc || 2515 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || 2516 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { 2517 return PTR_ERR(qmp->pcs_misc); 2518 } 2519 } 2520 2521 clk = devm_get_clk_from_child(dev, np, NULL); 2522 if (IS_ERR(clk)) { 2523 return dev_err_probe(dev, PTR_ERR(clk), 2524 "failed to get pipe clock\n"); 2525 } 2526 2527 qmp->num_pipe_clks = 1; 2528 qmp->pipe_clks[0].id = "pipe"; 2529 qmp->pipe_clks[0].clk = clk; 2530 2531 return 0; 2532 } 2533 2534 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) 2535 { 2536 struct regmap *tcsr; 2537 unsigned int args[2]; 2538 int ret; 2539 2540 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, 2541 "qcom,4ln-config-sel", 2542 ARRAY_SIZE(args), args); 2543 if (IS_ERR(tcsr)) { 2544 ret = PTR_ERR(tcsr); 2545 if (ret == -ENOENT) 2546 return 0; 2547 2548 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); 2549 return ret; 2550 } 2551 2552 ret = regmap_test_bits(tcsr, args[0], BIT(args[1])); 2553 if (ret < 0) { 2554 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); 2555 return ret; 2556 } 2557 2558 qmp->tcsr_4ln_config = ret; 2559 2560 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); 2561 2562 return 0; 2563 } 2564 2565 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) 2566 { 2567 struct platform_device *pdev = to_platform_device(qmp->dev); 2568 const struct qmp_phy_cfg *cfg = qmp->cfg; 2569 const struct qmp_pcie_offsets *offs = cfg->offsets; 2570 struct device *dev = qmp->dev; 2571 void __iomem *base; 2572 int ret; 2573 2574 if (!offs) 2575 return -EINVAL; 2576 2577 ret = qmp_pcie_get_4ln_config(qmp); 2578 if (ret) 2579 return ret; 2580 2581 base = devm_platform_ioremap_resource(pdev, 0); 2582 if (IS_ERR(base)) 2583 return PTR_ERR(base); 2584 2585 qmp->serdes = base + offs->serdes; 2586 qmp->pcs = base + offs->pcs; 2587 qmp->pcs_misc = base + offs->pcs_misc; 2588 qmp->tx = base + offs->tx; 2589 qmp->rx = base + offs->rx; 2590 2591 if (cfg->lanes >= 2) { 2592 qmp->tx2 = base + offs->tx2; 2593 qmp->rx2 = base + offs->rx2; 2594 } 2595 2596 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { 2597 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); 2598 if (IS_ERR(qmp->port_b)) 2599 return PTR_ERR(qmp->port_b); 2600 } 2601 2602 qmp->num_pipe_clks = 2; 2603 qmp->pipe_clks[0].id = "pipe"; 2604 qmp->pipe_clks[1].id = "pipediv2"; 2605 2606 ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks); 2607 if (ret) 2608 return ret; 2609 2610 return 0; 2611 } 2612 2613 static int qmp_pcie_probe(struct platform_device *pdev) 2614 { 2615 struct device *dev = &pdev->dev; 2616 struct phy_provider *phy_provider; 2617 struct device_node *np; 2618 struct qmp_pcie *qmp; 2619 int ret; 2620 2621 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2622 if (!qmp) 2623 return -ENOMEM; 2624 2625 qmp->dev = dev; 2626 2627 qmp->cfg = of_device_get_match_data(dev); 2628 if (!qmp->cfg) 2629 return -EINVAL; 2630 2631 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); 2632 WARN_ON_ONCE(!qmp->cfg->phy_status); 2633 2634 ret = qmp_pcie_clk_init(qmp); 2635 if (ret) 2636 return ret; 2637 2638 ret = qmp_pcie_reset_init(qmp); 2639 if (ret) 2640 return ret; 2641 2642 ret = qmp_pcie_vreg_init(qmp); 2643 if (ret) 2644 return ret; 2645 2646 /* Check for legacy binding with child node. */ 2647 np = of_get_next_available_child(dev->of_node, NULL); 2648 if (np) { 2649 ret = qmp_pcie_parse_dt_legacy(qmp, np); 2650 } else { 2651 np = of_node_get(dev->of_node); 2652 ret = qmp_pcie_parse_dt(qmp); 2653 } 2654 if (ret) 2655 goto err_node_put; 2656 2657 ret = phy_pipe_clk_register(qmp, np); 2658 if (ret) 2659 goto err_node_put; 2660 2661 qmp->mode = PHY_MODE_PCIE_RC; 2662 2663 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); 2664 if (IS_ERR(qmp->phy)) { 2665 ret = PTR_ERR(qmp->phy); 2666 dev_err(dev, "failed to create PHY: %d\n", ret); 2667 goto err_node_put; 2668 } 2669 2670 phy_set_drvdata(qmp->phy, qmp); 2671 2672 of_node_put(np); 2673 2674 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2675 2676 return PTR_ERR_OR_ZERO(phy_provider); 2677 2678 err_node_put: 2679 of_node_put(np); 2680 return ret; 2681 } 2682 2683 static const struct of_device_id qmp_pcie_of_match_table[] = { 2684 { 2685 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2686 .data = &ipq6018_pciephy_cfg, 2687 }, { 2688 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2689 .data = &ipq8074_pciephy_gen3_cfg, 2690 }, { 2691 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2692 .data = &ipq8074_pciephy_cfg, 2693 }, { 2694 .compatible = "qcom,msm8998-qmp-pcie-phy", 2695 .data = &msm8998_pciephy_cfg, 2696 }, { 2697 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2698 .data = &sc8180x_pciephy_cfg, 2699 }, { 2700 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy", 2701 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg, 2702 }, { 2703 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy", 2704 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg, 2705 }, { 2706 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy", 2707 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg, 2708 }, { 2709 .compatible = "qcom,sdm845-qhp-pcie-phy", 2710 .data = &sdm845_qhp_pciephy_cfg, 2711 }, { 2712 .compatible = "qcom,sdm845-qmp-pcie-phy", 2713 .data = &sdm845_qmp_pciephy_cfg, 2714 }, { 2715 .compatible = "qcom,sdx55-qmp-pcie-phy", 2716 .data = &sdx55_qmp_pciephy_cfg, 2717 }, { 2718 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2719 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2720 }, { 2721 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2722 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2723 }, { 2724 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2725 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2726 }, { 2727 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2728 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2729 }, { 2730 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2731 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2732 }, 2733 { }, 2734 }; 2735 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2736 2737 static struct platform_driver qmp_pcie_driver = { 2738 .probe = qmp_pcie_probe, 2739 .driver = { 2740 .name = "qcom-qmp-pcie-phy", 2741 .of_match_table = qmp_pcie_of_match_table, 2742 }, 2743 }; 2744 2745 module_platform_driver(qmp_pcie_driver); 2746 2747 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2748 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2749 MODULE_LICENSE("GPL v2"); 2750