1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/phy/phy.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * register part of layout ? 47 * if yes, then offset gives index in the reg-layout 48 */ 49 bool in_layout; 50 /* 51 * mask of lanes for which this register is written 52 * for cases when second lane needs different values 53 */ 54 u8 lane_mask; 55 }; 56 57 #define QMP_PHY_INIT_CFG(o, v) \ 58 { \ 59 .offset = o, \ 60 .val = v, \ 61 .lane_mask = 0xff, \ 62 } 63 64 #define QMP_PHY_INIT_CFG_L(o, v) \ 65 { \ 66 .offset = o, \ 67 .val = v, \ 68 .in_layout = true, \ 69 .lane_mask = 0xff, \ 70 } 71 72 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 73 { \ 74 .offset = o, \ 75 .val = v, \ 76 .lane_mask = l, \ 77 } 78 79 /* set of registers with offsets different per-PHY */ 80 enum qphy_reg_layout { 81 /* PCS registers */ 82 QPHY_SW_RESET, 83 QPHY_START_CTRL, 84 QPHY_PCS_STATUS, 85 QPHY_PCS_POWER_DOWN_CONTROL, 86 /* Keep last to ensure regs_layout arrays are properly initialized */ 87 QPHY_LAYOUT_SIZE 88 }; 89 90 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 91 [QPHY_SW_RESET] = 0x00, 92 [QPHY_START_CTRL] = 0x44, 93 [QPHY_PCS_STATUS] = 0x14, 94 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 95 }; 96 97 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 98 [QPHY_SW_RESET] = 0x00, 99 [QPHY_START_CTRL] = 0x08, 100 [QPHY_PCS_STATUS] = 0x174, 101 }; 102 103 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 104 [QPHY_SW_RESET] = 0x00, 105 [QPHY_START_CTRL] = 0x08, 106 [QPHY_PCS_STATUS] = 0x174, 107 }; 108 109 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 110 [QPHY_SW_RESET] = 0x00, 111 [QPHY_START_CTRL] = 0x08, 112 [QPHY_PCS_STATUS] = 0x2ac, 113 }; 114 115 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 116 [QPHY_SW_RESET] = 0x00, 117 [QPHY_START_CTRL] = 0x44, 118 [QPHY_PCS_STATUS] = 0x14, 119 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 120 }; 121 122 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 165 }; 166 167 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 169 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 170 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 171 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 172 }; 173 174 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 187 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 189 }; 190 191 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 202 }; 203 204 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 205 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 206 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 207 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 208 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 249 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 250 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 251 }; 252 253 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 254 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 255 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 256 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 257 }; 258 259 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 290 }; 291 292 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 300 }; 301 302 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 309 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 310 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 311 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 312 }; 313 314 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 315 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 316 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 317 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 318 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 319 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 320 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 321 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 322 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 323 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 324 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 325 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 326 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 327 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 328 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 329 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 331 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 332 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 333 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 334 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 335 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 336 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 337 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 338 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 340 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 341 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 342 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 343 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 344 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 345 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 346 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 352 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 353 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 354 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 355 }; 356 357 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 358 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 359 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 360 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 361 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 362 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 363 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 367 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 368 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 369 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 370 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 371 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 372 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 373 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 374 }; 375 376 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 380 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 381 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 382 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 383 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 386 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 387 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 388 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 389 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 390 }; 391 392 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 393 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 394 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 395 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 396 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 446 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 447 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 448 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 449 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 450 }; 451 452 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 453 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 454 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 455 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 456 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 457 }; 458 459 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 490 }; 491 492 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 517 }; 518 519 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 562 }; 563 564 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 565 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 566 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 567 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 568 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 569 }; 570 571 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 587 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 588 }; 589 590 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 592 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 598 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 606 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 610 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 612 }; 613 614 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 620 }; 621 622 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 668 }; 669 670 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 727 }; 728 729 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 730 }; 731 732 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 736 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 737 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 738 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 739 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 740 }; 741 742 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 785 }; 786 787 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 788 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 789 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 790 }; 791 792 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 829 }; 830 831 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 834 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 837 }; 838 839 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 845 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 846 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 847 }; 848 849 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 891 }; 892 893 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 895 }; 896 897 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 898 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 899 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 900 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 901 }; 902 903 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 904 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 905 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 906 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 934 }; 935 936 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 943 }; 944 945 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 946 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 947 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 948 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 949 }; 950 951 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 952 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 953 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 954 }; 955 956 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 958 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 959 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 964 }; 965 966 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 969 }; 970 971 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 972 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 973 }; 974 975 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 976 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 977 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 978 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 980 }; 981 982 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 983 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 984 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 985 }; 986 987 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 988 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 989 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 990 }; 991 992 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1032 }; 1033 1034 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1035 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1040 }; 1041 1042 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1043 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1068 }; 1069 1070 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1071 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1072 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1073 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1074 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1075 }; 1076 1077 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1078 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1079 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1080 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1081 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1082 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1083 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1084 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1085 }; 1086 1087 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1130 }; 1131 1132 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1133 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1138 }; 1139 1140 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1141 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1163 }; 1164 1165 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1166 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1167 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1168 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1169 }; 1170 1171 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1172 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1173 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1174 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1175 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1176 }; 1177 1178 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1179 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1192 }; 1193 1194 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1223 }; 1224 1225 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1226 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1229 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1230 }; 1231 1232 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1233 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1257 1258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1259 1260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1261 1262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1270 1271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1280 }; 1281 1282 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1283 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1284 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1285 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1286 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1287 }; 1288 1289 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1290 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1291 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1292 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1293 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1294 }; 1295 1296 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1299 }; 1300 1301 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1322 }; 1323 1324 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1325 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1326 }; 1327 1328 struct qmp_phy_cfg_tables { 1329 const struct qmp_phy_init_tbl *serdes; 1330 int serdes_num; 1331 const struct qmp_phy_init_tbl *tx; 1332 int tx_num; 1333 const struct qmp_phy_init_tbl *rx; 1334 int rx_num; 1335 const struct qmp_phy_init_tbl *pcs; 1336 int pcs_num; 1337 const struct qmp_phy_init_tbl *pcs_misc; 1338 int pcs_misc_num; 1339 }; 1340 1341 /* struct qmp_phy_cfg - per-PHY initialization config */ 1342 struct qmp_phy_cfg { 1343 int lanes; 1344 1345 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1346 const struct qmp_phy_cfg_tables tables; 1347 /* 1348 * Additional init sequences for PHY blocks, providing additional 1349 * register programming. They are used for providing separate sequences 1350 * for the Root Complex and End Point use cases. 1351 * 1352 * If EP mode is not supported, both tables can be left unset. 1353 */ 1354 const struct qmp_phy_cfg_tables *tables_rc; 1355 const struct qmp_phy_cfg_tables *tables_ep; 1356 1357 /* clock ids to be requested */ 1358 const char * const *clk_list; 1359 int num_clks; 1360 /* resets to be requested */ 1361 const char * const *reset_list; 1362 int num_resets; 1363 /* regulators to be requested */ 1364 const char * const *vreg_list; 1365 int num_vregs; 1366 1367 /* array of registers with different offsets */ 1368 const unsigned int *regs; 1369 1370 unsigned int start_ctrl; 1371 unsigned int pwrdn_ctrl; 1372 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1373 unsigned int phy_status; 1374 1375 /* true, if PHY needs delay after POWER_DOWN */ 1376 bool has_pwrdn_delay; 1377 /* power_down delay in usec */ 1378 int pwrdn_delay_min; 1379 int pwrdn_delay_max; 1380 1381 /* QMP PHY pipe clock interface rate */ 1382 unsigned long pipe_clock_rate; 1383 }; 1384 1385 /** 1386 * struct qmp_phy - per-lane phy descriptor 1387 * 1388 * @phy: generic phy 1389 * @cfg: phy specific configuration 1390 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1391 * @tx: iomapped memory space for lane's tx 1392 * @rx: iomapped memory space for lane's rx 1393 * @pcs: iomapped memory space for lane's pcs 1394 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1395 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1396 * @pcs_misc: iomapped memory space for lane's pcs_misc 1397 * @pipe_clk: pipe clock 1398 * @qmp: QMP phy to which this lane belongs 1399 * @mode: currently selected PHY mode 1400 */ 1401 struct qmp_phy { 1402 struct phy *phy; 1403 const struct qmp_phy_cfg *cfg; 1404 void __iomem *serdes; 1405 void __iomem *tx; 1406 void __iomem *rx; 1407 void __iomem *pcs; 1408 void __iomem *tx2; 1409 void __iomem *rx2; 1410 void __iomem *pcs_misc; 1411 struct clk *pipe_clk; 1412 struct qcom_qmp *qmp; 1413 int mode; 1414 }; 1415 1416 /** 1417 * struct qcom_qmp - structure holding QMP phy block attributes 1418 * 1419 * @dev: device 1420 * 1421 * @clks: array of clocks required by phy 1422 * @resets: array of resets required by phy 1423 * @vregs: regulator supplies bulk data 1424 * 1425 * @phys: array of per-lane phy descriptors 1426 */ 1427 struct qcom_qmp { 1428 struct device *dev; 1429 1430 struct clk_bulk_data *clks; 1431 struct reset_control_bulk_data *resets; 1432 struct regulator_bulk_data *vregs; 1433 1434 struct qmp_phy **phys; 1435 }; 1436 1437 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1438 { 1439 u32 reg; 1440 1441 reg = readl(base + offset); 1442 reg |= val; 1443 writel(reg, base + offset); 1444 1445 /* ensure that above write is through */ 1446 readl(base + offset); 1447 } 1448 1449 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1450 { 1451 u32 reg; 1452 1453 reg = readl(base + offset); 1454 reg &= ~val; 1455 writel(reg, base + offset); 1456 1457 /* ensure that above write is through */ 1458 readl(base + offset); 1459 } 1460 1461 /* list of clocks required by phy */ 1462 static const char * const msm8996_phy_clk_l[] = { 1463 "aux", "cfg_ahb", "ref", 1464 }; 1465 1466 1467 static const char * const sdm845_pciephy_clk_l[] = { 1468 "aux", "cfg_ahb", "ref", "refgen", 1469 }; 1470 1471 /* list of regulators */ 1472 static const char * const qmp_phy_vreg_l[] = { 1473 "vdda-phy", "vdda-pll", 1474 }; 1475 1476 static const char * const ipq8074_pciephy_clk_l[] = { 1477 "aux", "cfg_ahb", 1478 }; 1479 1480 /* list of resets */ 1481 static const char * const ipq8074_pciephy_reset_l[] = { 1482 "phy", "common", 1483 }; 1484 1485 static const char * const sdm845_pciephy_reset_l[] = { 1486 "phy", 1487 }; 1488 1489 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1490 .lanes = 1, 1491 1492 .tables = { 1493 .serdes = ipq8074_pcie_serdes_tbl, 1494 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1495 .tx = ipq8074_pcie_tx_tbl, 1496 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1497 .rx = ipq8074_pcie_rx_tbl, 1498 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1499 .pcs = ipq8074_pcie_pcs_tbl, 1500 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1501 }, 1502 .clk_list = ipq8074_pciephy_clk_l, 1503 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1504 .reset_list = ipq8074_pciephy_reset_l, 1505 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1506 .vreg_list = NULL, 1507 .num_vregs = 0, 1508 .regs = pciephy_regs_layout, 1509 1510 .start_ctrl = SERDES_START | PCS_START, 1511 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1512 .phy_status = PHYSTATUS, 1513 1514 .has_pwrdn_delay = true, 1515 .pwrdn_delay_min = 995, /* us */ 1516 .pwrdn_delay_max = 1005, /* us */ 1517 }; 1518 1519 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1520 .lanes = 1, 1521 1522 .tables = { 1523 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1524 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1525 .tx = ipq8074_pcie_gen3_tx_tbl, 1526 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1527 .rx = ipq8074_pcie_gen3_rx_tbl, 1528 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1529 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1530 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1531 }, 1532 .clk_list = ipq8074_pciephy_clk_l, 1533 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1534 .reset_list = ipq8074_pciephy_reset_l, 1535 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1536 .vreg_list = NULL, 1537 .num_vregs = 0, 1538 .regs = ipq_pciephy_gen3_regs_layout, 1539 1540 .start_ctrl = SERDES_START | PCS_START, 1541 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1542 1543 .has_pwrdn_delay = true, 1544 .pwrdn_delay_min = 995, /* us */ 1545 .pwrdn_delay_max = 1005, /* us */ 1546 1547 .pipe_clock_rate = 250000000, 1548 }; 1549 1550 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1551 .lanes = 1, 1552 1553 .tables = { 1554 .serdes = ipq6018_pcie_serdes_tbl, 1555 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1556 .tx = ipq6018_pcie_tx_tbl, 1557 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1558 .rx = ipq6018_pcie_rx_tbl, 1559 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1560 .pcs = ipq6018_pcie_pcs_tbl, 1561 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1562 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1563 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1564 }, 1565 .clk_list = ipq8074_pciephy_clk_l, 1566 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1567 .reset_list = ipq8074_pciephy_reset_l, 1568 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1569 .vreg_list = NULL, 1570 .num_vregs = 0, 1571 .regs = ipq_pciephy_gen3_regs_layout, 1572 1573 .start_ctrl = SERDES_START | PCS_START, 1574 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1575 1576 .has_pwrdn_delay = true, 1577 .pwrdn_delay_min = 995, /* us */ 1578 .pwrdn_delay_max = 1005, /* us */ 1579 }; 1580 1581 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1582 .lanes = 1, 1583 1584 .tables = { 1585 .serdes = sdm845_qmp_pcie_serdes_tbl, 1586 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1587 .tx = sdm845_qmp_pcie_tx_tbl, 1588 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1589 .rx = sdm845_qmp_pcie_rx_tbl, 1590 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1591 .pcs = sdm845_qmp_pcie_pcs_tbl, 1592 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1593 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1594 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1595 }, 1596 .clk_list = sdm845_pciephy_clk_l, 1597 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1598 .reset_list = sdm845_pciephy_reset_l, 1599 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1600 .vreg_list = qmp_phy_vreg_l, 1601 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1602 .regs = sdm845_qmp_pciephy_regs_layout, 1603 1604 .start_ctrl = PCS_START | SERDES_START, 1605 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1606 .phy_status = PHYSTATUS, 1607 1608 .has_pwrdn_delay = true, 1609 .pwrdn_delay_min = 995, /* us */ 1610 .pwrdn_delay_max = 1005, /* us */ 1611 }; 1612 1613 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1614 .lanes = 1, 1615 1616 .tables = { 1617 .serdes = sdm845_qhp_pcie_serdes_tbl, 1618 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1619 .tx = sdm845_qhp_pcie_tx_tbl, 1620 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1621 .rx = sdm845_qhp_pcie_rx_tbl, 1622 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1623 .pcs = sdm845_qhp_pcie_pcs_tbl, 1624 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1625 }, 1626 .clk_list = sdm845_pciephy_clk_l, 1627 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1628 .reset_list = sdm845_pciephy_reset_l, 1629 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1630 .vreg_list = qmp_phy_vreg_l, 1631 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1632 .regs = sdm845_qhp_pciephy_regs_layout, 1633 1634 .start_ctrl = PCS_START | SERDES_START, 1635 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1636 .phy_status = PHYSTATUS, 1637 1638 .has_pwrdn_delay = true, 1639 .pwrdn_delay_min = 995, /* us */ 1640 .pwrdn_delay_max = 1005, /* us */ 1641 }; 1642 1643 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1644 .lanes = 1, 1645 1646 .tables = { 1647 .serdes = sm8250_qmp_pcie_serdes_tbl, 1648 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1649 .tx = sm8250_qmp_pcie_tx_tbl, 1650 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1651 .rx = sm8250_qmp_pcie_rx_tbl, 1652 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1653 .pcs = sm8250_qmp_pcie_pcs_tbl, 1654 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1655 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1656 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1657 }, 1658 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1659 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1660 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1661 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1662 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1663 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1664 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1665 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1666 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1667 }, 1668 .clk_list = sdm845_pciephy_clk_l, 1669 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1670 .reset_list = sdm845_pciephy_reset_l, 1671 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1672 .vreg_list = qmp_phy_vreg_l, 1673 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1674 .regs = sm8250_pcie_regs_layout, 1675 1676 .start_ctrl = PCS_START | SERDES_START, 1677 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1678 .phy_status = PHYSTATUS, 1679 1680 .has_pwrdn_delay = true, 1681 .pwrdn_delay_min = 995, /* us */ 1682 .pwrdn_delay_max = 1005, /* us */ 1683 }; 1684 1685 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1686 .lanes = 2, 1687 1688 .tables = { 1689 .serdes = sm8250_qmp_pcie_serdes_tbl, 1690 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1691 .tx = sm8250_qmp_pcie_tx_tbl, 1692 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1693 .rx = sm8250_qmp_pcie_rx_tbl, 1694 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1695 .pcs = sm8250_qmp_pcie_pcs_tbl, 1696 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1697 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1698 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1699 }, 1700 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1701 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1702 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1703 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1704 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1705 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1706 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1707 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1708 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1709 }, 1710 .clk_list = sdm845_pciephy_clk_l, 1711 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1712 .reset_list = sdm845_pciephy_reset_l, 1713 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1714 .vreg_list = qmp_phy_vreg_l, 1715 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1716 .regs = sm8250_pcie_regs_layout, 1717 1718 .start_ctrl = PCS_START | SERDES_START, 1719 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1720 .phy_status = PHYSTATUS, 1721 1722 .has_pwrdn_delay = true, 1723 .pwrdn_delay_min = 995, /* us */ 1724 .pwrdn_delay_max = 1005, /* us */ 1725 }; 1726 1727 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1728 .lanes = 1, 1729 1730 .tables = { 1731 .serdes = msm8998_pcie_serdes_tbl, 1732 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1733 .tx = msm8998_pcie_tx_tbl, 1734 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1735 .rx = msm8998_pcie_rx_tbl, 1736 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1737 .pcs = msm8998_pcie_pcs_tbl, 1738 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1739 }, 1740 .clk_list = msm8996_phy_clk_l, 1741 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1742 .reset_list = ipq8074_pciephy_reset_l, 1743 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1744 .vreg_list = qmp_phy_vreg_l, 1745 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1746 .regs = pciephy_regs_layout, 1747 1748 .start_ctrl = SERDES_START | PCS_START, 1749 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1750 .phy_status = PHYSTATUS, 1751 }; 1752 1753 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1754 .lanes = 1, 1755 1756 .tables = { 1757 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1758 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1759 .tx = sc8180x_qmp_pcie_tx_tbl, 1760 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1761 .rx = sc8180x_qmp_pcie_rx_tbl, 1762 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1763 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1764 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1765 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1766 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1767 }, 1768 .clk_list = sdm845_pciephy_clk_l, 1769 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1770 .reset_list = sdm845_pciephy_reset_l, 1771 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1772 .vreg_list = qmp_phy_vreg_l, 1773 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1774 .regs = sm8250_pcie_regs_layout, 1775 1776 .start_ctrl = PCS_START | SERDES_START, 1777 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1778 1779 .has_pwrdn_delay = true, 1780 .pwrdn_delay_min = 995, /* us */ 1781 .pwrdn_delay_max = 1005, /* us */ 1782 }; 1783 1784 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1785 .lanes = 2, 1786 1787 .tables = { 1788 .serdes = sdx55_qmp_pcie_serdes_tbl, 1789 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1790 .tx = sdx55_qmp_pcie_tx_tbl, 1791 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1792 .rx = sdx55_qmp_pcie_rx_tbl, 1793 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1794 .pcs = sdx55_qmp_pcie_pcs_tbl, 1795 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1796 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1797 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1798 }, 1799 .clk_list = sdm845_pciephy_clk_l, 1800 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1801 .reset_list = sdm845_pciephy_reset_l, 1802 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1803 .vreg_list = qmp_phy_vreg_l, 1804 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1805 .regs = sm8250_pcie_regs_layout, 1806 1807 .start_ctrl = PCS_START | SERDES_START, 1808 .pwrdn_ctrl = SW_PWRDN, 1809 .phy_status = PHYSTATUS_4_20, 1810 1811 .has_pwrdn_delay = true, 1812 .pwrdn_delay_min = 995, /* us */ 1813 .pwrdn_delay_max = 1005, /* us */ 1814 }; 1815 1816 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1817 .lanes = 1, 1818 1819 .tables = { 1820 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1821 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1822 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1823 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1824 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1825 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1826 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1827 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1828 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1829 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1830 }, 1831 .clk_list = sdm845_pciephy_clk_l, 1832 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1833 .reset_list = sdm845_pciephy_reset_l, 1834 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1835 .vreg_list = qmp_phy_vreg_l, 1836 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1837 .regs = sm8250_pcie_regs_layout, 1838 1839 .start_ctrl = SERDES_START | PCS_START, 1840 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1841 .phy_status = PHYSTATUS, 1842 1843 .has_pwrdn_delay = true, 1844 .pwrdn_delay_min = 995, /* us */ 1845 .pwrdn_delay_max = 1005, /* us */ 1846 }; 1847 1848 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1849 .lanes = 2, 1850 1851 .tables = { 1852 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1853 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1854 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1855 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1856 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1857 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1858 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1859 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1860 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1861 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1862 }, 1863 1864 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1865 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 1866 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 1867 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 1868 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 1869 }, 1870 1871 .tables_ep = &(const struct qmp_phy_cfg_tables) { 1872 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 1873 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 1874 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 1875 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 1876 }, 1877 1878 .clk_list = sdm845_pciephy_clk_l, 1879 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1880 .reset_list = sdm845_pciephy_reset_l, 1881 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1882 .vreg_list = qmp_phy_vreg_l, 1883 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1884 .regs = sm8250_pcie_regs_layout, 1885 1886 .start_ctrl = SERDES_START | PCS_START, 1887 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1888 .phy_status = PHYSTATUS_4_20, 1889 1890 .has_pwrdn_delay = true, 1891 .pwrdn_delay_min = 995, /* us */ 1892 .pwrdn_delay_max = 1005, /* us */ 1893 }; 1894 1895 static void qmp_pcie_configure_lane(void __iomem *base, 1896 const unsigned int *regs, 1897 const struct qmp_phy_init_tbl tbl[], 1898 int num, 1899 u8 lane_mask) 1900 { 1901 int i; 1902 const struct qmp_phy_init_tbl *t = tbl; 1903 1904 if (!t) 1905 return; 1906 1907 for (i = 0; i < num; i++, t++) { 1908 if (!(t->lane_mask & lane_mask)) 1909 continue; 1910 1911 if (t->in_layout) 1912 writel(t->val, base + regs[t->offset]); 1913 else 1914 writel(t->val, base + t->offset); 1915 } 1916 } 1917 1918 static void qmp_pcie_configure(void __iomem *base, 1919 const unsigned int *regs, 1920 const struct qmp_phy_init_tbl tbl[], 1921 int num) 1922 { 1923 qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); 1924 } 1925 1926 static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1927 { 1928 const struct qmp_phy_cfg *cfg = qphy->cfg; 1929 void __iomem *serdes = qphy->serdes; 1930 1931 if (!tables) 1932 return; 1933 1934 qmp_pcie_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num); 1935 } 1936 1937 static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1938 { 1939 const struct qmp_phy_cfg *cfg = qphy->cfg; 1940 void __iomem *tx = qphy->tx; 1941 void __iomem *rx = qphy->rx; 1942 1943 if (!tables) 1944 return; 1945 1946 qmp_pcie_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1); 1947 1948 if (cfg->lanes >= 2) 1949 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num, 2); 1950 1951 qmp_pcie_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1); 1952 if (cfg->lanes >= 2) 1953 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num, 2); 1954 } 1955 1956 static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1957 { 1958 const struct qmp_phy_cfg *cfg = qphy->cfg; 1959 void __iomem *pcs = qphy->pcs; 1960 void __iomem *pcs_misc = qphy->pcs_misc; 1961 1962 if (!tables) 1963 return; 1964 1965 qmp_pcie_configure(pcs, cfg->regs, 1966 tables->pcs, tables->pcs_num); 1967 qmp_pcie_configure(pcs_misc, cfg->regs, 1968 tables->pcs_misc, tables->pcs_misc_num); 1969 } 1970 1971 static int qmp_pcie_init(struct phy *phy) 1972 { 1973 struct qmp_phy *qphy = phy_get_drvdata(phy); 1974 struct qcom_qmp *qmp = qphy->qmp; 1975 const struct qmp_phy_cfg *cfg = qphy->cfg; 1976 void __iomem *pcs = qphy->pcs; 1977 int ret; 1978 1979 /* turn on regulator supplies */ 1980 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1981 if (ret) { 1982 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1983 return ret; 1984 } 1985 1986 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1987 if (ret) { 1988 dev_err(qmp->dev, "reset assert failed\n"); 1989 goto err_disable_regulators; 1990 } 1991 1992 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1993 if (ret) { 1994 dev_err(qmp->dev, "reset deassert failed\n"); 1995 goto err_disable_regulators; 1996 } 1997 1998 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1999 if (ret) 2000 goto err_assert_reset; 2001 2002 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 2003 qphy_setbits(pcs, 2004 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2005 cfg->pwrdn_ctrl); 2006 else 2007 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2008 cfg->pwrdn_ctrl); 2009 2010 return 0; 2011 2012 err_assert_reset: 2013 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2014 err_disable_regulators: 2015 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2016 2017 return ret; 2018 } 2019 2020 static int qmp_pcie_exit(struct phy *phy) 2021 { 2022 struct qmp_phy *qphy = phy_get_drvdata(phy); 2023 struct qcom_qmp *qmp = qphy->qmp; 2024 const struct qmp_phy_cfg *cfg = qphy->cfg; 2025 2026 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2027 2028 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2029 2030 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2031 2032 return 0; 2033 } 2034 2035 static int qmp_pcie_power_on(struct phy *phy) 2036 { 2037 struct qmp_phy *qphy = phy_get_drvdata(phy); 2038 struct qcom_qmp *qmp = qphy->qmp; 2039 const struct qmp_phy_cfg *cfg = qphy->cfg; 2040 const struct qmp_phy_cfg_tables *mode_tables; 2041 void __iomem *pcs = qphy->pcs; 2042 void __iomem *status; 2043 unsigned int mask, val, ready; 2044 int ret; 2045 2046 if (qphy->mode == PHY_MODE_PCIE_RC) 2047 mode_tables = cfg->tables_rc; 2048 else 2049 mode_tables = cfg->tables_ep; 2050 2051 qmp_pcie_serdes_init(qphy, &cfg->tables); 2052 qmp_pcie_serdes_init(qphy, mode_tables); 2053 2054 ret = clk_prepare_enable(qphy->pipe_clk); 2055 if (ret) { 2056 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2057 return ret; 2058 } 2059 2060 /* Tx, Rx, and PCS configurations */ 2061 qmp_pcie_lanes_init(qphy, &cfg->tables); 2062 qmp_pcie_lanes_init(qphy, mode_tables); 2063 2064 qmp_pcie_pcs_init(qphy, &cfg->tables); 2065 qmp_pcie_pcs_init(qphy, mode_tables); 2066 2067 /* 2068 * Pull out PHY from POWER DOWN state. 2069 * This is active low enable signal to power-down PHY. 2070 */ 2071 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2072 2073 if (cfg->has_pwrdn_delay) 2074 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2075 2076 /* Pull PHY out of reset state */ 2077 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2078 2079 /* start SerDes and Phy-Coding-Sublayer */ 2080 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2081 2082 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2083 mask = cfg->phy_status; 2084 ready = 0; 2085 2086 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2087 PHY_INIT_COMPLETE_TIMEOUT); 2088 if (ret) { 2089 dev_err(qmp->dev, "phy initialization timed-out\n"); 2090 goto err_disable_pipe_clk; 2091 } 2092 2093 return 0; 2094 2095 err_disable_pipe_clk: 2096 clk_disable_unprepare(qphy->pipe_clk); 2097 2098 return ret; 2099 } 2100 2101 static int qmp_pcie_power_off(struct phy *phy) 2102 { 2103 struct qmp_phy *qphy = phy_get_drvdata(phy); 2104 const struct qmp_phy_cfg *cfg = qphy->cfg; 2105 2106 clk_disable_unprepare(qphy->pipe_clk); 2107 2108 /* PHY reset */ 2109 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2110 2111 /* stop SerDes and Phy-Coding-Sublayer */ 2112 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2113 2114 /* Put PHY into POWER DOWN state: active low */ 2115 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2116 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2117 cfg->pwrdn_ctrl); 2118 } else { 2119 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2120 cfg->pwrdn_ctrl); 2121 } 2122 2123 return 0; 2124 } 2125 2126 static int qmp_pcie_enable(struct phy *phy) 2127 { 2128 int ret; 2129 2130 ret = qmp_pcie_init(phy); 2131 if (ret) 2132 return ret; 2133 2134 ret = qmp_pcie_power_on(phy); 2135 if (ret) 2136 qmp_pcie_exit(phy); 2137 2138 return ret; 2139 } 2140 2141 static int qmp_pcie_disable(struct phy *phy) 2142 { 2143 int ret; 2144 2145 ret = qmp_pcie_power_off(phy); 2146 if (ret) 2147 return ret; 2148 2149 return qmp_pcie_exit(phy); 2150 } 2151 2152 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2153 { 2154 struct qmp_phy *qphy = phy_get_drvdata(phy); 2155 2156 switch (submode) { 2157 case PHY_MODE_PCIE_RC: 2158 case PHY_MODE_PCIE_EP: 2159 qphy->mode = submode; 2160 break; 2161 default: 2162 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2163 return -EINVAL; 2164 } 2165 2166 return 0; 2167 } 2168 2169 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2170 { 2171 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2172 int num = cfg->num_vregs; 2173 int i; 2174 2175 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2176 if (!qmp->vregs) 2177 return -ENOMEM; 2178 2179 for (i = 0; i < num; i++) 2180 qmp->vregs[i].supply = cfg->vreg_list[i]; 2181 2182 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2183 } 2184 2185 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2186 { 2187 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2188 int i; 2189 int ret; 2190 2191 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2192 sizeof(*qmp->resets), GFP_KERNEL); 2193 if (!qmp->resets) 2194 return -ENOMEM; 2195 2196 for (i = 0; i < cfg->num_resets; i++) 2197 qmp->resets[i].id = cfg->reset_list[i]; 2198 2199 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2200 if (ret) 2201 return dev_err_probe(dev, ret, "failed to get resets\n"); 2202 2203 return 0; 2204 } 2205 2206 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2207 { 2208 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2209 int num = cfg->num_clks; 2210 int i; 2211 2212 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2213 if (!qmp->clks) 2214 return -ENOMEM; 2215 2216 for (i = 0; i < num; i++) 2217 qmp->clks[i].id = cfg->clk_list[i]; 2218 2219 return devm_clk_bulk_get(dev, num, qmp->clks); 2220 } 2221 2222 static void phy_clk_release_provider(void *res) 2223 { 2224 of_clk_del_provider(res); 2225 } 2226 2227 /* 2228 * Register a fixed rate pipe clock. 2229 * 2230 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2231 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2232 * by the PHY driver for its operations. 2233 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2234 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2235 * Below picture shows this relationship. 2236 * 2237 * +---------------+ 2238 * | PHY block |<<---------------------------------------+ 2239 * | | | 2240 * | +-------+ | +-----+ | 2241 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2242 * clk | +-------+ | +-----+ 2243 * +---------------+ 2244 */ 2245 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2246 { 2247 struct clk_fixed_rate *fixed; 2248 struct clk_init_data init = { }; 2249 int ret; 2250 2251 ret = of_property_read_string(np, "clock-output-names", &init.name); 2252 if (ret) { 2253 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2254 return ret; 2255 } 2256 2257 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2258 if (!fixed) 2259 return -ENOMEM; 2260 2261 init.ops = &clk_fixed_rate_ops; 2262 2263 /* 2264 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2265 * unless other frequency is specified in the PHY config. 2266 */ 2267 if (qmp->phys[0]->cfg->pipe_clock_rate) 2268 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2269 else 2270 fixed->fixed_rate = 125000000; 2271 2272 fixed->hw.init = &init; 2273 2274 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2275 if (ret) 2276 return ret; 2277 2278 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2279 if (ret) 2280 return ret; 2281 2282 /* 2283 * Roll a devm action because the clock provider is the child node, but 2284 * the child node is not actually a device. 2285 */ 2286 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2287 } 2288 2289 static const struct phy_ops qmp_pcie_ops = { 2290 .power_on = qmp_pcie_enable, 2291 .power_off = qmp_pcie_disable, 2292 .set_mode = qmp_pcie_set_mode, 2293 .owner = THIS_MODULE, 2294 }; 2295 2296 static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2297 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2298 { 2299 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2300 struct phy *generic_phy; 2301 struct qmp_phy *qphy; 2302 int ret; 2303 2304 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2305 if (!qphy) 2306 return -ENOMEM; 2307 2308 qphy->mode = PHY_MODE_PCIE_RC; 2309 2310 qphy->cfg = cfg; 2311 qphy->serdes = serdes; 2312 /* 2313 * Get memory resources for the PHY: 2314 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2315 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2316 * For single lane PHYs: pcs_misc (optional) -> 3. 2317 */ 2318 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2319 if (IS_ERR(qphy->tx)) 2320 return PTR_ERR(qphy->tx); 2321 2322 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2323 qphy->rx = qphy->tx; 2324 else 2325 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2326 if (IS_ERR(qphy->rx)) 2327 return PTR_ERR(qphy->rx); 2328 2329 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2330 if (IS_ERR(qphy->pcs)) 2331 return PTR_ERR(qphy->pcs); 2332 2333 if (cfg->lanes >= 2) { 2334 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2335 if (IS_ERR(qphy->tx2)) 2336 return PTR_ERR(qphy->tx2); 2337 2338 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2339 if (IS_ERR(qphy->rx2)) 2340 return PTR_ERR(qphy->rx2); 2341 2342 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2343 } else { 2344 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2345 } 2346 2347 if (IS_ERR(qphy->pcs_misc) && 2348 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2349 qphy->pcs_misc = qphy->pcs + 0x400; 2350 2351 if (IS_ERR(qphy->pcs_misc)) { 2352 if (cfg->tables.pcs_misc || 2353 (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2354 (cfg->tables_ep && cfg->tables_ep->pcs_misc)) 2355 return PTR_ERR(qphy->pcs_misc); 2356 } 2357 2358 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2359 if (IS_ERR(qphy->pipe_clk)) { 2360 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2361 "failed to get lane%d pipe clock\n", id); 2362 } 2363 2364 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2365 if (IS_ERR(generic_phy)) { 2366 ret = PTR_ERR(generic_phy); 2367 dev_err(dev, "failed to create qphy %d\n", ret); 2368 return ret; 2369 } 2370 2371 qphy->phy = generic_phy; 2372 qphy->qmp = qmp; 2373 qmp->phys[id] = qphy; 2374 phy_set_drvdata(generic_phy, qphy); 2375 2376 return 0; 2377 } 2378 2379 static const struct of_device_id qmp_pcie_of_match_table[] = { 2380 { 2381 .compatible = "qcom,msm8998-qmp-pcie-phy", 2382 .data = &msm8998_pciephy_cfg, 2383 }, { 2384 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2385 .data = &ipq8074_pciephy_cfg, 2386 }, { 2387 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2388 .data = &ipq8074_pciephy_gen3_cfg, 2389 }, { 2390 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2391 .data = &ipq6018_pciephy_cfg, 2392 }, { 2393 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2394 .data = &sc8180x_pciephy_cfg, 2395 }, { 2396 .compatible = "qcom,sdm845-qhp-pcie-phy", 2397 .data = &sdm845_qhp_pciephy_cfg, 2398 }, { 2399 .compatible = "qcom,sdm845-qmp-pcie-phy", 2400 .data = &sdm845_qmp_pciephy_cfg, 2401 }, { 2402 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2403 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2404 }, { 2405 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2406 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2407 }, { 2408 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2409 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2410 }, { 2411 .compatible = "qcom,sdx55-qmp-pcie-phy", 2412 .data = &sdx55_qmp_pciephy_cfg, 2413 }, { 2414 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2415 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2416 }, { 2417 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2418 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2419 }, 2420 { }, 2421 }; 2422 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2423 2424 static int qmp_pcie_probe(struct platform_device *pdev) 2425 { 2426 struct qcom_qmp *qmp; 2427 struct device *dev = &pdev->dev; 2428 struct device_node *child; 2429 struct phy_provider *phy_provider; 2430 void __iomem *serdes; 2431 const struct qmp_phy_cfg *cfg = NULL; 2432 int num, id; 2433 int ret; 2434 2435 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2436 if (!qmp) 2437 return -ENOMEM; 2438 2439 qmp->dev = dev; 2440 dev_set_drvdata(dev, qmp); 2441 2442 /* Get the specific init parameters of QMP phy */ 2443 cfg = of_device_get_match_data(dev); 2444 if (!cfg) 2445 return -EINVAL; 2446 2447 /* per PHY serdes; usually located at base address */ 2448 serdes = devm_platform_ioremap_resource(pdev, 0); 2449 if (IS_ERR(serdes)) 2450 return PTR_ERR(serdes); 2451 2452 ret = qmp_pcie_clk_init(dev, cfg); 2453 if (ret) 2454 return ret; 2455 2456 ret = qmp_pcie_reset_init(dev, cfg); 2457 if (ret) 2458 return ret; 2459 2460 ret = qmp_pcie_vreg_init(dev, cfg); 2461 if (ret) 2462 return dev_err_probe(dev, ret, 2463 "failed to get regulator supplies\n"); 2464 2465 num = of_get_available_child_count(dev->of_node); 2466 /* do we have a rogue child node ? */ 2467 if (num > 1) 2468 return -EINVAL; 2469 2470 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2471 if (!qmp->phys) 2472 return -ENOMEM; 2473 2474 id = 0; 2475 for_each_available_child_of_node(dev->of_node, child) { 2476 /* Create per-lane phy */ 2477 ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2478 if (ret) { 2479 dev_err(dev, "failed to create lane%d phy, %d\n", 2480 id, ret); 2481 goto err_node_put; 2482 } 2483 2484 /* 2485 * Register the pipe clock provided by phy. 2486 * See function description to see details of this pipe clock. 2487 */ 2488 ret = phy_pipe_clk_register(qmp, child); 2489 if (ret) { 2490 dev_err(qmp->dev, 2491 "failed to register pipe clock source\n"); 2492 goto err_node_put; 2493 } 2494 2495 id++; 2496 } 2497 2498 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2499 2500 return PTR_ERR_OR_ZERO(phy_provider); 2501 2502 err_node_put: 2503 of_node_put(child); 2504 return ret; 2505 } 2506 2507 static struct platform_driver qmp_pcie_driver = { 2508 .probe = qmp_pcie_probe, 2509 .driver = { 2510 .name = "qcom-qmp-pcie-phy", 2511 .of_match_table = qmp_pcie_of_match_table, 2512 }, 2513 }; 2514 2515 module_platform_driver(qmp_pcie_driver); 2516 2517 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2518 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2519 MODULE_LICENSE("GPL v2"); 2520