1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy.h> 24 25 #include "phy-qcom-qmp.h" 26 27 /* QPHY_SW_RESET bit */ 28 #define SW_RESET BIT(0) 29 /* QPHY_POWER_DOWN_CONTROL */ 30 #define SW_PWRDN BIT(0) 31 #define REFCLK_DRV_DSBL BIT(1) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 /* QPHY_PCS_STATUS bit */ 36 #define PHYSTATUS BIT(6) 37 #define PHYSTATUS_4_20 BIT(7) 38 39 #define PHY_INIT_COMPLETE_TIMEOUT 10000 40 41 struct qmp_phy_init_tbl { 42 unsigned int offset; 43 unsigned int val; 44 /* 45 * register part of layout ? 46 * if yes, then offset gives index in the reg-layout 47 */ 48 bool in_layout; 49 /* 50 * mask of lanes for which this register is written 51 * for cases when second lane needs different values 52 */ 53 u8 lane_mask; 54 }; 55 56 #define QMP_PHY_INIT_CFG(o, v) \ 57 { \ 58 .offset = o, \ 59 .val = v, \ 60 .lane_mask = 0xff, \ 61 } 62 63 #define QMP_PHY_INIT_CFG_L(o, v) \ 64 { \ 65 .offset = o, \ 66 .val = v, \ 67 .in_layout = true, \ 68 .lane_mask = 0xff, \ 69 } 70 71 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 72 { \ 73 .offset = o, \ 74 .val = v, \ 75 .lane_mask = l, \ 76 } 77 78 /* set of registers with offsets different per-PHY */ 79 enum qphy_reg_layout { 80 /* Common block control registers */ 81 QPHY_COM_SW_RESET, 82 QPHY_COM_POWER_DOWN_CONTROL, 83 QPHY_COM_START_CONTROL, 84 QPHY_COM_PCS_READY_STATUS, 85 /* PCS registers */ 86 QPHY_SW_RESET, 87 QPHY_START_CTRL, 88 QPHY_PCS_STATUS, 89 QPHY_PCS_POWER_DOWN_CONTROL, 90 /* Keep last to ensure regs_layout arrays are properly initialized */ 91 QPHY_LAYOUT_SIZE 92 }; 93 94 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 95 [QPHY_SW_RESET] = 0x00, 96 [QPHY_START_CTRL] = 0x44, 97 [QPHY_PCS_STATUS] = 0x14, 98 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 99 }; 100 101 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 102 [QPHY_COM_SW_RESET] = 0x400, 103 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 104 [QPHY_COM_START_CONTROL] = 0x408, 105 [QPHY_COM_PCS_READY_STATUS] = 0x448, 106 [QPHY_SW_RESET] = 0x00, 107 [QPHY_START_CTRL] = 0x08, 108 [QPHY_PCS_STATUS] = 0x174, 109 }; 110 111 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 112 [QPHY_SW_RESET] = 0x00, 113 [QPHY_START_CTRL] = 0x08, 114 [QPHY_PCS_STATUS] = 0x174, 115 }; 116 117 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 118 [QPHY_SW_RESET] = 0x00, 119 [QPHY_START_CTRL] = 0x08, 120 [QPHY_PCS_STATUS] = 0x2ac, 121 }; 122 123 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 124 [QPHY_SW_RESET] = 0x00, 125 [QPHY_START_CTRL] = 0x44, 126 [QPHY_PCS_STATUS] = 0x14, 127 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 128 }; 129 130 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 168 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 169 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 170 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 171 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 172 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 173 }; 174 175 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 176 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 177 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 178 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 179 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 180 }; 181 182 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 187 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 189 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 190 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 191 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 192 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 193 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 194 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 195 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 196 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 197 }; 198 199 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 210 }; 211 212 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 213 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 249 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 250 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 251 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 252 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 253 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 254 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 255 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 256 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 257 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 258 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 259 }; 260 261 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 262 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 263 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 264 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 265 }; 266 267 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 290 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 293 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 294 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 295 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 298 }; 299 300 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 308 }; 309 310 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 311 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 312 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 313 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 314 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 315 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 316 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 317 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 318 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 319 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 320 }; 321 322 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 323 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 324 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 325 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 326 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 327 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 328 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 329 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 330 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 331 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 332 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 334 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 335 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 336 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 337 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 338 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 339 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 340 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 341 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 342 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 343 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 344 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 345 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 346 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 347 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 349 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 350 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 352 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 353 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 354 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 355 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 357 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 358 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 359 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 360 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 361 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 362 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 363 }; 364 365 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 366 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 367 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 368 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 369 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 370 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 371 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 372 }; 373 374 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 375 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 376 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 377 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 378 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 379 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 380 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 381 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 382 }; 383 384 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 386 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 387 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 388 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 389 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 390 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 391 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 392 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 395 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 396 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 397 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 398 }; 399 400 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 401 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 446 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 447 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 448 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 449 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 450 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 451 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 452 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 453 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 454 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 455 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 456 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 457 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 458 }; 459 460 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 461 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 462 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 463 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 464 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 465 }; 466 467 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 490 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 491 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 492 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 493 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 498 }; 499 500 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 518 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 519 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 520 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 521 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 522 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 523 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 524 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 525 }; 526 527 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 563 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 564 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 565 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 566 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 567 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 568 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 569 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 570 }; 571 572 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 573 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 574 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 575 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 576 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 577 }; 578 579 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 587 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 588 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 589 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 590 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 591 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 592 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 593 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 594 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 595 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 596 }; 597 598 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 600 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 606 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 614 615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 618 619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 620 }; 621 622 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 623 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 624 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 625 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 626 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 627 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 628 }; 629 630 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 676 }; 677 678 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 735 }; 736 737 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 738 }; 739 740 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 741 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 742 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 743 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 744 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 745 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 746 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 747 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 748 }; 749 750 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 793 }; 794 795 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 796 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 797 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 798 }; 799 800 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 832 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 833 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 834 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 837 }; 838 839 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 845 }; 846 847 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 848 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 849 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 850 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 851 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 852 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 853 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 854 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 855 }; 856 857 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 895 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 899 }; 900 901 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 903 }; 904 905 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 906 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 909 }; 910 911 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 942 }; 943 944 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 951 }; 952 953 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 954 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 957 }; 958 959 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 962 }; 963 964 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 972 }; 973 974 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 977 }; 978 979 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 980 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 981 }; 982 983 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 984 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 985 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 986 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 988 }; 989 990 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 991 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 992 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 993 }; 994 995 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 996 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 997 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 998 }; 999 1000 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1040 }; 1041 1042 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1043 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1044 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1048 }; 1049 1050 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1051 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1076 }; 1077 1078 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1079 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1080 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1081 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1082 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1083 }; 1084 1085 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1086 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1087 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1088 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1089 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1090 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1091 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1092 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1093 }; 1094 1095 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1138 }; 1139 1140 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1141 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1146 }; 1147 1148 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1171 }; 1172 1173 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1174 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1175 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1176 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1177 }; 1178 1179 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1180 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1181 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1182 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1183 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1184 }; 1185 1186 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1228 }; 1229 1230 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1231 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1235 }; 1236 1237 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1262 1263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1264 1265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1266 1267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1275 1276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1285 }; 1286 1287 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1288 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1290 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1291 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1292 }; 1293 1294 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1295 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1299 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1300 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1301 }; 1302 1303 struct qmp_phy_cfg_tables { 1304 const struct qmp_phy_init_tbl *serdes; 1305 int serdes_num; 1306 const struct qmp_phy_init_tbl *tx; 1307 int tx_num; 1308 const struct qmp_phy_init_tbl *rx; 1309 int rx_num; 1310 const struct qmp_phy_init_tbl *pcs; 1311 int pcs_num; 1312 const struct qmp_phy_init_tbl *pcs_misc; 1313 int pcs_misc_num; 1314 }; 1315 1316 /* struct qmp_phy_cfg - per-PHY initialization config */ 1317 struct qmp_phy_cfg { 1318 int lanes; 1319 1320 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1321 const struct qmp_phy_cfg_tables tables; 1322 /* 1323 * Additional init sequence for PHY blocks, providing additional 1324 * register programming. Unless required it can be left omitted. 1325 */ 1326 const struct qmp_phy_cfg_tables *tables_rc; 1327 1328 /* clock ids to be requested */ 1329 const char * const *clk_list; 1330 int num_clks; 1331 /* resets to be requested */ 1332 const char * const *reset_list; 1333 int num_resets; 1334 /* regulators to be requested */ 1335 const char * const *vreg_list; 1336 int num_vregs; 1337 1338 /* array of registers with different offsets */ 1339 const unsigned int *regs; 1340 1341 unsigned int start_ctrl; 1342 unsigned int pwrdn_ctrl; 1343 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1344 unsigned int phy_status; 1345 1346 /* true, if PHY needs delay after POWER_DOWN */ 1347 bool has_pwrdn_delay; 1348 /* power_down delay in usec */ 1349 int pwrdn_delay_min; 1350 int pwrdn_delay_max; 1351 1352 /* QMP PHY pipe clock interface rate */ 1353 unsigned long pipe_clock_rate; 1354 }; 1355 1356 /** 1357 * struct qmp_phy - per-lane phy descriptor 1358 * 1359 * @phy: generic phy 1360 * @cfg: phy specific configuration 1361 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1362 * @tx: iomapped memory space for lane's tx 1363 * @rx: iomapped memory space for lane's rx 1364 * @pcs: iomapped memory space for lane's pcs 1365 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1366 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1367 * @pcs_misc: iomapped memory space for lane's pcs_misc 1368 * @pipe_clk: pipe clock 1369 * @qmp: QMP phy to which this lane belongs 1370 */ 1371 struct qmp_phy { 1372 struct phy *phy; 1373 const struct qmp_phy_cfg *cfg; 1374 void __iomem *serdes; 1375 void __iomem *tx; 1376 void __iomem *rx; 1377 void __iomem *pcs; 1378 void __iomem *tx2; 1379 void __iomem *rx2; 1380 void __iomem *pcs_misc; 1381 struct clk *pipe_clk; 1382 struct qcom_qmp *qmp; 1383 }; 1384 1385 /** 1386 * struct qcom_qmp - structure holding QMP phy block attributes 1387 * 1388 * @dev: device 1389 * 1390 * @clks: array of clocks required by phy 1391 * @resets: array of resets required by phy 1392 * @vregs: regulator supplies bulk data 1393 * 1394 * @phys: array of per-lane phy descriptors 1395 */ 1396 struct qcom_qmp { 1397 struct device *dev; 1398 1399 struct clk_bulk_data *clks; 1400 struct reset_control_bulk_data *resets; 1401 struct regulator_bulk_data *vregs; 1402 1403 struct qmp_phy **phys; 1404 }; 1405 1406 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1407 { 1408 u32 reg; 1409 1410 reg = readl(base + offset); 1411 reg |= val; 1412 writel(reg, base + offset); 1413 1414 /* ensure that above write is through */ 1415 readl(base + offset); 1416 } 1417 1418 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1419 { 1420 u32 reg; 1421 1422 reg = readl(base + offset); 1423 reg &= ~val; 1424 writel(reg, base + offset); 1425 1426 /* ensure that above write is through */ 1427 readl(base + offset); 1428 } 1429 1430 /* list of clocks required by phy */ 1431 static const char * const msm8996_phy_clk_l[] = { 1432 "aux", "cfg_ahb", "ref", 1433 }; 1434 1435 1436 static const char * const sdm845_pciephy_clk_l[] = { 1437 "aux", "cfg_ahb", "ref", "refgen", 1438 }; 1439 1440 /* list of regulators */ 1441 static const char * const qmp_phy_vreg_l[] = { 1442 "vdda-phy", "vdda-pll", 1443 }; 1444 1445 static const char * const ipq8074_pciephy_clk_l[] = { 1446 "aux", "cfg_ahb", 1447 }; 1448 1449 /* list of resets */ 1450 static const char * const ipq8074_pciephy_reset_l[] = { 1451 "phy", "common", 1452 }; 1453 1454 static const char * const sdm845_pciephy_reset_l[] = { 1455 "phy", 1456 }; 1457 1458 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1459 .lanes = 1, 1460 1461 .tables = { 1462 .serdes = ipq8074_pcie_serdes_tbl, 1463 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1464 .tx = ipq8074_pcie_tx_tbl, 1465 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1466 .rx = ipq8074_pcie_rx_tbl, 1467 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1468 .pcs = ipq8074_pcie_pcs_tbl, 1469 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1470 }, 1471 .clk_list = ipq8074_pciephy_clk_l, 1472 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1473 .reset_list = ipq8074_pciephy_reset_l, 1474 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1475 .vreg_list = NULL, 1476 .num_vregs = 0, 1477 .regs = pciephy_regs_layout, 1478 1479 .start_ctrl = SERDES_START | PCS_START, 1480 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1481 .phy_status = PHYSTATUS, 1482 1483 .has_pwrdn_delay = true, 1484 .pwrdn_delay_min = 995, /* us */ 1485 .pwrdn_delay_max = 1005, /* us */ 1486 }; 1487 1488 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1489 .lanes = 1, 1490 1491 .tables = { 1492 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1493 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1494 .tx = ipq8074_pcie_gen3_tx_tbl, 1495 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1496 .rx = ipq8074_pcie_gen3_rx_tbl, 1497 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1498 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1499 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1500 }, 1501 .clk_list = ipq8074_pciephy_clk_l, 1502 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1503 .reset_list = ipq8074_pciephy_reset_l, 1504 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1505 .vreg_list = NULL, 1506 .num_vregs = 0, 1507 .regs = ipq_pciephy_gen3_regs_layout, 1508 1509 .start_ctrl = SERDES_START | PCS_START, 1510 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1511 1512 .has_pwrdn_delay = true, 1513 .pwrdn_delay_min = 995, /* us */ 1514 .pwrdn_delay_max = 1005, /* us */ 1515 1516 .pipe_clock_rate = 250000000, 1517 }; 1518 1519 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1520 .lanes = 1, 1521 1522 .tables = { 1523 .serdes = ipq6018_pcie_serdes_tbl, 1524 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1525 .tx = ipq6018_pcie_tx_tbl, 1526 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1527 .rx = ipq6018_pcie_rx_tbl, 1528 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1529 .pcs = ipq6018_pcie_pcs_tbl, 1530 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1531 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1532 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1533 }, 1534 .clk_list = ipq8074_pciephy_clk_l, 1535 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1536 .reset_list = ipq8074_pciephy_reset_l, 1537 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1538 .vreg_list = NULL, 1539 .num_vregs = 0, 1540 .regs = ipq_pciephy_gen3_regs_layout, 1541 1542 .start_ctrl = SERDES_START | PCS_START, 1543 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1544 1545 .has_pwrdn_delay = true, 1546 .pwrdn_delay_min = 995, /* us */ 1547 .pwrdn_delay_max = 1005, /* us */ 1548 }; 1549 1550 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1551 .lanes = 1, 1552 1553 .tables = { 1554 .serdes = sdm845_qmp_pcie_serdes_tbl, 1555 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1556 .tx = sdm845_qmp_pcie_tx_tbl, 1557 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1558 .rx = sdm845_qmp_pcie_rx_tbl, 1559 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1560 .pcs = sdm845_qmp_pcie_pcs_tbl, 1561 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1562 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1563 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1564 }, 1565 .clk_list = sdm845_pciephy_clk_l, 1566 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1567 .reset_list = sdm845_pciephy_reset_l, 1568 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1569 .vreg_list = qmp_phy_vreg_l, 1570 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1571 .regs = sdm845_qmp_pciephy_regs_layout, 1572 1573 .start_ctrl = PCS_START | SERDES_START, 1574 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1575 .phy_status = PHYSTATUS, 1576 1577 .has_pwrdn_delay = true, 1578 .pwrdn_delay_min = 995, /* us */ 1579 .pwrdn_delay_max = 1005, /* us */ 1580 }; 1581 1582 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1583 .lanes = 1, 1584 1585 .tables = { 1586 .serdes = sdm845_qhp_pcie_serdes_tbl, 1587 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1588 .tx = sdm845_qhp_pcie_tx_tbl, 1589 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1590 .rx = sdm845_qhp_pcie_rx_tbl, 1591 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1592 .pcs = sdm845_qhp_pcie_pcs_tbl, 1593 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1594 }, 1595 .clk_list = sdm845_pciephy_clk_l, 1596 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1597 .reset_list = sdm845_pciephy_reset_l, 1598 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1599 .vreg_list = qmp_phy_vreg_l, 1600 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1601 .regs = sdm845_qhp_pciephy_regs_layout, 1602 1603 .start_ctrl = PCS_START | SERDES_START, 1604 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1605 .phy_status = PHYSTATUS, 1606 1607 .has_pwrdn_delay = true, 1608 .pwrdn_delay_min = 995, /* us */ 1609 .pwrdn_delay_max = 1005, /* us */ 1610 }; 1611 1612 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1613 .lanes = 1, 1614 1615 .tables = { 1616 .serdes = sm8250_qmp_pcie_serdes_tbl, 1617 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1618 .tx = sm8250_qmp_pcie_tx_tbl, 1619 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1620 .rx = sm8250_qmp_pcie_rx_tbl, 1621 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1622 .pcs = sm8250_qmp_pcie_pcs_tbl, 1623 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1624 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1625 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1626 }, 1627 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1628 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1629 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1630 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1631 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1632 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1633 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1634 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1635 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1636 }, 1637 .clk_list = sdm845_pciephy_clk_l, 1638 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1639 .reset_list = sdm845_pciephy_reset_l, 1640 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1641 .vreg_list = qmp_phy_vreg_l, 1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1643 .regs = sm8250_pcie_regs_layout, 1644 1645 .start_ctrl = PCS_START | SERDES_START, 1646 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1647 .phy_status = PHYSTATUS, 1648 1649 .has_pwrdn_delay = true, 1650 .pwrdn_delay_min = 995, /* us */ 1651 .pwrdn_delay_max = 1005, /* us */ 1652 }; 1653 1654 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1655 .lanes = 2, 1656 1657 .tables = { 1658 .serdes = sm8250_qmp_pcie_serdes_tbl, 1659 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1660 .tx = sm8250_qmp_pcie_tx_tbl, 1661 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1662 .rx = sm8250_qmp_pcie_rx_tbl, 1663 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1664 .pcs = sm8250_qmp_pcie_pcs_tbl, 1665 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1666 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1667 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1668 }, 1669 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1670 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1671 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1672 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1673 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1674 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1675 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1676 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1677 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1678 }, 1679 .clk_list = sdm845_pciephy_clk_l, 1680 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1681 .reset_list = sdm845_pciephy_reset_l, 1682 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1683 .vreg_list = qmp_phy_vreg_l, 1684 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1685 .regs = sm8250_pcie_regs_layout, 1686 1687 .start_ctrl = PCS_START | SERDES_START, 1688 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1689 .phy_status = PHYSTATUS, 1690 1691 .has_pwrdn_delay = true, 1692 .pwrdn_delay_min = 995, /* us */ 1693 .pwrdn_delay_max = 1005, /* us */ 1694 }; 1695 1696 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1697 .lanes = 1, 1698 1699 .tables = { 1700 .serdes = msm8998_pcie_serdes_tbl, 1701 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1702 .tx = msm8998_pcie_tx_tbl, 1703 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1704 .rx = msm8998_pcie_rx_tbl, 1705 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1706 .pcs = msm8998_pcie_pcs_tbl, 1707 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1708 }, 1709 .clk_list = msm8996_phy_clk_l, 1710 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1711 .reset_list = ipq8074_pciephy_reset_l, 1712 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1713 .vreg_list = qmp_phy_vreg_l, 1714 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1715 .regs = pciephy_regs_layout, 1716 1717 .start_ctrl = SERDES_START | PCS_START, 1718 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1719 .phy_status = PHYSTATUS, 1720 }; 1721 1722 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1723 .lanes = 1, 1724 1725 .tables = { 1726 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1727 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1728 .tx = sc8180x_qmp_pcie_tx_tbl, 1729 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1730 .rx = sc8180x_qmp_pcie_rx_tbl, 1731 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1732 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1733 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1734 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1735 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1736 }, 1737 .clk_list = sdm845_pciephy_clk_l, 1738 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1739 .reset_list = sdm845_pciephy_reset_l, 1740 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1741 .vreg_list = qmp_phy_vreg_l, 1742 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1743 .regs = sm8250_pcie_regs_layout, 1744 1745 .start_ctrl = PCS_START | SERDES_START, 1746 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1747 1748 .has_pwrdn_delay = true, 1749 .pwrdn_delay_min = 995, /* us */ 1750 .pwrdn_delay_max = 1005, /* us */ 1751 }; 1752 1753 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1754 .lanes = 2, 1755 1756 .tables = { 1757 .serdes = sdx55_qmp_pcie_serdes_tbl, 1758 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1759 .tx = sdx55_qmp_pcie_tx_tbl, 1760 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1761 .rx = sdx55_qmp_pcie_rx_tbl, 1762 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1763 .pcs = sdx55_qmp_pcie_pcs_tbl, 1764 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1765 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1766 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1767 }, 1768 .clk_list = sdm845_pciephy_clk_l, 1769 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1770 .reset_list = sdm845_pciephy_reset_l, 1771 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1772 .vreg_list = qmp_phy_vreg_l, 1773 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1774 .regs = sm8250_pcie_regs_layout, 1775 1776 .start_ctrl = PCS_START | SERDES_START, 1777 .pwrdn_ctrl = SW_PWRDN, 1778 .phy_status = PHYSTATUS_4_20, 1779 1780 .has_pwrdn_delay = true, 1781 .pwrdn_delay_min = 995, /* us */ 1782 .pwrdn_delay_max = 1005, /* us */ 1783 }; 1784 1785 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1786 .lanes = 1, 1787 1788 .tables = { 1789 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1790 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1791 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1792 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1793 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1794 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1795 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1796 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1797 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1798 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1799 }, 1800 .clk_list = sdm845_pciephy_clk_l, 1801 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1802 .reset_list = sdm845_pciephy_reset_l, 1803 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1804 .vreg_list = qmp_phy_vreg_l, 1805 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1806 .regs = sm8250_pcie_regs_layout, 1807 1808 .start_ctrl = SERDES_START | PCS_START, 1809 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1810 .phy_status = PHYSTATUS, 1811 1812 .has_pwrdn_delay = true, 1813 .pwrdn_delay_min = 995, /* us */ 1814 .pwrdn_delay_max = 1005, /* us */ 1815 }; 1816 1817 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1818 .lanes = 2, 1819 1820 .tables = { 1821 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1822 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1823 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1824 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1825 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1826 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1827 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1828 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1829 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1830 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1831 }, 1832 .clk_list = sdm845_pciephy_clk_l, 1833 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1834 .reset_list = sdm845_pciephy_reset_l, 1835 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1836 .vreg_list = qmp_phy_vreg_l, 1837 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1838 .regs = sm8250_pcie_regs_layout, 1839 1840 .start_ctrl = SERDES_START | PCS_START, 1841 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1842 .phy_status = PHYSTATUS_4_20, 1843 1844 .has_pwrdn_delay = true, 1845 .pwrdn_delay_min = 995, /* us */ 1846 .pwrdn_delay_max = 1005, /* us */ 1847 }; 1848 1849 static void qmp_pcie_configure_lane(void __iomem *base, 1850 const unsigned int *regs, 1851 const struct qmp_phy_init_tbl tbl[], 1852 int num, 1853 u8 lane_mask) 1854 { 1855 int i; 1856 const struct qmp_phy_init_tbl *t = tbl; 1857 1858 if (!t) 1859 return; 1860 1861 for (i = 0; i < num; i++, t++) { 1862 if (!(t->lane_mask & lane_mask)) 1863 continue; 1864 1865 if (t->in_layout) 1866 writel(t->val, base + regs[t->offset]); 1867 else 1868 writel(t->val, base + t->offset); 1869 } 1870 } 1871 1872 static void qmp_pcie_configure(void __iomem *base, 1873 const unsigned int *regs, 1874 const struct qmp_phy_init_tbl tbl[], 1875 int num) 1876 { 1877 qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); 1878 } 1879 1880 static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1881 { 1882 const struct qmp_phy_cfg *cfg = qphy->cfg; 1883 void __iomem *serdes = qphy->serdes; 1884 1885 if (!tables) 1886 return; 1887 1888 qmp_pcie_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num); 1889 } 1890 1891 static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1892 { 1893 const struct qmp_phy_cfg *cfg = qphy->cfg; 1894 void __iomem *tx = qphy->tx; 1895 void __iomem *rx = qphy->rx; 1896 1897 if (!tables) 1898 return; 1899 1900 qmp_pcie_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1); 1901 1902 if (cfg->lanes >= 2) 1903 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num, 2); 1904 1905 qmp_pcie_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1); 1906 if (cfg->lanes >= 2) 1907 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num, 2); 1908 } 1909 1910 static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1911 { 1912 const struct qmp_phy_cfg *cfg = qphy->cfg; 1913 void __iomem *pcs = qphy->pcs; 1914 void __iomem *pcs_misc = qphy->pcs_misc; 1915 1916 if (!tables) 1917 return; 1918 1919 qmp_pcie_configure(pcs, cfg->regs, 1920 tables->pcs, tables->pcs_num); 1921 qmp_pcie_configure(pcs_misc, cfg->regs, 1922 tables->pcs_misc, tables->pcs_misc_num); 1923 } 1924 1925 static int qmp_pcie_init(struct phy *phy) 1926 { 1927 struct qmp_phy *qphy = phy_get_drvdata(phy); 1928 struct qcom_qmp *qmp = qphy->qmp; 1929 const struct qmp_phy_cfg *cfg = qphy->cfg; 1930 void __iomem *pcs = qphy->pcs; 1931 int ret; 1932 1933 /* turn on regulator supplies */ 1934 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1935 if (ret) { 1936 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1937 return ret; 1938 } 1939 1940 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1941 if (ret) { 1942 dev_err(qmp->dev, "reset assert failed\n"); 1943 goto err_disable_regulators; 1944 } 1945 1946 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1947 if (ret) { 1948 dev_err(qmp->dev, "reset deassert failed\n"); 1949 goto err_disable_regulators; 1950 } 1951 1952 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1953 if (ret) 1954 goto err_assert_reset; 1955 1956 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1957 qphy_setbits(pcs, 1958 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1959 cfg->pwrdn_ctrl); 1960 else 1961 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 1962 cfg->pwrdn_ctrl); 1963 1964 return 0; 1965 1966 err_assert_reset: 1967 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1968 err_disable_regulators: 1969 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1970 1971 return ret; 1972 } 1973 1974 static int qmp_pcie_exit(struct phy *phy) 1975 { 1976 struct qmp_phy *qphy = phy_get_drvdata(phy); 1977 struct qcom_qmp *qmp = qphy->qmp; 1978 const struct qmp_phy_cfg *cfg = qphy->cfg; 1979 1980 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1981 1982 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1983 1984 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1985 1986 return 0; 1987 } 1988 1989 static int qmp_pcie_power_on(struct phy *phy) 1990 { 1991 struct qmp_phy *qphy = phy_get_drvdata(phy); 1992 struct qcom_qmp *qmp = qphy->qmp; 1993 const struct qmp_phy_cfg *cfg = qphy->cfg; 1994 void __iomem *pcs = qphy->pcs; 1995 void __iomem *status; 1996 unsigned int mask, val, ready; 1997 int ret; 1998 1999 qmp_pcie_serdes_init(qphy, &cfg->tables); 2000 qmp_pcie_serdes_init(qphy, cfg->tables_rc); 2001 2002 ret = clk_prepare_enable(qphy->pipe_clk); 2003 if (ret) { 2004 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2005 return ret; 2006 } 2007 2008 /* Tx, Rx, and PCS configurations */ 2009 qmp_pcie_lanes_init(qphy, &cfg->tables); 2010 qmp_pcie_lanes_init(qphy, cfg->tables_rc); 2011 2012 qmp_pcie_pcs_init(qphy, &cfg->tables); 2013 qmp_pcie_pcs_init(qphy, cfg->tables_rc); 2014 2015 /* 2016 * Pull out PHY from POWER DOWN state. 2017 * This is active low enable signal to power-down PHY. 2018 */ 2019 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2020 2021 if (cfg->has_pwrdn_delay) 2022 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2023 2024 /* Pull PHY out of reset state */ 2025 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2026 2027 /* start SerDes and Phy-Coding-Sublayer */ 2028 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2029 2030 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2031 mask = cfg->phy_status; 2032 ready = 0; 2033 2034 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2035 PHY_INIT_COMPLETE_TIMEOUT); 2036 if (ret) { 2037 dev_err(qmp->dev, "phy initialization timed-out\n"); 2038 goto err_disable_pipe_clk; 2039 } 2040 2041 return 0; 2042 2043 err_disable_pipe_clk: 2044 clk_disable_unprepare(qphy->pipe_clk); 2045 2046 return ret; 2047 } 2048 2049 static int qmp_pcie_power_off(struct phy *phy) 2050 { 2051 struct qmp_phy *qphy = phy_get_drvdata(phy); 2052 const struct qmp_phy_cfg *cfg = qphy->cfg; 2053 2054 clk_disable_unprepare(qphy->pipe_clk); 2055 2056 /* PHY reset */ 2057 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2058 2059 /* stop SerDes and Phy-Coding-Sublayer */ 2060 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2061 2062 /* Put PHY into POWER DOWN state: active low */ 2063 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2064 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2065 cfg->pwrdn_ctrl); 2066 } else { 2067 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2068 cfg->pwrdn_ctrl); 2069 } 2070 2071 return 0; 2072 } 2073 2074 static int qmp_pcie_enable(struct phy *phy) 2075 { 2076 int ret; 2077 2078 ret = qmp_pcie_init(phy); 2079 if (ret) 2080 return ret; 2081 2082 ret = qmp_pcie_power_on(phy); 2083 if (ret) 2084 qmp_pcie_exit(phy); 2085 2086 return ret; 2087 } 2088 2089 static int qmp_pcie_disable(struct phy *phy) 2090 { 2091 int ret; 2092 2093 ret = qmp_pcie_power_off(phy); 2094 if (ret) 2095 return ret; 2096 2097 return qmp_pcie_exit(phy); 2098 } 2099 2100 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2101 { 2102 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2103 int num = cfg->num_vregs; 2104 int i; 2105 2106 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2107 if (!qmp->vregs) 2108 return -ENOMEM; 2109 2110 for (i = 0; i < num; i++) 2111 qmp->vregs[i].supply = cfg->vreg_list[i]; 2112 2113 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2114 } 2115 2116 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2117 { 2118 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2119 int i; 2120 int ret; 2121 2122 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2123 sizeof(*qmp->resets), GFP_KERNEL); 2124 if (!qmp->resets) 2125 return -ENOMEM; 2126 2127 for (i = 0; i < cfg->num_resets; i++) 2128 qmp->resets[i].id = cfg->reset_list[i]; 2129 2130 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2131 if (ret) 2132 return dev_err_probe(dev, ret, "failed to get resets\n"); 2133 2134 return 0; 2135 } 2136 2137 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2138 { 2139 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2140 int num = cfg->num_clks; 2141 int i; 2142 2143 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2144 if (!qmp->clks) 2145 return -ENOMEM; 2146 2147 for (i = 0; i < num; i++) 2148 qmp->clks[i].id = cfg->clk_list[i]; 2149 2150 return devm_clk_bulk_get(dev, num, qmp->clks); 2151 } 2152 2153 static void phy_clk_release_provider(void *res) 2154 { 2155 of_clk_del_provider(res); 2156 } 2157 2158 /* 2159 * Register a fixed rate pipe clock. 2160 * 2161 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2162 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2163 * by the PHY driver for its operations. 2164 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2165 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2166 * Below picture shows this relationship. 2167 * 2168 * +---------------+ 2169 * | PHY block |<<---------------------------------------+ 2170 * | | | 2171 * | +-------+ | +-----+ | 2172 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2173 * clk | +-------+ | +-----+ 2174 * +---------------+ 2175 */ 2176 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2177 { 2178 struct clk_fixed_rate *fixed; 2179 struct clk_init_data init = { }; 2180 int ret; 2181 2182 ret = of_property_read_string(np, "clock-output-names", &init.name); 2183 if (ret) { 2184 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2185 return ret; 2186 } 2187 2188 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2189 if (!fixed) 2190 return -ENOMEM; 2191 2192 init.ops = &clk_fixed_rate_ops; 2193 2194 /* 2195 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2196 * unless other frequency is specified in the PHY config. 2197 */ 2198 if (qmp->phys[0]->cfg->pipe_clock_rate) 2199 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2200 else 2201 fixed->fixed_rate = 125000000; 2202 2203 fixed->hw.init = &init; 2204 2205 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2206 if (ret) 2207 return ret; 2208 2209 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2210 if (ret) 2211 return ret; 2212 2213 /* 2214 * Roll a devm action because the clock provider is the child node, but 2215 * the child node is not actually a device. 2216 */ 2217 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2218 } 2219 2220 static const struct phy_ops qmp_pcie_ops = { 2221 .power_on = qmp_pcie_enable, 2222 .power_off = qmp_pcie_disable, 2223 .owner = THIS_MODULE, 2224 }; 2225 2226 static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2227 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2228 { 2229 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2230 struct phy *generic_phy; 2231 struct qmp_phy *qphy; 2232 int ret; 2233 2234 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2235 if (!qphy) 2236 return -ENOMEM; 2237 2238 qphy->cfg = cfg; 2239 qphy->serdes = serdes; 2240 /* 2241 * Get memory resources for each phy lane: 2242 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2243 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2244 * For single lane PHYs: pcs_misc (optional) -> 3. 2245 */ 2246 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2247 if (IS_ERR(qphy->tx)) 2248 return PTR_ERR(qphy->tx); 2249 2250 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2251 qphy->rx = qphy->tx; 2252 else 2253 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2254 if (IS_ERR(qphy->rx)) 2255 return PTR_ERR(qphy->rx); 2256 2257 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2258 if (IS_ERR(qphy->pcs)) 2259 return PTR_ERR(qphy->pcs); 2260 2261 if (cfg->lanes >= 2) { 2262 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2263 if (IS_ERR(qphy->tx2)) 2264 return PTR_ERR(qphy->tx2); 2265 2266 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2267 if (IS_ERR(qphy->rx2)) 2268 return PTR_ERR(qphy->rx2); 2269 2270 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2271 } else { 2272 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2273 } 2274 2275 if (IS_ERR(qphy->pcs_misc) && 2276 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2277 qphy->pcs_misc = qphy->pcs + 0x400; 2278 2279 if (IS_ERR(qphy->pcs_misc)) { 2280 if (cfg->tables.pcs_misc || 2281 (cfg->tables_rc && cfg->tables_rc->pcs_misc)) 2282 return PTR_ERR(qphy->pcs_misc); 2283 } 2284 2285 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2286 if (IS_ERR(qphy->pipe_clk)) { 2287 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2288 "failed to get lane%d pipe clock\n", id); 2289 } 2290 2291 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2292 if (IS_ERR(generic_phy)) { 2293 ret = PTR_ERR(generic_phy); 2294 dev_err(dev, "failed to create qphy %d\n", ret); 2295 return ret; 2296 } 2297 2298 qphy->phy = generic_phy; 2299 qphy->qmp = qmp; 2300 qmp->phys[id] = qphy; 2301 phy_set_drvdata(generic_phy, qphy); 2302 2303 return 0; 2304 } 2305 2306 static const struct of_device_id qmp_pcie_of_match_table[] = { 2307 { 2308 .compatible = "qcom,msm8998-qmp-pcie-phy", 2309 .data = &msm8998_pciephy_cfg, 2310 }, { 2311 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2312 .data = &ipq8074_pciephy_cfg, 2313 }, { 2314 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2315 .data = &ipq8074_pciephy_gen3_cfg, 2316 }, { 2317 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2318 .data = &ipq6018_pciephy_cfg, 2319 }, { 2320 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2321 .data = &sc8180x_pciephy_cfg, 2322 }, { 2323 .compatible = "qcom,sdm845-qhp-pcie-phy", 2324 .data = &sdm845_qhp_pciephy_cfg, 2325 }, { 2326 .compatible = "qcom,sdm845-qmp-pcie-phy", 2327 .data = &sdm845_qmp_pciephy_cfg, 2328 }, { 2329 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2330 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2331 }, { 2332 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2333 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2334 }, { 2335 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2336 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2337 }, { 2338 .compatible = "qcom,sdx55-qmp-pcie-phy", 2339 .data = &sdx55_qmp_pciephy_cfg, 2340 }, { 2341 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2342 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2343 }, { 2344 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2345 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2346 }, 2347 { }, 2348 }; 2349 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2350 2351 static int qmp_pcie_probe(struct platform_device *pdev) 2352 { 2353 struct qcom_qmp *qmp; 2354 struct device *dev = &pdev->dev; 2355 struct device_node *child; 2356 struct phy_provider *phy_provider; 2357 void __iomem *serdes; 2358 const struct qmp_phy_cfg *cfg = NULL; 2359 int num, id; 2360 int ret; 2361 2362 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2363 if (!qmp) 2364 return -ENOMEM; 2365 2366 qmp->dev = dev; 2367 dev_set_drvdata(dev, qmp); 2368 2369 /* Get the specific init parameters of QMP phy */ 2370 cfg = of_device_get_match_data(dev); 2371 if (!cfg) 2372 return -EINVAL; 2373 2374 /* per PHY serdes; usually located at base address */ 2375 serdes = devm_platform_ioremap_resource(pdev, 0); 2376 if (IS_ERR(serdes)) 2377 return PTR_ERR(serdes); 2378 2379 ret = qmp_pcie_clk_init(dev, cfg); 2380 if (ret) 2381 return ret; 2382 2383 ret = qmp_pcie_reset_init(dev, cfg); 2384 if (ret) 2385 return ret; 2386 2387 ret = qmp_pcie_vreg_init(dev, cfg); 2388 if (ret) 2389 return dev_err_probe(dev, ret, 2390 "failed to get regulator supplies\n"); 2391 2392 num = of_get_available_child_count(dev->of_node); 2393 /* do we have a rogue child node ? */ 2394 if (num > 1) 2395 return -EINVAL; 2396 2397 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2398 if (!qmp->phys) 2399 return -ENOMEM; 2400 2401 id = 0; 2402 for_each_available_child_of_node(dev->of_node, child) { 2403 /* Create per-lane phy */ 2404 ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2405 if (ret) { 2406 dev_err(dev, "failed to create lane%d phy, %d\n", 2407 id, ret); 2408 goto err_node_put; 2409 } 2410 2411 /* 2412 * Register the pipe clock provided by phy. 2413 * See function description to see details of this pipe clock. 2414 */ 2415 ret = phy_pipe_clk_register(qmp, child); 2416 if (ret) { 2417 dev_err(qmp->dev, 2418 "failed to register pipe clock source\n"); 2419 goto err_node_put; 2420 } 2421 2422 id++; 2423 } 2424 2425 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2426 2427 return PTR_ERR_OR_ZERO(phy_provider); 2428 2429 err_node_put: 2430 of_node_put(child); 2431 return ret; 2432 } 2433 2434 static struct platform_driver qmp_pcie_driver = { 2435 .probe = qmp_pcie_probe, 2436 .driver = { 2437 .name = "qcom-qmp-pcie-phy", 2438 .of_match_table = qmp_pcie_of_match_table, 2439 }, 2440 }; 2441 2442 module_platform_driver(qmp_pcie_driver); 2443 2444 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2445 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2446 MODULE_LICENSE("GPL v2"); 2447