1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/phy/phy.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * register part of layout ? 47 * if yes, then offset gives index in the reg-layout 48 */ 49 bool in_layout; 50 /* 51 * mask of lanes for which this register is written 52 * for cases when second lane needs different values 53 */ 54 u8 lane_mask; 55 }; 56 57 #define QMP_PHY_INIT_CFG(o, v) \ 58 { \ 59 .offset = o, \ 60 .val = v, \ 61 .lane_mask = 0xff, \ 62 } 63 64 #define QMP_PHY_INIT_CFG_L(o, v) \ 65 { \ 66 .offset = o, \ 67 .val = v, \ 68 .in_layout = true, \ 69 .lane_mask = 0xff, \ 70 } 71 72 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 73 { \ 74 .offset = o, \ 75 .val = v, \ 76 .lane_mask = l, \ 77 } 78 79 /* set of registers with offsets different per-PHY */ 80 enum qphy_reg_layout { 81 /* PCS registers */ 82 QPHY_SW_RESET, 83 QPHY_START_CTRL, 84 QPHY_PCS_STATUS, 85 QPHY_PCS_POWER_DOWN_CONTROL, 86 /* Keep last to ensure regs_layout arrays are properly initialized */ 87 QPHY_LAYOUT_SIZE 88 }; 89 90 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 91 [QPHY_SW_RESET] = 0x00, 92 [QPHY_START_CTRL] = 0x44, 93 [QPHY_PCS_STATUS] = 0x14, 94 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 95 }; 96 97 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 98 [QPHY_SW_RESET] = 0x00, 99 [QPHY_START_CTRL] = 0x08, 100 [QPHY_PCS_STATUS] = 0x174, 101 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 102 }; 103 104 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 105 [QPHY_SW_RESET] = 0x00, 106 [QPHY_START_CTRL] = 0x08, 107 [QPHY_PCS_STATUS] = 0x174, 108 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 109 }; 110 111 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 112 [QPHY_SW_RESET] = 0x00, 113 [QPHY_START_CTRL] = 0x08, 114 [QPHY_PCS_STATUS] = 0x2ac, 115 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 116 }; 117 118 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 119 [QPHY_SW_RESET] = 0x00, 120 [QPHY_START_CTRL] = 0x44, 121 [QPHY_PCS_STATUS] = 0x14, 122 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 123 }; 124 125 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 168 }; 169 170 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 171 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 172 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 173 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 174 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 175 }; 176 177 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 187 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 189 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 190 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 191 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 192 }; 193 194 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 205 }; 206 207 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 208 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 209 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 210 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 211 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 212 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 213 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 214 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 249 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 250 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 251 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 252 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 253 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 254 }; 255 256 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 257 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 258 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 259 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 260 }; 261 262 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 290 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 293 }; 294 295 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 297 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 298 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 299 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 303 }; 304 305 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 309 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 310 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 311 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 312 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 313 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 314 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 315 }; 316 317 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 318 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 319 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 320 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 321 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 322 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 323 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 324 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 326 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 327 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 329 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 330 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 331 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 332 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 334 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 335 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 336 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 337 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 338 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 339 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 340 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 341 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 342 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 343 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 344 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 345 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 346 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 347 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 348 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 349 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 351 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 352 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 353 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 354 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 355 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 357 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 358 }; 359 360 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 361 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 362 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 363 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 364 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 365 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 366 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 367 }; 368 369 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 370 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 371 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 372 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 373 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 374 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 375 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 376 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 377 }; 378 379 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 380 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 381 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 382 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 383 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 385 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 386 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 387 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 388 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 389 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 390 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 391 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 392 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 393 }; 394 395 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 396 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 397 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 398 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 399 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 400 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 401 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 402 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 446 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 447 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 448 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 449 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 450 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 451 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 452 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 453 }; 454 455 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 456 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 457 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 458 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 459 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 460 }; 461 462 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 490 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 491 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 492 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 493 }; 494 495 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 499 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 500 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 501 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 518 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 519 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 520 }; 521 522 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 563 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 564 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 565 }; 566 567 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 568 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 569 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 570 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 571 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 572 }; 573 574 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 587 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 588 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 589 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 590 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 591 }; 592 593 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 595 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 601 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 609 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 613 614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 615 }; 616 617 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 621 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 622 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 623 }; 624 625 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 671 }; 672 673 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 730 }; 731 732 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 733 }; 734 735 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 736 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 737 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 738 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 739 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 740 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 741 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 742 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 743 }; 744 745 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 788 }; 789 790 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 791 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 792 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 793 }; 794 795 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 832 }; 833 834 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 840 }; 841 842 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 845 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 846 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 847 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 848 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 849 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 850 }; 851 852 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 858 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 894 }; 895 896 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 898 }; 899 900 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 901 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 902 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 903 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 904 }; 905 906 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 907 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 908 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 909 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 910 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 911 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 912 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 937 }; 938 939 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 946 }; 947 948 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 949 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 950 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 951 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 952 }; 953 954 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 957 }; 958 959 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 967 }; 968 969 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 972 }; 973 974 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 975 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 976 }; 977 978 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 979 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 980 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 981 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 982 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 983 }; 984 985 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 986 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 987 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 988 }; 989 990 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 991 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 992 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 993 }; 994 995 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1035 }; 1036 1037 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1038 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1041 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1042 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1043 }; 1044 1045 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1046 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1049 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1050 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1051 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1052 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1071 }; 1072 1073 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1074 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1075 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1076 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1077 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1078 }; 1079 1080 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1081 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1082 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1083 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1084 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1085 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1086 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1087 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1088 }; 1089 1090 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1133 }; 1134 1135 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1136 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1141 }; 1142 1143 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1166 }; 1167 1168 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1169 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1170 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1171 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1172 }; 1173 1174 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1175 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1176 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1177 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1178 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1179 }; 1180 1181 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1182 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1195 }; 1196 1197 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = { 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1226 }; 1227 1228 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1229 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1230 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1233 }; 1234 1235 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1236 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1237 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1238 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1260 1261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1262 1263 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1264 1265 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1273 1274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1276 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1283 }; 1284 1285 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1286 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1287 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1288 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1290 }; 1291 1292 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1293 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1294 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1295 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1297 }; 1298 1299 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = { 1300 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1301 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1302 }; 1303 1304 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = { 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1325 }; 1326 1327 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = { 1328 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), 1329 }; 1330 1331 struct qmp_phy_cfg_tables { 1332 const struct qmp_phy_init_tbl *serdes; 1333 int serdes_num; 1334 const struct qmp_phy_init_tbl *tx; 1335 int tx_num; 1336 const struct qmp_phy_init_tbl *rx; 1337 int rx_num; 1338 const struct qmp_phy_init_tbl *pcs; 1339 int pcs_num; 1340 const struct qmp_phy_init_tbl *pcs_misc; 1341 int pcs_misc_num; 1342 }; 1343 1344 /* struct qmp_phy_cfg - per-PHY initialization config */ 1345 struct qmp_phy_cfg { 1346 int lanes; 1347 1348 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1349 const struct qmp_phy_cfg_tables tables; 1350 /* 1351 * Additional init sequences for PHY blocks, providing additional 1352 * register programming. They are used for providing separate sequences 1353 * for the Root Complex and End Point use cases. 1354 * 1355 * If EP mode is not supported, both tables can be left unset. 1356 */ 1357 const struct qmp_phy_cfg_tables *tables_rc; 1358 const struct qmp_phy_cfg_tables *tables_ep; 1359 1360 /* clock ids to be requested */ 1361 const char * const *clk_list; 1362 int num_clks; 1363 /* resets to be requested */ 1364 const char * const *reset_list; 1365 int num_resets; 1366 /* regulators to be requested */ 1367 const char * const *vreg_list; 1368 int num_vregs; 1369 1370 /* array of registers with different offsets */ 1371 const unsigned int *regs; 1372 1373 unsigned int start_ctrl; 1374 unsigned int pwrdn_ctrl; 1375 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1376 unsigned int phy_status; 1377 1378 /* true, if PHY needs delay after POWER_DOWN */ 1379 bool has_pwrdn_delay; 1380 /* power_down delay in usec */ 1381 int pwrdn_delay_min; 1382 int pwrdn_delay_max; 1383 1384 /* QMP PHY pipe clock interface rate */ 1385 unsigned long pipe_clock_rate; 1386 }; 1387 1388 /** 1389 * struct qmp_phy - per-lane phy descriptor 1390 * 1391 * @phy: generic phy 1392 * @cfg: phy specific configuration 1393 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1394 * @tx: iomapped memory space for lane's tx 1395 * @rx: iomapped memory space for lane's rx 1396 * @pcs: iomapped memory space for lane's pcs 1397 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1398 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1399 * @pcs_misc: iomapped memory space for lane's pcs_misc 1400 * @pipe_clk: pipe clock 1401 * @qmp: QMP phy to which this lane belongs 1402 * @mode: currently selected PHY mode 1403 */ 1404 struct qmp_phy { 1405 struct phy *phy; 1406 const struct qmp_phy_cfg *cfg; 1407 void __iomem *serdes; 1408 void __iomem *tx; 1409 void __iomem *rx; 1410 void __iomem *pcs; 1411 void __iomem *tx2; 1412 void __iomem *rx2; 1413 void __iomem *pcs_misc; 1414 struct clk *pipe_clk; 1415 struct qcom_qmp *qmp; 1416 int mode; 1417 }; 1418 1419 /** 1420 * struct qcom_qmp - structure holding QMP phy block attributes 1421 * 1422 * @dev: device 1423 * 1424 * @clks: array of clocks required by phy 1425 * @resets: array of resets required by phy 1426 * @vregs: regulator supplies bulk data 1427 * 1428 * @phys: array of per-lane phy descriptors 1429 */ 1430 struct qcom_qmp { 1431 struct device *dev; 1432 1433 struct clk_bulk_data *clks; 1434 struct reset_control_bulk_data *resets; 1435 struct regulator_bulk_data *vregs; 1436 1437 struct qmp_phy **phys; 1438 }; 1439 1440 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1441 { 1442 u32 reg; 1443 1444 reg = readl(base + offset); 1445 reg |= val; 1446 writel(reg, base + offset); 1447 1448 /* ensure that above write is through */ 1449 readl(base + offset); 1450 } 1451 1452 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1453 { 1454 u32 reg; 1455 1456 reg = readl(base + offset); 1457 reg &= ~val; 1458 writel(reg, base + offset); 1459 1460 /* ensure that above write is through */ 1461 readl(base + offset); 1462 } 1463 1464 /* list of clocks required by phy */ 1465 static const char * const ipq8074_pciephy_clk_l[] = { 1466 "aux", "cfg_ahb", 1467 }; 1468 1469 static const char * const msm8996_phy_clk_l[] = { 1470 "aux", "cfg_ahb", "ref", 1471 }; 1472 1473 1474 static const char * const sdm845_pciephy_clk_l[] = { 1475 "aux", "cfg_ahb", "ref", "refgen", 1476 }; 1477 1478 /* list of regulators */ 1479 static const char * const qmp_phy_vreg_l[] = { 1480 "vdda-phy", "vdda-pll", 1481 }; 1482 1483 /* list of resets */ 1484 static const char * const ipq8074_pciephy_reset_l[] = { 1485 "phy", "common", 1486 }; 1487 1488 static const char * const sdm845_pciephy_reset_l[] = { 1489 "phy", 1490 }; 1491 1492 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1493 .lanes = 1, 1494 1495 .tables = { 1496 .serdes = ipq8074_pcie_serdes_tbl, 1497 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1498 .tx = ipq8074_pcie_tx_tbl, 1499 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1500 .rx = ipq8074_pcie_rx_tbl, 1501 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1502 .pcs = ipq8074_pcie_pcs_tbl, 1503 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1504 }, 1505 .clk_list = ipq8074_pciephy_clk_l, 1506 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1507 .reset_list = ipq8074_pciephy_reset_l, 1508 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1509 .vreg_list = NULL, 1510 .num_vregs = 0, 1511 .regs = pciephy_regs_layout, 1512 1513 .start_ctrl = SERDES_START | PCS_START, 1514 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1515 .phy_status = PHYSTATUS, 1516 1517 .has_pwrdn_delay = true, 1518 .pwrdn_delay_min = 995, /* us */ 1519 .pwrdn_delay_max = 1005, /* us */ 1520 }; 1521 1522 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1523 .lanes = 1, 1524 1525 .tables = { 1526 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1527 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1528 .tx = ipq8074_pcie_gen3_tx_tbl, 1529 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1530 .rx = ipq8074_pcie_gen3_rx_tbl, 1531 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1532 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1533 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1534 }, 1535 .clk_list = ipq8074_pciephy_clk_l, 1536 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1537 .reset_list = ipq8074_pciephy_reset_l, 1538 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1539 .vreg_list = NULL, 1540 .num_vregs = 0, 1541 .regs = ipq_pciephy_gen3_regs_layout, 1542 1543 .start_ctrl = SERDES_START | PCS_START, 1544 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1545 1546 .has_pwrdn_delay = true, 1547 .pwrdn_delay_min = 995, /* us */ 1548 .pwrdn_delay_max = 1005, /* us */ 1549 1550 .pipe_clock_rate = 250000000, 1551 }; 1552 1553 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1554 .lanes = 1, 1555 1556 .tables = { 1557 .serdes = ipq6018_pcie_serdes_tbl, 1558 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1559 .tx = ipq6018_pcie_tx_tbl, 1560 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1561 .rx = ipq6018_pcie_rx_tbl, 1562 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1563 .pcs = ipq6018_pcie_pcs_tbl, 1564 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1565 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1566 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1567 }, 1568 .clk_list = ipq8074_pciephy_clk_l, 1569 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1570 .reset_list = ipq8074_pciephy_reset_l, 1571 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1572 .vreg_list = NULL, 1573 .num_vregs = 0, 1574 .regs = ipq_pciephy_gen3_regs_layout, 1575 1576 .start_ctrl = SERDES_START | PCS_START, 1577 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1578 1579 .has_pwrdn_delay = true, 1580 .pwrdn_delay_min = 995, /* us */ 1581 .pwrdn_delay_max = 1005, /* us */ 1582 }; 1583 1584 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1585 .lanes = 1, 1586 1587 .tables = { 1588 .serdes = sdm845_qmp_pcie_serdes_tbl, 1589 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1590 .tx = sdm845_qmp_pcie_tx_tbl, 1591 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1592 .rx = sdm845_qmp_pcie_rx_tbl, 1593 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1594 .pcs = sdm845_qmp_pcie_pcs_tbl, 1595 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1596 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1597 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1598 }, 1599 .clk_list = sdm845_pciephy_clk_l, 1600 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1601 .reset_list = sdm845_pciephy_reset_l, 1602 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1603 .vreg_list = qmp_phy_vreg_l, 1604 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1605 .regs = sdm845_qmp_pciephy_regs_layout, 1606 1607 .start_ctrl = PCS_START | SERDES_START, 1608 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1609 .phy_status = PHYSTATUS, 1610 1611 .has_pwrdn_delay = true, 1612 .pwrdn_delay_min = 995, /* us */ 1613 .pwrdn_delay_max = 1005, /* us */ 1614 }; 1615 1616 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1617 .lanes = 1, 1618 1619 .tables = { 1620 .serdes = sdm845_qhp_pcie_serdes_tbl, 1621 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1622 .tx = sdm845_qhp_pcie_tx_tbl, 1623 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1624 .rx = sdm845_qhp_pcie_rx_tbl, 1625 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1626 .pcs = sdm845_qhp_pcie_pcs_tbl, 1627 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1628 }, 1629 .clk_list = sdm845_pciephy_clk_l, 1630 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1631 .reset_list = sdm845_pciephy_reset_l, 1632 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1633 .vreg_list = qmp_phy_vreg_l, 1634 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1635 .regs = sdm845_qhp_pciephy_regs_layout, 1636 1637 .start_ctrl = PCS_START | SERDES_START, 1638 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1639 .phy_status = PHYSTATUS, 1640 1641 .has_pwrdn_delay = true, 1642 .pwrdn_delay_min = 995, /* us */ 1643 .pwrdn_delay_max = 1005, /* us */ 1644 }; 1645 1646 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1647 .lanes = 1, 1648 1649 .tables = { 1650 .serdes = sm8250_qmp_pcie_serdes_tbl, 1651 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1652 .tx = sm8250_qmp_pcie_tx_tbl, 1653 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1654 .rx = sm8250_qmp_pcie_rx_tbl, 1655 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1656 .pcs = sm8250_qmp_pcie_pcs_tbl, 1657 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1658 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1659 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1660 }, 1661 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1662 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1663 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1664 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1665 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1666 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1667 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1668 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1669 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1670 }, 1671 .clk_list = sdm845_pciephy_clk_l, 1672 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1673 .reset_list = sdm845_pciephy_reset_l, 1674 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1675 .vreg_list = qmp_phy_vreg_l, 1676 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1677 .regs = sm8250_pcie_regs_layout, 1678 1679 .start_ctrl = PCS_START | SERDES_START, 1680 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1681 .phy_status = PHYSTATUS, 1682 1683 .has_pwrdn_delay = true, 1684 .pwrdn_delay_min = 995, /* us */ 1685 .pwrdn_delay_max = 1005, /* us */ 1686 }; 1687 1688 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1689 .lanes = 2, 1690 1691 .tables = { 1692 .serdes = sm8250_qmp_pcie_serdes_tbl, 1693 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1694 .tx = sm8250_qmp_pcie_tx_tbl, 1695 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1696 .rx = sm8250_qmp_pcie_rx_tbl, 1697 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1698 .pcs = sm8250_qmp_pcie_pcs_tbl, 1699 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1700 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1701 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1702 }, 1703 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1704 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1705 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1706 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1707 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1708 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1709 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1710 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1711 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1712 }, 1713 .clk_list = sdm845_pciephy_clk_l, 1714 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1715 .reset_list = sdm845_pciephy_reset_l, 1716 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1717 .vreg_list = qmp_phy_vreg_l, 1718 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1719 .regs = sm8250_pcie_regs_layout, 1720 1721 .start_ctrl = PCS_START | SERDES_START, 1722 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1723 .phy_status = PHYSTATUS, 1724 1725 .has_pwrdn_delay = true, 1726 .pwrdn_delay_min = 995, /* us */ 1727 .pwrdn_delay_max = 1005, /* us */ 1728 }; 1729 1730 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1731 .lanes = 1, 1732 1733 .tables = { 1734 .serdes = msm8998_pcie_serdes_tbl, 1735 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1736 .tx = msm8998_pcie_tx_tbl, 1737 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1738 .rx = msm8998_pcie_rx_tbl, 1739 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1740 .pcs = msm8998_pcie_pcs_tbl, 1741 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1742 }, 1743 .clk_list = msm8996_phy_clk_l, 1744 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1745 .reset_list = ipq8074_pciephy_reset_l, 1746 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1747 .vreg_list = qmp_phy_vreg_l, 1748 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1749 .regs = pciephy_regs_layout, 1750 1751 .start_ctrl = SERDES_START | PCS_START, 1752 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1753 .phy_status = PHYSTATUS, 1754 }; 1755 1756 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1757 .lanes = 1, 1758 1759 .tables = { 1760 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1761 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1762 .tx = sc8180x_qmp_pcie_tx_tbl, 1763 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1764 .rx = sc8180x_qmp_pcie_rx_tbl, 1765 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1766 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1767 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1768 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1769 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1770 }, 1771 .clk_list = sdm845_pciephy_clk_l, 1772 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1773 .reset_list = sdm845_pciephy_reset_l, 1774 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1775 .vreg_list = qmp_phy_vreg_l, 1776 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1777 .regs = sm8250_pcie_regs_layout, 1778 1779 .start_ctrl = PCS_START | SERDES_START, 1780 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1781 1782 .has_pwrdn_delay = true, 1783 .pwrdn_delay_min = 995, /* us */ 1784 .pwrdn_delay_max = 1005, /* us */ 1785 }; 1786 1787 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1788 .lanes = 2, 1789 1790 .tables = { 1791 .serdes = sdx55_qmp_pcie_serdes_tbl, 1792 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1793 .tx = sdx55_qmp_pcie_tx_tbl, 1794 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1795 .rx = sdx55_qmp_pcie_rx_tbl, 1796 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1797 .pcs = sdx55_qmp_pcie_pcs_tbl, 1798 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1799 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1800 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1801 }, 1802 .clk_list = sdm845_pciephy_clk_l, 1803 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1804 .reset_list = sdm845_pciephy_reset_l, 1805 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1806 .vreg_list = qmp_phy_vreg_l, 1807 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1808 .regs = sm8250_pcie_regs_layout, 1809 1810 .start_ctrl = PCS_START | SERDES_START, 1811 .pwrdn_ctrl = SW_PWRDN, 1812 .phy_status = PHYSTATUS_4_20, 1813 1814 .has_pwrdn_delay = true, 1815 .pwrdn_delay_min = 995, /* us */ 1816 .pwrdn_delay_max = 1005, /* us */ 1817 }; 1818 1819 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1820 .lanes = 1, 1821 1822 .tables = { 1823 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1824 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1825 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1826 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1827 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1828 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1829 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1830 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1831 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1832 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1833 }, 1834 .clk_list = sdm845_pciephy_clk_l, 1835 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1836 .reset_list = sdm845_pciephy_reset_l, 1837 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1838 .vreg_list = qmp_phy_vreg_l, 1839 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1840 .regs = sm8250_pcie_regs_layout, 1841 1842 .start_ctrl = SERDES_START | PCS_START, 1843 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1844 .phy_status = PHYSTATUS, 1845 1846 .has_pwrdn_delay = true, 1847 .pwrdn_delay_min = 995, /* us */ 1848 .pwrdn_delay_max = 1005, /* us */ 1849 }; 1850 1851 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1852 .lanes = 2, 1853 1854 .tables = { 1855 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1856 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1857 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1858 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1859 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1860 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1861 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1862 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1863 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1864 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1865 }, 1866 1867 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1868 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl, 1869 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl), 1870 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl, 1871 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl), 1872 }, 1873 1874 .tables_ep = &(const struct qmp_phy_cfg_tables) { 1875 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl, 1876 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl), 1877 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl, 1878 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), 1879 }, 1880 1881 .clk_list = sdm845_pciephy_clk_l, 1882 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1883 .reset_list = sdm845_pciephy_reset_l, 1884 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1885 .vreg_list = qmp_phy_vreg_l, 1886 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1887 .regs = sm8250_pcie_regs_layout, 1888 1889 .start_ctrl = SERDES_START | PCS_START, 1890 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1891 .phy_status = PHYSTATUS_4_20, 1892 1893 .has_pwrdn_delay = true, 1894 .pwrdn_delay_min = 995, /* us */ 1895 .pwrdn_delay_max = 1005, /* us */ 1896 }; 1897 1898 static void qmp_pcie_configure_lane(void __iomem *base, 1899 const unsigned int *regs, 1900 const struct qmp_phy_init_tbl tbl[], 1901 int num, 1902 u8 lane_mask) 1903 { 1904 int i; 1905 const struct qmp_phy_init_tbl *t = tbl; 1906 1907 if (!t) 1908 return; 1909 1910 for (i = 0; i < num; i++, t++) { 1911 if (!(t->lane_mask & lane_mask)) 1912 continue; 1913 1914 if (t->in_layout) 1915 writel(t->val, base + regs[t->offset]); 1916 else 1917 writel(t->val, base + t->offset); 1918 } 1919 } 1920 1921 static void qmp_pcie_configure(void __iomem *base, 1922 const unsigned int *regs, 1923 const struct qmp_phy_init_tbl tbl[], 1924 int num) 1925 { 1926 qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); 1927 } 1928 1929 static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1930 { 1931 const struct qmp_phy_cfg *cfg = qphy->cfg; 1932 void __iomem *serdes = qphy->serdes; 1933 1934 if (!tables) 1935 return; 1936 1937 qmp_pcie_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num); 1938 } 1939 1940 static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1941 { 1942 const struct qmp_phy_cfg *cfg = qphy->cfg; 1943 void __iomem *tx = qphy->tx; 1944 void __iomem *rx = qphy->rx; 1945 1946 if (!tables) 1947 return; 1948 1949 qmp_pcie_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1); 1950 1951 if (cfg->lanes >= 2) 1952 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num, 2); 1953 1954 qmp_pcie_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1); 1955 if (cfg->lanes >= 2) 1956 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num, 2); 1957 } 1958 1959 static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1960 { 1961 const struct qmp_phy_cfg *cfg = qphy->cfg; 1962 void __iomem *pcs = qphy->pcs; 1963 void __iomem *pcs_misc = qphy->pcs_misc; 1964 1965 if (!tables) 1966 return; 1967 1968 qmp_pcie_configure(pcs, cfg->regs, 1969 tables->pcs, tables->pcs_num); 1970 qmp_pcie_configure(pcs_misc, cfg->regs, 1971 tables->pcs_misc, tables->pcs_misc_num); 1972 } 1973 1974 static int qmp_pcie_init(struct phy *phy) 1975 { 1976 struct qmp_phy *qphy = phy_get_drvdata(phy); 1977 struct qcom_qmp *qmp = qphy->qmp; 1978 const struct qmp_phy_cfg *cfg = qphy->cfg; 1979 int ret; 1980 1981 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1982 if (ret) { 1983 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1984 return ret; 1985 } 1986 1987 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1988 if (ret) { 1989 dev_err(qmp->dev, "reset assert failed\n"); 1990 goto err_disable_regulators; 1991 } 1992 1993 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1994 if (ret) { 1995 dev_err(qmp->dev, "reset deassert failed\n"); 1996 goto err_disable_regulators; 1997 } 1998 1999 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2000 if (ret) 2001 goto err_assert_reset; 2002 2003 return 0; 2004 2005 err_assert_reset: 2006 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2007 err_disable_regulators: 2008 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2009 2010 return ret; 2011 } 2012 2013 static int qmp_pcie_exit(struct phy *phy) 2014 { 2015 struct qmp_phy *qphy = phy_get_drvdata(phy); 2016 struct qcom_qmp *qmp = qphy->qmp; 2017 const struct qmp_phy_cfg *cfg = qphy->cfg; 2018 2019 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2020 2021 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2022 2023 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2024 2025 return 0; 2026 } 2027 2028 static int qmp_pcie_power_on(struct phy *phy) 2029 { 2030 struct qmp_phy *qphy = phy_get_drvdata(phy); 2031 struct qcom_qmp *qmp = qphy->qmp; 2032 const struct qmp_phy_cfg *cfg = qphy->cfg; 2033 const struct qmp_phy_cfg_tables *mode_tables; 2034 void __iomem *pcs = qphy->pcs; 2035 void __iomem *status; 2036 unsigned int mask, val, ready; 2037 int ret; 2038 2039 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2040 cfg->pwrdn_ctrl); 2041 2042 if (qphy->mode == PHY_MODE_PCIE_RC) 2043 mode_tables = cfg->tables_rc; 2044 else 2045 mode_tables = cfg->tables_ep; 2046 2047 qmp_pcie_serdes_init(qphy, &cfg->tables); 2048 qmp_pcie_serdes_init(qphy, mode_tables); 2049 2050 ret = clk_prepare_enable(qphy->pipe_clk); 2051 if (ret) { 2052 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2053 return ret; 2054 } 2055 2056 /* Tx, Rx, and PCS configurations */ 2057 qmp_pcie_lanes_init(qphy, &cfg->tables); 2058 qmp_pcie_lanes_init(qphy, mode_tables); 2059 2060 qmp_pcie_pcs_init(qphy, &cfg->tables); 2061 qmp_pcie_pcs_init(qphy, mode_tables); 2062 2063 if (cfg->has_pwrdn_delay) 2064 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2065 2066 /* Pull PHY out of reset state */ 2067 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2068 2069 /* start SerDes and Phy-Coding-Sublayer */ 2070 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2071 2072 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2073 mask = cfg->phy_status; 2074 ready = 0; 2075 2076 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2077 PHY_INIT_COMPLETE_TIMEOUT); 2078 if (ret) { 2079 dev_err(qmp->dev, "phy initialization timed-out\n"); 2080 goto err_disable_pipe_clk; 2081 } 2082 2083 return 0; 2084 2085 err_disable_pipe_clk: 2086 clk_disable_unprepare(qphy->pipe_clk); 2087 2088 return ret; 2089 } 2090 2091 static int qmp_pcie_power_off(struct phy *phy) 2092 { 2093 struct qmp_phy *qphy = phy_get_drvdata(phy); 2094 const struct qmp_phy_cfg *cfg = qphy->cfg; 2095 2096 clk_disable_unprepare(qphy->pipe_clk); 2097 2098 /* PHY reset */ 2099 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2100 2101 /* stop SerDes and Phy-Coding-Sublayer */ 2102 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2103 2104 /* Put PHY into POWER DOWN state: active low */ 2105 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2106 cfg->pwrdn_ctrl); 2107 2108 return 0; 2109 } 2110 2111 static int qmp_pcie_enable(struct phy *phy) 2112 { 2113 int ret; 2114 2115 ret = qmp_pcie_init(phy); 2116 if (ret) 2117 return ret; 2118 2119 ret = qmp_pcie_power_on(phy); 2120 if (ret) 2121 qmp_pcie_exit(phy); 2122 2123 return ret; 2124 } 2125 2126 static int qmp_pcie_disable(struct phy *phy) 2127 { 2128 int ret; 2129 2130 ret = qmp_pcie_power_off(phy); 2131 if (ret) 2132 return ret; 2133 2134 return qmp_pcie_exit(phy); 2135 } 2136 2137 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2138 { 2139 struct qmp_phy *qphy = phy_get_drvdata(phy); 2140 2141 switch (submode) { 2142 case PHY_MODE_PCIE_RC: 2143 case PHY_MODE_PCIE_EP: 2144 qphy->mode = submode; 2145 break; 2146 default: 2147 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2148 return -EINVAL; 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2155 { 2156 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2157 int num = cfg->num_vregs; 2158 int i; 2159 2160 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2161 if (!qmp->vregs) 2162 return -ENOMEM; 2163 2164 for (i = 0; i < num; i++) 2165 qmp->vregs[i].supply = cfg->vreg_list[i]; 2166 2167 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2168 } 2169 2170 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2171 { 2172 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2173 int i; 2174 int ret; 2175 2176 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2177 sizeof(*qmp->resets), GFP_KERNEL); 2178 if (!qmp->resets) 2179 return -ENOMEM; 2180 2181 for (i = 0; i < cfg->num_resets; i++) 2182 qmp->resets[i].id = cfg->reset_list[i]; 2183 2184 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2185 if (ret) 2186 return dev_err_probe(dev, ret, "failed to get resets\n"); 2187 2188 return 0; 2189 } 2190 2191 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2192 { 2193 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2194 int num = cfg->num_clks; 2195 int i; 2196 2197 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2198 if (!qmp->clks) 2199 return -ENOMEM; 2200 2201 for (i = 0; i < num; i++) 2202 qmp->clks[i].id = cfg->clk_list[i]; 2203 2204 return devm_clk_bulk_get(dev, num, qmp->clks); 2205 } 2206 2207 static void phy_clk_release_provider(void *res) 2208 { 2209 of_clk_del_provider(res); 2210 } 2211 2212 /* 2213 * Register a fixed rate pipe clock. 2214 * 2215 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2216 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2217 * by the PHY driver for its operations. 2218 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2219 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2220 * Below picture shows this relationship. 2221 * 2222 * +---------------+ 2223 * | PHY block |<<---------------------------------------+ 2224 * | | | 2225 * | +-------+ | +-----+ | 2226 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2227 * clk | +-------+ | +-----+ 2228 * +---------------+ 2229 */ 2230 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2231 { 2232 struct clk_fixed_rate *fixed; 2233 struct clk_init_data init = { }; 2234 int ret; 2235 2236 ret = of_property_read_string(np, "clock-output-names", &init.name); 2237 if (ret) { 2238 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2239 return ret; 2240 } 2241 2242 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2243 if (!fixed) 2244 return -ENOMEM; 2245 2246 init.ops = &clk_fixed_rate_ops; 2247 2248 /* 2249 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2250 * unless other frequency is specified in the PHY config. 2251 */ 2252 if (qmp->phys[0]->cfg->pipe_clock_rate) 2253 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2254 else 2255 fixed->fixed_rate = 125000000; 2256 2257 fixed->hw.init = &init; 2258 2259 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2260 if (ret) 2261 return ret; 2262 2263 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2264 if (ret) 2265 return ret; 2266 2267 /* 2268 * Roll a devm action because the clock provider is the child node, but 2269 * the child node is not actually a device. 2270 */ 2271 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2272 } 2273 2274 static const struct phy_ops qmp_pcie_ops = { 2275 .power_on = qmp_pcie_enable, 2276 .power_off = qmp_pcie_disable, 2277 .set_mode = qmp_pcie_set_mode, 2278 .owner = THIS_MODULE, 2279 }; 2280 2281 static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2282 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2283 { 2284 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2285 struct phy *generic_phy; 2286 struct qmp_phy *qphy; 2287 int ret; 2288 2289 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2290 if (!qphy) 2291 return -ENOMEM; 2292 2293 qphy->mode = PHY_MODE_PCIE_RC; 2294 2295 qphy->cfg = cfg; 2296 qphy->serdes = serdes; 2297 /* 2298 * Get memory resources for the PHY: 2299 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2300 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2301 * For single lane PHYs: pcs_misc (optional) -> 3. 2302 */ 2303 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2304 if (IS_ERR(qphy->tx)) 2305 return PTR_ERR(qphy->tx); 2306 2307 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2308 qphy->rx = qphy->tx; 2309 else 2310 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2311 if (IS_ERR(qphy->rx)) 2312 return PTR_ERR(qphy->rx); 2313 2314 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2315 if (IS_ERR(qphy->pcs)) 2316 return PTR_ERR(qphy->pcs); 2317 2318 if (cfg->lanes >= 2) { 2319 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2320 if (IS_ERR(qphy->tx2)) 2321 return PTR_ERR(qphy->tx2); 2322 2323 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2324 if (IS_ERR(qphy->rx2)) 2325 return PTR_ERR(qphy->rx2); 2326 2327 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2328 } else { 2329 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2330 } 2331 2332 if (IS_ERR(qphy->pcs_misc) && 2333 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2334 qphy->pcs_misc = qphy->pcs + 0x400; 2335 2336 if (IS_ERR(qphy->pcs_misc)) { 2337 if (cfg->tables.pcs_misc || 2338 (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2339 (cfg->tables_ep && cfg->tables_ep->pcs_misc)) 2340 return PTR_ERR(qphy->pcs_misc); 2341 } 2342 2343 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2344 if (IS_ERR(qphy->pipe_clk)) { 2345 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2346 "failed to get lane%d pipe clock\n", id); 2347 } 2348 2349 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2350 if (IS_ERR(generic_phy)) { 2351 ret = PTR_ERR(generic_phy); 2352 dev_err(dev, "failed to create qphy %d\n", ret); 2353 return ret; 2354 } 2355 2356 qphy->phy = generic_phy; 2357 qphy->qmp = qmp; 2358 qmp->phys[id] = qphy; 2359 phy_set_drvdata(generic_phy, qphy); 2360 2361 return 0; 2362 } 2363 2364 static const struct of_device_id qmp_pcie_of_match_table[] = { 2365 { 2366 .compatible = "qcom,msm8998-qmp-pcie-phy", 2367 .data = &msm8998_pciephy_cfg, 2368 }, { 2369 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2370 .data = &ipq8074_pciephy_cfg, 2371 }, { 2372 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2373 .data = &ipq8074_pciephy_gen3_cfg, 2374 }, { 2375 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2376 .data = &ipq6018_pciephy_cfg, 2377 }, { 2378 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2379 .data = &sc8180x_pciephy_cfg, 2380 }, { 2381 .compatible = "qcom,sdm845-qhp-pcie-phy", 2382 .data = &sdm845_qhp_pciephy_cfg, 2383 }, { 2384 .compatible = "qcom,sdm845-qmp-pcie-phy", 2385 .data = &sdm845_qmp_pciephy_cfg, 2386 }, { 2387 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2388 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2389 }, { 2390 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2391 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2392 }, { 2393 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2394 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2395 }, { 2396 .compatible = "qcom,sdx55-qmp-pcie-phy", 2397 .data = &sdx55_qmp_pciephy_cfg, 2398 }, { 2399 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2400 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2401 }, { 2402 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2403 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2404 }, 2405 { }, 2406 }; 2407 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2408 2409 static int qmp_pcie_probe(struct platform_device *pdev) 2410 { 2411 struct qcom_qmp *qmp; 2412 struct device *dev = &pdev->dev; 2413 struct device_node *child; 2414 struct phy_provider *phy_provider; 2415 void __iomem *serdes; 2416 const struct qmp_phy_cfg *cfg = NULL; 2417 int num, id; 2418 int ret; 2419 2420 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2421 if (!qmp) 2422 return -ENOMEM; 2423 2424 qmp->dev = dev; 2425 dev_set_drvdata(dev, qmp); 2426 2427 cfg = of_device_get_match_data(dev); 2428 if (!cfg) 2429 return -EINVAL; 2430 2431 serdes = devm_platform_ioremap_resource(pdev, 0); 2432 if (IS_ERR(serdes)) 2433 return PTR_ERR(serdes); 2434 2435 ret = qmp_pcie_clk_init(dev, cfg); 2436 if (ret) 2437 return ret; 2438 2439 ret = qmp_pcie_reset_init(dev, cfg); 2440 if (ret) 2441 return ret; 2442 2443 ret = qmp_pcie_vreg_init(dev, cfg); 2444 if (ret) 2445 return ret; 2446 2447 num = of_get_available_child_count(dev->of_node); 2448 /* do we have a rogue child node ? */ 2449 if (num > 1) 2450 return -EINVAL; 2451 2452 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2453 if (!qmp->phys) 2454 return -ENOMEM; 2455 2456 id = 0; 2457 for_each_available_child_of_node(dev->of_node, child) { 2458 /* Create per-lane phy */ 2459 ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2460 if (ret) { 2461 dev_err(dev, "failed to create lane%d phy, %d\n", 2462 id, ret); 2463 goto err_node_put; 2464 } 2465 2466 /* 2467 * Register the pipe clock provided by phy. 2468 * See function description to see details of this pipe clock. 2469 */ 2470 ret = phy_pipe_clk_register(qmp, child); 2471 if (ret) { 2472 dev_err(qmp->dev, 2473 "failed to register pipe clock source\n"); 2474 goto err_node_put; 2475 } 2476 2477 id++; 2478 } 2479 2480 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2481 2482 return PTR_ERR_OR_ZERO(phy_provider); 2483 2484 err_node_put: 2485 of_node_put(child); 2486 return ret; 2487 } 2488 2489 static struct platform_driver qmp_pcie_driver = { 2490 .probe = qmp_pcie_probe, 2491 .driver = { 2492 .name = "qcom-qmp-pcie-phy", 2493 .of_match_table = qmp_pcie_of_match_table, 2494 }, 2495 }; 2496 2497 module_platform_driver(qmp_pcie_driver); 2498 2499 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2500 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2501 MODULE_LICENSE("GPL v2"); 2502