1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/pcie.h> 18 #include <linux/phy/phy.h> 19 #include <linux/platform_device.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/reset.h> 22 #include <linux/slab.h> 23 24 #include <dt-bindings/phy/phy.h> 25 26 #include "phy-qcom-qmp.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 #define REFCLK_DRV_DSBL BIT(1) 33 /* QPHY_START_CONTROL bits */ 34 #define SERDES_START BIT(0) 35 #define PCS_START BIT(1) 36 /* QPHY_PCS_STATUS bit */ 37 #define PHYSTATUS BIT(6) 38 #define PHYSTATUS_4_20 BIT(7) 39 40 #define PHY_INIT_COMPLETE_TIMEOUT 10000 41 42 struct qmp_phy_init_tbl { 43 unsigned int offset; 44 unsigned int val; 45 /* 46 * register part of layout ? 47 * if yes, then offset gives index in the reg-layout 48 */ 49 bool in_layout; 50 /* 51 * mask of lanes for which this register is written 52 * for cases when second lane needs different values 53 */ 54 u8 lane_mask; 55 }; 56 57 #define QMP_PHY_INIT_CFG(o, v) \ 58 { \ 59 .offset = o, \ 60 .val = v, \ 61 .lane_mask = 0xff, \ 62 } 63 64 #define QMP_PHY_INIT_CFG_L(o, v) \ 65 { \ 66 .offset = o, \ 67 .val = v, \ 68 .in_layout = true, \ 69 .lane_mask = 0xff, \ 70 } 71 72 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 73 { \ 74 .offset = o, \ 75 .val = v, \ 76 .lane_mask = l, \ 77 } 78 79 /* set of registers with offsets different per-PHY */ 80 enum qphy_reg_layout { 81 /* Common block control registers */ 82 QPHY_COM_SW_RESET, 83 QPHY_COM_POWER_DOWN_CONTROL, 84 QPHY_COM_START_CONTROL, 85 QPHY_COM_PCS_READY_STATUS, 86 /* PCS registers */ 87 QPHY_SW_RESET, 88 QPHY_START_CTRL, 89 QPHY_PCS_STATUS, 90 QPHY_PCS_POWER_DOWN_CONTROL, 91 /* Keep last to ensure regs_layout arrays are properly initialized */ 92 QPHY_LAYOUT_SIZE 93 }; 94 95 static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { 96 [QPHY_SW_RESET] = 0x00, 97 [QPHY_START_CTRL] = 0x44, 98 [QPHY_PCS_STATUS] = 0x14, 99 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 100 }; 101 102 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 103 [QPHY_COM_SW_RESET] = 0x400, 104 [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, 105 [QPHY_COM_START_CONTROL] = 0x408, 106 [QPHY_COM_PCS_READY_STATUS] = 0x448, 107 [QPHY_SW_RESET] = 0x00, 108 [QPHY_START_CTRL] = 0x08, 109 [QPHY_PCS_STATUS] = 0x174, 110 }; 111 112 static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 113 [QPHY_SW_RESET] = 0x00, 114 [QPHY_START_CTRL] = 0x08, 115 [QPHY_PCS_STATUS] = 0x174, 116 }; 117 118 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { 119 [QPHY_SW_RESET] = 0x00, 120 [QPHY_START_CTRL] = 0x08, 121 [QPHY_PCS_STATUS] = 0x2ac, 122 }; 123 124 static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { 125 [QPHY_SW_RESET] = 0x00, 126 [QPHY_START_CTRL] = 0x44, 127 [QPHY_PCS_STATUS] = 0x14, 128 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 129 }; 130 131 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { 132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f), 135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03), 150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55), 151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55), 152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08), 157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34), 159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 162 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07), 163 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 164 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 165 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 166 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 167 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 168 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 169 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 170 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 171 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 172 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 173 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 174 }; 175 176 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = { 177 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 178 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 179 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 180 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 181 }; 182 183 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = { 184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c), 186 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 187 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a), 188 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 189 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 190 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 191 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 192 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 193 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00), 194 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 195 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 196 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 197 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 198 }; 199 200 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = { 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 211 }; 212 213 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = { 214 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d), 215 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01), 216 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a), 217 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05), 218 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08), 219 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04), 220 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 221 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 222 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 223 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 224 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 225 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4), 226 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14), 227 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa), 228 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29), 229 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 230 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09), 231 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09), 232 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 233 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 234 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 235 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 236 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 237 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 238 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 239 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 240 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68), 241 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53), 242 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab), 243 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa), 244 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02), 245 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55), 246 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55), 247 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05), 248 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0), 249 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0), 250 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 251 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 252 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 253 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 254 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 255 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), 256 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 258 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 259 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 260 }; 261 262 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = { 263 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 264 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 265 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 266 }; 267 268 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = { 269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), 274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), 276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), 285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 287 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 288 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 289 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 290 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 291 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 292 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 293 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 294 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 295 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 296 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 297 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 298 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 299 }; 300 301 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = { 302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 309 }; 310 311 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = { 312 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 313 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 314 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 315 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 316 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 317 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 318 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 319 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 320 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 321 }; 322 323 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = { 324 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 325 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), 326 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf), 327 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1), 328 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0), 329 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 330 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f), 331 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6), 332 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf), 333 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0), 334 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1), 335 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20), 336 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa), 337 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 338 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa), 339 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa), 340 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 341 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3), 342 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 343 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 344 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0), 345 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD), 346 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04), 347 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33), 348 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2), 349 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f), 350 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb), 351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 352 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 353 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0), 354 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 355 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1), 356 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1), 357 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 358 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1), 359 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2), 360 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0), 361 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f), 362 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19), 363 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19), 364 }; 365 366 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = { 367 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 368 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6), 369 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2), 370 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 371 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36), 372 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a), 373 }; 374 375 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = { 376 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c), 377 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 378 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1), 379 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0), 380 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb), 381 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 382 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4), 383 }; 384 385 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = { 386 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4), 387 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0), 388 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40), 389 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0), 390 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40), 391 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0), 392 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40), 393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99), 395 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15), 396 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe), 397 QMP_PHY_INIT_CFG_L(QPHY_SW_RESET, 0x0), 398 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3), 399 }; 400 401 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = { 402 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), 403 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), 404 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31), 405 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), 406 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), 407 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), 408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), 409 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), 410 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01), 411 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04), 412 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 413 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff), 414 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f), 415 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30), 416 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21), 417 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82), 418 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03), 419 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355), 420 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555), 421 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a), 422 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a), 423 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb), 424 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16), 425 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28), 426 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0), 427 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40), 428 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), 429 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), 430 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 431 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20), 432 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa), 433 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32), 434 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02), 435 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), 436 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08), 437 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa), 438 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1), 439 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68), 440 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2), 441 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa), 442 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab), 443 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 444 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34), 445 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414), 446 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b), 447 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16), 448 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28), 449 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0), 450 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40), 451 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), 452 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), 453 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), 454 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0), 455 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), 456 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19), 457 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28), 458 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90), 459 }; 460 461 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = { 462 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 463 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 464 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), 465 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06), 466 }; 467 468 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = { 469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe), 473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4), 474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), 479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), 481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), 482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), 484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 485 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), 486 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), 487 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 488 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), 489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 490 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), 491 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2), 492 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), 493 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), 494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), 495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 498 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), 499 }; 500 501 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = { 502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83), 503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9), 504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42), 505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40), 506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01), 507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0), 508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1), 509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0), 510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00), 513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), 515 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb), 516 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 517 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52), 518 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50), 519 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a), 520 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6), 521 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), 522 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 523 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01), 524 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 525 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 526 }; 527 528 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19), 544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90), 545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d), 551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04), 552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33), 558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 560 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04), 561 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 562 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 563 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09), 564 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 565 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40), 566 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 567 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02), 568 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 569 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e), 570 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15), 571 }; 572 573 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { 574 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02), 575 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 576 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 577 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 578 }; 579 580 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { 581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10), 583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 586 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 587 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 588 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04), 589 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04), 590 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71), 591 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 592 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59), 593 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 594 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 595 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71), 596 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40), 597 }; 598 599 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04), 601 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 607 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20), 612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00), 613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01), 614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73), 615 616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb), 617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03), 618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d), 619 620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00), 621 }; 622 623 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { 624 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52), 625 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10), 626 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a), 627 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06), 628 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 629 }; 630 631 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { 632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27), 633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01), 634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31), 635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01), 636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde), 637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07), 638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06), 640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18), 641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0), 642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c), 643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20), 644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14), 645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34), 646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06), 647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06), 648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16), 649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16), 650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36), 651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36), 652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05), 653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42), 654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82), 655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68), 656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55), 657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55), 658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03), 659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab), 660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa), 661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02), 662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10), 665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04), 666 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30), 667 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04), 668 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73), 669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c), 670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15), 671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04), 672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01), 673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22), 674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00), 675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20), 676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07), 677 }; 678 679 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { 680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00), 681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d), 682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01), 683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a), 684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f), 685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09), 686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09), 687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b), 688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01), 689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07), 690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31), 691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31), 692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03), 693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02), 694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00), 695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12), 696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25), 697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00), 698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05), 699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01), 700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26), 701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12), 702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04), 703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04), 704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09), 705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15), 706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28), 707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f), 708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07), 709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04), 710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70), 711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b), 712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08), 713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a), 714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03), 715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04), 716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04), 717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c), 718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02), 719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c), 720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e), 721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f), 722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01), 723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0), 724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08), 725 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01), 726 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3), 727 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00), 728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc), 729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f), 730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15), 731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c), 732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f), 733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04), 734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20), 735 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01), 736 }; 737 738 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { 739 }; 740 741 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { 742 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f), 743 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50), 744 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19), 745 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07), 746 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17), 747 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09), 748 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f), 749 }; 750 751 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = { 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 780 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 781 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 782 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 783 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 784 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 785 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 786 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 787 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 788 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 789 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 790 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 791 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 792 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 793 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 794 }; 795 796 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = { 797 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 798 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5), 799 }; 800 801 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = { 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39), 819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39), 824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb), 829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75), 830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 832 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 833 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0), 834 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05), 836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 837 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 838 }; 839 840 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = { 841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 842 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 843 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 844 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 845 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01), 846 }; 847 848 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = { 849 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 850 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 851 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 852 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 853 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 854 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 855 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 856 }; 857 858 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = { 859 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), 860 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), 861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), 864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), 866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), 867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 868 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 869 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 870 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03), 871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55), 872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55), 873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a), 874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a), 875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68), 876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa), 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 895 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 898 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06), 899 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), 900 }; 901 902 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = { 903 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07), 904 }; 905 906 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = { 907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 910 }; 911 912 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = { 913 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 914 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), 915 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b), 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), 943 }; 944 945 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = { 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00), 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14), 951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30), 952 }; 953 954 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = { 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), 957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b), 958 }; 959 960 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = { 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d), 962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12), 963 }; 964 965 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = { 966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), 969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), 970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), 972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 973 }; 974 975 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f), 978 }; 979 980 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = { 981 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 982 }; 983 984 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = { 985 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 986 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15), 988 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 989 }; 990 991 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = { 992 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05), 993 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), 994 }; 995 996 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = { 997 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), 998 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), 999 }; 1000 1001 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = { 1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b), 1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56), 1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d), 1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b), 1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f), 1040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22), 1041 }; 1042 1043 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = { 1044 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05), 1045 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6), 1046 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13), 1047 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00), 1048 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00), 1049 }; 1050 1051 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = { 1052 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c), 1053 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16), 1054 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f), 1055 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55), 1056 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c), 1057 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00), 1058 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08), 1059 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27), 1060 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a), 1061 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9), 1066 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf), 1067 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce), 1068 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62), 1069 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1076 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12), 1077 }; 1078 1079 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = { 1080 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77), 1081 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01), 1082 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16), 1083 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02), 1084 }; 1085 1086 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = { 1087 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17), 1088 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13), 1089 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13), 1090 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01), 1091 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1092 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00), 1093 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00), 1094 }; 1095 1096 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = { 1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1139 }; 1140 1141 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = { 1142 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04), 1147 }; 1148 1149 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = { 1150 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1172 }; 1173 1174 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = { 1175 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77), 1176 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b), 1177 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05), 1178 }; 1179 1180 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = { 1181 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1182 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), 1183 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f), 1184 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1185 }; 1186 1187 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = { 1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08), 1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46), 1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04), 1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a), 1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a), 1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14), 1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34), 1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0), 1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55), 1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03), 1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55), 1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34), 1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12), 1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88), 1225 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20), 1226 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06), 1227 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14), 1228 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f), 1229 }; 1230 1231 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = { 1232 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1236 }; 1237 1238 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { 1239 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16), 1240 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37), 1263 1264 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05), 1265 1266 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f), 1267 1268 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f), 1271 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f), 1272 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f), 1273 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f), 1274 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f), 1275 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f), 1276 1277 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c), 1278 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a), 1279 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a), 1280 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b), 1281 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10), 1282 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00), 1283 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f), 1284 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00), 1285 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f), 1286 }; 1287 1288 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { 1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), 1290 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), 1291 QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), 1292 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), 1293 }; 1294 1295 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { 1296 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), 1297 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), 1298 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02), 1299 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16), 1300 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28), 1301 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), 1302 }; 1303 1304 struct qmp_phy_cfg_tables { 1305 const struct qmp_phy_init_tbl *serdes; 1306 int serdes_num; 1307 const struct qmp_phy_init_tbl *tx; 1308 int tx_num; 1309 const struct qmp_phy_init_tbl *rx; 1310 int rx_num; 1311 const struct qmp_phy_init_tbl *pcs; 1312 int pcs_num; 1313 const struct qmp_phy_init_tbl *pcs_misc; 1314 int pcs_misc_num; 1315 }; 1316 1317 /* struct qmp_phy_cfg - per-PHY initialization config */ 1318 struct qmp_phy_cfg { 1319 int lanes; 1320 1321 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1322 const struct qmp_phy_cfg_tables tables; 1323 /* 1324 * Additional init sequences for PHY blocks, providing additional 1325 * register programming. They are used for providing separate sequences 1326 * for the Root Complex and End Point use cases. 1327 * 1328 * If EP mode is not supported, both tables can be left unset. 1329 */ 1330 const struct qmp_phy_cfg_tables *tables_rc; 1331 const struct qmp_phy_cfg_tables *tables_ep; 1332 1333 /* clock ids to be requested */ 1334 const char * const *clk_list; 1335 int num_clks; 1336 /* resets to be requested */ 1337 const char * const *reset_list; 1338 int num_resets; 1339 /* regulators to be requested */ 1340 const char * const *vreg_list; 1341 int num_vregs; 1342 1343 /* array of registers with different offsets */ 1344 const unsigned int *regs; 1345 1346 unsigned int start_ctrl; 1347 unsigned int pwrdn_ctrl; 1348 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */ 1349 unsigned int phy_status; 1350 1351 /* true, if PHY needs delay after POWER_DOWN */ 1352 bool has_pwrdn_delay; 1353 /* power_down delay in usec */ 1354 int pwrdn_delay_min; 1355 int pwrdn_delay_max; 1356 1357 /* QMP PHY pipe clock interface rate */ 1358 unsigned long pipe_clock_rate; 1359 }; 1360 1361 /** 1362 * struct qmp_phy - per-lane phy descriptor 1363 * 1364 * @phy: generic phy 1365 * @cfg: phy specific configuration 1366 * @serdes: iomapped memory space for phy's serdes (i.e. PLL) 1367 * @tx: iomapped memory space for lane's tx 1368 * @rx: iomapped memory space for lane's rx 1369 * @pcs: iomapped memory space for lane's pcs 1370 * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs) 1371 * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs) 1372 * @pcs_misc: iomapped memory space for lane's pcs_misc 1373 * @pipe_clk: pipe clock 1374 * @qmp: QMP phy to which this lane belongs 1375 * @mode: currently selected PHY mode 1376 */ 1377 struct qmp_phy { 1378 struct phy *phy; 1379 const struct qmp_phy_cfg *cfg; 1380 void __iomem *serdes; 1381 void __iomem *tx; 1382 void __iomem *rx; 1383 void __iomem *pcs; 1384 void __iomem *tx2; 1385 void __iomem *rx2; 1386 void __iomem *pcs_misc; 1387 struct clk *pipe_clk; 1388 struct qcom_qmp *qmp; 1389 int mode; 1390 }; 1391 1392 /** 1393 * struct qcom_qmp - structure holding QMP phy block attributes 1394 * 1395 * @dev: device 1396 * 1397 * @clks: array of clocks required by phy 1398 * @resets: array of resets required by phy 1399 * @vregs: regulator supplies bulk data 1400 * 1401 * @phys: array of per-lane phy descriptors 1402 */ 1403 struct qcom_qmp { 1404 struct device *dev; 1405 1406 struct clk_bulk_data *clks; 1407 struct reset_control_bulk_data *resets; 1408 struct regulator_bulk_data *vregs; 1409 1410 struct qmp_phy **phys; 1411 }; 1412 1413 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1414 { 1415 u32 reg; 1416 1417 reg = readl(base + offset); 1418 reg |= val; 1419 writel(reg, base + offset); 1420 1421 /* ensure that above write is through */ 1422 readl(base + offset); 1423 } 1424 1425 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1426 { 1427 u32 reg; 1428 1429 reg = readl(base + offset); 1430 reg &= ~val; 1431 writel(reg, base + offset); 1432 1433 /* ensure that above write is through */ 1434 readl(base + offset); 1435 } 1436 1437 /* list of clocks required by phy */ 1438 static const char * const msm8996_phy_clk_l[] = { 1439 "aux", "cfg_ahb", "ref", 1440 }; 1441 1442 1443 static const char * const sdm845_pciephy_clk_l[] = { 1444 "aux", "cfg_ahb", "ref", "refgen", 1445 }; 1446 1447 /* list of regulators */ 1448 static const char * const qmp_phy_vreg_l[] = { 1449 "vdda-phy", "vdda-pll", 1450 }; 1451 1452 static const char * const ipq8074_pciephy_clk_l[] = { 1453 "aux", "cfg_ahb", 1454 }; 1455 1456 /* list of resets */ 1457 static const char * const ipq8074_pciephy_reset_l[] = { 1458 "phy", "common", 1459 }; 1460 1461 static const char * const sdm845_pciephy_reset_l[] = { 1462 "phy", 1463 }; 1464 1465 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { 1466 .lanes = 1, 1467 1468 .tables = { 1469 .serdes = ipq8074_pcie_serdes_tbl, 1470 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), 1471 .tx = ipq8074_pcie_tx_tbl, 1472 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl), 1473 .rx = ipq8074_pcie_rx_tbl, 1474 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl), 1475 .pcs = ipq8074_pcie_pcs_tbl, 1476 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), 1477 }, 1478 .clk_list = ipq8074_pciephy_clk_l, 1479 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1480 .reset_list = ipq8074_pciephy_reset_l, 1481 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1482 .vreg_list = NULL, 1483 .num_vregs = 0, 1484 .regs = pciephy_regs_layout, 1485 1486 .start_ctrl = SERDES_START | PCS_START, 1487 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1488 .phy_status = PHYSTATUS, 1489 1490 .has_pwrdn_delay = true, 1491 .pwrdn_delay_min = 995, /* us */ 1492 .pwrdn_delay_max = 1005, /* us */ 1493 }; 1494 1495 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { 1496 .lanes = 1, 1497 1498 .tables = { 1499 .serdes = ipq8074_pcie_gen3_serdes_tbl, 1500 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), 1501 .tx = ipq8074_pcie_gen3_tx_tbl, 1502 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), 1503 .rx = ipq8074_pcie_gen3_rx_tbl, 1504 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl), 1505 .pcs = ipq8074_pcie_gen3_pcs_tbl, 1506 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl), 1507 }, 1508 .clk_list = ipq8074_pciephy_clk_l, 1509 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1510 .reset_list = ipq8074_pciephy_reset_l, 1511 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1512 .vreg_list = NULL, 1513 .num_vregs = 0, 1514 .regs = ipq_pciephy_gen3_regs_layout, 1515 1516 .start_ctrl = SERDES_START | PCS_START, 1517 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1518 1519 .has_pwrdn_delay = true, 1520 .pwrdn_delay_min = 995, /* us */ 1521 .pwrdn_delay_max = 1005, /* us */ 1522 1523 .pipe_clock_rate = 250000000, 1524 }; 1525 1526 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { 1527 .lanes = 1, 1528 1529 .tables = { 1530 .serdes = ipq6018_pcie_serdes_tbl, 1531 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), 1532 .tx = ipq6018_pcie_tx_tbl, 1533 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), 1534 .rx = ipq6018_pcie_rx_tbl, 1535 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl), 1536 .pcs = ipq6018_pcie_pcs_tbl, 1537 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), 1538 .pcs_misc = ipq6018_pcie_pcs_misc_tbl, 1539 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), 1540 }, 1541 .clk_list = ipq8074_pciephy_clk_l, 1542 .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), 1543 .reset_list = ipq8074_pciephy_reset_l, 1544 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1545 .vreg_list = NULL, 1546 .num_vregs = 0, 1547 .regs = ipq_pciephy_gen3_regs_layout, 1548 1549 .start_ctrl = SERDES_START | PCS_START, 1550 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1551 1552 .has_pwrdn_delay = true, 1553 .pwrdn_delay_min = 995, /* us */ 1554 .pwrdn_delay_max = 1005, /* us */ 1555 }; 1556 1557 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { 1558 .lanes = 1, 1559 1560 .tables = { 1561 .serdes = sdm845_qmp_pcie_serdes_tbl, 1562 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), 1563 .tx = sdm845_qmp_pcie_tx_tbl, 1564 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl), 1565 .rx = sdm845_qmp_pcie_rx_tbl, 1566 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl), 1567 .pcs = sdm845_qmp_pcie_pcs_tbl, 1568 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl), 1569 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, 1570 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), 1571 }, 1572 .clk_list = sdm845_pciephy_clk_l, 1573 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1574 .reset_list = sdm845_pciephy_reset_l, 1575 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1576 .vreg_list = qmp_phy_vreg_l, 1577 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1578 .regs = sdm845_qmp_pciephy_regs_layout, 1579 1580 .start_ctrl = PCS_START | SERDES_START, 1581 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1582 .phy_status = PHYSTATUS, 1583 1584 .has_pwrdn_delay = true, 1585 .pwrdn_delay_min = 995, /* us */ 1586 .pwrdn_delay_max = 1005, /* us */ 1587 }; 1588 1589 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { 1590 .lanes = 1, 1591 1592 .tables = { 1593 .serdes = sdm845_qhp_pcie_serdes_tbl, 1594 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), 1595 .tx = sdm845_qhp_pcie_tx_tbl, 1596 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl), 1597 .rx = sdm845_qhp_pcie_rx_tbl, 1598 .rx_num = ARRAY_SIZE(sdm845_qhp_pcie_rx_tbl), 1599 .pcs = sdm845_qhp_pcie_pcs_tbl, 1600 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), 1601 }, 1602 .clk_list = sdm845_pciephy_clk_l, 1603 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1604 .reset_list = sdm845_pciephy_reset_l, 1605 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1606 .vreg_list = qmp_phy_vreg_l, 1607 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1608 .regs = sdm845_qhp_pciephy_regs_layout, 1609 1610 .start_ctrl = PCS_START | SERDES_START, 1611 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1612 .phy_status = PHYSTATUS, 1613 1614 .has_pwrdn_delay = true, 1615 .pwrdn_delay_min = 995, /* us */ 1616 .pwrdn_delay_max = 1005, /* us */ 1617 }; 1618 1619 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { 1620 .lanes = 1, 1621 1622 .tables = { 1623 .serdes = sm8250_qmp_pcie_serdes_tbl, 1624 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1625 .tx = sm8250_qmp_pcie_tx_tbl, 1626 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1627 .rx = sm8250_qmp_pcie_rx_tbl, 1628 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1629 .pcs = sm8250_qmp_pcie_pcs_tbl, 1630 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1631 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1632 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1633 }, 1634 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1635 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl, 1636 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl), 1637 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl, 1638 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl), 1639 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl, 1640 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl), 1641 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, 1642 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), 1643 }, 1644 .clk_list = sdm845_pciephy_clk_l, 1645 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1646 .reset_list = sdm845_pciephy_reset_l, 1647 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1648 .vreg_list = qmp_phy_vreg_l, 1649 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1650 .regs = sm8250_pcie_regs_layout, 1651 1652 .start_ctrl = PCS_START | SERDES_START, 1653 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1654 .phy_status = PHYSTATUS, 1655 1656 .has_pwrdn_delay = true, 1657 .pwrdn_delay_min = 995, /* us */ 1658 .pwrdn_delay_max = 1005, /* us */ 1659 }; 1660 1661 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { 1662 .lanes = 2, 1663 1664 .tables = { 1665 .serdes = sm8250_qmp_pcie_serdes_tbl, 1666 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), 1667 .tx = sm8250_qmp_pcie_tx_tbl, 1668 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl), 1669 .rx = sm8250_qmp_pcie_rx_tbl, 1670 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl), 1671 .pcs = sm8250_qmp_pcie_pcs_tbl, 1672 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl), 1673 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl, 1674 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl), 1675 }, 1676 .tables_rc = &(const struct qmp_phy_cfg_tables) { 1677 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl, 1678 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl), 1679 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl, 1680 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl), 1681 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl, 1682 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl), 1683 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, 1684 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), 1685 }, 1686 .clk_list = sdm845_pciephy_clk_l, 1687 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1688 .reset_list = sdm845_pciephy_reset_l, 1689 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1690 .vreg_list = qmp_phy_vreg_l, 1691 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1692 .regs = sm8250_pcie_regs_layout, 1693 1694 .start_ctrl = PCS_START | SERDES_START, 1695 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1696 .phy_status = PHYSTATUS, 1697 1698 .has_pwrdn_delay = true, 1699 .pwrdn_delay_min = 995, /* us */ 1700 .pwrdn_delay_max = 1005, /* us */ 1701 }; 1702 1703 static const struct qmp_phy_cfg msm8998_pciephy_cfg = { 1704 .lanes = 1, 1705 1706 .tables = { 1707 .serdes = msm8998_pcie_serdes_tbl, 1708 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), 1709 .tx = msm8998_pcie_tx_tbl, 1710 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl), 1711 .rx = msm8998_pcie_rx_tbl, 1712 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl), 1713 .pcs = msm8998_pcie_pcs_tbl, 1714 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), 1715 }, 1716 .clk_list = msm8996_phy_clk_l, 1717 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1718 .reset_list = ipq8074_pciephy_reset_l, 1719 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), 1720 .vreg_list = qmp_phy_vreg_l, 1721 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1722 .regs = pciephy_regs_layout, 1723 1724 .start_ctrl = SERDES_START | PCS_START, 1725 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1726 .phy_status = PHYSTATUS, 1727 }; 1728 1729 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { 1730 .lanes = 1, 1731 1732 .tables = { 1733 .serdes = sc8180x_qmp_pcie_serdes_tbl, 1734 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), 1735 .tx = sc8180x_qmp_pcie_tx_tbl, 1736 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl), 1737 .rx = sc8180x_qmp_pcie_rx_tbl, 1738 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl), 1739 .pcs = sc8180x_qmp_pcie_pcs_tbl, 1740 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl), 1741 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, 1742 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), 1743 }, 1744 .clk_list = sdm845_pciephy_clk_l, 1745 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1746 .reset_list = sdm845_pciephy_reset_l, 1747 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1748 .vreg_list = qmp_phy_vreg_l, 1749 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1750 .regs = sm8250_pcie_regs_layout, 1751 1752 .start_ctrl = PCS_START | SERDES_START, 1753 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1754 1755 .has_pwrdn_delay = true, 1756 .pwrdn_delay_min = 995, /* us */ 1757 .pwrdn_delay_max = 1005, /* us */ 1758 }; 1759 1760 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { 1761 .lanes = 2, 1762 1763 .tables = { 1764 .serdes = sdx55_qmp_pcie_serdes_tbl, 1765 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), 1766 .tx = sdx55_qmp_pcie_tx_tbl, 1767 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl), 1768 .rx = sdx55_qmp_pcie_rx_tbl, 1769 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl), 1770 .pcs = sdx55_qmp_pcie_pcs_tbl, 1771 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl), 1772 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl, 1773 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl), 1774 }, 1775 .clk_list = sdm845_pciephy_clk_l, 1776 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1777 .reset_list = sdm845_pciephy_reset_l, 1778 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1779 .vreg_list = qmp_phy_vreg_l, 1780 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1781 .regs = sm8250_pcie_regs_layout, 1782 1783 .start_ctrl = PCS_START | SERDES_START, 1784 .pwrdn_ctrl = SW_PWRDN, 1785 .phy_status = PHYSTATUS_4_20, 1786 1787 .has_pwrdn_delay = true, 1788 .pwrdn_delay_min = 995, /* us */ 1789 .pwrdn_delay_max = 1005, /* us */ 1790 }; 1791 1792 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { 1793 .lanes = 1, 1794 1795 .tables = { 1796 .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl, 1797 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl), 1798 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl, 1799 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl), 1800 .rx = sm8450_qmp_gen3x1_pcie_rx_tbl, 1801 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl), 1802 .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl, 1803 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl), 1804 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl, 1805 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl), 1806 }, 1807 .clk_list = sdm845_pciephy_clk_l, 1808 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1809 .reset_list = sdm845_pciephy_reset_l, 1810 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1811 .vreg_list = qmp_phy_vreg_l, 1812 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1813 .regs = sm8250_pcie_regs_layout, 1814 1815 .start_ctrl = SERDES_START | PCS_START, 1816 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1817 .phy_status = PHYSTATUS, 1818 1819 .has_pwrdn_delay = true, 1820 .pwrdn_delay_min = 995, /* us */ 1821 .pwrdn_delay_max = 1005, /* us */ 1822 }; 1823 1824 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { 1825 .lanes = 2, 1826 1827 .tables = { 1828 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, 1829 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), 1830 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl, 1831 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl), 1832 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl, 1833 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl), 1834 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl, 1835 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl), 1836 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl, 1837 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl), 1838 }, 1839 .clk_list = sdm845_pciephy_clk_l, 1840 .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), 1841 .reset_list = sdm845_pciephy_reset_l, 1842 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), 1843 .vreg_list = qmp_phy_vreg_l, 1844 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1845 .regs = sm8250_pcie_regs_layout, 1846 1847 .start_ctrl = SERDES_START | PCS_START, 1848 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, 1849 .phy_status = PHYSTATUS_4_20, 1850 1851 .has_pwrdn_delay = true, 1852 .pwrdn_delay_min = 995, /* us */ 1853 .pwrdn_delay_max = 1005, /* us */ 1854 }; 1855 1856 static void qmp_pcie_configure_lane(void __iomem *base, 1857 const unsigned int *regs, 1858 const struct qmp_phy_init_tbl tbl[], 1859 int num, 1860 u8 lane_mask) 1861 { 1862 int i; 1863 const struct qmp_phy_init_tbl *t = tbl; 1864 1865 if (!t) 1866 return; 1867 1868 for (i = 0; i < num; i++, t++) { 1869 if (!(t->lane_mask & lane_mask)) 1870 continue; 1871 1872 if (t->in_layout) 1873 writel(t->val, base + regs[t->offset]); 1874 else 1875 writel(t->val, base + t->offset); 1876 } 1877 } 1878 1879 static void qmp_pcie_configure(void __iomem *base, 1880 const unsigned int *regs, 1881 const struct qmp_phy_init_tbl tbl[], 1882 int num) 1883 { 1884 qmp_pcie_configure_lane(base, regs, tbl, num, 0xff); 1885 } 1886 1887 static void qmp_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1888 { 1889 const struct qmp_phy_cfg *cfg = qphy->cfg; 1890 void __iomem *serdes = qphy->serdes; 1891 1892 if (!tables) 1893 return; 1894 1895 qmp_pcie_configure(serdes, cfg->regs, tables->serdes, tables->serdes_num); 1896 } 1897 1898 static void qmp_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1899 { 1900 const struct qmp_phy_cfg *cfg = qphy->cfg; 1901 void __iomem *tx = qphy->tx; 1902 void __iomem *rx = qphy->rx; 1903 1904 if (!tables) 1905 return; 1906 1907 qmp_pcie_configure_lane(tx, cfg->regs, tables->tx, tables->tx_num, 1); 1908 1909 if (cfg->lanes >= 2) 1910 qmp_pcie_configure_lane(qphy->tx2, cfg->regs, tables->tx, tables->tx_num, 2); 1911 1912 qmp_pcie_configure_lane(rx, cfg->regs, tables->rx, tables->rx_num, 1); 1913 if (cfg->lanes >= 2) 1914 qmp_pcie_configure_lane(qphy->rx2, cfg->regs, tables->rx, tables->rx_num, 2); 1915 } 1916 1917 static void qmp_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables) 1918 { 1919 const struct qmp_phy_cfg *cfg = qphy->cfg; 1920 void __iomem *pcs = qphy->pcs; 1921 void __iomem *pcs_misc = qphy->pcs_misc; 1922 1923 if (!tables) 1924 return; 1925 1926 qmp_pcie_configure(pcs, cfg->regs, 1927 tables->pcs, tables->pcs_num); 1928 qmp_pcie_configure(pcs_misc, cfg->regs, 1929 tables->pcs_misc, tables->pcs_misc_num); 1930 } 1931 1932 static int qmp_pcie_init(struct phy *phy) 1933 { 1934 struct qmp_phy *qphy = phy_get_drvdata(phy); 1935 struct qcom_qmp *qmp = qphy->qmp; 1936 const struct qmp_phy_cfg *cfg = qphy->cfg; 1937 void __iomem *pcs = qphy->pcs; 1938 int ret; 1939 1940 /* turn on regulator supplies */ 1941 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1942 if (ret) { 1943 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1944 return ret; 1945 } 1946 1947 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1948 if (ret) { 1949 dev_err(qmp->dev, "reset assert failed\n"); 1950 goto err_disable_regulators; 1951 } 1952 1953 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1954 if (ret) { 1955 dev_err(qmp->dev, "reset deassert failed\n"); 1956 goto err_disable_regulators; 1957 } 1958 1959 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1960 if (ret) 1961 goto err_assert_reset; 1962 1963 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) 1964 qphy_setbits(pcs, 1965 cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1966 cfg->pwrdn_ctrl); 1967 else 1968 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 1969 cfg->pwrdn_ctrl); 1970 1971 return 0; 1972 1973 err_assert_reset: 1974 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1975 err_disable_regulators: 1976 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1977 1978 return ret; 1979 } 1980 1981 static int qmp_pcie_exit(struct phy *phy) 1982 { 1983 struct qmp_phy *qphy = phy_get_drvdata(phy); 1984 struct qcom_qmp *qmp = qphy->qmp; 1985 const struct qmp_phy_cfg *cfg = qphy->cfg; 1986 1987 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1988 1989 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1990 1991 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1992 1993 return 0; 1994 } 1995 1996 static int qmp_pcie_power_on(struct phy *phy) 1997 { 1998 struct qmp_phy *qphy = phy_get_drvdata(phy); 1999 struct qcom_qmp *qmp = qphy->qmp; 2000 const struct qmp_phy_cfg *cfg = qphy->cfg; 2001 const struct qmp_phy_cfg_tables *mode_tables; 2002 void __iomem *pcs = qphy->pcs; 2003 void __iomem *status; 2004 unsigned int mask, val, ready; 2005 int ret; 2006 2007 if (qphy->mode == PHY_MODE_PCIE_RC) 2008 mode_tables = cfg->tables_rc; 2009 else 2010 mode_tables = cfg->tables_ep; 2011 2012 qmp_pcie_serdes_init(qphy, &cfg->tables); 2013 qmp_pcie_serdes_init(qphy, mode_tables); 2014 2015 ret = clk_prepare_enable(qphy->pipe_clk); 2016 if (ret) { 2017 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2018 return ret; 2019 } 2020 2021 /* Tx, Rx, and PCS configurations */ 2022 qmp_pcie_lanes_init(qphy, &cfg->tables); 2023 qmp_pcie_lanes_init(qphy, mode_tables); 2024 2025 qmp_pcie_pcs_init(qphy, &cfg->tables); 2026 qmp_pcie_pcs_init(qphy, mode_tables); 2027 2028 /* 2029 * Pull out PHY from POWER DOWN state. 2030 * This is active low enable signal to power-down PHY. 2031 */ 2032 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl); 2033 2034 if (cfg->has_pwrdn_delay) 2035 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max); 2036 2037 /* Pull PHY out of reset state */ 2038 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2039 2040 /* start SerDes and Phy-Coding-Sublayer */ 2041 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2042 2043 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2044 mask = cfg->phy_status; 2045 ready = 0; 2046 2047 ret = readl_poll_timeout(status, val, (val & mask) == ready, 10, 2048 PHY_INIT_COMPLETE_TIMEOUT); 2049 if (ret) { 2050 dev_err(qmp->dev, "phy initialization timed-out\n"); 2051 goto err_disable_pipe_clk; 2052 } 2053 2054 return 0; 2055 2056 err_disable_pipe_clk: 2057 clk_disable_unprepare(qphy->pipe_clk); 2058 2059 return ret; 2060 } 2061 2062 static int qmp_pcie_power_off(struct phy *phy) 2063 { 2064 struct qmp_phy *qphy = phy_get_drvdata(phy); 2065 const struct qmp_phy_cfg *cfg = qphy->cfg; 2066 2067 clk_disable_unprepare(qphy->pipe_clk); 2068 2069 /* PHY reset */ 2070 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2071 2072 /* stop SerDes and Phy-Coding-Sublayer */ 2073 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl); 2074 2075 /* Put PHY into POWER DOWN state: active low */ 2076 if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) { 2077 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2078 cfg->pwrdn_ctrl); 2079 } else { 2080 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL, 2081 cfg->pwrdn_ctrl); 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int qmp_pcie_enable(struct phy *phy) 2088 { 2089 int ret; 2090 2091 ret = qmp_pcie_init(phy); 2092 if (ret) 2093 return ret; 2094 2095 ret = qmp_pcie_power_on(phy); 2096 if (ret) 2097 qmp_pcie_exit(phy); 2098 2099 return ret; 2100 } 2101 2102 static int qmp_pcie_disable(struct phy *phy) 2103 { 2104 int ret; 2105 2106 ret = qmp_pcie_power_off(phy); 2107 if (ret) 2108 return ret; 2109 2110 return qmp_pcie_exit(phy); 2111 } 2112 2113 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2114 { 2115 struct qmp_phy *qphy = phy_get_drvdata(phy); 2116 2117 switch (submode) { 2118 case PHY_MODE_PCIE_RC: 2119 case PHY_MODE_PCIE_EP: 2120 qphy->mode = submode; 2121 break; 2122 default: 2123 dev_err(&phy->dev, "Unsupported submode %d\n", submode); 2124 return -EINVAL; 2125 } 2126 2127 return 0; 2128 } 2129 2130 static int qmp_pcie_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2131 { 2132 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2133 int num = cfg->num_vregs; 2134 int i; 2135 2136 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2137 if (!qmp->vregs) 2138 return -ENOMEM; 2139 2140 for (i = 0; i < num; i++) 2141 qmp->vregs[i].supply = cfg->vreg_list[i]; 2142 2143 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2144 } 2145 2146 static int qmp_pcie_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2147 { 2148 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2149 int i; 2150 int ret; 2151 2152 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2153 sizeof(*qmp->resets), GFP_KERNEL); 2154 if (!qmp->resets) 2155 return -ENOMEM; 2156 2157 for (i = 0; i < cfg->num_resets; i++) 2158 qmp->resets[i].id = cfg->reset_list[i]; 2159 2160 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2161 if (ret) 2162 return dev_err_probe(dev, ret, "failed to get resets\n"); 2163 2164 return 0; 2165 } 2166 2167 static int qmp_pcie_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg) 2168 { 2169 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2170 int num = cfg->num_clks; 2171 int i; 2172 2173 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2174 if (!qmp->clks) 2175 return -ENOMEM; 2176 2177 for (i = 0; i < num; i++) 2178 qmp->clks[i].id = cfg->clk_list[i]; 2179 2180 return devm_clk_bulk_get(dev, num, qmp->clks); 2181 } 2182 2183 static void phy_clk_release_provider(void *res) 2184 { 2185 of_clk_del_provider(res); 2186 } 2187 2188 /* 2189 * Register a fixed rate pipe clock. 2190 * 2191 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2192 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2193 * by the PHY driver for its operations. 2194 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2195 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2196 * Below picture shows this relationship. 2197 * 2198 * +---------------+ 2199 * | PHY block |<<---------------------------------------+ 2200 * | | | 2201 * | +-------+ | +-----+ | 2202 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2203 * clk | +-------+ | +-----+ 2204 * +---------------+ 2205 */ 2206 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np) 2207 { 2208 struct clk_fixed_rate *fixed; 2209 struct clk_init_data init = { }; 2210 int ret; 2211 2212 ret = of_property_read_string(np, "clock-output-names", &init.name); 2213 if (ret) { 2214 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2215 return ret; 2216 } 2217 2218 fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL); 2219 if (!fixed) 2220 return -ENOMEM; 2221 2222 init.ops = &clk_fixed_rate_ops; 2223 2224 /* 2225 * Controllers using QMP PHY-s use 125MHz pipe clock interface 2226 * unless other frequency is specified in the PHY config. 2227 */ 2228 if (qmp->phys[0]->cfg->pipe_clock_rate) 2229 fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate; 2230 else 2231 fixed->fixed_rate = 125000000; 2232 2233 fixed->hw.init = &init; 2234 2235 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2236 if (ret) 2237 return ret; 2238 2239 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2240 if (ret) 2241 return ret; 2242 2243 /* 2244 * Roll a devm action because the clock provider is the child node, but 2245 * the child node is not actually a device. 2246 */ 2247 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2248 } 2249 2250 static const struct phy_ops qmp_pcie_ops = { 2251 .power_on = qmp_pcie_enable, 2252 .power_off = qmp_pcie_disable, 2253 .set_mode = qmp_pcie_set_mode, 2254 .owner = THIS_MODULE, 2255 }; 2256 2257 static int qmp_pcie_create(struct device *dev, struct device_node *np, int id, 2258 void __iomem *serdes, const struct qmp_phy_cfg *cfg) 2259 { 2260 struct qcom_qmp *qmp = dev_get_drvdata(dev); 2261 struct phy *generic_phy; 2262 struct qmp_phy *qphy; 2263 int ret; 2264 2265 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 2266 if (!qphy) 2267 return -ENOMEM; 2268 2269 qphy->mode = PHY_MODE_PCIE_RC; 2270 2271 qphy->cfg = cfg; 2272 qphy->serdes = serdes; 2273 /* 2274 * Get memory resources for each phy lane: 2275 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2276 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2277 * For single lane PHYs: pcs_misc (optional) -> 3. 2278 */ 2279 qphy->tx = devm_of_iomap(dev, np, 0, NULL); 2280 if (IS_ERR(qphy->tx)) 2281 return PTR_ERR(qphy->tx); 2282 2283 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) 2284 qphy->rx = qphy->tx; 2285 else 2286 qphy->rx = devm_of_iomap(dev, np, 1, NULL); 2287 if (IS_ERR(qphy->rx)) 2288 return PTR_ERR(qphy->rx); 2289 2290 qphy->pcs = devm_of_iomap(dev, np, 2, NULL); 2291 if (IS_ERR(qphy->pcs)) 2292 return PTR_ERR(qphy->pcs); 2293 2294 if (cfg->lanes >= 2) { 2295 qphy->tx2 = devm_of_iomap(dev, np, 3, NULL); 2296 if (IS_ERR(qphy->tx2)) 2297 return PTR_ERR(qphy->tx2); 2298 2299 qphy->rx2 = devm_of_iomap(dev, np, 4, NULL); 2300 if (IS_ERR(qphy->rx2)) 2301 return PTR_ERR(qphy->rx2); 2302 2303 qphy->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2304 } else { 2305 qphy->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2306 } 2307 2308 if (IS_ERR(qphy->pcs_misc) && 2309 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) 2310 qphy->pcs_misc = qphy->pcs + 0x400; 2311 2312 if (IS_ERR(qphy->pcs_misc)) { 2313 if (cfg->tables.pcs_misc || 2314 (cfg->tables_rc && cfg->tables_rc->pcs_misc) || 2315 (cfg->tables_ep && cfg->tables_ep->pcs_misc)) 2316 return PTR_ERR(qphy->pcs_misc); 2317 } 2318 2319 qphy->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2320 if (IS_ERR(qphy->pipe_clk)) { 2321 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk), 2322 "failed to get lane%d pipe clock\n", id); 2323 } 2324 2325 generic_phy = devm_phy_create(dev, np, &qmp_pcie_ops); 2326 if (IS_ERR(generic_phy)) { 2327 ret = PTR_ERR(generic_phy); 2328 dev_err(dev, "failed to create qphy %d\n", ret); 2329 return ret; 2330 } 2331 2332 qphy->phy = generic_phy; 2333 qphy->qmp = qmp; 2334 qmp->phys[id] = qphy; 2335 phy_set_drvdata(generic_phy, qphy); 2336 2337 return 0; 2338 } 2339 2340 static const struct of_device_id qmp_pcie_of_match_table[] = { 2341 { 2342 .compatible = "qcom,msm8998-qmp-pcie-phy", 2343 .data = &msm8998_pciephy_cfg, 2344 }, { 2345 .compatible = "qcom,ipq8074-qmp-pcie-phy", 2346 .data = &ipq8074_pciephy_cfg, 2347 }, { 2348 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy", 2349 .data = &ipq8074_pciephy_gen3_cfg, 2350 }, { 2351 .compatible = "qcom,ipq6018-qmp-pcie-phy", 2352 .data = &ipq6018_pciephy_cfg, 2353 }, { 2354 .compatible = "qcom,sc8180x-qmp-pcie-phy", 2355 .data = &sc8180x_pciephy_cfg, 2356 }, { 2357 .compatible = "qcom,sdm845-qhp-pcie-phy", 2358 .data = &sdm845_qhp_pciephy_cfg, 2359 }, { 2360 .compatible = "qcom,sdm845-qmp-pcie-phy", 2361 .data = &sdm845_qmp_pciephy_cfg, 2362 }, { 2363 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy", 2364 .data = &sm8250_qmp_gen3x1_pciephy_cfg, 2365 }, { 2366 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy", 2367 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2368 }, { 2369 .compatible = "qcom,sm8250-qmp-modem-pcie-phy", 2370 .data = &sm8250_qmp_gen3x2_pciephy_cfg, 2371 }, { 2372 .compatible = "qcom,sdx55-qmp-pcie-phy", 2373 .data = &sdx55_qmp_pciephy_cfg, 2374 }, { 2375 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy", 2376 .data = &sm8450_qmp_gen3x1_pciephy_cfg, 2377 }, { 2378 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy", 2379 .data = &sm8450_qmp_gen4x2_pciephy_cfg, 2380 }, 2381 { }, 2382 }; 2383 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table); 2384 2385 static int qmp_pcie_probe(struct platform_device *pdev) 2386 { 2387 struct qcom_qmp *qmp; 2388 struct device *dev = &pdev->dev; 2389 struct device_node *child; 2390 struct phy_provider *phy_provider; 2391 void __iomem *serdes; 2392 const struct qmp_phy_cfg *cfg = NULL; 2393 int num, id; 2394 int ret; 2395 2396 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2397 if (!qmp) 2398 return -ENOMEM; 2399 2400 qmp->dev = dev; 2401 dev_set_drvdata(dev, qmp); 2402 2403 /* Get the specific init parameters of QMP phy */ 2404 cfg = of_device_get_match_data(dev); 2405 if (!cfg) 2406 return -EINVAL; 2407 2408 /* per PHY serdes; usually located at base address */ 2409 serdes = devm_platform_ioremap_resource(pdev, 0); 2410 if (IS_ERR(serdes)) 2411 return PTR_ERR(serdes); 2412 2413 ret = qmp_pcie_clk_init(dev, cfg); 2414 if (ret) 2415 return ret; 2416 2417 ret = qmp_pcie_reset_init(dev, cfg); 2418 if (ret) 2419 return ret; 2420 2421 ret = qmp_pcie_vreg_init(dev, cfg); 2422 if (ret) 2423 return dev_err_probe(dev, ret, 2424 "failed to get regulator supplies\n"); 2425 2426 num = of_get_available_child_count(dev->of_node); 2427 /* do we have a rogue child node ? */ 2428 if (num > 1) 2429 return -EINVAL; 2430 2431 qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL); 2432 if (!qmp->phys) 2433 return -ENOMEM; 2434 2435 id = 0; 2436 for_each_available_child_of_node(dev->of_node, child) { 2437 /* Create per-lane phy */ 2438 ret = qmp_pcie_create(dev, child, id, serdes, cfg); 2439 if (ret) { 2440 dev_err(dev, "failed to create lane%d phy, %d\n", 2441 id, ret); 2442 goto err_node_put; 2443 } 2444 2445 /* 2446 * Register the pipe clock provided by phy. 2447 * See function description to see details of this pipe clock. 2448 */ 2449 ret = phy_pipe_clk_register(qmp, child); 2450 if (ret) { 2451 dev_err(qmp->dev, 2452 "failed to register pipe clock source\n"); 2453 goto err_node_put; 2454 } 2455 2456 id++; 2457 } 2458 2459 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2460 2461 return PTR_ERR_OR_ZERO(phy_provider); 2462 2463 err_node_put: 2464 of_node_put(child); 2465 return ret; 2466 } 2467 2468 static struct platform_driver qmp_pcie_driver = { 2469 .probe = qmp_pcie_probe, 2470 .driver = { 2471 .name = "qcom-qmp-pcie-phy", 2472 .of_match_table = qmp_pcie_of_match_table, 2473 }, 2474 }; 2475 2476 module_platform_driver(qmp_pcie_driver); 2477 2478 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2479 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver"); 2480 MODULE_LICENSE("GPL v2"); 2481