1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2021 NXP 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/io.h> 8 #include <linux/iopoll.h> 9 #include <linux/delay.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 12 #include <linux/module.h> 13 #include <linux/phy/phy.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <dt-bindings/phy/phy-imx8-pcie.h> 18 19 #define IMX8MM_PCIE_PHY_CMN_REG061 0x184 20 #define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) 21 #define IMX8MM_PCIE_PHY_CMN_REG062 0x188 22 #define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) 23 #define IMX8MM_PCIE_PHY_CMN_REG063 0x18C 24 #define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) 25 #define IMX8MM_PCIE_PHY_CMN_REG064 0x190 26 #define ANA_AUX_RX_TX_SEL_TX BIT(7) 27 #define ANA_AUX_RX_TERM_GND_EN BIT(3) 28 #define ANA_AUX_TX_TERM BIT(2) 29 #define IMX8MM_PCIE_PHY_CMN_REG065 0x194 30 #define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) 31 #define ANA_AUX_TX_LVL GENMASK(3, 0) 32 #define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 33 #define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 34 #define PCIE_PHY_TRSV_REG5 0x414 35 #define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D 36 #define PCIE_PHY_TRSV_REG6 0x418 37 #define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF 38 39 #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) 40 #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) 41 #define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) 42 #define IMX8MM_GPR_PCIE_AUX_EN BIT(19) 43 #define IMX8MM_GPR_PCIE_CMN_RST BIT(18) 44 #define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) 45 #define IMX8MM_GPR_PCIE_SSC_EN BIT(16) 46 #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) 47 48 struct imx8_pcie_phy { 49 void __iomem *base; 50 struct clk *clk; 51 struct phy *phy; 52 struct regmap *iomuxc_gpr; 53 struct reset_control *reset; 54 u32 refclk_pad_mode; 55 u32 tx_deemph_gen1; 56 u32 tx_deemph_gen2; 57 bool clkreq_unused; 58 }; 59 60 static int imx8_pcie_phy_init(struct phy *phy) 61 { 62 int ret; 63 u32 val, pad_mode; 64 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 65 66 reset_control_assert(imx8_phy->reset); 67 68 pad_mode = imx8_phy->refclk_pad_mode; 69 /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ 70 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 71 IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, 72 imx8_phy->clkreq_unused ? 73 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); 74 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 75 IMX8MM_GPR_PCIE_AUX_EN, 76 IMX8MM_GPR_PCIE_AUX_EN); 77 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 78 IMX8MM_GPR_PCIE_POWER_OFF, 0); 79 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 80 IMX8MM_GPR_PCIE_SSC_EN, 0); 81 82 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 83 IMX8MM_GPR_PCIE_REF_CLK_SEL, 84 pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? 85 IMX8MM_GPR_PCIE_REF_CLK_EXT : 86 IMX8MM_GPR_PCIE_REF_CLK_PLL); 87 usleep_range(100, 200); 88 89 /* Do the PHY common block reset */ 90 regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, 91 IMX8MM_GPR_PCIE_CMN_RST, 92 IMX8MM_GPR_PCIE_CMN_RST); 93 usleep_range(200, 500); 94 95 if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { 96 /* Configure the pad as input */ 97 val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 98 writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, 99 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 100 } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { 101 /* Configure the PHY to output the refclock via pad */ 102 writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, 103 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); 104 writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, 105 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); 106 writel(AUX_PLL_REFCLK_SEL_SYS_PLL, 107 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); 108 val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; 109 writel(val | ANA_AUX_RX_TERM_GND_EN, 110 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); 111 writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, 112 imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); 113 } 114 115 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ 116 if (imx8_phy->tx_deemph_gen1) 117 writel(imx8_phy->tx_deemph_gen1, 118 imx8_phy->base + PCIE_PHY_TRSV_REG5); 119 if (imx8_phy->tx_deemph_gen2) 120 writel(imx8_phy->tx_deemph_gen2, 121 imx8_phy->base + PCIE_PHY_TRSV_REG6); 122 123 reset_control_deassert(imx8_phy->reset); 124 125 /* Polling to check the phy is ready or not. */ 126 ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, 127 val, val == PCIE_PHY_CMN_REG75_PLL_DONE, 128 10, 20000); 129 return ret; 130 } 131 132 static int imx8_pcie_phy_power_on(struct phy *phy) 133 { 134 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 135 136 return clk_prepare_enable(imx8_phy->clk); 137 } 138 139 static int imx8_pcie_phy_power_off(struct phy *phy) 140 { 141 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); 142 143 clk_disable_unprepare(imx8_phy->clk); 144 145 return 0; 146 } 147 148 static const struct phy_ops imx8_pcie_phy_ops = { 149 .init = imx8_pcie_phy_init, 150 .power_on = imx8_pcie_phy_power_on, 151 .power_off = imx8_pcie_phy_power_off, 152 .owner = THIS_MODULE, 153 }; 154 155 static int imx8_pcie_phy_probe(struct platform_device *pdev) 156 { 157 struct phy_provider *phy_provider; 158 struct device *dev = &pdev->dev; 159 struct device_node *np = dev->of_node; 160 struct imx8_pcie_phy *imx8_phy; 161 struct resource *res; 162 163 imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); 164 if (!imx8_phy) 165 return -ENOMEM; 166 167 /* get PHY refclk pad mode */ 168 of_property_read_u32(np, "fsl,refclk-pad-mode", 169 &imx8_phy->refclk_pad_mode); 170 171 if (of_property_read_u32(np, "fsl,tx-deemph-gen1", 172 &imx8_phy->tx_deemph_gen1)) 173 imx8_phy->tx_deemph_gen1 = 0; 174 175 if (of_property_read_u32(np, "fsl,tx-deemph-gen2", 176 &imx8_phy->tx_deemph_gen2)) 177 imx8_phy->tx_deemph_gen2 = 0; 178 179 if (of_property_read_bool(np, "fsl,clkreq-unsupported")) 180 imx8_phy->clkreq_unused = true; 181 else 182 imx8_phy->clkreq_unused = false; 183 184 imx8_phy->clk = devm_clk_get(dev, "ref"); 185 if (IS_ERR(imx8_phy->clk)) { 186 dev_err(dev, "failed to get imx pcie phy clock\n"); 187 return PTR_ERR(imx8_phy->clk); 188 } 189 190 /* Grab GPR config register range */ 191 imx8_phy->iomuxc_gpr = 192 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 193 if (IS_ERR(imx8_phy->iomuxc_gpr)) { 194 dev_err(dev, "unable to find iomuxc registers\n"); 195 return PTR_ERR(imx8_phy->iomuxc_gpr); 196 } 197 198 imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy"); 199 if (IS_ERR(imx8_phy->reset)) { 200 dev_err(dev, "Failed to get PCIEPHY reset control\n"); 201 return PTR_ERR(imx8_phy->reset); 202 } 203 204 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 205 imx8_phy->base = devm_ioremap_resource(dev, res); 206 if (IS_ERR(imx8_phy->base)) 207 return PTR_ERR(imx8_phy->base); 208 209 imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops); 210 if (IS_ERR(imx8_phy->phy)) 211 return PTR_ERR(imx8_phy->phy); 212 213 phy_set_drvdata(imx8_phy->phy, imx8_phy); 214 215 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 216 217 return PTR_ERR_OR_ZERO(phy_provider); 218 } 219 220 static const struct of_device_id imx8_pcie_phy_of_match[] = { 221 {.compatible = "fsl,imx8mm-pcie-phy",}, 222 { }, 223 }; 224 MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); 225 226 static struct platform_driver imx8_pcie_phy_driver = { 227 .probe = imx8_pcie_phy_probe, 228 .driver = { 229 .name = "imx8-pcie-phy", 230 .of_match_table = imx8_pcie_phy_of_match, 231 } 232 }; 233 module_platform_driver(imx8_pcie_phy_driver); 234 235 MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver"); 236 MODULE_LICENSE("GPL v2"); 237