1 /* 2 * drivers/pci/setup-bus.c 3 * 4 * Extruded from code written by 5 * Dave Rusling (david.rusling@reo.mts.dec.com) 6 * David Mosberger (davidm@cs.arizona.edu) 7 * David Miller (davem@redhat.com) 8 * 9 * Support routines for initializing a PCI subsystem. 10 */ 11 12 /* 13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 14 * PCI-PCI bridges cleanup, sorted resource allocation. 15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> 16 * Converted to allocation in 3 passes, which gives 17 * tighter packing. Prefetchable range support. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/pci.h> 24 #include <linux/errno.h> 25 #include <linux/ioport.h> 26 #include <linux/cache.h> 27 #include <linux/slab.h> 28 #include "pci.h" 29 30 static void pbus_assign_resources_sorted(const struct pci_bus *bus) 31 { 32 struct pci_dev *dev; 33 struct resource *res; 34 struct resource_list head, *list, *tmp; 35 int idx; 36 37 head.next = NULL; 38 list_for_each_entry(dev, &bus->devices, bus_list) { 39 u16 class = dev->class >> 8; 40 41 /* Don't touch classless devices or host bridges or ioapics. */ 42 if (class == PCI_CLASS_NOT_DEFINED || 43 class == PCI_CLASS_BRIDGE_HOST) 44 continue; 45 46 /* Don't touch ioapic devices already enabled by firmware */ 47 if (class == PCI_CLASS_SYSTEM_PIC) { 48 u16 command; 49 pci_read_config_word(dev, PCI_COMMAND, &command); 50 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) 51 continue; 52 } 53 54 pdev_sort_resources(dev, &head); 55 } 56 57 for (list = head.next; list;) { 58 res = list->res; 59 idx = res - &list->dev->resource[0]; 60 if (pci_assign_resource(list->dev, idx)) { 61 res->start = 0; 62 res->end = 0; 63 res->flags = 0; 64 } 65 tmp = list; 66 list = list->next; 67 kfree(tmp); 68 } 69 } 70 71 void pci_setup_cardbus(struct pci_bus *bus) 72 { 73 struct pci_dev *bridge = bus->self; 74 struct resource *res; 75 struct pci_bus_region region; 76 77 dev_info(&bridge->dev, "CardBus bridge to [bus %02x-%02x]\n", 78 bus->secondary, bus->subordinate); 79 80 res = bus->resource[0]; 81 pcibios_resource_to_bus(bridge, ®ion, res); 82 if (res->flags & IORESOURCE_IO) { 83 /* 84 * The IO resource is allocated a range twice as large as it 85 * would normally need. This allows us to set both IO regs. 86 */ 87 dev_info(&bridge->dev, " bridge window %pR\n", res); 88 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 89 region.start); 90 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 91 region.end); 92 } 93 94 res = bus->resource[1]; 95 pcibios_resource_to_bus(bridge, ®ion, res); 96 if (res->flags & IORESOURCE_IO) { 97 dev_info(&bridge->dev, " bridge window %pR\n", res); 98 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 99 region.start); 100 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 101 region.end); 102 } 103 104 res = bus->resource[2]; 105 pcibios_resource_to_bus(bridge, ®ion, res); 106 if (res->flags & IORESOURCE_MEM) { 107 dev_info(&bridge->dev, " bridge window %pR\n", res); 108 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 109 region.start); 110 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 111 region.end); 112 } 113 114 res = bus->resource[3]; 115 pcibios_resource_to_bus(bridge, ®ion, res); 116 if (res->flags & IORESOURCE_MEM) { 117 dev_info(&bridge->dev, " bridge window %pR\n", res); 118 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 119 region.start); 120 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 121 region.end); 122 } 123 } 124 EXPORT_SYMBOL(pci_setup_cardbus); 125 126 /* Initialize bridges with base/limit values we have collected. 127 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) 128 requires that if there is no I/O ports or memory behind the 129 bridge, corresponding range must be turned off by writing base 130 value greater than limit to the bridge's base/limit registers. 131 132 Note: care must be taken when updating I/O base/limit registers 133 of bridges which support 32-bit I/O. This update requires two 134 config space writes, so it's quite possible that an I/O window of 135 the bridge will have some undesirable address (e.g. 0) after the 136 first write. Ditto 64-bit prefetchable MMIO. */ 137 static void pci_setup_bridge_io(struct pci_bus *bus) 138 { 139 struct pci_dev *bridge = bus->self; 140 struct resource *res; 141 struct pci_bus_region region; 142 u32 l, io_upper16; 143 144 /* Set up the top and bottom of the PCI I/O segment for this bus. */ 145 res = bus->resource[0]; 146 pcibios_resource_to_bus(bridge, ®ion, res); 147 if (res->flags & IORESOURCE_IO) { 148 pci_read_config_dword(bridge, PCI_IO_BASE, &l); 149 l &= 0xffff0000; 150 l |= (region.start >> 8) & 0x00f0; 151 l |= region.end & 0xf000; 152 /* Set up upper 16 bits of I/O base/limit. */ 153 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 154 dev_info(&bridge->dev, " bridge window %pR\n", res); 155 } else { 156 /* Clear upper 16 bits of I/O base/limit. */ 157 io_upper16 = 0; 158 l = 0x00f0; 159 dev_info(&bridge->dev, " bridge window [io disabled]\n"); 160 } 161 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ 162 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); 163 /* Update lower 16 bits of I/O base/limit. */ 164 pci_write_config_dword(bridge, PCI_IO_BASE, l); 165 /* Update upper 16 bits of I/O base/limit. */ 166 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); 167 } 168 169 static void pci_setup_bridge_mmio(struct pci_bus *bus) 170 { 171 struct pci_dev *bridge = bus->self; 172 struct resource *res; 173 struct pci_bus_region region; 174 u32 l; 175 176 /* Set up the top and bottom of the PCI Memory segment for this bus. */ 177 res = bus->resource[1]; 178 pcibios_resource_to_bus(bridge, ®ion, res); 179 if (res->flags & IORESOURCE_MEM) { 180 l = (region.start >> 16) & 0xfff0; 181 l |= region.end & 0xfff00000; 182 dev_info(&bridge->dev, " bridge window %pR\n", res); 183 } else { 184 l = 0x0000fff0; 185 dev_info(&bridge->dev, " bridge window [mem disabled]\n"); 186 } 187 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); 188 } 189 190 static void pci_setup_bridge_mmio_pref(struct pci_bus *bus) 191 { 192 struct pci_dev *bridge = bus->self; 193 struct resource *res; 194 struct pci_bus_region region; 195 u32 l, bu, lu; 196 197 /* Clear out the upper 32 bits of PREF limit. 198 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily 199 disables PREF range, which is ok. */ 200 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 201 202 /* Set up PREF base/limit. */ 203 bu = lu = 0; 204 res = bus->resource[2]; 205 pcibios_resource_to_bus(bridge, ®ion, res); 206 if (res->flags & IORESOURCE_PREFETCH) { 207 l = (region.start >> 16) & 0xfff0; 208 l |= region.end & 0xfff00000; 209 if (res->flags & IORESOURCE_MEM_64) { 210 bu = upper_32_bits(region.start); 211 lu = upper_32_bits(region.end); 212 } 213 dev_info(&bridge->dev, " bridge window %pR\n", res); 214 } else { 215 l = 0x0000fff0; 216 dev_info(&bridge->dev, " bridge window [mem pref disabled]\n"); 217 } 218 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 219 220 /* Set the upper 32 bits of PREF base & limit. */ 221 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu); 222 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu); 223 } 224 225 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type) 226 { 227 struct pci_dev *bridge = bus->self; 228 229 if (pci_is_enabled(bridge)) 230 return; 231 232 dev_info(&bridge->dev, "PCI bridge to [bus %02x-%02x]\n", 233 bus->secondary, bus->subordinate); 234 235 if (type & IORESOURCE_IO) 236 pci_setup_bridge_io(bus); 237 238 if (type & IORESOURCE_MEM) 239 pci_setup_bridge_mmio(bus); 240 241 if (type & IORESOURCE_PREFETCH) 242 pci_setup_bridge_mmio_pref(bus); 243 244 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 245 } 246 247 static void pci_setup_bridge(struct pci_bus *bus) 248 { 249 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM | 250 IORESOURCE_PREFETCH; 251 252 __pci_setup_bridge(bus, type); 253 } 254 255 /* Check whether the bridge supports optional I/O and 256 prefetchable memory ranges. If not, the respective 257 base/limit registers must be read-only and read as 0. */ 258 static void pci_bridge_check_ranges(struct pci_bus *bus) 259 { 260 u16 io; 261 u32 pmem; 262 struct pci_dev *bridge = bus->self; 263 struct resource *b_res; 264 265 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 266 b_res[1].flags |= IORESOURCE_MEM; 267 268 pci_read_config_word(bridge, PCI_IO_BASE, &io); 269 if (!io) { 270 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); 271 pci_read_config_word(bridge, PCI_IO_BASE, &io); 272 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 273 } 274 if (io) 275 b_res[0].flags |= IORESOURCE_IO; 276 /* DECchip 21050 pass 2 errata: the bridge may miss an address 277 disconnect boundary by one PCI data phase. 278 Workaround: do not use prefetching on this device. */ 279 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 280 return; 281 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 282 if (!pmem) { 283 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 284 0xfff0fff0); 285 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 286 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 287 } 288 if (pmem) { 289 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; 290 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) 291 b_res[2].flags |= IORESOURCE_MEM_64; 292 } 293 294 /* double check if bridge does support 64 bit pref */ 295 if (b_res[2].flags & IORESOURCE_MEM_64) { 296 u32 mem_base_hi, tmp; 297 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, 298 &mem_base_hi); 299 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 300 0xffffffff); 301 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 302 if (!tmp) 303 b_res[2].flags &= ~IORESOURCE_MEM_64; 304 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 305 mem_base_hi); 306 } 307 } 308 309 /* Helper function for sizing routines: find first available 310 bus resource of a given type. Note: we intentionally skip 311 the bus resources which have already been assigned (that is, 312 have non-NULL parent resource). */ 313 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type) 314 { 315 int i; 316 struct resource *r; 317 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | 318 IORESOURCE_PREFETCH; 319 320 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 321 r = bus->resource[i]; 322 if (r == &ioport_resource || r == &iomem_resource) 323 continue; 324 if (r && (r->flags & type_mask) == type && !r->parent) 325 return r; 326 } 327 return NULL; 328 } 329 330 /* Sizing the IO windows of the PCI-PCI bridge is trivial, 331 since these windows have 4K granularity and the IO ranges 332 of non-bridge PCI devices are limited to 256 bytes. 333 We must be careful with the ISA aliasing though. */ 334 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size) 335 { 336 struct pci_dev *dev; 337 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); 338 unsigned long size = 0, size1 = 0; 339 340 if (!b_res) 341 return; 342 343 list_for_each_entry(dev, &bus->devices, bus_list) { 344 int i; 345 346 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 347 struct resource *r = &dev->resource[i]; 348 unsigned long r_size; 349 350 if (r->parent || !(r->flags & IORESOURCE_IO)) 351 continue; 352 r_size = resource_size(r); 353 354 if (r_size < 0x400) 355 /* Might be re-aligned for ISA */ 356 size += r_size; 357 else 358 size1 += r_size; 359 } 360 } 361 if (size < min_size) 362 size = min_size; 363 /* To be fixed in 2.5: we should have sort of HAVE_ISA 364 flag in the struct pci_bus. */ 365 #if defined(CONFIG_ISA) || defined(CONFIG_EISA) 366 size = (size & 0xff) + ((size & ~0xffUL) << 2); 367 #endif 368 size = ALIGN(size + size1, 4096); 369 if (!size) { 370 if (b_res->start || b_res->end) 371 dev_info(&bus->self->dev, "disabling bridge window " 372 "%pR to [bus %02x-%02x] (unused)\n", b_res, 373 bus->secondary, bus->subordinate); 374 b_res->flags = 0; 375 return; 376 } 377 /* Alignment of the IO window is always 4K */ 378 b_res->start = 4096; 379 b_res->end = b_res->start + size - 1; 380 b_res->flags |= IORESOURCE_STARTALIGN; 381 } 382 383 /* Calculate the size of the bus and minimal alignment which 384 guarantees that all child resources fit in this size. */ 385 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, 386 unsigned long type, resource_size_t min_size) 387 { 388 struct pci_dev *dev; 389 resource_size_t min_align, align, size; 390 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */ 391 int order, max_order; 392 struct resource *b_res = find_free_bus_resource(bus, type); 393 unsigned int mem64_mask = 0; 394 395 if (!b_res) 396 return 0; 397 398 memset(aligns, 0, sizeof(aligns)); 399 max_order = 0; 400 size = 0; 401 402 mem64_mask = b_res->flags & IORESOURCE_MEM_64; 403 b_res->flags &= ~IORESOURCE_MEM_64; 404 405 list_for_each_entry(dev, &bus->devices, bus_list) { 406 int i; 407 408 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 409 struct resource *r = &dev->resource[i]; 410 resource_size_t r_size; 411 412 if (r->parent || (r->flags & mask) != type) 413 continue; 414 r_size = resource_size(r); 415 /* For bridges size != alignment */ 416 align = pci_resource_alignment(dev, r); 417 order = __ffs(align) - 20; 418 if (order > 11) { 419 dev_warn(&dev->dev, "disabling BAR %d: %pR " 420 "(bad alignment %#llx)\n", i, r, 421 (unsigned long long) align); 422 r->flags = 0; 423 continue; 424 } 425 size += r_size; 426 if (order < 0) 427 order = 0; 428 /* Exclude ranges with size > align from 429 calculation of the alignment. */ 430 if (r_size == align) 431 aligns[order] += align; 432 if (order > max_order) 433 max_order = order; 434 mem64_mask &= r->flags & IORESOURCE_MEM_64; 435 } 436 } 437 if (size < min_size) 438 size = min_size; 439 440 align = 0; 441 min_align = 0; 442 for (order = 0; order <= max_order; order++) { 443 resource_size_t align1 = 1; 444 445 align1 <<= (order + 20); 446 447 if (!align) 448 min_align = align1; 449 else if (ALIGN(align + min_align, min_align) < align1) 450 min_align = align1 >> 1; 451 align += aligns[order]; 452 } 453 size = ALIGN(size, min_align); 454 if (!size) { 455 if (b_res->start || b_res->end) 456 dev_info(&bus->self->dev, "disabling bridge window " 457 "%pR to [bus %02x-%02x] (unused)\n", b_res, 458 bus->secondary, bus->subordinate); 459 b_res->flags = 0; 460 return 1; 461 } 462 b_res->start = min_align; 463 b_res->end = size + min_align - 1; 464 b_res->flags |= IORESOURCE_STARTALIGN; 465 b_res->flags |= mem64_mask; 466 return 1; 467 } 468 469 static void pci_bus_size_cardbus(struct pci_bus *bus) 470 { 471 struct pci_dev *bridge = bus->self; 472 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; 473 u16 ctrl; 474 475 /* 476 * Reserve some resources for CardBus. We reserve 477 * a fixed amount of bus space for CardBus bridges. 478 */ 479 b_res[0].start = 0; 480 b_res[0].end = pci_cardbus_io_size - 1; 481 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 482 483 b_res[1].start = 0; 484 b_res[1].end = pci_cardbus_io_size - 1; 485 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN; 486 487 /* 488 * Check whether prefetchable memory is supported 489 * by this bridge. 490 */ 491 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 492 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { 493 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; 494 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); 495 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); 496 } 497 498 /* 499 * If we have prefetchable memory support, allocate 500 * two regions. Otherwise, allocate one region of 501 * twice the size. 502 */ 503 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { 504 b_res[2].start = 0; 505 b_res[2].end = pci_cardbus_mem_size - 1; 506 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN; 507 508 b_res[3].start = 0; 509 b_res[3].end = pci_cardbus_mem_size - 1; 510 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 511 } else { 512 b_res[3].start = 0; 513 b_res[3].end = pci_cardbus_mem_size * 2 - 1; 514 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN; 515 } 516 } 517 518 void __ref pci_bus_size_bridges(struct pci_bus *bus) 519 { 520 struct pci_dev *dev; 521 unsigned long mask, prefmask; 522 resource_size_t min_mem_size = 0, min_io_size = 0; 523 524 list_for_each_entry(dev, &bus->devices, bus_list) { 525 struct pci_bus *b = dev->subordinate; 526 if (!b) 527 continue; 528 529 switch (dev->class >> 8) { 530 case PCI_CLASS_BRIDGE_CARDBUS: 531 pci_bus_size_cardbus(b); 532 break; 533 534 case PCI_CLASS_BRIDGE_PCI: 535 default: 536 pci_bus_size_bridges(b); 537 break; 538 } 539 } 540 541 /* The root bus? */ 542 if (!bus->self) 543 return; 544 545 switch (bus->self->class >> 8) { 546 case PCI_CLASS_BRIDGE_CARDBUS: 547 /* don't size cardbuses yet. */ 548 break; 549 550 case PCI_CLASS_BRIDGE_PCI: 551 pci_bridge_check_ranges(bus); 552 if (bus->self->is_hotplug_bridge) { 553 min_io_size = pci_hotplug_io_size; 554 min_mem_size = pci_hotplug_mem_size; 555 } 556 default: 557 pbus_size_io(bus, min_io_size); 558 /* If the bridge supports prefetchable range, size it 559 separately. If it doesn't, or its prefetchable window 560 has already been allocated by arch code, try 561 non-prefetchable range for both types of PCI memory 562 resources. */ 563 mask = IORESOURCE_MEM; 564 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; 565 if (pbus_size_mem(bus, prefmask, prefmask, min_mem_size)) 566 mask = prefmask; /* Success, size non-prefetch only. */ 567 else 568 min_mem_size += min_mem_size; 569 pbus_size_mem(bus, mask, IORESOURCE_MEM, min_mem_size); 570 break; 571 } 572 } 573 EXPORT_SYMBOL(pci_bus_size_bridges); 574 575 void __ref pci_bus_assign_resources(const struct pci_bus *bus) 576 { 577 struct pci_bus *b; 578 struct pci_dev *dev; 579 580 pbus_assign_resources_sorted(bus); 581 582 list_for_each_entry(dev, &bus->devices, bus_list) { 583 b = dev->subordinate; 584 if (!b) 585 continue; 586 587 pci_bus_assign_resources(b); 588 589 switch (dev->class >> 8) { 590 case PCI_CLASS_BRIDGE_PCI: 591 pci_setup_bridge(b); 592 break; 593 594 case PCI_CLASS_BRIDGE_CARDBUS: 595 pci_setup_cardbus(b); 596 break; 597 598 default: 599 dev_info(&dev->dev, "not setting up bridge for bus " 600 "%04x:%02x\n", pci_domain_nr(b), b->number); 601 break; 602 } 603 } 604 } 605 EXPORT_SYMBOL(pci_bus_assign_resources); 606 607 static void pci_bus_dump_res(struct pci_bus *bus) 608 { 609 int i; 610 611 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 612 struct resource *res = bus->resource[i]; 613 614 if (!res || !res->end || !res->flags) 615 continue; 616 617 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res); 618 } 619 } 620 621 static void pci_bus_dump_resources(struct pci_bus *bus) 622 { 623 struct pci_bus *b; 624 struct pci_dev *dev; 625 626 627 pci_bus_dump_res(bus); 628 629 list_for_each_entry(dev, &bus->devices, bus_list) { 630 b = dev->subordinate; 631 if (!b) 632 continue; 633 634 pci_bus_dump_resources(b); 635 } 636 } 637 638 void __init 639 pci_assign_unassigned_resources(void) 640 { 641 struct pci_bus *bus; 642 643 /* Depth first, calculate sizes and alignments of all 644 subordinate buses. */ 645 list_for_each_entry(bus, &pci_root_buses, node) { 646 pci_bus_size_bridges(bus); 647 } 648 /* Depth last, allocate resources and update the hardware. */ 649 list_for_each_entry(bus, &pci_root_buses, node) { 650 pci_bus_assign_resources(bus); 651 pci_enable_bridges(bus); 652 } 653 654 /* dump the resource on buses */ 655 list_for_each_entry(bus, &pci_root_buses, node) { 656 pci_bus_dump_resources(bus); 657 } 658 } 659