xref: /openbmc/linux/drivers/pci/setup-bus.c (revision 552bc94ebeeb189d0ac682dae95cf05e6b72d7fd)
11da177e4SLinus Torvalds /*
21da177e4SLinus Torvalds  *	drivers/pci/setup-bus.c
31da177e4SLinus Torvalds  *
41da177e4SLinus Torvalds  * Extruded from code written by
51da177e4SLinus Torvalds  *      Dave Rusling (david.rusling@reo.mts.dec.com)
61da177e4SLinus Torvalds  *      David Mosberger (davidm@cs.arizona.edu)
71da177e4SLinus Torvalds  *	David Miller (davem@redhat.com)
81da177e4SLinus Torvalds  *
91da177e4SLinus Torvalds  * Support routines for initializing a PCI subsystem.
101da177e4SLinus Torvalds  */
111da177e4SLinus Torvalds 
121da177e4SLinus Torvalds /*
131da177e4SLinus Torvalds  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
141da177e4SLinus Torvalds  *	     PCI-PCI bridges cleanup, sorted resource allocation.
151da177e4SLinus Torvalds  * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
161da177e4SLinus Torvalds  *	     Converted to allocation in 3 passes, which gives
171da177e4SLinus Torvalds  *	     tighter packing. Prefetchable range support.
181da177e4SLinus Torvalds  */
191da177e4SLinus Torvalds 
201da177e4SLinus Torvalds #include <linux/init.h>
211da177e4SLinus Torvalds #include <linux/kernel.h>
221da177e4SLinus Torvalds #include <linux/module.h>
231da177e4SLinus Torvalds #include <linux/pci.h>
241da177e4SLinus Torvalds #include <linux/errno.h>
251da177e4SLinus Torvalds #include <linux/ioport.h>
261da177e4SLinus Torvalds #include <linux/cache.h>
271da177e4SLinus Torvalds #include <linux/slab.h>
2847087700SBjorn Helgaas #include <asm-generic/pci-bridge.h>
296faf17f6SChris Wright #include "pci.h"
301da177e4SLinus Torvalds 
31844393f4SBjorn Helgaas unsigned int pci_flags;
3247087700SBjorn Helgaas 
33bdc4abecSYinghai Lu struct pci_dev_resource {
34bdc4abecSYinghai Lu 	struct list_head list;
352934a0deSYinghai Lu 	struct resource *res;
362934a0deSYinghai Lu 	struct pci_dev *dev;
37568ddef8SYinghai Lu 	resource_size_t start;
38568ddef8SYinghai Lu 	resource_size_t end;
39c8adf9a3SRam Pai 	resource_size_t add_size;
402bbc6942SRam Pai 	resource_size_t min_align;
41568ddef8SYinghai Lu 	unsigned long flags;
42568ddef8SYinghai Lu };
43568ddef8SYinghai Lu 
44bffc56d4SYinghai Lu static void free_list(struct list_head *head)
45bffc56d4SYinghai Lu {
46bffc56d4SYinghai Lu 	struct pci_dev_resource *dev_res, *tmp;
47bffc56d4SYinghai Lu 
48bffc56d4SYinghai Lu 	list_for_each_entry_safe(dev_res, tmp, head, list) {
49bffc56d4SYinghai Lu 		list_del(&dev_res->list);
50bffc56d4SYinghai Lu 		kfree(dev_res);
51bffc56d4SYinghai Lu 	}
52bffc56d4SYinghai Lu }
53094732a5SRam Pai 
54c8adf9a3SRam Pai /**
55c8adf9a3SRam Pai  * add_to_list() - add a new resource tracker to the list
56c8adf9a3SRam Pai  * @head:	Head of the list
57c8adf9a3SRam Pai  * @dev:	device corresponding to which the resource
58c8adf9a3SRam Pai  *		belongs
59c8adf9a3SRam Pai  * @res:	The resource to be tracked
60c8adf9a3SRam Pai  * @add_size:	additional size to be optionally added
61c8adf9a3SRam Pai  *              to the resource
62c8adf9a3SRam Pai  */
63bdc4abecSYinghai Lu static int add_to_list(struct list_head *head,
64c8adf9a3SRam Pai 		 struct pci_dev *dev, struct resource *res,
652bbc6942SRam Pai 		 resource_size_t add_size, resource_size_t min_align)
66568ddef8SYinghai Lu {
67764242a0SYinghai Lu 	struct pci_dev_resource *tmp;
68568ddef8SYinghai Lu 
69bdc4abecSYinghai Lu 	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
70568ddef8SYinghai Lu 	if (!tmp) {
713c78bc61SRyan Desfosses 		pr_warn("add_to_list: kmalloc() failed!\n");
72ef62dfefSYinghai Lu 		return -ENOMEM;
73568ddef8SYinghai Lu 	}
74568ddef8SYinghai Lu 
75568ddef8SYinghai Lu 	tmp->res = res;
76568ddef8SYinghai Lu 	tmp->dev = dev;
77568ddef8SYinghai Lu 	tmp->start = res->start;
78568ddef8SYinghai Lu 	tmp->end = res->end;
79568ddef8SYinghai Lu 	tmp->flags = res->flags;
80c8adf9a3SRam Pai 	tmp->add_size = add_size;
812bbc6942SRam Pai 	tmp->min_align = min_align;
82bdc4abecSYinghai Lu 
83bdc4abecSYinghai Lu 	list_add(&tmp->list, head);
84ef62dfefSYinghai Lu 
85ef62dfefSYinghai Lu 	return 0;
86568ddef8SYinghai Lu }
87568ddef8SYinghai Lu 
88b9b0bba9SYinghai Lu static void remove_from_list(struct list_head *head,
893e6e0d80SYinghai Lu 				 struct resource *res)
903e6e0d80SYinghai Lu {
91b9b0bba9SYinghai Lu 	struct pci_dev_resource *dev_res, *tmp;
923e6e0d80SYinghai Lu 
93b9b0bba9SYinghai Lu 	list_for_each_entry_safe(dev_res, tmp, head, list) {
94b9b0bba9SYinghai Lu 		if (dev_res->res == res) {
95b9b0bba9SYinghai Lu 			list_del(&dev_res->list);
96b9b0bba9SYinghai Lu 			kfree(dev_res);
97bdc4abecSYinghai Lu 			break;
983e6e0d80SYinghai Lu 		}
993e6e0d80SYinghai Lu 	}
1003e6e0d80SYinghai Lu }
1013e6e0d80SYinghai Lu 
102d74b9027SWei Yang static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
1031c372353SYinghai Lu 					       struct resource *res)
1041c372353SYinghai Lu {
105b9b0bba9SYinghai Lu 	struct pci_dev_resource *dev_res;
1061c372353SYinghai Lu 
107b9b0bba9SYinghai Lu 	list_for_each_entry(dev_res, head, list) {
108b9b0bba9SYinghai Lu 		if (dev_res->res == res) {
109b592443dSYinghai Lu 			int idx = res - &dev_res->dev->resource[0];
110b592443dSYinghai Lu 
111b9b0bba9SYinghai Lu 			dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112d74b9027SWei Yang 				 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n",
113b592443dSYinghai Lu 				 idx, dev_res->res,
114d74b9027SWei Yang 				 (unsigned long long)dev_res->add_size,
115d74b9027SWei Yang 				 (unsigned long long)dev_res->min_align);
116b592443dSYinghai Lu 
117d74b9027SWei Yang 			return dev_res;
118bdc4abecSYinghai Lu 		}
1193e6e0d80SYinghai Lu 	}
1201c372353SYinghai Lu 
121d74b9027SWei Yang 	return NULL;
1221c372353SYinghai Lu }
1231c372353SYinghai Lu 
124d74b9027SWei Yang static resource_size_t get_res_add_size(struct list_head *head,
125d74b9027SWei Yang 					struct resource *res)
126d74b9027SWei Yang {
127d74b9027SWei Yang 	struct pci_dev_resource *dev_res;
128d74b9027SWei Yang 
129d74b9027SWei Yang 	dev_res = res_to_dev_res(head, res);
130d74b9027SWei Yang 	return dev_res ? dev_res->add_size : 0;
131d74b9027SWei Yang }
132d74b9027SWei Yang 
133d74b9027SWei Yang static resource_size_t get_res_add_align(struct list_head *head,
134d74b9027SWei Yang 					 struct resource *res)
135d74b9027SWei Yang {
136d74b9027SWei Yang 	struct pci_dev_resource *dev_res;
137d74b9027SWei Yang 
138d74b9027SWei Yang 	dev_res = res_to_dev_res(head, res);
139d74b9027SWei Yang 	return dev_res ? dev_res->min_align : 0;
140d74b9027SWei Yang }
141d74b9027SWei Yang 
142d74b9027SWei Yang 
14378c3b329SYinghai Lu /* Sort resources by alignment */
144bdc4abecSYinghai Lu static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
14578c3b329SYinghai Lu {
14678c3b329SYinghai Lu 	int i;
14778c3b329SYinghai Lu 
14878c3b329SYinghai Lu 	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
14978c3b329SYinghai Lu 		struct resource *r;
150bdc4abecSYinghai Lu 		struct pci_dev_resource *dev_res, *tmp;
15178c3b329SYinghai Lu 		resource_size_t r_align;
152bdc4abecSYinghai Lu 		struct list_head *n;
15378c3b329SYinghai Lu 
15478c3b329SYinghai Lu 		r = &dev->resource[i];
15578c3b329SYinghai Lu 
15678c3b329SYinghai Lu 		if (r->flags & IORESOURCE_PCI_FIXED)
15778c3b329SYinghai Lu 			continue;
15878c3b329SYinghai Lu 
15978c3b329SYinghai Lu 		if (!(r->flags) || r->parent)
16078c3b329SYinghai Lu 			continue;
16178c3b329SYinghai Lu 
16278c3b329SYinghai Lu 		r_align = pci_resource_alignment(dev, r);
16378c3b329SYinghai Lu 		if (!r_align) {
16478c3b329SYinghai Lu 			dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
16578c3b329SYinghai Lu 				 i, r);
16678c3b329SYinghai Lu 			continue;
16778c3b329SYinghai Lu 		}
16878c3b329SYinghai Lu 
169bdc4abecSYinghai Lu 		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
17078c3b329SYinghai Lu 		if (!tmp)
171227f0647SRyan Desfosses 			panic("pdev_sort_resources(): kmalloc() failed!\n");
17278c3b329SYinghai Lu 		tmp->res = r;
17378c3b329SYinghai Lu 		tmp->dev = dev;
174bdc4abecSYinghai Lu 
175bdc4abecSYinghai Lu 		/* fallback is smallest one or list is empty*/
176bdc4abecSYinghai Lu 		n = head;
177bdc4abecSYinghai Lu 		list_for_each_entry(dev_res, head, list) {
178bdc4abecSYinghai Lu 			resource_size_t align;
179bdc4abecSYinghai Lu 
180bdc4abecSYinghai Lu 			align = pci_resource_alignment(dev_res->dev,
181bdc4abecSYinghai Lu 							 dev_res->res);
182bdc4abecSYinghai Lu 
183bdc4abecSYinghai Lu 			if (r_align > align) {
184bdc4abecSYinghai Lu 				n = &dev_res->list;
18578c3b329SYinghai Lu 				break;
18678c3b329SYinghai Lu 			}
18778c3b329SYinghai Lu 		}
188bdc4abecSYinghai Lu 		/* Insert it just before n*/
189bdc4abecSYinghai Lu 		list_add_tail(&tmp->list, n);
19078c3b329SYinghai Lu 	}
19178c3b329SYinghai Lu }
19278c3b329SYinghai Lu 
1936841ec68SYinghai Lu static void __dev_sort_resources(struct pci_dev *dev,
194bdc4abecSYinghai Lu 				 struct list_head *head)
1951da177e4SLinus Torvalds {
1961da177e4SLinus Torvalds 	u16 class = dev->class >> 8;
1971da177e4SLinus Torvalds 
1989bded00bSKenji Kaneshige 	/* Don't touch classless devices or host bridges or ioapics.  */
1996841ec68SYinghai Lu 	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
2006841ec68SYinghai Lu 		return;
2011da177e4SLinus Torvalds 
2029bded00bSKenji Kaneshige 	/* Don't touch ioapic devices already enabled by firmware */
20323186279SSatoru Takeuchi 	if (class == PCI_CLASS_SYSTEM_PIC) {
2049bded00bSKenji Kaneshige 		u16 command;
2059bded00bSKenji Kaneshige 		pci_read_config_word(dev, PCI_COMMAND, &command);
2069bded00bSKenji Kaneshige 		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
2076841ec68SYinghai Lu 			return;
20823186279SSatoru Takeuchi 	}
20923186279SSatoru Takeuchi 
2106841ec68SYinghai Lu 	pdev_sort_resources(dev, head);
2111da177e4SLinus Torvalds }
2121da177e4SLinus Torvalds 
213fc075e1dSRam Pai static inline void reset_resource(struct resource *res)
214fc075e1dSRam Pai {
215fc075e1dSRam Pai 	res->start = 0;
216fc075e1dSRam Pai 	res->end = 0;
217fc075e1dSRam Pai 	res->flags = 0;
218fc075e1dSRam Pai }
219fc075e1dSRam Pai 
220c8adf9a3SRam Pai /**
2219e8bf93aSRam Pai  * reassign_resources_sorted() - satisfy any additional resource requests
222c8adf9a3SRam Pai  *
2239e8bf93aSRam Pai  * @realloc_head : head of the list tracking requests requiring additional
224c8adf9a3SRam Pai  *             resources
225c8adf9a3SRam Pai  * @head     : head of the list tracking requests with allocated
226c8adf9a3SRam Pai  *             resources
227c8adf9a3SRam Pai  *
2289e8bf93aSRam Pai  * Walk through each element of the realloc_head and try to procure
229c8adf9a3SRam Pai  * additional resources for the element, provided the element
230c8adf9a3SRam Pai  * is in the head list.
231c8adf9a3SRam Pai  */
232bdc4abecSYinghai Lu static void reassign_resources_sorted(struct list_head *realloc_head,
233bdc4abecSYinghai Lu 		struct list_head *head)
234c8adf9a3SRam Pai {
235c8adf9a3SRam Pai 	struct resource *res;
236b9b0bba9SYinghai Lu 	struct pci_dev_resource *add_res, *tmp;
237bdc4abecSYinghai Lu 	struct pci_dev_resource *dev_res;
238d74b9027SWei Yang 	resource_size_t add_size, align;
239c8adf9a3SRam Pai 	int idx;
240c8adf9a3SRam Pai 
241b9b0bba9SYinghai Lu 	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
242bdc4abecSYinghai Lu 		bool found_match = false;
243bdc4abecSYinghai Lu 
244b9b0bba9SYinghai Lu 		res = add_res->res;
245c8adf9a3SRam Pai 		/* skip resource that has been reset */
246c8adf9a3SRam Pai 		if (!res->flags)
247c8adf9a3SRam Pai 			goto out;
248c8adf9a3SRam Pai 
249c8adf9a3SRam Pai 		/* skip this resource if not found in head list */
250bdc4abecSYinghai Lu 		list_for_each_entry(dev_res, head, list) {
251bdc4abecSYinghai Lu 			if (dev_res->res == res) {
252bdc4abecSYinghai Lu 				found_match = true;
253bdc4abecSYinghai Lu 				break;
254c8adf9a3SRam Pai 			}
255bdc4abecSYinghai Lu 		}
256bdc4abecSYinghai Lu 		if (!found_match)/* just skip */
257bdc4abecSYinghai Lu 			continue;
258c8adf9a3SRam Pai 
259b9b0bba9SYinghai Lu 		idx = res - &add_res->dev->resource[0];
260b9b0bba9SYinghai Lu 		add_size = add_res->add_size;
261d74b9027SWei Yang 		align = add_res->min_align;
2622bbc6942SRam Pai 		if (!resource_size(res)) {
263d74b9027SWei Yang 			res->start = align;
264c8adf9a3SRam Pai 			res->end = res->start + add_size - 1;
265b9b0bba9SYinghai Lu 			if (pci_assign_resource(add_res->dev, idx))
266c8adf9a3SRam Pai 				reset_resource(res);
2672bbc6942SRam Pai 		} else {
268b9b0bba9SYinghai Lu 			res->flags |= add_res->flags &
269bdc4abecSYinghai Lu 				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
270b9b0bba9SYinghai Lu 			if (pci_reassign_resource(add_res->dev, idx,
271bdc4abecSYinghai Lu 						  add_size, align))
272b9b0bba9SYinghai Lu 				dev_printk(KERN_DEBUG, &add_res->dev->dev,
273b592443dSYinghai Lu 					   "failed to add %llx res[%d]=%pR\n",
274b592443dSYinghai Lu 					   (unsigned long long)add_size,
275b592443dSYinghai Lu 					   idx, res);
276c8adf9a3SRam Pai 		}
277c8adf9a3SRam Pai out:
278b9b0bba9SYinghai Lu 		list_del(&add_res->list);
279b9b0bba9SYinghai Lu 		kfree(add_res);
280c8adf9a3SRam Pai 	}
281c8adf9a3SRam Pai }
282c8adf9a3SRam Pai 
283c8adf9a3SRam Pai /**
284c8adf9a3SRam Pai  * assign_requested_resources_sorted() - satisfy resource requests
285c8adf9a3SRam Pai  *
286c8adf9a3SRam Pai  * @head : head of the list tracking requests for resources
2878356aad4SWanpeng Li  * @fail_head : head of the list tracking requests that could
288c8adf9a3SRam Pai  *		not be allocated
289c8adf9a3SRam Pai  *
290c8adf9a3SRam Pai  * Satisfy resource requests of each element in the list. Add
291c8adf9a3SRam Pai  * requests that could not satisfied to the failed_list.
292c8adf9a3SRam Pai  */
293bdc4abecSYinghai Lu static void assign_requested_resources_sorted(struct list_head *head,
294bdc4abecSYinghai Lu 				 struct list_head *fail_head)
2956841ec68SYinghai Lu {
2966841ec68SYinghai Lu 	struct resource *res;
297bdc4abecSYinghai Lu 	struct pci_dev_resource *dev_res;
2986841ec68SYinghai Lu 	int idx;
2996841ec68SYinghai Lu 
300bdc4abecSYinghai Lu 	list_for_each_entry(dev_res, head, list) {
301bdc4abecSYinghai Lu 		res = dev_res->res;
302bdc4abecSYinghai Lu 		idx = res - &dev_res->dev->resource[0];
303bdc4abecSYinghai Lu 		if (resource_size(res) &&
304bdc4abecSYinghai Lu 		    pci_assign_resource(dev_res->dev, idx)) {
305a3cb999dSYinghai Lu 			if (fail_head) {
3069a928660SYinghai Lu 				/*
3079a928660SYinghai Lu 				 * if the failed res is for ROM BAR, and it will
3089a928660SYinghai Lu 				 * be enabled later, don't add it to the list
3099a928660SYinghai Lu 				 */
3109a928660SYinghai Lu 				if (!((idx == PCI_ROM_RESOURCE) &&
3119a928660SYinghai Lu 				      (!(res->flags & IORESOURCE_ROM_ENABLE))))
31267cc7e26SYinghai Lu 					add_to_list(fail_head,
31367cc7e26SYinghai Lu 						    dev_res->dev, res,
314f7625980SBjorn Helgaas 						    0 /* don't care */,
315f7625980SBjorn Helgaas 						    0 /* don't care */);
3169a928660SYinghai Lu 			}
317fc075e1dSRam Pai 			reset_resource(res);
318542df5deSRajesh Shah 		}
3191da177e4SLinus Torvalds 	}
3201da177e4SLinus Torvalds }
3211da177e4SLinus Torvalds 
322aa914f5eSYinghai Lu static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
323aa914f5eSYinghai Lu {
324aa914f5eSYinghai Lu 	struct pci_dev_resource *fail_res;
325aa914f5eSYinghai Lu 	unsigned long mask = 0;
326aa914f5eSYinghai Lu 
327aa914f5eSYinghai Lu 	/* check failed type */
328aa914f5eSYinghai Lu 	list_for_each_entry(fail_res, fail_head, list)
329aa914f5eSYinghai Lu 		mask |= fail_res->flags;
330aa914f5eSYinghai Lu 
331aa914f5eSYinghai Lu 	/*
332aa914f5eSYinghai Lu 	 * one pref failed resource will set IORESOURCE_MEM,
333aa914f5eSYinghai Lu 	 * as we can allocate pref in non-pref range.
334aa914f5eSYinghai Lu 	 * Will release all assigned non-pref sibling resources
335aa914f5eSYinghai Lu 	 * according to that bit.
336aa914f5eSYinghai Lu 	 */
337aa914f5eSYinghai Lu 	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
338aa914f5eSYinghai Lu }
339aa914f5eSYinghai Lu 
340aa914f5eSYinghai Lu static bool pci_need_to_release(unsigned long mask, struct resource *res)
341aa914f5eSYinghai Lu {
342aa914f5eSYinghai Lu 	if (res->flags & IORESOURCE_IO)
343aa914f5eSYinghai Lu 		return !!(mask & IORESOURCE_IO);
344aa914f5eSYinghai Lu 
345aa914f5eSYinghai Lu 	/* check pref at first */
346aa914f5eSYinghai Lu 	if (res->flags & IORESOURCE_PREFETCH) {
347aa914f5eSYinghai Lu 		if (mask & IORESOURCE_PREFETCH)
348aa914f5eSYinghai Lu 			return true;
349aa914f5eSYinghai Lu 		/* count pref if its parent is non-pref */
350aa914f5eSYinghai Lu 		else if ((mask & IORESOURCE_MEM) &&
351aa914f5eSYinghai Lu 			 !(res->parent->flags & IORESOURCE_PREFETCH))
352aa914f5eSYinghai Lu 			return true;
353aa914f5eSYinghai Lu 		else
354aa914f5eSYinghai Lu 			return false;
355aa914f5eSYinghai Lu 	}
356aa914f5eSYinghai Lu 
357aa914f5eSYinghai Lu 	if (res->flags & IORESOURCE_MEM)
358aa914f5eSYinghai Lu 		return !!(mask & IORESOURCE_MEM);
359aa914f5eSYinghai Lu 
360aa914f5eSYinghai Lu 	return false;	/* should not get here */
361aa914f5eSYinghai Lu }
362aa914f5eSYinghai Lu 
363bdc4abecSYinghai Lu static void __assign_resources_sorted(struct list_head *head,
364bdc4abecSYinghai Lu 				 struct list_head *realloc_head,
365bdc4abecSYinghai Lu 				 struct list_head *fail_head)
366c8adf9a3SRam Pai {
3673e6e0d80SYinghai Lu 	/*
3683e6e0d80SYinghai Lu 	 * Should not assign requested resources at first.
3693e6e0d80SYinghai Lu 	 *   they could be adjacent, so later reassign can not reallocate
3703e6e0d80SYinghai Lu 	 *   them one by one in parent resource window.
371367fa982SMasanari Iida 	 * Try to assign requested + add_size at beginning
3723e6e0d80SYinghai Lu 	 *  if could do that, could get out early.
3733e6e0d80SYinghai Lu 	 *  if could not do that, we still try to assign requested at first,
3743e6e0d80SYinghai Lu 	 *    then try to reassign add_size for some resources.
375aa914f5eSYinghai Lu 	 *
376aa914f5eSYinghai Lu 	 * Separate three resource type checking if we need to release
377aa914f5eSYinghai Lu 	 * assigned resource after requested + add_size try.
378aa914f5eSYinghai Lu 	 *	1. if there is io port assign fail, will release assigned
379aa914f5eSYinghai Lu 	 *	   io port.
380aa914f5eSYinghai Lu 	 *	2. if there is pref mmio assign fail, release assigned
381aa914f5eSYinghai Lu 	 *	   pref mmio.
382aa914f5eSYinghai Lu 	 *	   if assigned pref mmio's parent is non-pref mmio and there
383aa914f5eSYinghai Lu 	 *	   is non-pref mmio assign fail, will release that assigned
384aa914f5eSYinghai Lu 	 *	   pref mmio.
385aa914f5eSYinghai Lu 	 *	3. if there is non-pref mmio assign fail or pref mmio
386aa914f5eSYinghai Lu 	 *	   assigned fail, will release assigned non-pref mmio.
3873e6e0d80SYinghai Lu 	 */
388bdc4abecSYinghai Lu 	LIST_HEAD(save_head);
389bdc4abecSYinghai Lu 	LIST_HEAD(local_fail_head);
390b9b0bba9SYinghai Lu 	struct pci_dev_resource *save_res;
391d74b9027SWei Yang 	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
392aa914f5eSYinghai Lu 	unsigned long fail_type;
393d74b9027SWei Yang 	resource_size_t add_align, align;
3943e6e0d80SYinghai Lu 
3953e6e0d80SYinghai Lu 	/* Check if optional add_size is there */
396bdc4abecSYinghai Lu 	if (!realloc_head || list_empty(realloc_head))
3973e6e0d80SYinghai Lu 		goto requested_and_reassign;
3983e6e0d80SYinghai Lu 
3993e6e0d80SYinghai Lu 	/* Save original start, end, flags etc at first */
400bdc4abecSYinghai Lu 	list_for_each_entry(dev_res, head, list) {
401bdc4abecSYinghai Lu 		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
402bffc56d4SYinghai Lu 			free_list(&save_head);
4033e6e0d80SYinghai Lu 			goto requested_and_reassign;
4043e6e0d80SYinghai Lu 		}
405bdc4abecSYinghai Lu 	}
4063e6e0d80SYinghai Lu 
4073e6e0d80SYinghai Lu 	/* Update res in head list with add_size in realloc_head list */
408d74b9027SWei Yang 	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
409bdc4abecSYinghai Lu 		dev_res->res->end += get_res_add_size(realloc_head,
410bdc4abecSYinghai Lu 							dev_res->res);
4113e6e0d80SYinghai Lu 
412d74b9027SWei Yang 		/*
413d74b9027SWei Yang 		 * There are two kinds of additional resources in the list:
414d74b9027SWei Yang 		 * 1. bridge resource  -- IORESOURCE_STARTALIGN
415d74b9027SWei Yang 		 * 2. SR-IOV resource   -- IORESOURCE_SIZEALIGN
416d74b9027SWei Yang 		 * Here just fix the additional alignment for bridge
417d74b9027SWei Yang 		 */
418d74b9027SWei Yang 		if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
419d74b9027SWei Yang 			continue;
420d74b9027SWei Yang 
421d74b9027SWei Yang 		add_align = get_res_add_align(realloc_head, dev_res->res);
422d74b9027SWei Yang 
423d74b9027SWei Yang 		/*
424d74b9027SWei Yang 		 * The "head" list is sorted by the alignment to make sure
425d74b9027SWei Yang 		 * resources with bigger alignment will be assigned first.
426d74b9027SWei Yang 		 * After we change the alignment of a dev_res in "head" list,
427d74b9027SWei Yang 		 * we need to reorder the list by alignment to make it
428d74b9027SWei Yang 		 * consistent.
429d74b9027SWei Yang 		 */
430d74b9027SWei Yang 		if (add_align > dev_res->res->start) {
431*552bc94eSYinghai Lu 			resource_size_t r_size = resource_size(dev_res->res);
432*552bc94eSYinghai Lu 
433d74b9027SWei Yang 			dev_res->res->start = add_align;
434*552bc94eSYinghai Lu 			dev_res->res->end = add_align + r_size - 1;
435d74b9027SWei Yang 
436d74b9027SWei Yang 			list_for_each_entry(dev_res2, head, list) {
437d74b9027SWei Yang 				align = pci_resource_alignment(dev_res2->dev,
438d74b9027SWei Yang 							       dev_res2->res);
439a6b65983SWei Yang 				if (add_align > align) {
440d74b9027SWei Yang 					list_move_tail(&dev_res->list,
441d74b9027SWei Yang 						       &dev_res2->list);
442a6b65983SWei Yang 					break;
443a6b65983SWei Yang 				}
444d74b9027SWei Yang 			}
445d74b9027SWei Yang                }
446d74b9027SWei Yang 
447d74b9027SWei Yang 	}
448d74b9027SWei Yang 
4493e6e0d80SYinghai Lu 	/* Try updated head list with add_size added */
4503e6e0d80SYinghai Lu 	assign_requested_resources_sorted(head, &local_fail_head);
4513e6e0d80SYinghai Lu 
4523e6e0d80SYinghai Lu 	/* all assigned with add_size ? */
453bdc4abecSYinghai Lu 	if (list_empty(&local_fail_head)) {
4543e6e0d80SYinghai Lu 		/* Remove head list from realloc_head list */
455bdc4abecSYinghai Lu 		list_for_each_entry(dev_res, head, list)
456bdc4abecSYinghai Lu 			remove_from_list(realloc_head, dev_res->res);
457bffc56d4SYinghai Lu 		free_list(&save_head);
458bffc56d4SYinghai Lu 		free_list(head);
4593e6e0d80SYinghai Lu 		return;
4603e6e0d80SYinghai Lu 	}
4613e6e0d80SYinghai Lu 
462aa914f5eSYinghai Lu 	/* check failed type */
463aa914f5eSYinghai Lu 	fail_type = pci_fail_res_type_mask(&local_fail_head);
464aa914f5eSYinghai Lu 	/* remove not need to be released assigned res from head list etc */
465aa914f5eSYinghai Lu 	list_for_each_entry_safe(dev_res, tmp_res, head, list)
466aa914f5eSYinghai Lu 		if (dev_res->res->parent &&
467aa914f5eSYinghai Lu 		    !pci_need_to_release(fail_type, dev_res->res)) {
468aa914f5eSYinghai Lu 			/* remove it from realloc_head list */
469aa914f5eSYinghai Lu 			remove_from_list(realloc_head, dev_res->res);
470aa914f5eSYinghai Lu 			remove_from_list(&save_head, dev_res->res);
471aa914f5eSYinghai Lu 			list_del(&dev_res->list);
472aa914f5eSYinghai Lu 			kfree(dev_res);
473aa914f5eSYinghai Lu 		}
474aa914f5eSYinghai Lu 
475bffc56d4SYinghai Lu 	free_list(&local_fail_head);
4763e6e0d80SYinghai Lu 	/* Release assigned resource */
477bdc4abecSYinghai Lu 	list_for_each_entry(dev_res, head, list)
478bdc4abecSYinghai Lu 		if (dev_res->res->parent)
479bdc4abecSYinghai Lu 			release_resource(dev_res->res);
4803e6e0d80SYinghai Lu 	/* Restore start/end/flags from saved list */
481b9b0bba9SYinghai Lu 	list_for_each_entry(save_res, &save_head, list) {
482b9b0bba9SYinghai Lu 		struct resource *res = save_res->res;
4833e6e0d80SYinghai Lu 
484b9b0bba9SYinghai Lu 		res->start = save_res->start;
485b9b0bba9SYinghai Lu 		res->end = save_res->end;
486b9b0bba9SYinghai Lu 		res->flags = save_res->flags;
4873e6e0d80SYinghai Lu 	}
488bffc56d4SYinghai Lu 	free_list(&save_head);
4893e6e0d80SYinghai Lu 
4903e6e0d80SYinghai Lu requested_and_reassign:
491c8adf9a3SRam Pai 	/* Satisfy the must-have resource requests */
492c8adf9a3SRam Pai 	assign_requested_resources_sorted(head, fail_head);
493c8adf9a3SRam Pai 
4940a2daa1cSRam Pai 	/* Try to satisfy any additional optional resource
495c8adf9a3SRam Pai 		requests */
4969e8bf93aSRam Pai 	if (realloc_head)
4979e8bf93aSRam Pai 		reassign_resources_sorted(realloc_head, head);
498bffc56d4SYinghai Lu 	free_list(head);
499c8adf9a3SRam Pai }
500c8adf9a3SRam Pai 
5016841ec68SYinghai Lu static void pdev_assign_resources_sorted(struct pci_dev *dev,
502bdc4abecSYinghai Lu 				 struct list_head *add_head,
503bdc4abecSYinghai Lu 				 struct list_head *fail_head)
5046841ec68SYinghai Lu {
505bdc4abecSYinghai Lu 	LIST_HEAD(head);
5066841ec68SYinghai Lu 
5076841ec68SYinghai Lu 	__dev_sort_resources(dev, &head);
5088424d759SYinghai Lu 	__assign_resources_sorted(&head, add_head, fail_head);
5096841ec68SYinghai Lu 
5106841ec68SYinghai Lu }
5116841ec68SYinghai Lu 
5126841ec68SYinghai Lu static void pbus_assign_resources_sorted(const struct pci_bus *bus,
513bdc4abecSYinghai Lu 					 struct list_head *realloc_head,
514bdc4abecSYinghai Lu 					 struct list_head *fail_head)
5156841ec68SYinghai Lu {
5166841ec68SYinghai Lu 	struct pci_dev *dev;
517bdc4abecSYinghai Lu 	LIST_HEAD(head);
5186841ec68SYinghai Lu 
5196841ec68SYinghai Lu 	list_for_each_entry(dev, &bus->devices, bus_list)
5206841ec68SYinghai Lu 		__dev_sort_resources(dev, &head);
5216841ec68SYinghai Lu 
5229e8bf93aSRam Pai 	__assign_resources_sorted(&head, realloc_head, fail_head);
5236841ec68SYinghai Lu }
5246841ec68SYinghai Lu 
525b3743fa4SDominik Brodowski void pci_setup_cardbus(struct pci_bus *bus)
5261da177e4SLinus Torvalds {
5271da177e4SLinus Torvalds 	struct pci_dev *bridge = bus->self;
528c7dabef8SBjorn Helgaas 	struct resource *res;
5291da177e4SLinus Torvalds 	struct pci_bus_region region;
5301da177e4SLinus Torvalds 
531b918c62eSYinghai Lu 	dev_info(&bridge->dev, "CardBus bridge to %pR\n",
532b918c62eSYinghai Lu 		 &bus->busn_res);
5331da177e4SLinus Torvalds 
534c7dabef8SBjorn Helgaas 	res = bus->resource[0];
535fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
536c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_IO) {
5371da177e4SLinus Torvalds 		/*
5381da177e4SLinus Torvalds 		 * The IO resource is allocated a range twice as large as it
5391da177e4SLinus Torvalds 		 * would normally need.  This allows us to set both IO regs.
5401da177e4SLinus Torvalds 		 */
541c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
5421da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
5431da177e4SLinus Torvalds 					region.start);
5441da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
5451da177e4SLinus Torvalds 					region.end);
5461da177e4SLinus Torvalds 	}
5471da177e4SLinus Torvalds 
548c7dabef8SBjorn Helgaas 	res = bus->resource[1];
549fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
550c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_IO) {
551c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
5521da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
5531da177e4SLinus Torvalds 					region.start);
5541da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
5551da177e4SLinus Torvalds 					region.end);
5561da177e4SLinus Torvalds 	}
5571da177e4SLinus Torvalds 
558c7dabef8SBjorn Helgaas 	res = bus->resource[2];
559fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
560c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_MEM) {
561c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
5621da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
5631da177e4SLinus Torvalds 					region.start);
5641da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
5651da177e4SLinus Torvalds 					region.end);
5661da177e4SLinus Torvalds 	}
5671da177e4SLinus Torvalds 
568c7dabef8SBjorn Helgaas 	res = bus->resource[3];
569fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
570c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_MEM) {
571c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
5721da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
5731da177e4SLinus Torvalds 					region.start);
5741da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
5751da177e4SLinus Torvalds 					region.end);
5761da177e4SLinus Torvalds 	}
5771da177e4SLinus Torvalds }
578b3743fa4SDominik Brodowski EXPORT_SYMBOL(pci_setup_cardbus);
5791da177e4SLinus Torvalds 
5801da177e4SLinus Torvalds /* Initialize bridges with base/limit values we have collected.
5811da177e4SLinus Torvalds    PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
5821da177e4SLinus Torvalds    requires that if there is no I/O ports or memory behind the
5831da177e4SLinus Torvalds    bridge, corresponding range must be turned off by writing base
5841da177e4SLinus Torvalds    value greater than limit to the bridge's base/limit registers.
5851da177e4SLinus Torvalds 
5861da177e4SLinus Torvalds    Note: care must be taken when updating I/O base/limit registers
5871da177e4SLinus Torvalds    of bridges which support 32-bit I/O. This update requires two
5881da177e4SLinus Torvalds    config space writes, so it's quite possible that an I/O window of
5891da177e4SLinus Torvalds    the bridge will have some undesirable address (e.g. 0) after the
5901da177e4SLinus Torvalds    first write. Ditto 64-bit prefetchable MMIO.  */
5913f2f4dc4SYinghai Lu static void pci_setup_bridge_io(struct pci_dev *bridge)
5921da177e4SLinus Torvalds {
593c7dabef8SBjorn Helgaas 	struct resource *res;
5941da177e4SLinus Torvalds 	struct pci_bus_region region;
5952b28ae19SBjorn Helgaas 	unsigned long io_mask;
5962b28ae19SBjorn Helgaas 	u8 io_base_lo, io_limit_lo;
5975b764b83SBjorn Helgaas 	u16 l;
5985b764b83SBjorn Helgaas 	u32 io_upper16;
5991da177e4SLinus Torvalds 
6002b28ae19SBjorn Helgaas 	io_mask = PCI_IO_RANGE_MASK;
6012b28ae19SBjorn Helgaas 	if (bridge->io_window_1k)
6022b28ae19SBjorn Helgaas 		io_mask = PCI_IO_1K_RANGE_MASK;
6032b28ae19SBjorn Helgaas 
6041da177e4SLinus Torvalds 	/* Set up the top and bottom of the PCI I/O segment for this bus. */
6053f2f4dc4SYinghai Lu 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
606fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
607c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_IO) {
6085b764b83SBjorn Helgaas 		pci_read_config_word(bridge, PCI_IO_BASE, &l);
6092b28ae19SBjorn Helgaas 		io_base_lo = (region.start >> 8) & io_mask;
6102b28ae19SBjorn Helgaas 		io_limit_lo = (region.end >> 8) & io_mask;
6115b764b83SBjorn Helgaas 		l = ((u16) io_limit_lo << 8) | io_base_lo;
6121da177e4SLinus Torvalds 		/* Set up upper 16 bits of I/O base/limit. */
6131da177e4SLinus Torvalds 		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
614c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
6157cc5997dSYinghai Lu 	} else {
6161da177e4SLinus Torvalds 		/* Clear upper 16 bits of I/O base/limit. */
6171da177e4SLinus Torvalds 		io_upper16 = 0;
6181da177e4SLinus Torvalds 		l = 0x00f0;
6191da177e4SLinus Torvalds 	}
6201da177e4SLinus Torvalds 	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
6211da177e4SLinus Torvalds 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
6221da177e4SLinus Torvalds 	/* Update lower 16 bits of I/O base/limit. */
6235b764b83SBjorn Helgaas 	pci_write_config_word(bridge, PCI_IO_BASE, l);
6241da177e4SLinus Torvalds 	/* Update upper 16 bits of I/O base/limit. */
6251da177e4SLinus Torvalds 	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
6267cc5997dSYinghai Lu }
6271da177e4SLinus Torvalds 
6283f2f4dc4SYinghai Lu static void pci_setup_bridge_mmio(struct pci_dev *bridge)
6297cc5997dSYinghai Lu {
6307cc5997dSYinghai Lu 	struct resource *res;
6317cc5997dSYinghai Lu 	struct pci_bus_region region;
6327cc5997dSYinghai Lu 	u32 l;
6337cc5997dSYinghai Lu 
6347cc5997dSYinghai Lu 	/* Set up the top and bottom of the PCI Memory segment for this bus. */
6353f2f4dc4SYinghai Lu 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
636fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
637c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_MEM) {
6381da177e4SLinus Torvalds 		l = (region.start >> 16) & 0xfff0;
6391da177e4SLinus Torvalds 		l |= region.end & 0xfff00000;
640c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
6417cc5997dSYinghai Lu 	} else {
6421da177e4SLinus Torvalds 		l = 0x0000fff0;
6431da177e4SLinus Torvalds 	}
6441da177e4SLinus Torvalds 	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
6457cc5997dSYinghai Lu }
6467cc5997dSYinghai Lu 
6473f2f4dc4SYinghai Lu static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
6487cc5997dSYinghai Lu {
6497cc5997dSYinghai Lu 	struct resource *res;
6507cc5997dSYinghai Lu 	struct pci_bus_region region;
6517cc5997dSYinghai Lu 	u32 l, bu, lu;
6521da177e4SLinus Torvalds 
6531da177e4SLinus Torvalds 	/* Clear out the upper 32 bits of PREF limit.
6541da177e4SLinus Torvalds 	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
6551da177e4SLinus Torvalds 	   disables PREF range, which is ok. */
6561da177e4SLinus Torvalds 	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
6571da177e4SLinus Torvalds 
6581da177e4SLinus Torvalds 	/* Set up PREF base/limit. */
659c40a22e0SBenjamin Herrenschmidt 	bu = lu = 0;
6603f2f4dc4SYinghai Lu 	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
661fc279850SYinghai Lu 	pcibios_resource_to_bus(bridge->bus, &region, res);
662c7dabef8SBjorn Helgaas 	if (res->flags & IORESOURCE_PREFETCH) {
6631da177e4SLinus Torvalds 		l = (region.start >> 16) & 0xfff0;
6641da177e4SLinus Torvalds 		l |= region.end & 0xfff00000;
665c7dabef8SBjorn Helgaas 		if (res->flags & IORESOURCE_MEM_64) {
66613d36c24SAndrew Morton 			bu = upper_32_bits(region.start);
66713d36c24SAndrew Morton 			lu = upper_32_bits(region.end);
6681f82de10SYinghai Lu 		}
669c7dabef8SBjorn Helgaas 		dev_info(&bridge->dev, "  bridge window %pR\n", res);
6707cc5997dSYinghai Lu 	} else {
6711da177e4SLinus Torvalds 		l = 0x0000fff0;
6721da177e4SLinus Torvalds 	}
6731da177e4SLinus Torvalds 	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
6741da177e4SLinus Torvalds 
675c40a22e0SBenjamin Herrenschmidt 	/* Set the upper 32 bits of PREF base & limit. */
676c40a22e0SBenjamin Herrenschmidt 	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
677c40a22e0SBenjamin Herrenschmidt 	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
6787cc5997dSYinghai Lu }
6797cc5997dSYinghai Lu 
6807cc5997dSYinghai Lu static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
6817cc5997dSYinghai Lu {
6827cc5997dSYinghai Lu 	struct pci_dev *bridge = bus->self;
6837cc5997dSYinghai Lu 
684b918c62eSYinghai Lu 	dev_info(&bridge->dev, "PCI bridge to %pR\n",
685b918c62eSYinghai Lu 		 &bus->busn_res);
6867cc5997dSYinghai Lu 
6877cc5997dSYinghai Lu 	if (type & IORESOURCE_IO)
6883f2f4dc4SYinghai Lu 		pci_setup_bridge_io(bridge);
6897cc5997dSYinghai Lu 
6907cc5997dSYinghai Lu 	if (type & IORESOURCE_MEM)
6913f2f4dc4SYinghai Lu 		pci_setup_bridge_mmio(bridge);
6927cc5997dSYinghai Lu 
6937cc5997dSYinghai Lu 	if (type & IORESOURCE_PREFETCH)
6943f2f4dc4SYinghai Lu 		pci_setup_bridge_mmio_pref(bridge);
6951da177e4SLinus Torvalds 
6961da177e4SLinus Torvalds 	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
6971da177e4SLinus Torvalds }
6981da177e4SLinus Torvalds 
699e2444273SBenjamin Herrenschmidt void pci_setup_bridge(struct pci_bus *bus)
7007cc5997dSYinghai Lu {
7017cc5997dSYinghai Lu 	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
7027cc5997dSYinghai Lu 				  IORESOURCE_PREFETCH;
7037cc5997dSYinghai Lu 
7047cc5997dSYinghai Lu 	__pci_setup_bridge(bus, type);
7057cc5997dSYinghai Lu }
7067cc5997dSYinghai Lu 
7078505e729SYinghai Lu 
7088505e729SYinghai Lu int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
7098505e729SYinghai Lu {
7108505e729SYinghai Lu 	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
7118505e729SYinghai Lu 		return 0;
7128505e729SYinghai Lu 
7138505e729SYinghai Lu 	if (pci_claim_resource(bridge, i) == 0)
7148505e729SYinghai Lu 		return 0;	/* claimed the window */
7158505e729SYinghai Lu 
7168505e729SYinghai Lu 	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
7178505e729SYinghai Lu 		return 0;
7188505e729SYinghai Lu 
7198505e729SYinghai Lu 	if (!pci_bus_clip_resource(bridge, i))
7208505e729SYinghai Lu 		return -EINVAL;	/* clipping didn't change anything */
7218505e729SYinghai Lu 
7228505e729SYinghai Lu 	switch (i - PCI_BRIDGE_RESOURCES) {
7238505e729SYinghai Lu 	case 0:
7248505e729SYinghai Lu 		pci_setup_bridge_io(bridge);
7258505e729SYinghai Lu 		break;
7268505e729SYinghai Lu 	case 1:
7278505e729SYinghai Lu 		pci_setup_bridge_mmio(bridge);
7288505e729SYinghai Lu 		break;
7298505e729SYinghai Lu 	case 2:
7308505e729SYinghai Lu 		pci_setup_bridge_mmio_pref(bridge);
7318505e729SYinghai Lu 		break;
7328505e729SYinghai Lu 	default:
7338505e729SYinghai Lu 		return -EINVAL;
7348505e729SYinghai Lu 	}
7358505e729SYinghai Lu 
7368505e729SYinghai Lu 	if (pci_claim_resource(bridge, i) == 0)
7378505e729SYinghai Lu 		return 0;	/* claimed a smaller window */
7388505e729SYinghai Lu 
7398505e729SYinghai Lu 	return -EINVAL;
7408505e729SYinghai Lu }
7418505e729SYinghai Lu 
7421da177e4SLinus Torvalds /* Check whether the bridge supports optional I/O and
7431da177e4SLinus Torvalds    prefetchable memory ranges. If not, the respective
7441da177e4SLinus Torvalds    base/limit registers must be read-only and read as 0. */
74596bde06aSSam Ravnborg static void pci_bridge_check_ranges(struct pci_bus *bus)
7461da177e4SLinus Torvalds {
7471da177e4SLinus Torvalds 	u16 io;
7481da177e4SLinus Torvalds 	u32 pmem;
7491da177e4SLinus Torvalds 	struct pci_dev *bridge = bus->self;
7501da177e4SLinus Torvalds 	struct resource *b_res;
7511da177e4SLinus Torvalds 
7521da177e4SLinus Torvalds 	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
7531da177e4SLinus Torvalds 	b_res[1].flags |= IORESOURCE_MEM;
7541da177e4SLinus Torvalds 
7551da177e4SLinus Torvalds 	pci_read_config_word(bridge, PCI_IO_BASE, &io);
7561da177e4SLinus Torvalds 	if (!io) {
757d2f54d9bSBjorn Helgaas 		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
7581da177e4SLinus Torvalds 		pci_read_config_word(bridge, PCI_IO_BASE, &io);
7591da177e4SLinus Torvalds 		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
7601da177e4SLinus Torvalds 	}
7611da177e4SLinus Torvalds 	if (io)
7621da177e4SLinus Torvalds 		b_res[0].flags |= IORESOURCE_IO;
763d2f54d9bSBjorn Helgaas 
7641da177e4SLinus Torvalds 	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
7651da177e4SLinus Torvalds 	    disconnect boundary by one PCI data phase.
7661da177e4SLinus Torvalds 	    Workaround: do not use prefetching on this device. */
7671da177e4SLinus Torvalds 	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
7681da177e4SLinus Torvalds 		return;
769d2f54d9bSBjorn Helgaas 
7701da177e4SLinus Torvalds 	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
7711da177e4SLinus Torvalds 	if (!pmem) {
7721da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
773d2f54d9bSBjorn Helgaas 					       0xffe0fff0);
7741da177e4SLinus Torvalds 		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
7751da177e4SLinus Torvalds 		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
7761da177e4SLinus Torvalds 	}
7771f82de10SYinghai Lu 	if (pmem) {
7781da177e4SLinus Torvalds 		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
77999586105SYinghai Lu 		if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
78099586105SYinghai Lu 		    PCI_PREF_RANGE_TYPE_64) {
7811f82de10SYinghai Lu 			b_res[2].flags |= IORESOURCE_MEM_64;
78299586105SYinghai Lu 			b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
78399586105SYinghai Lu 		}
7841f82de10SYinghai Lu 	}
7851f82de10SYinghai Lu 
7861f82de10SYinghai Lu 	/* double check if bridge does support 64 bit pref */
7871f82de10SYinghai Lu 	if (b_res[2].flags & IORESOURCE_MEM_64) {
7881f82de10SYinghai Lu 		u32 mem_base_hi, tmp;
7891f82de10SYinghai Lu 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
7901f82de10SYinghai Lu 					 &mem_base_hi);
7911f82de10SYinghai Lu 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
7921f82de10SYinghai Lu 					       0xffffffff);
7931f82de10SYinghai Lu 		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
7941f82de10SYinghai Lu 		if (!tmp)
7951f82de10SYinghai Lu 			b_res[2].flags &= ~IORESOURCE_MEM_64;
7961f82de10SYinghai Lu 		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
7971f82de10SYinghai Lu 				       mem_base_hi);
7981f82de10SYinghai Lu 	}
7991da177e4SLinus Torvalds }
8001da177e4SLinus Torvalds 
8011da177e4SLinus Torvalds /* Helper function for sizing routines: find first available
8021da177e4SLinus Torvalds    bus resource of a given type. Note: we intentionally skip
8031da177e4SLinus Torvalds    the bus resources which have already been assigned (that is,
8041da177e4SLinus Torvalds    have non-NULL parent resource). */
8055b285415SYinghai Lu static struct resource *find_free_bus_resource(struct pci_bus *bus,
8065b285415SYinghai Lu 			 unsigned long type_mask, unsigned long type)
8071da177e4SLinus Torvalds {
8081da177e4SLinus Torvalds 	int i;
8091da177e4SLinus Torvalds 	struct resource *r;
8101da177e4SLinus Torvalds 
81189a74eccSBjorn Helgaas 	pci_bus_for_each_resource(bus, r, i) {
812299de034SIvan Kokshaysky 		if (r == &ioport_resource || r == &iomem_resource)
813299de034SIvan Kokshaysky 			continue;
81455a10984SJesse Barnes 		if (r && (r->flags & type_mask) == type && !r->parent)
8151da177e4SLinus Torvalds 			return r;
8161da177e4SLinus Torvalds 	}
8171da177e4SLinus Torvalds 	return NULL;
8181da177e4SLinus Torvalds }
8191da177e4SLinus Torvalds 
82013583b16SRam Pai static resource_size_t calculate_iosize(resource_size_t size,
82113583b16SRam Pai 		resource_size_t min_size,
82213583b16SRam Pai 		resource_size_t size1,
82313583b16SRam Pai 		resource_size_t old_size,
82413583b16SRam Pai 		resource_size_t align)
82513583b16SRam Pai {
82613583b16SRam Pai 	if (size < min_size)
82713583b16SRam Pai 		size = min_size;
82813583b16SRam Pai 	if (old_size == 1)
82913583b16SRam Pai 		old_size = 0;
83013583b16SRam Pai 	/* To be fixed in 2.5: we should have sort of HAVE_ISA
83113583b16SRam Pai 	   flag in the struct pci_bus. */
83213583b16SRam Pai #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
83313583b16SRam Pai 	size = (size & 0xff) + ((size & ~0xffUL) << 2);
83413583b16SRam Pai #endif
83513583b16SRam Pai 	size = ALIGN(size + size1, align);
83613583b16SRam Pai 	if (size < old_size)
83713583b16SRam Pai 		size = old_size;
83813583b16SRam Pai 	return size;
83913583b16SRam Pai }
84013583b16SRam Pai 
84113583b16SRam Pai static resource_size_t calculate_memsize(resource_size_t size,
84213583b16SRam Pai 		resource_size_t min_size,
84313583b16SRam Pai 		resource_size_t size1,
84413583b16SRam Pai 		resource_size_t old_size,
84513583b16SRam Pai 		resource_size_t align)
84613583b16SRam Pai {
84713583b16SRam Pai 	if (size < min_size)
84813583b16SRam Pai 		size = min_size;
84913583b16SRam Pai 	if (old_size == 1)
85013583b16SRam Pai 		old_size = 0;
85113583b16SRam Pai 	if (size < old_size)
85213583b16SRam Pai 		size = old_size;
85313583b16SRam Pai 	size = ALIGN(size + size1, align);
85413583b16SRam Pai 	return size;
85513583b16SRam Pai }
85613583b16SRam Pai 
857ac5ad93eSGavin Shan resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
858ac5ad93eSGavin Shan 						unsigned long type)
859ac5ad93eSGavin Shan {
860ac5ad93eSGavin Shan 	return 1;
861ac5ad93eSGavin Shan }
862ac5ad93eSGavin Shan 
863ac5ad93eSGavin Shan #define PCI_P2P_DEFAULT_MEM_ALIGN	0x100000	/* 1MiB */
864ac5ad93eSGavin Shan #define PCI_P2P_DEFAULT_IO_ALIGN	0x1000		/* 4KiB */
865ac5ad93eSGavin Shan #define PCI_P2P_DEFAULT_IO_ALIGN_1K	0x400		/* 1KiB */
866ac5ad93eSGavin Shan 
867ac5ad93eSGavin Shan static resource_size_t window_alignment(struct pci_bus *bus,
868ac5ad93eSGavin Shan 					unsigned long type)
869ac5ad93eSGavin Shan {
870ac5ad93eSGavin Shan 	resource_size_t align = 1, arch_align;
871ac5ad93eSGavin Shan 
872ac5ad93eSGavin Shan 	if (type & IORESOURCE_MEM)
873ac5ad93eSGavin Shan 		align = PCI_P2P_DEFAULT_MEM_ALIGN;
874ac5ad93eSGavin Shan 	else if (type & IORESOURCE_IO) {
875ac5ad93eSGavin Shan 		/*
876ac5ad93eSGavin Shan 		 * Per spec, I/O windows are 4K-aligned, but some
877ac5ad93eSGavin Shan 		 * bridges have an extension to support 1K alignment.
878ac5ad93eSGavin Shan 		 */
879ac5ad93eSGavin Shan 		if (bus->self->io_window_1k)
880ac5ad93eSGavin Shan 			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
881ac5ad93eSGavin Shan 		else
882ac5ad93eSGavin Shan 			align = PCI_P2P_DEFAULT_IO_ALIGN;
883ac5ad93eSGavin Shan 	}
884ac5ad93eSGavin Shan 
885ac5ad93eSGavin Shan 	arch_align = pcibios_window_alignment(bus, type);
886ac5ad93eSGavin Shan 	return max(align, arch_align);
887ac5ad93eSGavin Shan }
888ac5ad93eSGavin Shan 
889c8adf9a3SRam Pai /**
890c8adf9a3SRam Pai  * pbus_size_io() - size the io window of a given bus
891c8adf9a3SRam Pai  *
892c8adf9a3SRam Pai  * @bus : the bus
893c8adf9a3SRam Pai  * @min_size : the minimum io window that must to be allocated
894c8adf9a3SRam Pai  * @add_size : additional optional io window
8959e8bf93aSRam Pai  * @realloc_head : track the additional io window on this list
896c8adf9a3SRam Pai  *
897c8adf9a3SRam Pai  * Sizing the IO windows of the PCI-PCI bridge is trivial,
898fd591341SYinghai Lu  * since these windows have 1K or 4K granularity and the IO ranges
899c8adf9a3SRam Pai  * of non-bridge PCI devices are limited to 256 bytes.
900c8adf9a3SRam Pai  * We must be careful with the ISA aliasing though.
901c8adf9a3SRam Pai  */
902c8adf9a3SRam Pai static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
903bdc4abecSYinghai Lu 		resource_size_t add_size, struct list_head *realloc_head)
9041da177e4SLinus Torvalds {
9051da177e4SLinus Torvalds 	struct pci_dev *dev;
9065b285415SYinghai Lu 	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
9075b285415SYinghai Lu 							IORESOURCE_IO);
90811251a86SWei Yang 	resource_size_t size = 0, size0 = 0, size1 = 0;
909be768912SYinghai Lu 	resource_size_t children_add_size = 0;
9102d1d6678SBjorn Helgaas 	resource_size_t min_align, align;
9111da177e4SLinus Torvalds 
9121da177e4SLinus Torvalds 	if (!b_res)
9131da177e4SLinus Torvalds 		return;
9141da177e4SLinus Torvalds 
9152d1d6678SBjorn Helgaas 	min_align = window_alignment(bus, IORESOURCE_IO);
9161da177e4SLinus Torvalds 	list_for_each_entry(dev, &bus->devices, bus_list) {
9171da177e4SLinus Torvalds 		int i;
9181da177e4SLinus Torvalds 
9191da177e4SLinus Torvalds 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
9201da177e4SLinus Torvalds 			struct resource *r = &dev->resource[i];
9211da177e4SLinus Torvalds 			unsigned long r_size;
9221da177e4SLinus Torvalds 
9231da177e4SLinus Torvalds 			if (r->parent || !(r->flags & IORESOURCE_IO))
9241da177e4SLinus Torvalds 				continue;
925022edd86SZhao, Yu 			r_size = resource_size(r);
9261da177e4SLinus Torvalds 
9271da177e4SLinus Torvalds 			if (r_size < 0x400)
9281da177e4SLinus Torvalds 				/* Might be re-aligned for ISA */
9291da177e4SLinus Torvalds 				size += r_size;
9301da177e4SLinus Torvalds 			else
9311da177e4SLinus Torvalds 				size1 += r_size;
932be768912SYinghai Lu 
933fd591341SYinghai Lu 			align = pci_resource_alignment(dev, r);
934fd591341SYinghai Lu 			if (align > min_align)
935fd591341SYinghai Lu 				min_align = align;
936fd591341SYinghai Lu 
9379e8bf93aSRam Pai 			if (realloc_head)
9389e8bf93aSRam Pai 				children_add_size += get_res_add_size(realloc_head, r);
9391da177e4SLinus Torvalds 		}
9401da177e4SLinus Torvalds 	}
941fd591341SYinghai Lu 
942c8adf9a3SRam Pai 	size0 = calculate_iosize(size, min_size, size1,
943fd591341SYinghai Lu 			resource_size(b_res), min_align);
944be768912SYinghai Lu 	if (children_add_size > add_size)
945be768912SYinghai Lu 		add_size = children_add_size;
9469e8bf93aSRam Pai 	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
947a4ac9feaSYinghai Lu 		calculate_iosize(size, min_size, add_size + size1,
948fd591341SYinghai Lu 			resource_size(b_res), min_align);
949c8adf9a3SRam Pai 	if (!size0 && !size1) {
950865df576SBjorn Helgaas 		if (b_res->start || b_res->end)
951227f0647SRyan Desfosses 			dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
952227f0647SRyan Desfosses 				 b_res, &bus->busn_res);
9531da177e4SLinus Torvalds 		b_res->flags = 0;
9541da177e4SLinus Torvalds 		return;
9551da177e4SLinus Torvalds 	}
956fd591341SYinghai Lu 
957fd591341SYinghai Lu 	b_res->start = min_align;
958c8adf9a3SRam Pai 	b_res->end = b_res->start + size0 - 1;
95988452565SIvan Kokshaysky 	b_res->flags |= IORESOURCE_STARTALIGN;
960b592443dSYinghai Lu 	if (size1 > size0 && realloc_head) {
961fd591341SYinghai Lu 		add_to_list(realloc_head, bus->self, b_res, size1-size0,
962fd591341SYinghai Lu 			    min_align);
963227f0647SRyan Desfosses 		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
964227f0647SRyan Desfosses 			   b_res, &bus->busn_res,
96511251a86SWei Yang 			   (unsigned long long)size1-size0);
966b592443dSYinghai Lu 	}
9671da177e4SLinus Torvalds }
9681da177e4SLinus Torvalds 
969c121504eSGavin Shan static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
970c121504eSGavin Shan 						  int max_order)
971c121504eSGavin Shan {
972c121504eSGavin Shan 	resource_size_t align = 0;
973c121504eSGavin Shan 	resource_size_t min_align = 0;
974c121504eSGavin Shan 	int order;
975c121504eSGavin Shan 
976c121504eSGavin Shan 	for (order = 0; order <= max_order; order++) {
977c121504eSGavin Shan 		resource_size_t align1 = 1;
978c121504eSGavin Shan 
979c121504eSGavin Shan 		align1 <<= (order + 20);
980c121504eSGavin Shan 
981c121504eSGavin Shan 		if (!align)
982c121504eSGavin Shan 			min_align = align1;
983c121504eSGavin Shan 		else if (ALIGN(align + min_align, min_align) < align1)
984c121504eSGavin Shan 			min_align = align1 >> 1;
985c121504eSGavin Shan 		align += aligns[order];
986c121504eSGavin Shan 	}
987c121504eSGavin Shan 
988c121504eSGavin Shan 	return min_align;
989c121504eSGavin Shan }
990c121504eSGavin Shan 
991c8adf9a3SRam Pai /**
992c8adf9a3SRam Pai  * pbus_size_mem() - size the memory window of a given bus
993c8adf9a3SRam Pai  *
994c8adf9a3SRam Pai  * @bus : the bus
995496f70cfSWei Yang  * @mask: mask the resource flag, then compare it with type
996496f70cfSWei Yang  * @type: the type of free resource from bridge
9975b285415SYinghai Lu  * @type2: second match type
9985b285415SYinghai Lu  * @type3: third match type
999c8adf9a3SRam Pai  * @min_size : the minimum memory window that must to be allocated
1000c8adf9a3SRam Pai  * @add_size : additional optional memory window
10019e8bf93aSRam Pai  * @realloc_head : track the additional memory window on this list
1002c8adf9a3SRam Pai  *
1003c8adf9a3SRam Pai  * Calculate the size of the bus and minimal alignment which
1004c8adf9a3SRam Pai  * guarantees that all child resources fit in this size.
100530afe8d0SBjorn Helgaas  *
100630afe8d0SBjorn Helgaas  * Returns -ENOSPC if there's no available bus resource of the desired type.
100730afe8d0SBjorn Helgaas  * Otherwise, sets the bus resource start/end to indicate the required
100830afe8d0SBjorn Helgaas  * size, adds things to realloc_head (if supplied), and returns 0.
1009c8adf9a3SRam Pai  */
101028760489SEric W. Biederman static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
10115b285415SYinghai Lu 			 unsigned long type, unsigned long type2,
10125b285415SYinghai Lu 			 unsigned long type3,
10135b285415SYinghai Lu 			 resource_size_t min_size, resource_size_t add_size,
1014bdc4abecSYinghai Lu 			 struct list_head *realloc_head)
10151da177e4SLinus Torvalds {
10161da177e4SLinus Torvalds 	struct pci_dev *dev;
1017c8adf9a3SRam Pai 	resource_size_t min_align, align, size, size0, size1;
1018096d4221SYinghai Lu 	resource_size_t aligns[18];	/* Alignments from 1Mb to 128Gb */
10191da177e4SLinus Torvalds 	int order, max_order;
10205b285415SYinghai Lu 	struct resource *b_res = find_free_bus_resource(bus,
10215b285415SYinghai Lu 					mask | IORESOURCE_PREFETCH, type);
1022be768912SYinghai Lu 	resource_size_t children_add_size = 0;
1023d74b9027SWei Yang 	resource_size_t children_add_align = 0;
1024d74b9027SWei Yang 	resource_size_t add_align = 0;
10251da177e4SLinus Torvalds 
10261da177e4SLinus Torvalds 	if (!b_res)
102730afe8d0SBjorn Helgaas 		return -ENOSPC;
10281da177e4SLinus Torvalds 
10291da177e4SLinus Torvalds 	memset(aligns, 0, sizeof(aligns));
10301da177e4SLinus Torvalds 	max_order = 0;
10311da177e4SLinus Torvalds 	size = 0;
10321da177e4SLinus Torvalds 
10331da177e4SLinus Torvalds 	list_for_each_entry(dev, &bus->devices, bus_list) {
10341da177e4SLinus Torvalds 		int i;
10351da177e4SLinus Torvalds 
10361da177e4SLinus Torvalds 		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
10371da177e4SLinus Torvalds 			struct resource *r = &dev->resource[i];
1038c40a22e0SBenjamin Herrenschmidt 			resource_size_t r_size;
10391da177e4SLinus Torvalds 
10405b285415SYinghai Lu 			if (r->parent || ((r->flags & mask) != type &&
10415b285415SYinghai Lu 					  (r->flags & mask) != type2 &&
10425b285415SYinghai Lu 					  (r->flags & mask) != type3))
10431da177e4SLinus Torvalds 				continue;
1044022edd86SZhao, Yu 			r_size = resource_size(r);
10452aceefcbSYinghai Lu #ifdef CONFIG_PCI_IOV
10462aceefcbSYinghai Lu 			/* put SRIOV requested res to the optional list */
10479e8bf93aSRam Pai 			if (realloc_head && i >= PCI_IOV_RESOURCES &&
10482aceefcbSYinghai Lu 					i <= PCI_IOV_RESOURCE_END) {
1049d74b9027SWei Yang 				add_align = max(pci_resource_alignment(dev, r), add_align);
10502aceefcbSYinghai Lu 				r->end = r->start - 1;
1051f7625980SBjorn Helgaas 				add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
10522aceefcbSYinghai Lu 				children_add_size += r_size;
10532aceefcbSYinghai Lu 				continue;
10542aceefcbSYinghai Lu 			}
10552aceefcbSYinghai Lu #endif
105614c8530dSAlan 			/*
105714c8530dSAlan 			 * aligns[0] is for 1MB (since bridge memory
105814c8530dSAlan 			 * windows are always at least 1MB aligned), so
105914c8530dSAlan 			 * keep "order" from being negative for smaller
106014c8530dSAlan 			 * resources.
106114c8530dSAlan 			 */
10626faf17f6SChris Wright 			align = pci_resource_alignment(dev, r);
10631da177e4SLinus Torvalds 			order = __ffs(align) - 20;
106414c8530dSAlan 			if (order < 0)
106514c8530dSAlan 				order = 0;
106614c8530dSAlan 			if (order >= ARRAY_SIZE(aligns)) {
1067227f0647SRyan Desfosses 				dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1068227f0647SRyan Desfosses 					 i, r, (unsigned long long) align);
10691da177e4SLinus Torvalds 				r->flags = 0;
10701da177e4SLinus Torvalds 				continue;
10711da177e4SLinus Torvalds 			}
10721da177e4SLinus Torvalds 			size += r_size;
10731da177e4SLinus Torvalds 			/* Exclude ranges with size > align from
10741da177e4SLinus Torvalds 			   calculation of the alignment. */
10751da177e4SLinus Torvalds 			if (r_size == align)
10761da177e4SLinus Torvalds 				aligns[order] += align;
10771da177e4SLinus Torvalds 			if (order > max_order)
10781da177e4SLinus Torvalds 				max_order = order;
1079be768912SYinghai Lu 
1080d74b9027SWei Yang 			if (realloc_head) {
10819e8bf93aSRam Pai 				children_add_size += get_res_add_size(realloc_head, r);
1082d74b9027SWei Yang 				children_add_align = get_res_add_align(realloc_head, r);
1083d74b9027SWei Yang 				add_align = max(add_align, children_add_align);
1084d74b9027SWei Yang 			}
10851da177e4SLinus Torvalds 		}
10861da177e4SLinus Torvalds 	}
10878308c54dSJeremy Fitzhardinge 
1088c121504eSGavin Shan 	min_align = calculate_mem_align(aligns, max_order);
10893ad94b0dSWei Yang 	min_align = max(min_align, window_alignment(bus, b_res->flags));
1090b42282e5SLinus Torvalds 	size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1091d74b9027SWei Yang 	add_align = max(min_align, add_align);
1092be768912SYinghai Lu 	if (children_add_size > add_size)
1093be768912SYinghai Lu 		add_size = children_add_size;
10949e8bf93aSRam Pai 	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1095a4ac9feaSYinghai Lu 		calculate_memsize(size, min_size, add_size,
1096d74b9027SWei Yang 				resource_size(b_res), add_align);
1097c8adf9a3SRam Pai 	if (!size0 && !size1) {
1098865df576SBjorn Helgaas 		if (b_res->start || b_res->end)
1099227f0647SRyan Desfosses 			dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
1100227f0647SRyan Desfosses 				 b_res, &bus->busn_res);
11011da177e4SLinus Torvalds 		b_res->flags = 0;
110230afe8d0SBjorn Helgaas 		return 0;
11031da177e4SLinus Torvalds 	}
11041da177e4SLinus Torvalds 	b_res->start = min_align;
1105c8adf9a3SRam Pai 	b_res->end = size0 + min_align - 1;
11065b285415SYinghai Lu 	b_res->flags |= IORESOURCE_STARTALIGN;
1107b592443dSYinghai Lu 	if (size1 > size0 && realloc_head) {
1108d74b9027SWei Yang 		add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1109d74b9027SWei Yang 		dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1110227f0647SRyan Desfosses 			   b_res, &bus->busn_res,
1111d74b9027SWei Yang 			   (unsigned long long) (size1 - size0),
1112d74b9027SWei Yang 			   (unsigned long long) add_align);
1113b592443dSYinghai Lu 	}
111430afe8d0SBjorn Helgaas 	return 0;
11151da177e4SLinus Torvalds }
11161da177e4SLinus Torvalds 
11170a2daa1cSRam Pai unsigned long pci_cardbus_resource_alignment(struct resource *res)
11180a2daa1cSRam Pai {
11190a2daa1cSRam Pai 	if (res->flags & IORESOURCE_IO)
11200a2daa1cSRam Pai 		return pci_cardbus_io_size;
11210a2daa1cSRam Pai 	if (res->flags & IORESOURCE_MEM)
11220a2daa1cSRam Pai 		return pci_cardbus_mem_size;
11230a2daa1cSRam Pai 	return 0;
11240a2daa1cSRam Pai }
11250a2daa1cSRam Pai 
11260a2daa1cSRam Pai static void pci_bus_size_cardbus(struct pci_bus *bus,
1127bdc4abecSYinghai Lu 			struct list_head *realloc_head)
11281da177e4SLinus Torvalds {
11291da177e4SLinus Torvalds 	struct pci_dev *bridge = bus->self;
11301da177e4SLinus Torvalds 	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
113111848934SYinghai Lu 	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
11321da177e4SLinus Torvalds 	u16 ctrl;
11331da177e4SLinus Torvalds 
11343796f1e2SYinghai Lu 	if (b_res[0].parent)
11353796f1e2SYinghai Lu 		goto handle_b_res_1;
11361da177e4SLinus Torvalds 	/*
11371da177e4SLinus Torvalds 	 * Reserve some resources for CardBus.  We reserve
11381da177e4SLinus Torvalds 	 * a fixed amount of bus space for CardBus bridges.
11391da177e4SLinus Torvalds 	 */
114011848934SYinghai Lu 	b_res[0].start = pci_cardbus_io_size;
114111848934SYinghai Lu 	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
114211848934SYinghai Lu 	b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
114311848934SYinghai Lu 	if (realloc_head) {
114411848934SYinghai Lu 		b_res[0].end -= pci_cardbus_io_size;
114511848934SYinghai Lu 		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
114611848934SYinghai Lu 				pci_cardbus_io_size);
114711848934SYinghai Lu 	}
11481da177e4SLinus Torvalds 
11493796f1e2SYinghai Lu handle_b_res_1:
11503796f1e2SYinghai Lu 	if (b_res[1].parent)
11513796f1e2SYinghai Lu 		goto handle_b_res_2;
115211848934SYinghai Lu 	b_res[1].start = pci_cardbus_io_size;
115311848934SYinghai Lu 	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
115411848934SYinghai Lu 	b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
115511848934SYinghai Lu 	if (realloc_head) {
115611848934SYinghai Lu 		b_res[1].end -= pci_cardbus_io_size;
115711848934SYinghai Lu 		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
115811848934SYinghai Lu 				 pci_cardbus_io_size);
115911848934SYinghai Lu 	}
11601da177e4SLinus Torvalds 
11613796f1e2SYinghai Lu handle_b_res_2:
1162dcef0d06SYinghai Lu 	/* MEM1 must not be pref mmio */
1163dcef0d06SYinghai Lu 	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1164dcef0d06SYinghai Lu 	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1165dcef0d06SYinghai Lu 		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1166dcef0d06SYinghai Lu 		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1167dcef0d06SYinghai Lu 		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1168dcef0d06SYinghai Lu 	}
1169dcef0d06SYinghai Lu 
11701da177e4SLinus Torvalds 	/*
11711da177e4SLinus Torvalds 	 * Check whether prefetchable memory is supported
11721da177e4SLinus Torvalds 	 * by this bridge.
11731da177e4SLinus Torvalds 	 */
11741da177e4SLinus Torvalds 	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
11751da177e4SLinus Torvalds 	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
11761da177e4SLinus Torvalds 		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
11771da177e4SLinus Torvalds 		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
11781da177e4SLinus Torvalds 		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
11791da177e4SLinus Torvalds 	}
11801da177e4SLinus Torvalds 
11813796f1e2SYinghai Lu 	if (b_res[2].parent)
11823796f1e2SYinghai Lu 		goto handle_b_res_3;
11831da177e4SLinus Torvalds 	/*
11841da177e4SLinus Torvalds 	 * If we have prefetchable memory support, allocate
11851da177e4SLinus Torvalds 	 * two regions.  Otherwise, allocate one region of
11861da177e4SLinus Torvalds 	 * twice the size.
11871da177e4SLinus Torvalds 	 */
11881da177e4SLinus Torvalds 	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
118911848934SYinghai Lu 		b_res[2].start = pci_cardbus_mem_size;
119011848934SYinghai Lu 		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
119111848934SYinghai Lu 		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
119211848934SYinghai Lu 				  IORESOURCE_STARTALIGN;
119311848934SYinghai Lu 		if (realloc_head) {
119411848934SYinghai Lu 			b_res[2].end -= pci_cardbus_mem_size;
119511848934SYinghai Lu 			add_to_list(realloc_head, bridge, b_res+2,
119611848934SYinghai Lu 				 pci_cardbus_mem_size, pci_cardbus_mem_size);
11971da177e4SLinus Torvalds 		}
11980a2daa1cSRam Pai 
119911848934SYinghai Lu 		/* reduce that to half */
120011848934SYinghai Lu 		b_res_3_size = pci_cardbus_mem_size;
120111848934SYinghai Lu 	}
120211848934SYinghai Lu 
12033796f1e2SYinghai Lu handle_b_res_3:
12043796f1e2SYinghai Lu 	if (b_res[3].parent)
12053796f1e2SYinghai Lu 		goto handle_done;
120611848934SYinghai Lu 	b_res[3].start = pci_cardbus_mem_size;
120711848934SYinghai Lu 	b_res[3].end = b_res[3].start + b_res_3_size - 1;
120811848934SYinghai Lu 	b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
120911848934SYinghai Lu 	if (realloc_head) {
121011848934SYinghai Lu 		b_res[3].end -= b_res_3_size;
121111848934SYinghai Lu 		add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
121211848934SYinghai Lu 				 pci_cardbus_mem_size);
121311848934SYinghai Lu 	}
12143796f1e2SYinghai Lu 
12153796f1e2SYinghai Lu handle_done:
12163796f1e2SYinghai Lu 	;
12171da177e4SLinus Torvalds }
12181da177e4SLinus Torvalds 
121910874f5aSBjorn Helgaas void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
12201da177e4SLinus Torvalds {
12211da177e4SLinus Torvalds 	struct pci_dev *dev;
12225b285415SYinghai Lu 	unsigned long mask, prefmask, type2 = 0, type3 = 0;
1223c8adf9a3SRam Pai 	resource_size_t additional_mem_size = 0, additional_io_size = 0;
12245b285415SYinghai Lu 	struct resource *b_res;
122530afe8d0SBjorn Helgaas 	int ret;
12261da177e4SLinus Torvalds 
12271da177e4SLinus Torvalds 	list_for_each_entry(dev, &bus->devices, bus_list) {
12281da177e4SLinus Torvalds 		struct pci_bus *b = dev->subordinate;
12291da177e4SLinus Torvalds 		if (!b)
12301da177e4SLinus Torvalds 			continue;
12311da177e4SLinus Torvalds 
12321da177e4SLinus Torvalds 		switch (dev->class >> 8) {
12331da177e4SLinus Torvalds 		case PCI_CLASS_BRIDGE_CARDBUS:
12349e8bf93aSRam Pai 			pci_bus_size_cardbus(b, realloc_head);
12351da177e4SLinus Torvalds 			break;
12361da177e4SLinus Torvalds 
12371da177e4SLinus Torvalds 		case PCI_CLASS_BRIDGE_PCI:
12381da177e4SLinus Torvalds 		default:
12399e8bf93aSRam Pai 			__pci_bus_size_bridges(b, realloc_head);
12401da177e4SLinus Torvalds 			break;
12411da177e4SLinus Torvalds 		}
12421da177e4SLinus Torvalds 	}
12431da177e4SLinus Torvalds 
12441da177e4SLinus Torvalds 	/* The root bus? */
12452ba29e27SWei Yang 	if (pci_is_root_bus(bus))
12461da177e4SLinus Torvalds 		return;
12471da177e4SLinus Torvalds 
12481da177e4SLinus Torvalds 	switch (bus->self->class >> 8) {
12491da177e4SLinus Torvalds 	case PCI_CLASS_BRIDGE_CARDBUS:
12501da177e4SLinus Torvalds 		/* don't size cardbuses yet. */
12511da177e4SLinus Torvalds 		break;
12521da177e4SLinus Torvalds 
12531da177e4SLinus Torvalds 	case PCI_CLASS_BRIDGE_PCI:
12541da177e4SLinus Torvalds 		pci_bridge_check_ranges(bus);
125528760489SEric W. Biederman 		if (bus->self->is_hotplug_bridge) {
1256c8adf9a3SRam Pai 			additional_io_size  = pci_hotplug_io_size;
1257c8adf9a3SRam Pai 			additional_mem_size = pci_hotplug_mem_size;
125828760489SEric W. Biederman 		}
125967d29b5cSBjorn Helgaas 		/* Fall through */
12601da177e4SLinus Torvalds 	default:
126119aa7ee4SYinghai Lu 		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
126219aa7ee4SYinghai Lu 			     additional_io_size, realloc_head);
126367d29b5cSBjorn Helgaas 
126467d29b5cSBjorn Helgaas 		/*
126567d29b5cSBjorn Helgaas 		 * If there's a 64-bit prefetchable MMIO window, compute
126667d29b5cSBjorn Helgaas 		 * the size required to put all 64-bit prefetchable
126767d29b5cSBjorn Helgaas 		 * resources in it.
126867d29b5cSBjorn Helgaas 		 */
12695b285415SYinghai Lu 		b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
12701da177e4SLinus Torvalds 		mask = IORESOURCE_MEM;
12711da177e4SLinus Torvalds 		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
12725b285415SYinghai Lu 		if (b_res[2].flags & IORESOURCE_MEM_64) {
12735b285415SYinghai Lu 			prefmask |= IORESOURCE_MEM_64;
127430afe8d0SBjorn Helgaas 			ret = pbus_size_mem(bus, prefmask, prefmask,
12755b285415SYinghai Lu 				  prefmask, prefmask,
127619aa7ee4SYinghai Lu 				  realloc_head ? 0 : additional_mem_size,
127730afe8d0SBjorn Helgaas 				  additional_mem_size, realloc_head);
127867d29b5cSBjorn Helgaas 
12795b285415SYinghai Lu 			/*
128067d29b5cSBjorn Helgaas 			 * If successful, all non-prefetchable resources
128167d29b5cSBjorn Helgaas 			 * and any 32-bit prefetchable resources will go in
128267d29b5cSBjorn Helgaas 			 * the non-prefetchable window.
128367d29b5cSBjorn Helgaas 			 */
128467d29b5cSBjorn Helgaas 			if (ret == 0) {
12855b285415SYinghai Lu 				mask = prefmask;
12865b285415SYinghai Lu 				type2 = prefmask & ~IORESOURCE_MEM_64;
12875b285415SYinghai Lu 				type3 = prefmask & ~IORESOURCE_PREFETCH;
12885b285415SYinghai Lu 			}
12895b285415SYinghai Lu 		}
129067d29b5cSBjorn Helgaas 
129167d29b5cSBjorn Helgaas 		/*
129267d29b5cSBjorn Helgaas 		 * If there is no 64-bit prefetchable window, compute the
129367d29b5cSBjorn Helgaas 		 * size required to put all prefetchable resources in the
129467d29b5cSBjorn Helgaas 		 * 32-bit prefetchable window (if there is one).
129567d29b5cSBjorn Helgaas 		 */
12965b285415SYinghai Lu 		if (!type2) {
12975b285415SYinghai Lu 			prefmask &= ~IORESOURCE_MEM_64;
129830afe8d0SBjorn Helgaas 			ret = pbus_size_mem(bus, prefmask, prefmask,
12995b285415SYinghai Lu 					 prefmask, prefmask,
13005b285415SYinghai Lu 					 realloc_head ? 0 : additional_mem_size,
130130afe8d0SBjorn Helgaas 					 additional_mem_size, realloc_head);
130267d29b5cSBjorn Helgaas 
130367d29b5cSBjorn Helgaas 			/*
130467d29b5cSBjorn Helgaas 			 * If successful, only non-prefetchable resources
130567d29b5cSBjorn Helgaas 			 * will go in the non-prefetchable window.
130667d29b5cSBjorn Helgaas 			 */
130767d29b5cSBjorn Helgaas 			if (ret == 0)
13085b285415SYinghai Lu 				mask = prefmask;
130928760489SEric W. Biederman 			else
1310c8adf9a3SRam Pai 				additional_mem_size += additional_mem_size;
131167d29b5cSBjorn Helgaas 
13125b285415SYinghai Lu 			type2 = type3 = IORESOURCE_MEM;
13135b285415SYinghai Lu 		}
131467d29b5cSBjorn Helgaas 
131567d29b5cSBjorn Helgaas 		/*
131667d29b5cSBjorn Helgaas 		 * Compute the size required to put everything else in the
131767d29b5cSBjorn Helgaas 		 * non-prefetchable window.  This includes:
131867d29b5cSBjorn Helgaas 		 *
131967d29b5cSBjorn Helgaas 		 *   - all non-prefetchable resources
132067d29b5cSBjorn Helgaas 		 *   - 32-bit prefetchable resources if there's a 64-bit
132167d29b5cSBjorn Helgaas 		 *     prefetchable window or no prefetchable window at all
132267d29b5cSBjorn Helgaas 		 *   - 64-bit prefetchable resources if there's no
132367d29b5cSBjorn Helgaas 		 *     prefetchable window at all
132467d29b5cSBjorn Helgaas 		 *
132567d29b5cSBjorn Helgaas 		 * Note that the strategy in __pci_assign_resource() must
132667d29b5cSBjorn Helgaas 		 * match that used here.  Specifically, we cannot put a
132767d29b5cSBjorn Helgaas 		 * 32-bit prefetchable resource in a 64-bit prefetchable
132867d29b5cSBjorn Helgaas 		 * window.
132967d29b5cSBjorn Helgaas 		 */
13305b285415SYinghai Lu 		pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
133119aa7ee4SYinghai Lu 				realloc_head ? 0 : additional_mem_size,
133219aa7ee4SYinghai Lu 				additional_mem_size, realloc_head);
13331da177e4SLinus Torvalds 		break;
13341da177e4SLinus Torvalds 	}
13351da177e4SLinus Torvalds }
1336c8adf9a3SRam Pai 
133710874f5aSBjorn Helgaas void pci_bus_size_bridges(struct pci_bus *bus)
1338c8adf9a3SRam Pai {
1339c8adf9a3SRam Pai 	__pci_bus_size_bridges(bus, NULL);
1340c8adf9a3SRam Pai }
13411da177e4SLinus Torvalds EXPORT_SYMBOL(pci_bus_size_bridges);
13421da177e4SLinus Torvalds 
134310874f5aSBjorn Helgaas void __pci_bus_assign_resources(const struct pci_bus *bus,
1344bdc4abecSYinghai Lu 				struct list_head *realloc_head,
1345bdc4abecSYinghai Lu 				struct list_head *fail_head)
13461da177e4SLinus Torvalds {
13471da177e4SLinus Torvalds 	struct pci_bus *b;
13481da177e4SLinus Torvalds 	struct pci_dev *dev;
13491da177e4SLinus Torvalds 
13509e8bf93aSRam Pai 	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
13511da177e4SLinus Torvalds 
13521da177e4SLinus Torvalds 	list_for_each_entry(dev, &bus->devices, bus_list) {
13531da177e4SLinus Torvalds 		b = dev->subordinate;
13541da177e4SLinus Torvalds 		if (!b)
13551da177e4SLinus Torvalds 			continue;
13561da177e4SLinus Torvalds 
13579e8bf93aSRam Pai 		__pci_bus_assign_resources(b, realloc_head, fail_head);
13581da177e4SLinus Torvalds 
13591da177e4SLinus Torvalds 		switch (dev->class >> 8) {
13601da177e4SLinus Torvalds 		case PCI_CLASS_BRIDGE_PCI:
13616841ec68SYinghai Lu 			if (!pci_is_enabled(dev))
13621da177e4SLinus Torvalds 				pci_setup_bridge(b);
13631da177e4SLinus Torvalds 			break;
13641da177e4SLinus Torvalds 
13651da177e4SLinus Torvalds 		case PCI_CLASS_BRIDGE_CARDBUS:
13661da177e4SLinus Torvalds 			pci_setup_cardbus(b);
13671da177e4SLinus Torvalds 			break;
13681da177e4SLinus Torvalds 
13691da177e4SLinus Torvalds 		default:
1370227f0647SRyan Desfosses 			dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
1371227f0647SRyan Desfosses 				 pci_domain_nr(b), b->number);
13721da177e4SLinus Torvalds 			break;
13731da177e4SLinus Torvalds 		}
13741da177e4SLinus Torvalds 	}
13751da177e4SLinus Torvalds }
1376568ddef8SYinghai Lu 
137710874f5aSBjorn Helgaas void pci_bus_assign_resources(const struct pci_bus *bus)
1378568ddef8SYinghai Lu {
1379c8adf9a3SRam Pai 	__pci_bus_assign_resources(bus, NULL, NULL);
1380568ddef8SYinghai Lu }
13811da177e4SLinus Torvalds EXPORT_SYMBOL(pci_bus_assign_resources);
13821da177e4SLinus Torvalds 
138310874f5aSBjorn Helgaas static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1384bdc4abecSYinghai Lu 					  struct list_head *add_head,
1385bdc4abecSYinghai Lu 					  struct list_head *fail_head)
13866841ec68SYinghai Lu {
13876841ec68SYinghai Lu 	struct pci_bus *b;
13886841ec68SYinghai Lu 
13898424d759SYinghai Lu 	pdev_assign_resources_sorted((struct pci_dev *)bridge,
13908424d759SYinghai Lu 					 add_head, fail_head);
13916841ec68SYinghai Lu 
13926841ec68SYinghai Lu 	b = bridge->subordinate;
13936841ec68SYinghai Lu 	if (!b)
13946841ec68SYinghai Lu 		return;
13956841ec68SYinghai Lu 
13968424d759SYinghai Lu 	__pci_bus_assign_resources(b, add_head, fail_head);
13976841ec68SYinghai Lu 
13986841ec68SYinghai Lu 	switch (bridge->class >> 8) {
13996841ec68SYinghai Lu 	case PCI_CLASS_BRIDGE_PCI:
14006841ec68SYinghai Lu 		pci_setup_bridge(b);
14016841ec68SYinghai Lu 		break;
14026841ec68SYinghai Lu 
14036841ec68SYinghai Lu 	case PCI_CLASS_BRIDGE_CARDBUS:
14046841ec68SYinghai Lu 		pci_setup_cardbus(b);
14056841ec68SYinghai Lu 		break;
14066841ec68SYinghai Lu 
14076841ec68SYinghai Lu 	default:
1408227f0647SRyan Desfosses 		dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
1409227f0647SRyan Desfosses 			 pci_domain_nr(b), b->number);
14106841ec68SYinghai Lu 		break;
14116841ec68SYinghai Lu 	}
14126841ec68SYinghai Lu }
14135009b460SYinghai Lu static void pci_bridge_release_resources(struct pci_bus *bus,
14145009b460SYinghai Lu 					  unsigned long type)
14155009b460SYinghai Lu {
14165b285415SYinghai Lu 	struct pci_dev *dev = bus->self;
14175009b460SYinghai Lu 	struct resource *r;
14185009b460SYinghai Lu 	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
14195b285415SYinghai Lu 				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
14205b285415SYinghai Lu 	unsigned old_flags = 0;
14215b285415SYinghai Lu 	struct resource *b_res;
14225b285415SYinghai Lu 	int idx = 1;
14235009b460SYinghai Lu 
14245b285415SYinghai Lu 	b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
14255b285415SYinghai Lu 
14265b285415SYinghai Lu 	/*
14275b285415SYinghai Lu 	 *     1. if there is io port assign fail, will release bridge
14285b285415SYinghai Lu 	 *	  io port.
14295b285415SYinghai Lu 	 *     2. if there is non pref mmio assign fail, release bridge
14305b285415SYinghai Lu 	 *	  nonpref mmio.
14315b285415SYinghai Lu 	 *     3. if there is 64bit pref mmio assign fail, and bridge pref
14325b285415SYinghai Lu 	 *	  is 64bit, release bridge pref mmio.
14335b285415SYinghai Lu 	 *     4. if there is pref mmio assign fail, and bridge pref is
14345b285415SYinghai Lu 	 *	  32bit mmio, release bridge pref mmio
14355b285415SYinghai Lu 	 *     5. if there is pref mmio assign fail, and bridge pref is not
14365b285415SYinghai Lu 	 *	  assigned, release bridge nonpref mmio.
14375b285415SYinghai Lu 	 */
14385b285415SYinghai Lu 	if (type & IORESOURCE_IO)
14395b285415SYinghai Lu 		idx = 0;
14405b285415SYinghai Lu 	else if (!(type & IORESOURCE_PREFETCH))
14415b285415SYinghai Lu 		idx = 1;
14425b285415SYinghai Lu 	else if ((type & IORESOURCE_MEM_64) &&
14435b285415SYinghai Lu 		 (b_res[2].flags & IORESOURCE_MEM_64))
14445b285415SYinghai Lu 		idx = 2;
14455b285415SYinghai Lu 	else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
14465b285415SYinghai Lu 		 (b_res[2].flags & IORESOURCE_PREFETCH))
14475b285415SYinghai Lu 		idx = 2;
14485b285415SYinghai Lu 	else
14495b285415SYinghai Lu 		idx = 1;
14505b285415SYinghai Lu 
14515b285415SYinghai Lu 	r = &b_res[idx];
14525b285415SYinghai Lu 
14535009b460SYinghai Lu 	if (!r->parent)
14545b285415SYinghai Lu 		return;
14555b285415SYinghai Lu 
14565009b460SYinghai Lu 	/*
14575009b460SYinghai Lu 	 * if there are children under that, we should release them
14585009b460SYinghai Lu 	 *  all
14595009b460SYinghai Lu 	 */
14605009b460SYinghai Lu 	release_child_resources(r);
14615009b460SYinghai Lu 	if (!release_resource(r)) {
14625b285415SYinghai Lu 		type = old_flags = r->flags & type_mask;
14635b285415SYinghai Lu 		dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
14645b285415SYinghai Lu 					PCI_BRIDGE_RESOURCES + idx, r);
14655009b460SYinghai Lu 		/* keep the old size */
14665009b460SYinghai Lu 		r->end = resource_size(r) - 1;
14675009b460SYinghai Lu 		r->start = 0;
14685009b460SYinghai Lu 		r->flags = 0;
14695009b460SYinghai Lu 
14705009b460SYinghai Lu 		/* avoiding touch the one without PREF */
14715009b460SYinghai Lu 		if (type & IORESOURCE_PREFETCH)
14725009b460SYinghai Lu 			type = IORESOURCE_PREFETCH;
14735009b460SYinghai Lu 		__pci_setup_bridge(bus, type);
14745b285415SYinghai Lu 		/* for next child res under same bridge */
14755b285415SYinghai Lu 		r->flags = old_flags;
14765009b460SYinghai Lu 	}
14775009b460SYinghai Lu }
14785009b460SYinghai Lu 
14795009b460SYinghai Lu enum release_type {
14805009b460SYinghai Lu 	leaf_only,
14815009b460SYinghai Lu 	whole_subtree,
14825009b460SYinghai Lu };
14835009b460SYinghai Lu /*
14845009b460SYinghai Lu  * try to release pci bridge resources that is from leaf bridge,
14855009b460SYinghai Lu  * so we can allocate big new one later
14865009b460SYinghai Lu  */
148710874f5aSBjorn Helgaas static void pci_bus_release_bridge_resources(struct pci_bus *bus,
14885009b460SYinghai Lu 					     unsigned long type,
14895009b460SYinghai Lu 					     enum release_type rel_type)
14905009b460SYinghai Lu {
14915009b460SYinghai Lu 	struct pci_dev *dev;
14925009b460SYinghai Lu 	bool is_leaf_bridge = true;
14935009b460SYinghai Lu 
14945009b460SYinghai Lu 	list_for_each_entry(dev, &bus->devices, bus_list) {
14955009b460SYinghai Lu 		struct pci_bus *b = dev->subordinate;
14965009b460SYinghai Lu 		if (!b)
14975009b460SYinghai Lu 			continue;
14985009b460SYinghai Lu 
14995009b460SYinghai Lu 		is_leaf_bridge = false;
15005009b460SYinghai Lu 
15015009b460SYinghai Lu 		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
15025009b460SYinghai Lu 			continue;
15035009b460SYinghai Lu 
15045009b460SYinghai Lu 		if (rel_type == whole_subtree)
15055009b460SYinghai Lu 			pci_bus_release_bridge_resources(b, type,
15065009b460SYinghai Lu 						 whole_subtree);
15075009b460SYinghai Lu 	}
15085009b460SYinghai Lu 
15095009b460SYinghai Lu 	if (pci_is_root_bus(bus))
15105009b460SYinghai Lu 		return;
15115009b460SYinghai Lu 
15125009b460SYinghai Lu 	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
15135009b460SYinghai Lu 		return;
15145009b460SYinghai Lu 
15155009b460SYinghai Lu 	if ((rel_type == whole_subtree) || is_leaf_bridge)
15165009b460SYinghai Lu 		pci_bridge_release_resources(bus, type);
15175009b460SYinghai Lu }
15185009b460SYinghai Lu 
151976fbc263SYinghai Lu static void pci_bus_dump_res(struct pci_bus *bus)
152076fbc263SYinghai Lu {
152189a74eccSBjorn Helgaas 	struct resource *res;
152276fbc263SYinghai Lu 	int i;
152376fbc263SYinghai Lu 
152489a74eccSBjorn Helgaas 	pci_bus_for_each_resource(bus, res, i) {
15257c9342b8SYinghai Lu 		if (!res || !res->end || !res->flags)
152676fbc263SYinghai Lu 			continue;
152776fbc263SYinghai Lu 
1528c7dabef8SBjorn Helgaas 		dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
152976fbc263SYinghai Lu 	}
153076fbc263SYinghai Lu }
153176fbc263SYinghai Lu 
153276fbc263SYinghai Lu static void pci_bus_dump_resources(struct pci_bus *bus)
153376fbc263SYinghai Lu {
153476fbc263SYinghai Lu 	struct pci_bus *b;
153576fbc263SYinghai Lu 	struct pci_dev *dev;
153676fbc263SYinghai Lu 
153776fbc263SYinghai Lu 
153876fbc263SYinghai Lu 	pci_bus_dump_res(bus);
153976fbc263SYinghai Lu 
154076fbc263SYinghai Lu 	list_for_each_entry(dev, &bus->devices, bus_list) {
154176fbc263SYinghai Lu 		b = dev->subordinate;
154276fbc263SYinghai Lu 		if (!b)
154376fbc263SYinghai Lu 			continue;
154476fbc263SYinghai Lu 
154576fbc263SYinghai Lu 		pci_bus_dump_resources(b);
154676fbc263SYinghai Lu 	}
154776fbc263SYinghai Lu }
154876fbc263SYinghai Lu 
1549ff35147cSYinghai Lu static int pci_bus_get_depth(struct pci_bus *bus)
1550da7822e5SYinghai Lu {
1551da7822e5SYinghai Lu 	int depth = 0;
1552f2a230bdSWei Yang 	struct pci_bus *child_bus;
1553da7822e5SYinghai Lu 
1554f2a230bdSWei Yang 	list_for_each_entry(child_bus, &bus->children, node) {
1555da7822e5SYinghai Lu 		int ret;
1556da7822e5SYinghai Lu 
1557f2a230bdSWei Yang 		ret = pci_bus_get_depth(child_bus);
1558da7822e5SYinghai Lu 		if (ret + 1 > depth)
1559da7822e5SYinghai Lu 			depth = ret + 1;
1560da7822e5SYinghai Lu 	}
1561da7822e5SYinghai Lu 
1562da7822e5SYinghai Lu 	return depth;
1563da7822e5SYinghai Lu }
1564da7822e5SYinghai Lu 
1565b55438fdSYinghai Lu /*
1566b55438fdSYinghai Lu  * -1: undefined, will auto detect later
1567b55438fdSYinghai Lu  *  0: disabled by user
1568b55438fdSYinghai Lu  *  1: disabled by auto detect
1569b55438fdSYinghai Lu  *  2: enabled by user
1570b55438fdSYinghai Lu  *  3: enabled by auto detect
1571b55438fdSYinghai Lu  */
1572b55438fdSYinghai Lu enum enable_type {
1573b55438fdSYinghai Lu 	undefined = -1,
1574b55438fdSYinghai Lu 	user_disabled,
1575b55438fdSYinghai Lu 	auto_disabled,
1576b55438fdSYinghai Lu 	user_enabled,
1577b55438fdSYinghai Lu 	auto_enabled,
1578b55438fdSYinghai Lu };
1579b55438fdSYinghai Lu 
1580ff35147cSYinghai Lu static enum enable_type pci_realloc_enable = undefined;
1581b55438fdSYinghai Lu void __init pci_realloc_get_opt(char *str)
1582b55438fdSYinghai Lu {
1583b55438fdSYinghai Lu 	if (!strncmp(str, "off", 3))
1584b55438fdSYinghai Lu 		pci_realloc_enable = user_disabled;
1585b55438fdSYinghai Lu 	else if (!strncmp(str, "on", 2))
1586b55438fdSYinghai Lu 		pci_realloc_enable = user_enabled;
1587b55438fdSYinghai Lu }
1588ff35147cSYinghai Lu static bool pci_realloc_enabled(enum enable_type enable)
1589b55438fdSYinghai Lu {
1590967260cdSYinghai Lu 	return enable >= user_enabled;
1591b55438fdSYinghai Lu }
1592f483d392SRam Pai 
1593b07f2ebcSYinghai Lu #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1594ff35147cSYinghai Lu static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1595223d96fcSYinghai Lu {
1596b07f2ebcSYinghai Lu 	int i;
1597223d96fcSYinghai Lu 	bool *unassigned = data;
1598b07f2ebcSYinghai Lu 
1599b07f2ebcSYinghai Lu 	for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1600b07f2ebcSYinghai Lu 		struct resource *r = &dev->resource[i];
1601fa216bf4SYinghai Lu 		struct pci_bus_region region;
1602b07f2ebcSYinghai Lu 
1603223d96fcSYinghai Lu 		/* Not assigned or rejected by kernel? */
1604fa216bf4SYinghai Lu 		if (!r->flags)
1605fa216bf4SYinghai Lu 			continue;
1606b07f2ebcSYinghai Lu 
1607fc279850SYinghai Lu 		pcibios_resource_to_bus(dev->bus, &region, r);
1608fa216bf4SYinghai Lu 		if (!region.start) {
1609223d96fcSYinghai Lu 			*unassigned = true;
1610223d96fcSYinghai Lu 			return 1; /* return early from pci_walk_bus() */
1611b07f2ebcSYinghai Lu 		}
1612b07f2ebcSYinghai Lu 	}
1613b07f2ebcSYinghai Lu 
1614223d96fcSYinghai Lu 	return 0;
1615223d96fcSYinghai Lu }
1616223d96fcSYinghai Lu 
1617ff35147cSYinghai Lu static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1618967260cdSYinghai Lu 			 enum enable_type enable_local)
1619223d96fcSYinghai Lu {
1620223d96fcSYinghai Lu 	bool unassigned = false;
1621223d96fcSYinghai Lu 
1622967260cdSYinghai Lu 	if (enable_local != undefined)
1623967260cdSYinghai Lu 		return enable_local;
1624223d96fcSYinghai Lu 
1625223d96fcSYinghai Lu 	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1626967260cdSYinghai Lu 	if (unassigned)
1627967260cdSYinghai Lu 		return auto_enabled;
1628967260cdSYinghai Lu 
1629967260cdSYinghai Lu 	return enable_local;
1630b07f2ebcSYinghai Lu }
1631223d96fcSYinghai Lu #else
1632ff35147cSYinghai Lu static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1633967260cdSYinghai Lu 			 enum enable_type enable_local)
1634967260cdSYinghai Lu {
1635967260cdSYinghai Lu 	return enable_local;
1636b07f2ebcSYinghai Lu }
1637b07f2ebcSYinghai Lu #endif
1638b07f2ebcSYinghai Lu 
1639da7822e5SYinghai Lu /*
1640da7822e5SYinghai Lu  * first try will not touch pci bridge res
1641da7822e5SYinghai Lu  * second and later try will clear small leaf bridge res
1642f7625980SBjorn Helgaas  * will stop till to the max depth if can not find good one
1643da7822e5SYinghai Lu  */
164439772038SYinghai Lu void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
16451da177e4SLinus Torvalds {
1646bdc4abecSYinghai Lu 	LIST_HEAD(realloc_head); /* list of resources that
1647c8adf9a3SRam Pai 					want additional resources */
1648bdc4abecSYinghai Lu 	struct list_head *add_list = NULL;
1649da7822e5SYinghai Lu 	int tried_times = 0;
1650da7822e5SYinghai Lu 	enum release_type rel_type = leaf_only;
1651bdc4abecSYinghai Lu 	LIST_HEAD(fail_head);
1652b9b0bba9SYinghai Lu 	struct pci_dev_resource *fail_res;
1653da7822e5SYinghai Lu 	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
16545b285415SYinghai Lu 				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
165519aa7ee4SYinghai Lu 	int pci_try_num = 1;
165655ed83a6SYinghai Lu 	enum enable_type enable_local;
1657da7822e5SYinghai Lu 
165819aa7ee4SYinghai Lu 	/* don't realloc if asked to do so */
165955ed83a6SYinghai Lu 	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1660967260cdSYinghai Lu 	if (pci_realloc_enabled(enable_local)) {
166155ed83a6SYinghai Lu 		int max_depth = pci_bus_get_depth(bus);
166219aa7ee4SYinghai Lu 
1663da7822e5SYinghai Lu 		pci_try_num = max_depth + 1;
166455ed83a6SYinghai Lu 		dev_printk(KERN_DEBUG, &bus->dev,
166555ed83a6SYinghai Lu 			   "max bus depth: %d pci_try_num: %d\n",
1666da7822e5SYinghai Lu 			   max_depth, pci_try_num);
166719aa7ee4SYinghai Lu 	}
1668da7822e5SYinghai Lu 
1669da7822e5SYinghai Lu again:
167019aa7ee4SYinghai Lu 	/*
167119aa7ee4SYinghai Lu 	 * last try will use add_list, otherwise will try good to have as
167219aa7ee4SYinghai Lu 	 * must have, so can realloc parent bridge resource
167319aa7ee4SYinghai Lu 	 */
167419aa7ee4SYinghai Lu 	if (tried_times + 1 == pci_try_num)
1675bdc4abecSYinghai Lu 		add_list = &realloc_head;
16761da177e4SLinus Torvalds 	/* Depth first, calculate sizes and alignments of all
16771da177e4SLinus Torvalds 	   subordinate buses. */
167819aa7ee4SYinghai Lu 	__pci_bus_size_bridges(bus, add_list);
1679c8adf9a3SRam Pai 
16801da177e4SLinus Torvalds 	/* Depth last, allocate resources and update the hardware. */
1681bdc4abecSYinghai Lu 	__pci_bus_assign_resources(bus, add_list, &fail_head);
168219aa7ee4SYinghai Lu 	if (add_list)
1683bdc4abecSYinghai Lu 		BUG_ON(!list_empty(add_list));
1684da7822e5SYinghai Lu 	tried_times++;
1685da7822e5SYinghai Lu 
1686da7822e5SYinghai Lu 	/* any device complain? */
1687bdc4abecSYinghai Lu 	if (list_empty(&fail_head))
1688928bea96SYinghai Lu 		goto dump;
1689f483d392SRam Pai 
16900c5be0cbSYinghai Lu 	if (tried_times >= pci_try_num) {
1691967260cdSYinghai Lu 		if (enable_local == undefined)
169255ed83a6SYinghai Lu 			dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1693967260cdSYinghai Lu 		else if (enable_local == auto_enabled)
169455ed83a6SYinghai Lu 			dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1695eb572e7cSYinghai Lu 
1696bffc56d4SYinghai Lu 		free_list(&fail_head);
1697928bea96SYinghai Lu 		goto dump;
1698da7822e5SYinghai Lu 	}
1699da7822e5SYinghai Lu 
170055ed83a6SYinghai Lu 	dev_printk(KERN_DEBUG, &bus->dev,
170155ed83a6SYinghai Lu 		   "No. %d try to assign unassigned res\n", tried_times + 1);
1702da7822e5SYinghai Lu 
1703da7822e5SYinghai Lu 	/* third times and later will not check if it is leaf */
1704da7822e5SYinghai Lu 	if ((tried_times + 1) > 2)
1705da7822e5SYinghai Lu 		rel_type = whole_subtree;
1706da7822e5SYinghai Lu 
1707da7822e5SYinghai Lu 	/*
1708da7822e5SYinghai Lu 	 * Try to release leaf bridge's resources that doesn't fit resource of
1709da7822e5SYinghai Lu 	 * child device under that bridge
1710da7822e5SYinghai Lu 	 */
171161e83cddSYinghai Lu 	list_for_each_entry(fail_res, &fail_head, list)
171261e83cddSYinghai Lu 		pci_bus_release_bridge_resources(fail_res->dev->bus,
1713b9b0bba9SYinghai Lu 						 fail_res->flags & type_mask,
1714da7822e5SYinghai Lu 						 rel_type);
171561e83cddSYinghai Lu 
1716da7822e5SYinghai Lu 	/* restore size and flags */
1717b9b0bba9SYinghai Lu 	list_for_each_entry(fail_res, &fail_head, list) {
1718b9b0bba9SYinghai Lu 		struct resource *res = fail_res->res;
1719da7822e5SYinghai Lu 
1720b9b0bba9SYinghai Lu 		res->start = fail_res->start;
1721b9b0bba9SYinghai Lu 		res->end = fail_res->end;
1722b9b0bba9SYinghai Lu 		res->flags = fail_res->flags;
1723b9b0bba9SYinghai Lu 		if (fail_res->dev->subordinate)
1724da7822e5SYinghai Lu 			res->flags = 0;
1725da7822e5SYinghai Lu 	}
1726bffc56d4SYinghai Lu 	free_list(&fail_head);
1727da7822e5SYinghai Lu 
1728da7822e5SYinghai Lu 	goto again;
1729da7822e5SYinghai Lu 
1730928bea96SYinghai Lu dump:
173176fbc263SYinghai Lu 	/* dump the resource on buses */
173276fbc263SYinghai Lu 	pci_bus_dump_resources(bus);
173376fbc263SYinghai Lu }
17346841ec68SYinghai Lu 
173555ed83a6SYinghai Lu void __init pci_assign_unassigned_resources(void)
173655ed83a6SYinghai Lu {
173755ed83a6SYinghai Lu 	struct pci_bus *root_bus;
173855ed83a6SYinghai Lu 
173955ed83a6SYinghai Lu 	list_for_each_entry(root_bus, &pci_root_buses, node)
174055ed83a6SYinghai Lu 		pci_assign_unassigned_root_bus_resources(root_bus);
174155ed83a6SYinghai Lu }
174255ed83a6SYinghai Lu 
17436841ec68SYinghai Lu void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
17446841ec68SYinghai Lu {
17456841ec68SYinghai Lu 	struct pci_bus *parent = bridge->subordinate;
1746bdc4abecSYinghai Lu 	LIST_HEAD(add_list); /* list of resources that
17478424d759SYinghai Lu 					want additional resources */
174832180e40SYinghai Lu 	int tried_times = 0;
1749bdc4abecSYinghai Lu 	LIST_HEAD(fail_head);
1750b9b0bba9SYinghai Lu 	struct pci_dev_resource *fail_res;
17516841ec68SYinghai Lu 	int retval;
175232180e40SYinghai Lu 	unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1753d61b0e87SYinghai Lu 				  IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
17546841ec68SYinghai Lu 
175532180e40SYinghai Lu again:
17568424d759SYinghai Lu 	__pci_bus_size_bridges(parent, &add_list);
1757bdc4abecSYinghai Lu 	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1758bdc4abecSYinghai Lu 	BUG_ON(!list_empty(&add_list));
175932180e40SYinghai Lu 	tried_times++;
176032180e40SYinghai Lu 
1761bdc4abecSYinghai Lu 	if (list_empty(&fail_head))
17623f579c34SYinghai Lu 		goto enable_all;
176332180e40SYinghai Lu 
176432180e40SYinghai Lu 	if (tried_times >= 2) {
176532180e40SYinghai Lu 		/* still fail, don't need to try more */
1766bffc56d4SYinghai Lu 		free_list(&fail_head);
17673f579c34SYinghai Lu 		goto enable_all;
176832180e40SYinghai Lu 	}
176932180e40SYinghai Lu 
177032180e40SYinghai Lu 	printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
177132180e40SYinghai Lu 			 tried_times + 1);
177232180e40SYinghai Lu 
177332180e40SYinghai Lu 	/*
177432180e40SYinghai Lu 	 * Try to release leaf bridge's resources that doesn't fit resource of
177532180e40SYinghai Lu 	 * child device under that bridge
177632180e40SYinghai Lu 	 */
177761e83cddSYinghai Lu 	list_for_each_entry(fail_res, &fail_head, list)
177861e83cddSYinghai Lu 		pci_bus_release_bridge_resources(fail_res->dev->bus,
177961e83cddSYinghai Lu 						 fail_res->flags & type_mask,
178032180e40SYinghai Lu 						 whole_subtree);
178161e83cddSYinghai Lu 
178232180e40SYinghai Lu 	/* restore size and flags */
1783b9b0bba9SYinghai Lu 	list_for_each_entry(fail_res, &fail_head, list) {
1784b9b0bba9SYinghai Lu 		struct resource *res = fail_res->res;
178532180e40SYinghai Lu 
1786b9b0bba9SYinghai Lu 		res->start = fail_res->start;
1787b9b0bba9SYinghai Lu 		res->end = fail_res->end;
1788b9b0bba9SYinghai Lu 		res->flags = fail_res->flags;
1789b9b0bba9SYinghai Lu 		if (fail_res->dev->subordinate)
179032180e40SYinghai Lu 			res->flags = 0;
179132180e40SYinghai Lu 	}
1792bffc56d4SYinghai Lu 	free_list(&fail_head);
179332180e40SYinghai Lu 
179432180e40SYinghai Lu 	goto again;
17953f579c34SYinghai Lu 
17963f579c34SYinghai Lu enable_all:
17973f579c34SYinghai Lu 	retval = pci_reenable_device(bridge);
17989fc9eea0SBjorn Helgaas 	if (retval)
17999fc9eea0SBjorn Helgaas 		dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
18003f579c34SYinghai Lu 	pci_set_master(bridge);
18016841ec68SYinghai Lu }
18026841ec68SYinghai Lu EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
18039b03088fSYinghai Lu 
180417787940SYinghai Lu void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
18059b03088fSYinghai Lu {
18069b03088fSYinghai Lu 	struct pci_dev *dev;
1807bdc4abecSYinghai Lu 	LIST_HEAD(add_list); /* list of resources that
18089b03088fSYinghai Lu 					want additional resources */
18099b03088fSYinghai Lu 
18109b03088fSYinghai Lu 	down_read(&pci_bus_sem);
18119b03088fSYinghai Lu 	list_for_each_entry(dev, &bus->devices, bus_list)
18126788a51fSYijing Wang 		if (pci_is_bridge(dev) && pci_has_subordinate(dev))
18139b03088fSYinghai Lu 				__pci_bus_size_bridges(dev->subordinate,
18149b03088fSYinghai Lu 							 &add_list);
18159b03088fSYinghai Lu 	up_read(&pci_bus_sem);
18169b03088fSYinghai Lu 	__pci_bus_assign_resources(bus, &add_list, NULL);
1817bdc4abecSYinghai Lu 	BUG_ON(!list_empty(&add_list));
181817787940SYinghai Lu }
1819e6b29deaSRay Jui EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
1820