1 /* 2 * PCI Bus Services, see include/linux/pci.h for further explanation. 3 * 4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, 5 * David Mosberger-Tang 6 * 7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/delay.h> 12 #include <linux/init.h> 13 #include <linux/pci.h> 14 #include <linux/pm.h> 15 #include <linux/module.h> 16 #include <linux/spinlock.h> 17 #include <linux/string.h> 18 #include <linux/log2.h> 19 #include <linux/pci-aspm.h> 20 #include <linux/pm_wakeup.h> 21 #include <linux/interrupt.h> 22 #include <asm/dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/device.h> 24 #include <asm/setup.h> 25 #include "pci.h" 26 27 const char *pci_power_names[] = { 28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown", 29 }; 30 EXPORT_SYMBOL_GPL(pci_power_names); 31 32 unsigned int pci_pm_d3_delay; 33 34 static void pci_dev_d3_sleep(struct pci_dev *dev) 35 { 36 unsigned int delay = dev->d3_delay; 37 38 if (delay < pci_pm_d3_delay) 39 delay = pci_pm_d3_delay; 40 41 msleep(delay); 42 } 43 44 #ifdef CONFIG_PCI_DOMAINS 45 int pci_domains_supported = 1; 46 #endif 47 48 #define DEFAULT_CARDBUS_IO_SIZE (256) 49 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024) 50 /* pci=cbmemsize=nnM,cbiosize=nn can override this */ 51 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE; 52 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE; 53 54 #define DEFAULT_HOTPLUG_IO_SIZE (256) 55 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024) 56 /* pci=hpmemsize=nnM,hpiosize=nn can override this */ 57 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE; 58 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE; 59 60 /* 61 * The default CLS is used if arch didn't set CLS explicitly and not 62 * all pci devices agree on the same value. Arch can override either 63 * the dfl or actual value as it sees fit. Don't forget this is 64 * measured in 32-bit words, not bytes. 65 */ 66 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2; 67 u8 pci_cache_line_size; 68 69 /** 70 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children 71 * @bus: pointer to PCI bus structure to search 72 * 73 * Given a PCI bus, returns the highest PCI bus number present in the set 74 * including the given PCI bus and its list of child PCI buses. 75 */ 76 unsigned char pci_bus_max_busnr(struct pci_bus* bus) 77 { 78 struct list_head *tmp; 79 unsigned char max, n; 80 81 max = bus->subordinate; 82 list_for_each(tmp, &bus->children) { 83 n = pci_bus_max_busnr(pci_bus_b(tmp)); 84 if(n > max) 85 max = n; 86 } 87 return max; 88 } 89 EXPORT_SYMBOL_GPL(pci_bus_max_busnr); 90 91 #ifdef CONFIG_HAS_IOMEM 92 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) 93 { 94 /* 95 * Make sure the BAR is actually a memory resource, not an IO resource 96 */ 97 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 98 WARN_ON(1); 99 return NULL; 100 } 101 return ioremap_nocache(pci_resource_start(pdev, bar), 102 pci_resource_len(pdev, bar)); 103 } 104 EXPORT_SYMBOL_GPL(pci_ioremap_bar); 105 #endif 106 107 #if 0 108 /** 109 * pci_max_busnr - returns maximum PCI bus number 110 * 111 * Returns the highest PCI bus number present in the system global list of 112 * PCI buses. 113 */ 114 unsigned char __devinit 115 pci_max_busnr(void) 116 { 117 struct pci_bus *bus = NULL; 118 unsigned char max, n; 119 120 max = 0; 121 while ((bus = pci_find_next_bus(bus)) != NULL) { 122 n = pci_bus_max_busnr(bus); 123 if(n > max) 124 max = n; 125 } 126 return max; 127 } 128 129 #endif /* 0 */ 130 131 #define PCI_FIND_CAP_TTL 48 132 133 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, 134 u8 pos, int cap, int *ttl) 135 { 136 u8 id; 137 138 while ((*ttl)--) { 139 pci_bus_read_config_byte(bus, devfn, pos, &pos); 140 if (pos < 0x40) 141 break; 142 pos &= ~3; 143 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, 144 &id); 145 if (id == 0xff) 146 break; 147 if (id == cap) 148 return pos; 149 pos += PCI_CAP_LIST_NEXT; 150 } 151 return 0; 152 } 153 154 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, 155 u8 pos, int cap) 156 { 157 int ttl = PCI_FIND_CAP_TTL; 158 159 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl); 160 } 161 162 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) 163 { 164 return __pci_find_next_cap(dev->bus, dev->devfn, 165 pos + PCI_CAP_LIST_NEXT, cap); 166 } 167 EXPORT_SYMBOL_GPL(pci_find_next_capability); 168 169 static int __pci_bus_find_cap_start(struct pci_bus *bus, 170 unsigned int devfn, u8 hdr_type) 171 { 172 u16 status; 173 174 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); 175 if (!(status & PCI_STATUS_CAP_LIST)) 176 return 0; 177 178 switch (hdr_type) { 179 case PCI_HEADER_TYPE_NORMAL: 180 case PCI_HEADER_TYPE_BRIDGE: 181 return PCI_CAPABILITY_LIST; 182 case PCI_HEADER_TYPE_CARDBUS: 183 return PCI_CB_CAPABILITY_LIST; 184 default: 185 return 0; 186 } 187 188 return 0; 189 } 190 191 /** 192 * pci_find_capability - query for devices' capabilities 193 * @dev: PCI device to query 194 * @cap: capability code 195 * 196 * Tell if a device supports a given PCI capability. 197 * Returns the address of the requested capability structure within the 198 * device's PCI configuration space or 0 in case the device does not 199 * support it. Possible values for @cap: 200 * 201 * %PCI_CAP_ID_PM Power Management 202 * %PCI_CAP_ID_AGP Accelerated Graphics Port 203 * %PCI_CAP_ID_VPD Vital Product Data 204 * %PCI_CAP_ID_SLOTID Slot Identification 205 * %PCI_CAP_ID_MSI Message Signalled Interrupts 206 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap 207 * %PCI_CAP_ID_PCIX PCI-X 208 * %PCI_CAP_ID_EXP PCI Express 209 */ 210 int pci_find_capability(struct pci_dev *dev, int cap) 211 { 212 int pos; 213 214 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 215 if (pos) 216 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); 217 218 return pos; 219 } 220 221 /** 222 * pci_bus_find_capability - query for devices' capabilities 223 * @bus: the PCI bus to query 224 * @devfn: PCI device to query 225 * @cap: capability code 226 * 227 * Like pci_find_capability() but works for pci devices that do not have a 228 * pci_dev structure set up yet. 229 * 230 * Returns the address of the requested capability structure within the 231 * device's PCI configuration space or 0 in case the device does not 232 * support it. 233 */ 234 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) 235 { 236 int pos; 237 u8 hdr_type; 238 239 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type); 240 241 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f); 242 if (pos) 243 pos = __pci_find_next_cap(bus, devfn, pos, cap); 244 245 return pos; 246 } 247 248 /** 249 * pci_find_ext_capability - Find an extended capability 250 * @dev: PCI device to query 251 * @cap: capability code 252 * 253 * Returns the address of the requested extended capability structure 254 * within the device's PCI configuration space or 0 if the device does 255 * not support it. Possible values for @cap: 256 * 257 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 258 * %PCI_EXT_CAP_ID_VC Virtual Channel 259 * %PCI_EXT_CAP_ID_DSN Device Serial Number 260 * %PCI_EXT_CAP_ID_PWR Power Budgeting 261 */ 262 int pci_find_ext_capability(struct pci_dev *dev, int cap) 263 { 264 u32 header; 265 int ttl; 266 int pos = PCI_CFG_SPACE_SIZE; 267 268 /* minimum 8 bytes per capability */ 269 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; 270 271 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) 272 return 0; 273 274 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 275 return 0; 276 277 /* 278 * If we have no capabilities, this is indicated by cap ID, 279 * cap version and next pointer all being 0. 280 */ 281 if (header == 0) 282 return 0; 283 284 while (ttl-- > 0) { 285 if (PCI_EXT_CAP_ID(header) == cap) 286 return pos; 287 288 pos = PCI_EXT_CAP_NEXT(header); 289 if (pos < PCI_CFG_SPACE_SIZE) 290 break; 291 292 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL) 293 break; 294 } 295 296 return 0; 297 } 298 EXPORT_SYMBOL_GPL(pci_find_ext_capability); 299 300 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) 301 { 302 int rc, ttl = PCI_FIND_CAP_TTL; 303 u8 cap, mask; 304 305 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST) 306 mask = HT_3BIT_CAP_MASK; 307 else 308 mask = HT_5BIT_CAP_MASK; 309 310 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, 311 PCI_CAP_ID_HT, &ttl); 312 while (pos) { 313 rc = pci_read_config_byte(dev, pos + 3, &cap); 314 if (rc != PCIBIOS_SUCCESSFUL) 315 return 0; 316 317 if ((cap & mask) == ht_cap) 318 return pos; 319 320 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, 321 pos + PCI_CAP_LIST_NEXT, 322 PCI_CAP_ID_HT, &ttl); 323 } 324 325 return 0; 326 } 327 /** 328 * pci_find_next_ht_capability - query a device's Hypertransport capabilities 329 * @dev: PCI device to query 330 * @pos: Position from which to continue searching 331 * @ht_cap: Hypertransport capability code 332 * 333 * To be used in conjunction with pci_find_ht_capability() to search for 334 * all capabilities matching @ht_cap. @pos should always be a value returned 335 * from pci_find_ht_capability(). 336 * 337 * NB. To be 100% safe against broken PCI devices, the caller should take 338 * steps to avoid an infinite loop. 339 */ 340 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap) 341 { 342 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap); 343 } 344 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability); 345 346 /** 347 * pci_find_ht_capability - query a device's Hypertransport capabilities 348 * @dev: PCI device to query 349 * @ht_cap: Hypertransport capability code 350 * 351 * Tell if a device supports a given Hypertransport capability. 352 * Returns an address within the device's PCI configuration space 353 * or 0 in case the device does not support the request capability. 354 * The address points to the PCI capability, of type PCI_CAP_ID_HT, 355 * which has a Hypertransport capability matching @ht_cap. 356 */ 357 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap) 358 { 359 int pos; 360 361 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); 362 if (pos) 363 pos = __pci_find_next_ht_cap(dev, pos, ht_cap); 364 365 return pos; 366 } 367 EXPORT_SYMBOL_GPL(pci_find_ht_capability); 368 369 /** 370 * pci_find_parent_resource - return resource region of parent bus of given region 371 * @dev: PCI device structure contains resources to be searched 372 * @res: child resource record for which parent is sought 373 * 374 * For given resource region of given device, return the resource 375 * region of parent bus the given region is contained in or where 376 * it should be allocated from. 377 */ 378 struct resource * 379 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) 380 { 381 const struct pci_bus *bus = dev->bus; 382 int i; 383 struct resource *best = NULL; 384 385 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { 386 struct resource *r = bus->resource[i]; 387 if (!r) 388 continue; 389 if (res->start && !(res->start >= r->start && res->end <= r->end)) 390 continue; /* Not contained */ 391 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) 392 continue; /* Wrong type */ 393 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) 394 return r; /* Exact match */ 395 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */ 396 if (r->flags & IORESOURCE_PREFETCH) 397 continue; 398 /* .. but we can put a prefetchable resource inside a non-prefetchable one */ 399 if (!best) 400 best = r; 401 } 402 return best; 403 } 404 405 /** 406 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up) 407 * @dev: PCI device to have its BARs restored 408 * 409 * Restore the BAR values for a given device, so as to make it 410 * accessible by its driver. 411 */ 412 static void 413 pci_restore_bars(struct pci_dev *dev) 414 { 415 int i; 416 417 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) 418 pci_update_resource(dev, i); 419 } 420 421 static struct pci_platform_pm_ops *pci_platform_pm; 422 423 int pci_set_platform_pm(struct pci_platform_pm_ops *ops) 424 { 425 if (!ops->is_manageable || !ops->set_state || !ops->choose_state 426 || !ops->sleep_wake || !ops->can_wakeup) 427 return -EINVAL; 428 pci_platform_pm = ops; 429 return 0; 430 } 431 432 static inline bool platform_pci_power_manageable(struct pci_dev *dev) 433 { 434 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false; 435 } 436 437 static inline int platform_pci_set_power_state(struct pci_dev *dev, 438 pci_power_t t) 439 { 440 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS; 441 } 442 443 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev) 444 { 445 return pci_platform_pm ? 446 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR; 447 } 448 449 static inline bool platform_pci_can_wakeup(struct pci_dev *dev) 450 { 451 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false; 452 } 453 454 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable) 455 { 456 return pci_platform_pm ? 457 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV; 458 } 459 460 /** 461 * pci_raw_set_power_state - Use PCI PM registers to set the power state of 462 * given PCI device 463 * @dev: PCI device to handle. 464 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 465 * 466 * RETURN VALUE: 467 * -EINVAL if the requested state is invalid. 468 * -EIO if device does not support PCI PM or its PM capabilities register has a 469 * wrong version, or device doesn't support the requested state. 470 * 0 if device already is in the requested state. 471 * 0 if device's power state has been successfully changed. 472 */ 473 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state) 474 { 475 u16 pmcsr; 476 bool need_restore = false; 477 478 /* Check if we're already there */ 479 if (dev->current_state == state) 480 return 0; 481 482 if (!dev->pm_cap) 483 return -EIO; 484 485 if (state < PCI_D0 || state > PCI_D3hot) 486 return -EINVAL; 487 488 /* Validate current state: 489 * Can enter D0 from any state, but if we can only go deeper 490 * to sleep if we're already in a low power state 491 */ 492 if (state != PCI_D0 && dev->current_state <= PCI_D3cold 493 && dev->current_state > state) { 494 dev_err(&dev->dev, "invalid power transition " 495 "(from state %d to %d)\n", dev->current_state, state); 496 return -EINVAL; 497 } 498 499 /* check if this device supports the desired state */ 500 if ((state == PCI_D1 && !dev->d1_support) 501 || (state == PCI_D2 && !dev->d2_support)) 502 return -EIO; 503 504 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 505 506 /* If we're (effectively) in D3, force entire word to 0. 507 * This doesn't affect PME_Status, disables PME_En, and 508 * sets PowerState to 0. 509 */ 510 switch (dev->current_state) { 511 case PCI_D0: 512 case PCI_D1: 513 case PCI_D2: 514 pmcsr &= ~PCI_PM_CTRL_STATE_MASK; 515 pmcsr |= state; 516 break; 517 case PCI_D3hot: 518 case PCI_D3cold: 519 case PCI_UNKNOWN: /* Boot-up */ 520 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot 521 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) 522 need_restore = true; 523 /* Fall-through: force to D0 */ 524 default: 525 pmcsr = 0; 526 break; 527 } 528 529 /* enter specified state */ 530 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 531 532 /* Mandatory power management transition delays */ 533 /* see PCI PM 1.1 5.6.1 table 18 */ 534 if (state == PCI_D3hot || dev->current_state == PCI_D3hot) 535 pci_dev_d3_sleep(dev); 536 else if (state == PCI_D2 || dev->current_state == PCI_D2) 537 udelay(PCI_PM_D2_DELAY); 538 539 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 540 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 541 if (dev->current_state != state && printk_ratelimit()) 542 dev_info(&dev->dev, "Refused to change power state, " 543 "currently in D%d\n", dev->current_state); 544 545 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT 546 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning 547 * from D3hot to D0 _may_ perform an internal reset, thereby 548 * going to "D0 Uninitialized" rather than "D0 Initialized". 549 * For example, at least some versions of the 3c905B and the 550 * 3c556B exhibit this behaviour. 551 * 552 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave 553 * devices in a D3hot state at boot. Consequently, we need to 554 * restore at least the BARs so that the device will be 555 * accessible to its driver. 556 */ 557 if (need_restore) 558 pci_restore_bars(dev); 559 560 if (dev->bus->self) 561 pcie_aspm_pm_state_change(dev->bus->self); 562 563 return 0; 564 } 565 566 /** 567 * pci_update_current_state - Read PCI power state of given device from its 568 * PCI PM registers and cache it 569 * @dev: PCI device to handle. 570 * @state: State to cache in case the device doesn't have the PM capability 571 */ 572 void pci_update_current_state(struct pci_dev *dev, pci_power_t state) 573 { 574 if (dev->pm_cap) { 575 u16 pmcsr; 576 577 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 578 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK); 579 } else { 580 dev->current_state = state; 581 } 582 } 583 584 /** 585 * pci_platform_power_transition - Use platform to change device power state 586 * @dev: PCI device to handle. 587 * @state: State to put the device into. 588 */ 589 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 590 { 591 int error; 592 593 if (platform_pci_power_manageable(dev)) { 594 error = platform_pci_set_power_state(dev, state); 595 if (!error) 596 pci_update_current_state(dev, state); 597 } else { 598 error = -ENODEV; 599 /* Fall back to PCI_D0 if native PM is not supported */ 600 if (!dev->pm_cap) 601 dev->current_state = PCI_D0; 602 } 603 604 return error; 605 } 606 607 /** 608 * __pci_start_power_transition - Start power transition of a PCI device 609 * @dev: PCI device to handle. 610 * @state: State to put the device into. 611 */ 612 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state) 613 { 614 if (state == PCI_D0) 615 pci_platform_power_transition(dev, PCI_D0); 616 } 617 618 /** 619 * __pci_complete_power_transition - Complete power transition of a PCI device 620 * @dev: PCI device to handle. 621 * @state: State to put the device into. 622 * 623 * This function should not be called directly by device drivers. 624 */ 625 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state) 626 { 627 return state > PCI_D0 ? 628 pci_platform_power_transition(dev, state) : -EINVAL; 629 } 630 EXPORT_SYMBOL_GPL(__pci_complete_power_transition); 631 632 /** 633 * pci_set_power_state - Set the power state of a PCI device 634 * @dev: PCI device to handle. 635 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into. 636 * 637 * Transition a device to a new power state, using the platform firmware and/or 638 * the device's PCI PM registers. 639 * 640 * RETURN VALUE: 641 * -EINVAL if the requested state is invalid. 642 * -EIO if device does not support PCI PM or its PM capabilities register has a 643 * wrong version, or device doesn't support the requested state. 644 * 0 if device already is in the requested state. 645 * 0 if device's power state has been successfully changed. 646 */ 647 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) 648 { 649 int error; 650 651 /* bound the state we're entering */ 652 if (state > PCI_D3hot) 653 state = PCI_D3hot; 654 else if (state < PCI_D0) 655 state = PCI_D0; 656 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev)) 657 /* 658 * If the device or the parent bridge do not support PCI PM, 659 * ignore the request if we're doing anything other than putting 660 * it into D0 (which would only happen on boot). 661 */ 662 return 0; 663 664 /* Check if we're already there */ 665 if (dev->current_state == state) 666 return 0; 667 668 __pci_start_power_transition(dev, state); 669 670 /* This device is quirked not to be put into D3, so 671 don't put it in D3 */ 672 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) 673 return 0; 674 675 error = pci_raw_set_power_state(dev, state); 676 677 if (!__pci_complete_power_transition(dev, state)) 678 error = 0; 679 680 return error; 681 } 682 683 /** 684 * pci_choose_state - Choose the power state of a PCI device 685 * @dev: PCI device to be suspended 686 * @state: target sleep state for the whole system. This is the value 687 * that is passed to suspend() function. 688 * 689 * Returns PCI power state suitable for given device and given system 690 * message. 691 */ 692 693 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state) 694 { 695 pci_power_t ret; 696 697 if (!pci_find_capability(dev, PCI_CAP_ID_PM)) 698 return PCI_D0; 699 700 ret = platform_pci_choose_state(dev); 701 if (ret != PCI_POWER_ERROR) 702 return ret; 703 704 switch (state.event) { 705 case PM_EVENT_ON: 706 return PCI_D0; 707 case PM_EVENT_FREEZE: 708 case PM_EVENT_PRETHAW: 709 /* REVISIT both freeze and pre-thaw "should" use D0 */ 710 case PM_EVENT_SUSPEND: 711 case PM_EVENT_HIBERNATE: 712 return PCI_D3hot; 713 default: 714 dev_info(&dev->dev, "unrecognized suspend event %d\n", 715 state.event); 716 BUG(); 717 } 718 return PCI_D0; 719 } 720 721 EXPORT_SYMBOL(pci_choose_state); 722 723 #define PCI_EXP_SAVE_REGS 7 724 725 #define pcie_cap_has_devctl(type, flags) 1 726 #define pcie_cap_has_lnkctl(type, flags) \ 727 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 728 (type == PCI_EXP_TYPE_ROOT_PORT || \ 729 type == PCI_EXP_TYPE_ENDPOINT || \ 730 type == PCI_EXP_TYPE_LEG_END)) 731 #define pcie_cap_has_sltctl(type, flags) \ 732 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 733 ((type == PCI_EXP_TYPE_ROOT_PORT) || \ 734 (type == PCI_EXP_TYPE_DOWNSTREAM && \ 735 (flags & PCI_EXP_FLAGS_SLOT)))) 736 #define pcie_cap_has_rtctl(type, flags) \ 737 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \ 738 (type == PCI_EXP_TYPE_ROOT_PORT || \ 739 type == PCI_EXP_TYPE_RC_EC)) 740 #define pcie_cap_has_devctl2(type, flags) \ 741 ((flags & PCI_EXP_FLAGS_VERS) > 1) 742 #define pcie_cap_has_lnkctl2(type, flags) \ 743 ((flags & PCI_EXP_FLAGS_VERS) > 1) 744 #define pcie_cap_has_sltctl2(type, flags) \ 745 ((flags & PCI_EXP_FLAGS_VERS) > 1) 746 747 static int pci_save_pcie_state(struct pci_dev *dev) 748 { 749 int pos, i = 0; 750 struct pci_cap_saved_state *save_state; 751 u16 *cap; 752 u16 flags; 753 754 pos = pci_pcie_cap(dev); 755 if (!pos) 756 return 0; 757 758 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 759 if (!save_state) { 760 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 761 return -ENOMEM; 762 } 763 cap = (u16 *)&save_state->data[0]; 764 765 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 766 767 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 768 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]); 769 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 770 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 771 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 772 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 773 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 774 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 775 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 776 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]); 777 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 778 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]); 779 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 780 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]); 781 782 return 0; 783 } 784 785 static void pci_restore_pcie_state(struct pci_dev *dev) 786 { 787 int i = 0, pos; 788 struct pci_cap_saved_state *save_state; 789 u16 *cap; 790 u16 flags; 791 792 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 793 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 794 if (!save_state || pos <= 0) 795 return; 796 cap = (u16 *)&save_state->data[0]; 797 798 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags); 799 800 if (pcie_cap_has_devctl(dev->pcie_type, flags)) 801 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]); 802 if (pcie_cap_has_lnkctl(dev->pcie_type, flags)) 803 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]); 804 if (pcie_cap_has_sltctl(dev->pcie_type, flags)) 805 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]); 806 if (pcie_cap_has_rtctl(dev->pcie_type, flags)) 807 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]); 808 if (pcie_cap_has_devctl2(dev->pcie_type, flags)) 809 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]); 810 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags)) 811 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]); 812 if (pcie_cap_has_sltctl2(dev->pcie_type, flags)) 813 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]); 814 } 815 816 817 static int pci_save_pcix_state(struct pci_dev *dev) 818 { 819 int pos; 820 struct pci_cap_saved_state *save_state; 821 822 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 823 if (pos <= 0) 824 return 0; 825 826 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 827 if (!save_state) { 828 dev_err(&dev->dev, "buffer not found in %s\n", __func__); 829 return -ENOMEM; 830 } 831 832 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data); 833 834 return 0; 835 } 836 837 static void pci_restore_pcix_state(struct pci_dev *dev) 838 { 839 int i = 0, pos; 840 struct pci_cap_saved_state *save_state; 841 u16 *cap; 842 843 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX); 844 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 845 if (!save_state || pos <= 0) 846 return; 847 cap = (u16 *)&save_state->data[0]; 848 849 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]); 850 } 851 852 853 /** 854 * pci_save_state - save the PCI configuration space of a device before suspending 855 * @dev: - PCI device that we're dealing with 856 */ 857 int 858 pci_save_state(struct pci_dev *dev) 859 { 860 int i; 861 /* XXX: 100% dword access ok here? */ 862 for (i = 0; i < 16; i++) 863 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); 864 dev->state_saved = true; 865 if ((i = pci_save_pcie_state(dev)) != 0) 866 return i; 867 if ((i = pci_save_pcix_state(dev)) != 0) 868 return i; 869 return 0; 870 } 871 872 /** 873 * pci_restore_state - Restore the saved state of a PCI device 874 * @dev: - PCI device that we're dealing with 875 */ 876 int 877 pci_restore_state(struct pci_dev *dev) 878 { 879 int i; 880 u32 val; 881 882 if (!dev->state_saved) 883 return 0; 884 885 /* PCI Express register must be restored first */ 886 pci_restore_pcie_state(dev); 887 888 /* 889 * The Base Address register should be programmed before the command 890 * register(s) 891 */ 892 for (i = 15; i >= 0; i--) { 893 pci_read_config_dword(dev, i * 4, &val); 894 if (val != dev->saved_config_space[i]) { 895 dev_printk(KERN_DEBUG, &dev->dev, "restoring config " 896 "space at offset %#x (was %#x, writing %#x)\n", 897 i, val, (int)dev->saved_config_space[i]); 898 pci_write_config_dword(dev,i * 4, 899 dev->saved_config_space[i]); 900 } 901 } 902 pci_restore_pcix_state(dev); 903 pci_restore_msi_state(dev); 904 pci_restore_iov_state(dev); 905 906 dev->state_saved = false; 907 908 return 0; 909 } 910 911 static int do_pci_enable_device(struct pci_dev *dev, int bars) 912 { 913 int err; 914 915 err = pci_set_power_state(dev, PCI_D0); 916 if (err < 0 && err != -EIO) 917 return err; 918 err = pcibios_enable_device(dev, bars); 919 if (err < 0) 920 return err; 921 pci_fixup_device(pci_fixup_enable, dev); 922 923 return 0; 924 } 925 926 /** 927 * pci_reenable_device - Resume abandoned device 928 * @dev: PCI device to be resumed 929 * 930 * Note this function is a backend of pci_default_resume and is not supposed 931 * to be called by normal code, write proper resume handler and use it instead. 932 */ 933 int pci_reenable_device(struct pci_dev *dev) 934 { 935 if (pci_is_enabled(dev)) 936 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); 937 return 0; 938 } 939 940 static int __pci_enable_device_flags(struct pci_dev *dev, 941 resource_size_t flags) 942 { 943 int err; 944 int i, bars = 0; 945 946 if (atomic_add_return(1, &dev->enable_cnt) > 1) 947 return 0; /* already enabled */ 948 949 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 950 if (dev->resource[i].flags & flags) 951 bars |= (1 << i); 952 953 err = do_pci_enable_device(dev, bars); 954 if (err < 0) 955 atomic_dec(&dev->enable_cnt); 956 return err; 957 } 958 959 /** 960 * pci_enable_device_io - Initialize a device for use with IO space 961 * @dev: PCI device to be initialized 962 * 963 * Initialize device before it's used by a driver. Ask low-level code 964 * to enable I/O resources. Wake up the device if it was suspended. 965 * Beware, this function can fail. 966 */ 967 int pci_enable_device_io(struct pci_dev *dev) 968 { 969 return __pci_enable_device_flags(dev, IORESOURCE_IO); 970 } 971 972 /** 973 * pci_enable_device_mem - Initialize a device for use with Memory space 974 * @dev: PCI device to be initialized 975 * 976 * Initialize device before it's used by a driver. Ask low-level code 977 * to enable Memory resources. Wake up the device if it was suspended. 978 * Beware, this function can fail. 979 */ 980 int pci_enable_device_mem(struct pci_dev *dev) 981 { 982 return __pci_enable_device_flags(dev, IORESOURCE_MEM); 983 } 984 985 /** 986 * pci_enable_device - Initialize device before it's used by a driver. 987 * @dev: PCI device to be initialized 988 * 989 * Initialize device before it's used by a driver. Ask low-level code 990 * to enable I/O and memory. Wake up the device if it was suspended. 991 * Beware, this function can fail. 992 * 993 * Note we don't actually enable the device many times if we call 994 * this function repeatedly (we just increment the count). 995 */ 996 int pci_enable_device(struct pci_dev *dev) 997 { 998 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO); 999 } 1000 1001 /* 1002 * Managed PCI resources. This manages device on/off, intx/msi/msix 1003 * on/off and BAR regions. pci_dev itself records msi/msix status, so 1004 * there's no need to track it separately. pci_devres is initialized 1005 * when a device is enabled using managed PCI device enable interface. 1006 */ 1007 struct pci_devres { 1008 unsigned int enabled:1; 1009 unsigned int pinned:1; 1010 unsigned int orig_intx:1; 1011 unsigned int restore_intx:1; 1012 u32 region_mask; 1013 }; 1014 1015 static void pcim_release(struct device *gendev, void *res) 1016 { 1017 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev); 1018 struct pci_devres *this = res; 1019 int i; 1020 1021 if (dev->msi_enabled) 1022 pci_disable_msi(dev); 1023 if (dev->msix_enabled) 1024 pci_disable_msix(dev); 1025 1026 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 1027 if (this->region_mask & (1 << i)) 1028 pci_release_region(dev, i); 1029 1030 if (this->restore_intx) 1031 pci_intx(dev, this->orig_intx); 1032 1033 if (this->enabled && !this->pinned) 1034 pci_disable_device(dev); 1035 } 1036 1037 static struct pci_devres * get_pci_dr(struct pci_dev *pdev) 1038 { 1039 struct pci_devres *dr, *new_dr; 1040 1041 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL); 1042 if (dr) 1043 return dr; 1044 1045 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL); 1046 if (!new_dr) 1047 return NULL; 1048 return devres_get(&pdev->dev, new_dr, NULL, NULL); 1049 } 1050 1051 static struct pci_devres * find_pci_dr(struct pci_dev *pdev) 1052 { 1053 if (pci_is_managed(pdev)) 1054 return devres_find(&pdev->dev, pcim_release, NULL, NULL); 1055 return NULL; 1056 } 1057 1058 /** 1059 * pcim_enable_device - Managed pci_enable_device() 1060 * @pdev: PCI device to be initialized 1061 * 1062 * Managed pci_enable_device(). 1063 */ 1064 int pcim_enable_device(struct pci_dev *pdev) 1065 { 1066 struct pci_devres *dr; 1067 int rc; 1068 1069 dr = get_pci_dr(pdev); 1070 if (unlikely(!dr)) 1071 return -ENOMEM; 1072 if (dr->enabled) 1073 return 0; 1074 1075 rc = pci_enable_device(pdev); 1076 if (!rc) { 1077 pdev->is_managed = 1; 1078 dr->enabled = 1; 1079 } 1080 return rc; 1081 } 1082 1083 /** 1084 * pcim_pin_device - Pin managed PCI device 1085 * @pdev: PCI device to pin 1086 * 1087 * Pin managed PCI device @pdev. Pinned device won't be disabled on 1088 * driver detach. @pdev must have been enabled with 1089 * pcim_enable_device(). 1090 */ 1091 void pcim_pin_device(struct pci_dev *pdev) 1092 { 1093 struct pci_devres *dr; 1094 1095 dr = find_pci_dr(pdev); 1096 WARN_ON(!dr || !dr->enabled); 1097 if (dr) 1098 dr->pinned = 1; 1099 } 1100 1101 /** 1102 * pcibios_disable_device - disable arch specific PCI resources for device dev 1103 * @dev: the PCI device to disable 1104 * 1105 * Disables architecture specific PCI resources for the device. This 1106 * is the default implementation. Architecture implementations can 1107 * override this. 1108 */ 1109 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {} 1110 1111 static void do_pci_disable_device(struct pci_dev *dev) 1112 { 1113 u16 pci_command; 1114 1115 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 1116 if (pci_command & PCI_COMMAND_MASTER) { 1117 pci_command &= ~PCI_COMMAND_MASTER; 1118 pci_write_config_word(dev, PCI_COMMAND, pci_command); 1119 } 1120 1121 pcibios_disable_device(dev); 1122 } 1123 1124 /** 1125 * pci_disable_enabled_device - Disable device without updating enable_cnt 1126 * @dev: PCI device to disable 1127 * 1128 * NOTE: This function is a backend of PCI power management routines and is 1129 * not supposed to be called drivers. 1130 */ 1131 void pci_disable_enabled_device(struct pci_dev *dev) 1132 { 1133 if (pci_is_enabled(dev)) 1134 do_pci_disable_device(dev); 1135 } 1136 1137 /** 1138 * pci_disable_device - Disable PCI device after use 1139 * @dev: PCI device to be disabled 1140 * 1141 * Signal to the system that the PCI device is not in use by the system 1142 * anymore. This only involves disabling PCI bus-mastering, if active. 1143 * 1144 * Note we don't actually disable the device until all callers of 1145 * pci_device_enable() have called pci_device_disable(). 1146 */ 1147 void 1148 pci_disable_device(struct pci_dev *dev) 1149 { 1150 struct pci_devres *dr; 1151 1152 dr = find_pci_dr(dev); 1153 if (dr) 1154 dr->enabled = 0; 1155 1156 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 1157 return; 1158 1159 do_pci_disable_device(dev); 1160 1161 dev->is_busmaster = 0; 1162 } 1163 1164 /** 1165 * pcibios_set_pcie_reset_state - set reset state for device dev 1166 * @dev: the PCIe device reset 1167 * @state: Reset state to enter into 1168 * 1169 * 1170 * Sets the PCIe reset state for the device. This is the default 1171 * implementation. Architecture implementations can override this. 1172 */ 1173 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev, 1174 enum pcie_reset_state state) 1175 { 1176 return -EINVAL; 1177 } 1178 1179 /** 1180 * pci_set_pcie_reset_state - set reset state for device dev 1181 * @dev: the PCIe device reset 1182 * @state: Reset state to enter into 1183 * 1184 * 1185 * Sets the PCI reset state for the device. 1186 */ 1187 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) 1188 { 1189 return pcibios_set_pcie_reset_state(dev, state); 1190 } 1191 1192 /** 1193 * pci_pme_capable - check the capability of PCI device to generate PME# 1194 * @dev: PCI device to handle. 1195 * @state: PCI state from which device will issue PME#. 1196 */ 1197 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state) 1198 { 1199 if (!dev->pm_cap) 1200 return false; 1201 1202 return !!(dev->pme_support & (1 << state)); 1203 } 1204 1205 /** 1206 * pci_pme_active - enable or disable PCI device's PME# function 1207 * @dev: PCI device to handle. 1208 * @enable: 'true' to enable PME# generation; 'false' to disable it. 1209 * 1210 * The caller must verify that the device is capable of generating PME# before 1211 * calling this function with @enable equal to 'true'. 1212 */ 1213 void pci_pme_active(struct pci_dev *dev, bool enable) 1214 { 1215 u16 pmcsr; 1216 1217 if (!dev->pm_cap) 1218 return; 1219 1220 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 1221 /* Clear PME_Status by writing 1 to it and enable PME# */ 1222 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; 1223 if (!enable) 1224 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE; 1225 1226 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); 1227 1228 dev_printk(KERN_DEBUG, &dev->dev, "PME# %s\n", 1229 enable ? "enabled" : "disabled"); 1230 } 1231 1232 /** 1233 * pci_enable_wake - enable PCI device as wakeup event source 1234 * @dev: PCI device affected 1235 * @state: PCI state from which device will issue wakeup events 1236 * @enable: True to enable event generation; false to disable 1237 * 1238 * This enables the device as a wakeup event source, or disables it. 1239 * When such events involves platform-specific hooks, those hooks are 1240 * called automatically by this routine. 1241 * 1242 * Devices with legacy power management (no standard PCI PM capabilities) 1243 * always require such platform hooks. 1244 * 1245 * RETURN VALUE: 1246 * 0 is returned on success 1247 * -EINVAL is returned if device is not supposed to wake up the system 1248 * Error code depending on the platform is returned if both the platform and 1249 * the native mechanism fail to enable the generation of wake-up events 1250 */ 1251 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) 1252 { 1253 int ret = 0; 1254 1255 if (enable && !device_may_wakeup(&dev->dev)) 1256 return -EINVAL; 1257 1258 /* Don't do the same thing twice in a row for one device. */ 1259 if (!!enable == !!dev->wakeup_prepared) 1260 return 0; 1261 1262 /* 1263 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don 1264 * Anderson we should be doing PME# wake enable followed by ACPI wake 1265 * enable. To disable wake-up we call the platform first, for symmetry. 1266 */ 1267 1268 if (enable) { 1269 int error; 1270 1271 if (pci_pme_capable(dev, state)) 1272 pci_pme_active(dev, true); 1273 else 1274 ret = 1; 1275 error = platform_pci_sleep_wake(dev, true); 1276 if (ret) 1277 ret = error; 1278 if (!ret) 1279 dev->wakeup_prepared = true; 1280 } else { 1281 platform_pci_sleep_wake(dev, false); 1282 pci_pme_active(dev, false); 1283 dev->wakeup_prepared = false; 1284 } 1285 1286 return ret; 1287 } 1288 1289 /** 1290 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold 1291 * @dev: PCI device to prepare 1292 * @enable: True to enable wake-up event generation; false to disable 1293 * 1294 * Many drivers want the device to wake up the system from D3_hot or D3_cold 1295 * and this function allows them to set that up cleanly - pci_enable_wake() 1296 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI 1297 * ordering constraints. 1298 * 1299 * This function only returns error code if the device is not capable of 1300 * generating PME# from both D3_hot and D3_cold, and the platform is unable to 1301 * enable wake-up power for it. 1302 */ 1303 int pci_wake_from_d3(struct pci_dev *dev, bool enable) 1304 { 1305 return pci_pme_capable(dev, PCI_D3cold) ? 1306 pci_enable_wake(dev, PCI_D3cold, enable) : 1307 pci_enable_wake(dev, PCI_D3hot, enable); 1308 } 1309 1310 /** 1311 * pci_target_state - find an appropriate low power state for a given PCI dev 1312 * @dev: PCI device 1313 * 1314 * Use underlying platform code to find a supported low power state for @dev. 1315 * If the platform can't manage @dev, return the deepest state from which it 1316 * can generate wake events, based on any available PME info. 1317 */ 1318 pci_power_t pci_target_state(struct pci_dev *dev) 1319 { 1320 pci_power_t target_state = PCI_D3hot; 1321 1322 if (platform_pci_power_manageable(dev)) { 1323 /* 1324 * Call the platform to choose the target state of the device 1325 * and enable wake-up from this state if supported. 1326 */ 1327 pci_power_t state = platform_pci_choose_state(dev); 1328 1329 switch (state) { 1330 case PCI_POWER_ERROR: 1331 case PCI_UNKNOWN: 1332 break; 1333 case PCI_D1: 1334 case PCI_D2: 1335 if (pci_no_d1d2(dev)) 1336 break; 1337 default: 1338 target_state = state; 1339 } 1340 } else if (!dev->pm_cap) { 1341 target_state = PCI_D0; 1342 } else if (device_may_wakeup(&dev->dev)) { 1343 /* 1344 * Find the deepest state from which the device can generate 1345 * wake-up events, make it the target state and enable device 1346 * to generate PME#. 1347 */ 1348 if (dev->pme_support) { 1349 while (target_state 1350 && !(dev->pme_support & (1 << target_state))) 1351 target_state--; 1352 } 1353 } 1354 1355 return target_state; 1356 } 1357 1358 /** 1359 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state 1360 * @dev: Device to handle. 1361 * 1362 * Choose the power state appropriate for the device depending on whether 1363 * it can wake up the system and/or is power manageable by the platform 1364 * (PCI_D3hot is the default) and put the device into that state. 1365 */ 1366 int pci_prepare_to_sleep(struct pci_dev *dev) 1367 { 1368 pci_power_t target_state = pci_target_state(dev); 1369 int error; 1370 1371 if (target_state == PCI_POWER_ERROR) 1372 return -EIO; 1373 1374 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev)); 1375 1376 error = pci_set_power_state(dev, target_state); 1377 1378 if (error) 1379 pci_enable_wake(dev, target_state, false); 1380 1381 return error; 1382 } 1383 1384 /** 1385 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state 1386 * @dev: Device to handle. 1387 * 1388 * Disable device's sytem wake-up capability and put it into D0. 1389 */ 1390 int pci_back_from_sleep(struct pci_dev *dev) 1391 { 1392 pci_enable_wake(dev, PCI_D0, false); 1393 return pci_set_power_state(dev, PCI_D0); 1394 } 1395 1396 /** 1397 * pci_pm_init - Initialize PM functions of given PCI device 1398 * @dev: PCI device to handle. 1399 */ 1400 void pci_pm_init(struct pci_dev *dev) 1401 { 1402 int pm; 1403 u16 pmc; 1404 1405 dev->wakeup_prepared = false; 1406 dev->pm_cap = 0; 1407 1408 /* find PCI PM capability in list */ 1409 pm = pci_find_capability(dev, PCI_CAP_ID_PM); 1410 if (!pm) 1411 return; 1412 /* Check device's ability to generate PME# */ 1413 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc); 1414 1415 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) { 1416 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n", 1417 pmc & PCI_PM_CAP_VER_MASK); 1418 return; 1419 } 1420 1421 dev->pm_cap = pm; 1422 dev->d3_delay = PCI_PM_D3_WAIT; 1423 1424 dev->d1_support = false; 1425 dev->d2_support = false; 1426 if (!pci_no_d1d2(dev)) { 1427 if (pmc & PCI_PM_CAP_D1) 1428 dev->d1_support = true; 1429 if (pmc & PCI_PM_CAP_D2) 1430 dev->d2_support = true; 1431 1432 if (dev->d1_support || dev->d2_support) 1433 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n", 1434 dev->d1_support ? " D1" : "", 1435 dev->d2_support ? " D2" : ""); 1436 } 1437 1438 pmc &= PCI_PM_CAP_PME_MASK; 1439 if (pmc) { 1440 dev_printk(KERN_DEBUG, &dev->dev, 1441 "PME# supported from%s%s%s%s%s\n", 1442 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "", 1443 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "", 1444 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "", 1445 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "", 1446 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : ""); 1447 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT; 1448 /* 1449 * Make device's PM flags reflect the wake-up capability, but 1450 * let the user space enable it to wake up the system as needed. 1451 */ 1452 device_set_wakeup_capable(&dev->dev, true); 1453 device_set_wakeup_enable(&dev->dev, false); 1454 /* Disable the PME# generation functionality */ 1455 pci_pme_active(dev, false); 1456 } else { 1457 dev->pme_support = 0; 1458 } 1459 } 1460 1461 /** 1462 * platform_pci_wakeup_init - init platform wakeup if present 1463 * @dev: PCI device 1464 * 1465 * Some devices don't have PCI PM caps but can still generate wakeup 1466 * events through platform methods (like ACPI events). If @dev supports 1467 * platform wakeup events, set the device flag to indicate as much. This 1468 * may be redundant if the device also supports PCI PM caps, but double 1469 * initialization should be safe in that case. 1470 */ 1471 void platform_pci_wakeup_init(struct pci_dev *dev) 1472 { 1473 if (!platform_pci_can_wakeup(dev)) 1474 return; 1475 1476 device_set_wakeup_capable(&dev->dev, true); 1477 device_set_wakeup_enable(&dev->dev, false); 1478 platform_pci_sleep_wake(dev, false); 1479 } 1480 1481 /** 1482 * pci_add_save_buffer - allocate buffer for saving given capability registers 1483 * @dev: the PCI device 1484 * @cap: the capability to allocate the buffer for 1485 * @size: requested size of the buffer 1486 */ 1487 static int pci_add_cap_save_buffer( 1488 struct pci_dev *dev, char cap, unsigned int size) 1489 { 1490 int pos; 1491 struct pci_cap_saved_state *save_state; 1492 1493 pos = pci_find_capability(dev, cap); 1494 if (pos <= 0) 1495 return 0; 1496 1497 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL); 1498 if (!save_state) 1499 return -ENOMEM; 1500 1501 save_state->cap_nr = cap; 1502 pci_add_saved_cap(dev, save_state); 1503 1504 return 0; 1505 } 1506 1507 /** 1508 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities 1509 * @dev: the PCI device 1510 */ 1511 void pci_allocate_cap_save_buffers(struct pci_dev *dev) 1512 { 1513 int error; 1514 1515 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP, 1516 PCI_EXP_SAVE_REGS * sizeof(u16)); 1517 if (error) 1518 dev_err(&dev->dev, 1519 "unable to preallocate PCI Express save buffer\n"); 1520 1521 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16)); 1522 if (error) 1523 dev_err(&dev->dev, 1524 "unable to preallocate PCI-X save buffer\n"); 1525 } 1526 1527 /** 1528 * pci_enable_ari - enable ARI forwarding if hardware support it 1529 * @dev: the PCI device 1530 */ 1531 void pci_enable_ari(struct pci_dev *dev) 1532 { 1533 int pos; 1534 u32 cap; 1535 u16 ctrl; 1536 struct pci_dev *bridge; 1537 1538 if (!pci_is_pcie(dev) || dev->devfn) 1539 return; 1540 1541 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 1542 if (!pos) 1543 return; 1544 1545 bridge = dev->bus->self; 1546 if (!bridge || !pci_is_pcie(bridge)) 1547 return; 1548 1549 pos = pci_pcie_cap(bridge); 1550 if (!pos) 1551 return; 1552 1553 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap); 1554 if (!(cap & PCI_EXP_DEVCAP2_ARI)) 1555 return; 1556 1557 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl); 1558 ctrl |= PCI_EXP_DEVCTL2_ARI; 1559 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl); 1560 1561 bridge->ari_enabled = 1; 1562 } 1563 1564 static int pci_acs_enable; 1565 1566 /** 1567 * pci_request_acs - ask for ACS to be enabled if supported 1568 */ 1569 void pci_request_acs(void) 1570 { 1571 pci_acs_enable = 1; 1572 } 1573 1574 /** 1575 * pci_enable_acs - enable ACS if hardware support it 1576 * @dev: the PCI device 1577 */ 1578 void pci_enable_acs(struct pci_dev *dev) 1579 { 1580 int pos; 1581 u16 cap; 1582 u16 ctrl; 1583 1584 if (!pci_acs_enable) 1585 return; 1586 1587 if (!pci_is_pcie(dev)) 1588 return; 1589 1590 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); 1591 if (!pos) 1592 return; 1593 1594 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); 1595 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); 1596 1597 /* Source Validation */ 1598 ctrl |= (cap & PCI_ACS_SV); 1599 1600 /* P2P Request Redirect */ 1601 ctrl |= (cap & PCI_ACS_RR); 1602 1603 /* P2P Completion Redirect */ 1604 ctrl |= (cap & PCI_ACS_CR); 1605 1606 /* Upstream Forwarding */ 1607 ctrl |= (cap & PCI_ACS_UF); 1608 1609 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); 1610 } 1611 1612 /** 1613 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge 1614 * @dev: the PCI device 1615 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD) 1616 * 1617 * Perform INTx swizzling for a device behind one level of bridge. This is 1618 * required by section 9.1 of the PCI-to-PCI bridge specification for devices 1619 * behind bridges on add-in cards. For devices with ARI enabled, the slot 1620 * number is always 0 (see the Implementation Note in section 2.2.8.1 of 1621 * the PCI Express Base Specification, Revision 2.1) 1622 */ 1623 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin) 1624 { 1625 int slot; 1626 1627 if (pci_ari_enabled(dev->bus)) 1628 slot = 0; 1629 else 1630 slot = PCI_SLOT(dev->devfn); 1631 1632 return (((pin - 1) + slot) % 4) + 1; 1633 } 1634 1635 int 1636 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) 1637 { 1638 u8 pin; 1639 1640 pin = dev->pin; 1641 if (!pin) 1642 return -1; 1643 1644 while (!pci_is_root_bus(dev->bus)) { 1645 pin = pci_swizzle_interrupt_pin(dev, pin); 1646 dev = dev->bus->self; 1647 } 1648 *bridge = dev; 1649 return pin; 1650 } 1651 1652 /** 1653 * pci_common_swizzle - swizzle INTx all the way to root bridge 1654 * @dev: the PCI device 1655 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD) 1656 * 1657 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI 1658 * bridges all the way up to a PCI root bus. 1659 */ 1660 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp) 1661 { 1662 u8 pin = *pinp; 1663 1664 while (!pci_is_root_bus(dev->bus)) { 1665 pin = pci_swizzle_interrupt_pin(dev, pin); 1666 dev = dev->bus->self; 1667 } 1668 *pinp = pin; 1669 return PCI_SLOT(dev->devfn); 1670 } 1671 1672 /** 1673 * pci_release_region - Release a PCI bar 1674 * @pdev: PCI device whose resources were previously reserved by pci_request_region 1675 * @bar: BAR to release 1676 * 1677 * Releases the PCI I/O and memory resources previously reserved by a 1678 * successful call to pci_request_region. Call this function only 1679 * after all use of the PCI regions has ceased. 1680 */ 1681 void pci_release_region(struct pci_dev *pdev, int bar) 1682 { 1683 struct pci_devres *dr; 1684 1685 if (pci_resource_len(pdev, bar) == 0) 1686 return; 1687 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) 1688 release_region(pci_resource_start(pdev, bar), 1689 pci_resource_len(pdev, bar)); 1690 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) 1691 release_mem_region(pci_resource_start(pdev, bar), 1692 pci_resource_len(pdev, bar)); 1693 1694 dr = find_pci_dr(pdev); 1695 if (dr) 1696 dr->region_mask &= ~(1 << bar); 1697 } 1698 1699 /** 1700 * __pci_request_region - Reserved PCI I/O and memory resource 1701 * @pdev: PCI device whose resources are to be reserved 1702 * @bar: BAR to be reserved 1703 * @res_name: Name to be associated with resource. 1704 * @exclusive: whether the region access is exclusive or not 1705 * 1706 * Mark the PCI region associated with PCI device @pdev BR @bar as 1707 * being reserved by owner @res_name. Do not access any 1708 * address inside the PCI regions unless this call returns 1709 * successfully. 1710 * 1711 * If @exclusive is set, then the region is marked so that userspace 1712 * is explicitly not allowed to map the resource via /dev/mem or 1713 * sysfs MMIO access. 1714 * 1715 * Returns 0 on success, or %EBUSY on error. A warning 1716 * message is also printed on failure. 1717 */ 1718 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name, 1719 int exclusive) 1720 { 1721 struct pci_devres *dr; 1722 1723 if (pci_resource_len(pdev, bar) == 0) 1724 return 0; 1725 1726 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { 1727 if (!request_region(pci_resource_start(pdev, bar), 1728 pci_resource_len(pdev, bar), res_name)) 1729 goto err_out; 1730 } 1731 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { 1732 if (!__request_mem_region(pci_resource_start(pdev, bar), 1733 pci_resource_len(pdev, bar), res_name, 1734 exclusive)) 1735 goto err_out; 1736 } 1737 1738 dr = find_pci_dr(pdev); 1739 if (dr) 1740 dr->region_mask |= 1 << bar; 1741 1742 return 0; 1743 1744 err_out: 1745 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar, 1746 &pdev->resource[bar]); 1747 return -EBUSY; 1748 } 1749 1750 /** 1751 * pci_request_region - Reserve PCI I/O and memory resource 1752 * @pdev: PCI device whose resources are to be reserved 1753 * @bar: BAR to be reserved 1754 * @res_name: Name to be associated with resource 1755 * 1756 * Mark the PCI region associated with PCI device @pdev BAR @bar as 1757 * being reserved by owner @res_name. Do not access any 1758 * address inside the PCI regions unless this call returns 1759 * successfully. 1760 * 1761 * Returns 0 on success, or %EBUSY on error. A warning 1762 * message is also printed on failure. 1763 */ 1764 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name) 1765 { 1766 return __pci_request_region(pdev, bar, res_name, 0); 1767 } 1768 1769 /** 1770 * pci_request_region_exclusive - Reserved PCI I/O and memory resource 1771 * @pdev: PCI device whose resources are to be reserved 1772 * @bar: BAR to be reserved 1773 * @res_name: Name to be associated with resource. 1774 * 1775 * Mark the PCI region associated with PCI device @pdev BR @bar as 1776 * being reserved by owner @res_name. Do not access any 1777 * address inside the PCI regions unless this call returns 1778 * successfully. 1779 * 1780 * Returns 0 on success, or %EBUSY on error. A warning 1781 * message is also printed on failure. 1782 * 1783 * The key difference that _exclusive makes it that userspace is 1784 * explicitly not allowed to map the resource via /dev/mem or 1785 * sysfs. 1786 */ 1787 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name) 1788 { 1789 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE); 1790 } 1791 /** 1792 * pci_release_selected_regions - Release selected PCI I/O and memory resources 1793 * @pdev: PCI device whose resources were previously reserved 1794 * @bars: Bitmask of BARs to be released 1795 * 1796 * Release selected PCI I/O and memory resources previously reserved. 1797 * Call this function only after all use of the PCI regions has ceased. 1798 */ 1799 void pci_release_selected_regions(struct pci_dev *pdev, int bars) 1800 { 1801 int i; 1802 1803 for (i = 0; i < 6; i++) 1804 if (bars & (1 << i)) 1805 pci_release_region(pdev, i); 1806 } 1807 1808 int __pci_request_selected_regions(struct pci_dev *pdev, int bars, 1809 const char *res_name, int excl) 1810 { 1811 int i; 1812 1813 for (i = 0; i < 6; i++) 1814 if (bars & (1 << i)) 1815 if (__pci_request_region(pdev, i, res_name, excl)) 1816 goto err_out; 1817 return 0; 1818 1819 err_out: 1820 while(--i >= 0) 1821 if (bars & (1 << i)) 1822 pci_release_region(pdev, i); 1823 1824 return -EBUSY; 1825 } 1826 1827 1828 /** 1829 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources 1830 * @pdev: PCI device whose resources are to be reserved 1831 * @bars: Bitmask of BARs to be requested 1832 * @res_name: Name to be associated with resource 1833 */ 1834 int pci_request_selected_regions(struct pci_dev *pdev, int bars, 1835 const char *res_name) 1836 { 1837 return __pci_request_selected_regions(pdev, bars, res_name, 0); 1838 } 1839 1840 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, 1841 int bars, const char *res_name) 1842 { 1843 return __pci_request_selected_regions(pdev, bars, res_name, 1844 IORESOURCE_EXCLUSIVE); 1845 } 1846 1847 /** 1848 * pci_release_regions - Release reserved PCI I/O and memory resources 1849 * @pdev: PCI device whose resources were previously reserved by pci_request_regions 1850 * 1851 * Releases all PCI I/O and memory resources previously reserved by a 1852 * successful call to pci_request_regions. Call this function only 1853 * after all use of the PCI regions has ceased. 1854 */ 1855 1856 void pci_release_regions(struct pci_dev *pdev) 1857 { 1858 pci_release_selected_regions(pdev, (1 << 6) - 1); 1859 } 1860 1861 /** 1862 * pci_request_regions - Reserved PCI I/O and memory resources 1863 * @pdev: PCI device whose resources are to be reserved 1864 * @res_name: Name to be associated with resource. 1865 * 1866 * Mark all PCI regions associated with PCI device @pdev as 1867 * being reserved by owner @res_name. Do not access any 1868 * address inside the PCI regions unless this call returns 1869 * successfully. 1870 * 1871 * Returns 0 on success, or %EBUSY on error. A warning 1872 * message is also printed on failure. 1873 */ 1874 int pci_request_regions(struct pci_dev *pdev, const char *res_name) 1875 { 1876 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name); 1877 } 1878 1879 /** 1880 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources 1881 * @pdev: PCI device whose resources are to be reserved 1882 * @res_name: Name to be associated with resource. 1883 * 1884 * Mark all PCI regions associated with PCI device @pdev as 1885 * being reserved by owner @res_name. Do not access any 1886 * address inside the PCI regions unless this call returns 1887 * successfully. 1888 * 1889 * pci_request_regions_exclusive() will mark the region so that 1890 * /dev/mem and the sysfs MMIO access will not be allowed. 1891 * 1892 * Returns 0 on success, or %EBUSY on error. A warning 1893 * message is also printed on failure. 1894 */ 1895 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name) 1896 { 1897 return pci_request_selected_regions_exclusive(pdev, 1898 ((1 << 6) - 1), res_name); 1899 } 1900 1901 static void __pci_set_master(struct pci_dev *dev, bool enable) 1902 { 1903 u16 old_cmd, cmd; 1904 1905 pci_read_config_word(dev, PCI_COMMAND, &old_cmd); 1906 if (enable) 1907 cmd = old_cmd | PCI_COMMAND_MASTER; 1908 else 1909 cmd = old_cmd & ~PCI_COMMAND_MASTER; 1910 if (cmd != old_cmd) { 1911 dev_dbg(&dev->dev, "%s bus mastering\n", 1912 enable ? "enabling" : "disabling"); 1913 pci_write_config_word(dev, PCI_COMMAND, cmd); 1914 } 1915 dev->is_busmaster = enable; 1916 } 1917 1918 /** 1919 * pci_set_master - enables bus-mastering for device dev 1920 * @dev: the PCI device to enable 1921 * 1922 * Enables bus-mastering on the device and calls pcibios_set_master() 1923 * to do the needed arch specific settings. 1924 */ 1925 void pci_set_master(struct pci_dev *dev) 1926 { 1927 __pci_set_master(dev, true); 1928 pcibios_set_master(dev); 1929 } 1930 1931 /** 1932 * pci_clear_master - disables bus-mastering for device dev 1933 * @dev: the PCI device to disable 1934 */ 1935 void pci_clear_master(struct pci_dev *dev) 1936 { 1937 __pci_set_master(dev, false); 1938 } 1939 1940 /** 1941 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed 1942 * @dev: the PCI device for which MWI is to be enabled 1943 * 1944 * Helper function for pci_set_mwi. 1945 * Originally copied from drivers/net/acenic.c. 1946 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. 1947 * 1948 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 1949 */ 1950 int pci_set_cacheline_size(struct pci_dev *dev) 1951 { 1952 u8 cacheline_size; 1953 1954 if (!pci_cache_line_size) 1955 return -EINVAL; 1956 1957 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be 1958 equal to or multiple of the right value. */ 1959 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1960 if (cacheline_size >= pci_cache_line_size && 1961 (cacheline_size % pci_cache_line_size) == 0) 1962 return 0; 1963 1964 /* Write the correct value. */ 1965 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); 1966 /* Read it back. */ 1967 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); 1968 if (cacheline_size == pci_cache_line_size) 1969 return 0; 1970 1971 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not " 1972 "supported\n", pci_cache_line_size << 2); 1973 1974 return -EINVAL; 1975 } 1976 EXPORT_SYMBOL_GPL(pci_set_cacheline_size); 1977 1978 #ifdef PCI_DISABLE_MWI 1979 int pci_set_mwi(struct pci_dev *dev) 1980 { 1981 return 0; 1982 } 1983 1984 int pci_try_set_mwi(struct pci_dev *dev) 1985 { 1986 return 0; 1987 } 1988 1989 void pci_clear_mwi(struct pci_dev *dev) 1990 { 1991 } 1992 1993 #else 1994 1995 /** 1996 * pci_set_mwi - enables memory-write-invalidate PCI transaction 1997 * @dev: the PCI device for which MWI is enabled 1998 * 1999 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2000 * 2001 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2002 */ 2003 int 2004 pci_set_mwi(struct pci_dev *dev) 2005 { 2006 int rc; 2007 u16 cmd; 2008 2009 rc = pci_set_cacheline_size(dev); 2010 if (rc) 2011 return rc; 2012 2013 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2014 if (! (cmd & PCI_COMMAND_INVALIDATE)) { 2015 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n"); 2016 cmd |= PCI_COMMAND_INVALIDATE; 2017 pci_write_config_word(dev, PCI_COMMAND, cmd); 2018 } 2019 2020 return 0; 2021 } 2022 2023 /** 2024 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction 2025 * @dev: the PCI device for which MWI is enabled 2026 * 2027 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND. 2028 * Callers are not required to check the return value. 2029 * 2030 * RETURNS: An appropriate -ERRNO error value on error, or zero for success. 2031 */ 2032 int pci_try_set_mwi(struct pci_dev *dev) 2033 { 2034 int rc = pci_set_mwi(dev); 2035 return rc; 2036 } 2037 2038 /** 2039 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev 2040 * @dev: the PCI device to disable 2041 * 2042 * Disables PCI Memory-Write-Invalidate transaction on the device 2043 */ 2044 void 2045 pci_clear_mwi(struct pci_dev *dev) 2046 { 2047 u16 cmd; 2048 2049 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2050 if (cmd & PCI_COMMAND_INVALIDATE) { 2051 cmd &= ~PCI_COMMAND_INVALIDATE; 2052 pci_write_config_word(dev, PCI_COMMAND, cmd); 2053 } 2054 } 2055 #endif /* ! PCI_DISABLE_MWI */ 2056 2057 /** 2058 * pci_intx - enables/disables PCI INTx for device dev 2059 * @pdev: the PCI device to operate on 2060 * @enable: boolean: whether to enable or disable PCI INTx 2061 * 2062 * Enables/disables PCI INTx for device dev 2063 */ 2064 void 2065 pci_intx(struct pci_dev *pdev, int enable) 2066 { 2067 u16 pci_command, new; 2068 2069 pci_read_config_word(pdev, PCI_COMMAND, &pci_command); 2070 2071 if (enable) { 2072 new = pci_command & ~PCI_COMMAND_INTX_DISABLE; 2073 } else { 2074 new = pci_command | PCI_COMMAND_INTX_DISABLE; 2075 } 2076 2077 if (new != pci_command) { 2078 struct pci_devres *dr; 2079 2080 pci_write_config_word(pdev, PCI_COMMAND, new); 2081 2082 dr = find_pci_dr(pdev); 2083 if (dr && !dr->restore_intx) { 2084 dr->restore_intx = 1; 2085 dr->orig_intx = !enable; 2086 } 2087 } 2088 } 2089 2090 /** 2091 * pci_msi_off - disables any msi or msix capabilities 2092 * @dev: the PCI device to operate on 2093 * 2094 * If you want to use msi see pci_enable_msi and friends. 2095 * This is a lower level primitive that allows us to disable 2096 * msi operation at the device level. 2097 */ 2098 void pci_msi_off(struct pci_dev *dev) 2099 { 2100 int pos; 2101 u16 control; 2102 2103 pos = pci_find_capability(dev, PCI_CAP_ID_MSI); 2104 if (pos) { 2105 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control); 2106 control &= ~PCI_MSI_FLAGS_ENABLE; 2107 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control); 2108 } 2109 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX); 2110 if (pos) { 2111 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control); 2112 control &= ~PCI_MSIX_FLAGS_ENABLE; 2113 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control); 2114 } 2115 } 2116 2117 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK 2118 /* 2119 * These can be overridden by arch-specific implementations 2120 */ 2121 int 2122 pci_set_dma_mask(struct pci_dev *dev, u64 mask) 2123 { 2124 if (!pci_dma_supported(dev, mask)) 2125 return -EIO; 2126 2127 dev->dma_mask = mask; 2128 dev_dbg(&dev->dev, "using %dbit DMA mask\n", fls64(mask)); 2129 2130 return 0; 2131 } 2132 2133 int 2134 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) 2135 { 2136 if (!pci_dma_supported(dev, mask)) 2137 return -EIO; 2138 2139 dev->dev.coherent_dma_mask = mask; 2140 dev_dbg(&dev->dev, "using %dbit consistent DMA mask\n", fls64(mask)); 2141 2142 return 0; 2143 } 2144 #endif 2145 2146 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE 2147 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size) 2148 { 2149 return dma_set_max_seg_size(&dev->dev, size); 2150 } 2151 EXPORT_SYMBOL(pci_set_dma_max_seg_size); 2152 #endif 2153 2154 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY 2155 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask) 2156 { 2157 return dma_set_seg_boundary(&dev->dev, mask); 2158 } 2159 EXPORT_SYMBOL(pci_set_dma_seg_boundary); 2160 #endif 2161 2162 static int pcie_flr(struct pci_dev *dev, int probe) 2163 { 2164 int i; 2165 int pos; 2166 u32 cap; 2167 u16 status, control; 2168 2169 pos = pci_pcie_cap(dev); 2170 if (!pos) 2171 return -ENOTTY; 2172 2173 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap); 2174 if (!(cap & PCI_EXP_DEVCAP_FLR)) 2175 return -ENOTTY; 2176 2177 if (probe) 2178 return 0; 2179 2180 /* Wait for Transaction Pending bit clean */ 2181 for (i = 0; i < 4; i++) { 2182 if (i) 2183 msleep((1 << (i - 1)) * 100); 2184 2185 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status); 2186 if (!(status & PCI_EXP_DEVSTA_TRPND)) 2187 goto clear; 2188 } 2189 2190 dev_err(&dev->dev, "transaction is not cleared; " 2191 "proceeding with reset anyway\n"); 2192 2193 clear: 2194 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control); 2195 control |= PCI_EXP_DEVCTL_BCR_FLR; 2196 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, control); 2197 2198 msleep(100); 2199 2200 return 0; 2201 } 2202 2203 static int pci_af_flr(struct pci_dev *dev, int probe) 2204 { 2205 int i; 2206 int pos; 2207 u8 cap; 2208 u8 status; 2209 2210 pos = pci_find_capability(dev, PCI_CAP_ID_AF); 2211 if (!pos) 2212 return -ENOTTY; 2213 2214 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap); 2215 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 2216 return -ENOTTY; 2217 2218 if (probe) 2219 return 0; 2220 2221 /* Wait for Transaction Pending bit clean */ 2222 for (i = 0; i < 4; i++) { 2223 if (i) 2224 msleep((1 << (i - 1)) * 100); 2225 2226 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status); 2227 if (!(status & PCI_AF_STATUS_TP)) 2228 goto clear; 2229 } 2230 2231 dev_err(&dev->dev, "transaction is not cleared; " 2232 "proceeding with reset anyway\n"); 2233 2234 clear: 2235 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); 2236 msleep(100); 2237 2238 return 0; 2239 } 2240 2241 static int pci_pm_reset(struct pci_dev *dev, int probe) 2242 { 2243 u16 csr; 2244 2245 if (!dev->pm_cap) 2246 return -ENOTTY; 2247 2248 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); 2249 if (csr & PCI_PM_CTRL_NO_SOFT_RESET) 2250 return -ENOTTY; 2251 2252 if (probe) 2253 return 0; 2254 2255 if (dev->current_state != PCI_D0) 2256 return -EINVAL; 2257 2258 csr &= ~PCI_PM_CTRL_STATE_MASK; 2259 csr |= PCI_D3hot; 2260 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2261 pci_dev_d3_sleep(dev); 2262 2263 csr &= ~PCI_PM_CTRL_STATE_MASK; 2264 csr |= PCI_D0; 2265 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); 2266 pci_dev_d3_sleep(dev); 2267 2268 return 0; 2269 } 2270 2271 static int pci_parent_bus_reset(struct pci_dev *dev, int probe) 2272 { 2273 u16 ctrl; 2274 struct pci_dev *pdev; 2275 2276 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self) 2277 return -ENOTTY; 2278 2279 list_for_each_entry(pdev, &dev->bus->devices, bus_list) 2280 if (pdev != dev) 2281 return -ENOTTY; 2282 2283 if (probe) 2284 return 0; 2285 2286 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl); 2287 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 2288 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2289 msleep(100); 2290 2291 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 2292 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl); 2293 msleep(100); 2294 2295 return 0; 2296 } 2297 2298 static int pci_dev_reset(struct pci_dev *dev, int probe) 2299 { 2300 int rc; 2301 2302 might_sleep(); 2303 2304 if (!probe) { 2305 pci_block_user_cfg_access(dev); 2306 /* block PM suspend, driver probe, etc. */ 2307 down(&dev->dev.sem); 2308 } 2309 2310 rc = pci_dev_specific_reset(dev, probe); 2311 if (rc != -ENOTTY) 2312 goto done; 2313 2314 rc = pcie_flr(dev, probe); 2315 if (rc != -ENOTTY) 2316 goto done; 2317 2318 rc = pci_af_flr(dev, probe); 2319 if (rc != -ENOTTY) 2320 goto done; 2321 2322 rc = pci_pm_reset(dev, probe); 2323 if (rc != -ENOTTY) 2324 goto done; 2325 2326 rc = pci_parent_bus_reset(dev, probe); 2327 done: 2328 if (!probe) { 2329 up(&dev->dev.sem); 2330 pci_unblock_user_cfg_access(dev); 2331 } 2332 2333 return rc; 2334 } 2335 2336 /** 2337 * __pci_reset_function - reset a PCI device function 2338 * @dev: PCI device to reset 2339 * 2340 * Some devices allow an individual function to be reset without affecting 2341 * other functions in the same device. The PCI device must be responsive 2342 * to PCI config space in order to use this function. 2343 * 2344 * The device function is presumed to be unused when this function is called. 2345 * Resetting the device will make the contents of PCI configuration space 2346 * random, so any caller of this must be prepared to reinitialise the 2347 * device including MSI, bus mastering, BARs, decoding IO and memory spaces, 2348 * etc. 2349 * 2350 * Returns 0 if the device function was successfully reset or negative if the 2351 * device doesn't support resetting a single function. 2352 */ 2353 int __pci_reset_function(struct pci_dev *dev) 2354 { 2355 return pci_dev_reset(dev, 0); 2356 } 2357 EXPORT_SYMBOL_GPL(__pci_reset_function); 2358 2359 /** 2360 * pci_probe_reset_function - check whether the device can be safely reset 2361 * @dev: PCI device to reset 2362 * 2363 * Some devices allow an individual function to be reset without affecting 2364 * other functions in the same device. The PCI device must be responsive 2365 * to PCI config space in order to use this function. 2366 * 2367 * Returns 0 if the device function can be reset or negative if the 2368 * device doesn't support resetting a single function. 2369 */ 2370 int pci_probe_reset_function(struct pci_dev *dev) 2371 { 2372 return pci_dev_reset(dev, 1); 2373 } 2374 2375 /** 2376 * pci_reset_function - quiesce and reset a PCI device function 2377 * @dev: PCI device to reset 2378 * 2379 * Some devices allow an individual function to be reset without affecting 2380 * other functions in the same device. The PCI device must be responsive 2381 * to PCI config space in order to use this function. 2382 * 2383 * This function does not just reset the PCI portion of a device, but 2384 * clears all the state associated with the device. This function differs 2385 * from __pci_reset_function in that it saves and restores device state 2386 * over the reset. 2387 * 2388 * Returns 0 if the device function was successfully reset or negative if the 2389 * device doesn't support resetting a single function. 2390 */ 2391 int pci_reset_function(struct pci_dev *dev) 2392 { 2393 int rc; 2394 2395 rc = pci_dev_reset(dev, 1); 2396 if (rc) 2397 return rc; 2398 2399 pci_save_state(dev); 2400 2401 /* 2402 * both INTx and MSI are disabled after the Interrupt Disable bit 2403 * is set and the Bus Master bit is cleared. 2404 */ 2405 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE); 2406 2407 rc = pci_dev_reset(dev, 0); 2408 2409 pci_restore_state(dev); 2410 2411 return rc; 2412 } 2413 EXPORT_SYMBOL_GPL(pci_reset_function); 2414 2415 /** 2416 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count 2417 * @dev: PCI device to query 2418 * 2419 * Returns mmrbc: maximum designed memory read count in bytes 2420 * or appropriate error value. 2421 */ 2422 int pcix_get_max_mmrbc(struct pci_dev *dev) 2423 { 2424 int err, cap; 2425 u32 stat; 2426 2427 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2428 if (!cap) 2429 return -EINVAL; 2430 2431 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 2432 if (err) 2433 return -EINVAL; 2434 2435 return (stat & PCI_X_STATUS_MAX_READ) >> 12; 2436 } 2437 EXPORT_SYMBOL(pcix_get_max_mmrbc); 2438 2439 /** 2440 * pcix_get_mmrbc - get PCI-X maximum memory read byte count 2441 * @dev: PCI device to query 2442 * 2443 * Returns mmrbc: maximum memory read count in bytes 2444 * or appropriate error value. 2445 */ 2446 int pcix_get_mmrbc(struct pci_dev *dev) 2447 { 2448 int ret, cap; 2449 u32 cmd; 2450 2451 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2452 if (!cap) 2453 return -EINVAL; 2454 2455 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 2456 if (!ret) 2457 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2); 2458 2459 return ret; 2460 } 2461 EXPORT_SYMBOL(pcix_get_mmrbc); 2462 2463 /** 2464 * pcix_set_mmrbc - set PCI-X maximum memory read byte count 2465 * @dev: PCI device to query 2466 * @mmrbc: maximum memory read count in bytes 2467 * valid values are 512, 1024, 2048, 4096 2468 * 2469 * If possible sets maximum memory read byte count, some bridges have erratas 2470 * that prevent this. 2471 */ 2472 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) 2473 { 2474 int cap, err = -EINVAL; 2475 u32 stat, cmd, v, o; 2476 2477 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc)) 2478 goto out; 2479 2480 v = ffs(mmrbc) - 10; 2481 2482 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 2483 if (!cap) 2484 goto out; 2485 2486 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat); 2487 if (err) 2488 goto out; 2489 2490 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21) 2491 return -E2BIG; 2492 2493 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd); 2494 if (err) 2495 goto out; 2496 2497 o = (cmd & PCI_X_CMD_MAX_READ) >> 2; 2498 if (o != v) { 2499 if (v > o && dev->bus && 2500 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) 2501 return -EIO; 2502 2503 cmd &= ~PCI_X_CMD_MAX_READ; 2504 cmd |= v << 2; 2505 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd); 2506 } 2507 out: 2508 return err; 2509 } 2510 EXPORT_SYMBOL(pcix_set_mmrbc); 2511 2512 /** 2513 * pcie_get_readrq - get PCI Express read request size 2514 * @dev: PCI device to query 2515 * 2516 * Returns maximum memory read request in bytes 2517 * or appropriate error value. 2518 */ 2519 int pcie_get_readrq(struct pci_dev *dev) 2520 { 2521 int ret, cap; 2522 u16 ctl; 2523 2524 cap = pci_pcie_cap(dev); 2525 if (!cap) 2526 return -EINVAL; 2527 2528 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 2529 if (!ret) 2530 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12); 2531 2532 return ret; 2533 } 2534 EXPORT_SYMBOL(pcie_get_readrq); 2535 2536 /** 2537 * pcie_set_readrq - set PCI Express maximum memory read request 2538 * @dev: PCI device to query 2539 * @rq: maximum memory read count in bytes 2540 * valid values are 128, 256, 512, 1024, 2048, 4096 2541 * 2542 * If possible sets maximum read byte count 2543 */ 2544 int pcie_set_readrq(struct pci_dev *dev, int rq) 2545 { 2546 int cap, err = -EINVAL; 2547 u16 ctl, v; 2548 2549 if (rq < 128 || rq > 4096 || !is_power_of_2(rq)) 2550 goto out; 2551 2552 v = (ffs(rq) - 8) << 12; 2553 2554 cap = pci_pcie_cap(dev); 2555 if (!cap) 2556 goto out; 2557 2558 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl); 2559 if (err) 2560 goto out; 2561 2562 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) { 2563 ctl &= ~PCI_EXP_DEVCTL_READRQ; 2564 ctl |= v; 2565 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl); 2566 } 2567 2568 out: 2569 return err; 2570 } 2571 EXPORT_SYMBOL(pcie_set_readrq); 2572 2573 /** 2574 * pci_select_bars - Make BAR mask from the type of resource 2575 * @dev: the PCI device for which BAR mask is made 2576 * @flags: resource type mask to be selected 2577 * 2578 * This helper routine makes bar mask from the type of resource. 2579 */ 2580 int pci_select_bars(struct pci_dev *dev, unsigned long flags) 2581 { 2582 int i, bars = 0; 2583 for (i = 0; i < PCI_NUM_RESOURCES; i++) 2584 if (pci_resource_flags(dev, i) & flags) 2585 bars |= (1 << i); 2586 return bars; 2587 } 2588 2589 /** 2590 * pci_resource_bar - get position of the BAR associated with a resource 2591 * @dev: the PCI device 2592 * @resno: the resource number 2593 * @type: the BAR type to be filled in 2594 * 2595 * Returns BAR position in config space, or 0 if the BAR is invalid. 2596 */ 2597 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type) 2598 { 2599 int reg; 2600 2601 if (resno < PCI_ROM_RESOURCE) { 2602 *type = pci_bar_unknown; 2603 return PCI_BASE_ADDRESS_0 + 4 * resno; 2604 } else if (resno == PCI_ROM_RESOURCE) { 2605 *type = pci_bar_mem32; 2606 return dev->rom_base_reg; 2607 } else if (resno < PCI_BRIDGE_RESOURCES) { 2608 /* device specific resource */ 2609 reg = pci_iov_resource_bar(dev, resno, type); 2610 if (reg) 2611 return reg; 2612 } 2613 2614 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno); 2615 return 0; 2616 } 2617 2618 /** 2619 * pci_set_vga_state - set VGA decode state on device and parents if requested 2620 * @dev: the PCI device 2621 * @decode: true = enable decoding, false = disable decoding 2622 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY 2623 * @change_bridge: traverse ancestors and change bridges 2624 */ 2625 int pci_set_vga_state(struct pci_dev *dev, bool decode, 2626 unsigned int command_bits, bool change_bridge) 2627 { 2628 struct pci_bus *bus; 2629 struct pci_dev *bridge; 2630 u16 cmd; 2631 2632 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)); 2633 2634 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2635 if (decode == true) 2636 cmd |= command_bits; 2637 else 2638 cmd &= ~command_bits; 2639 pci_write_config_word(dev, PCI_COMMAND, cmd); 2640 2641 if (change_bridge == false) 2642 return 0; 2643 2644 bus = dev->bus; 2645 while (bus) { 2646 bridge = bus->self; 2647 if (bridge) { 2648 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, 2649 &cmd); 2650 if (decode == true) 2651 cmd |= PCI_BRIDGE_CTL_VGA; 2652 else 2653 cmd &= ~PCI_BRIDGE_CTL_VGA; 2654 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, 2655 cmd); 2656 } 2657 bus = bus->parent; 2658 } 2659 return 0; 2660 } 2661 2662 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE 2663 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0}; 2664 static DEFINE_SPINLOCK(resource_alignment_lock); 2665 2666 /** 2667 * pci_specified_resource_alignment - get resource alignment specified by user. 2668 * @dev: the PCI device to get 2669 * 2670 * RETURNS: Resource alignment if it is specified. 2671 * Zero if it is not specified. 2672 */ 2673 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev) 2674 { 2675 int seg, bus, slot, func, align_order, count; 2676 resource_size_t align = 0; 2677 char *p; 2678 2679 spin_lock(&resource_alignment_lock); 2680 p = resource_alignment_param; 2681 while (*p) { 2682 count = 0; 2683 if (sscanf(p, "%d%n", &align_order, &count) == 1 && 2684 p[count] == '@') { 2685 p += count + 1; 2686 } else { 2687 align_order = -1; 2688 } 2689 if (sscanf(p, "%x:%x:%x.%x%n", 2690 &seg, &bus, &slot, &func, &count) != 4) { 2691 seg = 0; 2692 if (sscanf(p, "%x:%x.%x%n", 2693 &bus, &slot, &func, &count) != 3) { 2694 /* Invalid format */ 2695 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n", 2696 p); 2697 break; 2698 } 2699 } 2700 p += count; 2701 if (seg == pci_domain_nr(dev->bus) && 2702 bus == dev->bus->number && 2703 slot == PCI_SLOT(dev->devfn) && 2704 func == PCI_FUNC(dev->devfn)) { 2705 if (align_order == -1) { 2706 align = PAGE_SIZE; 2707 } else { 2708 align = 1 << align_order; 2709 } 2710 /* Found */ 2711 break; 2712 } 2713 if (*p != ';' && *p != ',') { 2714 /* End of param or invalid format */ 2715 break; 2716 } 2717 p++; 2718 } 2719 spin_unlock(&resource_alignment_lock); 2720 return align; 2721 } 2722 2723 /** 2724 * pci_is_reassigndev - check if specified PCI is target device to reassign 2725 * @dev: the PCI device to check 2726 * 2727 * RETURNS: non-zero for PCI device is a target device to reassign, 2728 * or zero is not. 2729 */ 2730 int pci_is_reassigndev(struct pci_dev *dev) 2731 { 2732 return (pci_specified_resource_alignment(dev) != 0); 2733 } 2734 2735 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count) 2736 { 2737 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1) 2738 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1; 2739 spin_lock(&resource_alignment_lock); 2740 strncpy(resource_alignment_param, buf, count); 2741 resource_alignment_param[count] = '\0'; 2742 spin_unlock(&resource_alignment_lock); 2743 return count; 2744 } 2745 2746 ssize_t pci_get_resource_alignment_param(char *buf, size_t size) 2747 { 2748 size_t count; 2749 spin_lock(&resource_alignment_lock); 2750 count = snprintf(buf, size, "%s", resource_alignment_param); 2751 spin_unlock(&resource_alignment_lock); 2752 return count; 2753 } 2754 2755 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf) 2756 { 2757 return pci_get_resource_alignment_param(buf, PAGE_SIZE); 2758 } 2759 2760 static ssize_t pci_resource_alignment_store(struct bus_type *bus, 2761 const char *buf, size_t count) 2762 { 2763 return pci_set_resource_alignment_param(buf, count); 2764 } 2765 2766 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show, 2767 pci_resource_alignment_store); 2768 2769 static int __init pci_resource_alignment_sysfs_init(void) 2770 { 2771 return bus_create_file(&pci_bus_type, 2772 &bus_attr_resource_alignment); 2773 } 2774 2775 late_initcall(pci_resource_alignment_sysfs_init); 2776 2777 static void __devinit pci_no_domains(void) 2778 { 2779 #ifdef CONFIG_PCI_DOMAINS 2780 pci_domains_supported = 0; 2781 #endif 2782 } 2783 2784 /** 2785 * pci_ext_cfg_enabled - can we access extended PCI config space? 2786 * @dev: The PCI device of the root bridge. 2787 * 2788 * Returns 1 if we can access PCI extended config space (offsets 2789 * greater than 0xff). This is the default implementation. Architecture 2790 * implementations can override this. 2791 */ 2792 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev) 2793 { 2794 return 1; 2795 } 2796 2797 void __weak pci_fixup_cardbus(struct pci_bus *bus) 2798 { 2799 } 2800 EXPORT_SYMBOL(pci_fixup_cardbus); 2801 2802 static int __init pci_setup(char *str) 2803 { 2804 while (str) { 2805 char *k = strchr(str, ','); 2806 if (k) 2807 *k++ = 0; 2808 if (*str && (str = pcibios_setup(str)) && *str) { 2809 if (!strcmp(str, "nomsi")) { 2810 pci_no_msi(); 2811 } else if (!strcmp(str, "noaer")) { 2812 pci_no_aer(); 2813 } else if (!strcmp(str, "nodomains")) { 2814 pci_no_domains(); 2815 } else if (!strncmp(str, "cbiosize=", 9)) { 2816 pci_cardbus_io_size = memparse(str + 9, &str); 2817 } else if (!strncmp(str, "cbmemsize=", 10)) { 2818 pci_cardbus_mem_size = memparse(str + 10, &str); 2819 } else if (!strncmp(str, "resource_alignment=", 19)) { 2820 pci_set_resource_alignment_param(str + 19, 2821 strlen(str + 19)); 2822 } else if (!strncmp(str, "ecrc=", 5)) { 2823 pcie_ecrc_get_policy(str + 5); 2824 } else if (!strncmp(str, "hpiosize=", 9)) { 2825 pci_hotplug_io_size = memparse(str + 9, &str); 2826 } else if (!strncmp(str, "hpmemsize=", 10)) { 2827 pci_hotplug_mem_size = memparse(str + 10, &str); 2828 } else { 2829 printk(KERN_ERR "PCI: Unknown option `%s'\n", 2830 str); 2831 } 2832 } 2833 str = k; 2834 } 2835 return 0; 2836 } 2837 early_param("pci", pci_setup); 2838 2839 EXPORT_SYMBOL(pci_reenable_device); 2840 EXPORT_SYMBOL(pci_enable_device_io); 2841 EXPORT_SYMBOL(pci_enable_device_mem); 2842 EXPORT_SYMBOL(pci_enable_device); 2843 EXPORT_SYMBOL(pcim_enable_device); 2844 EXPORT_SYMBOL(pcim_pin_device); 2845 EXPORT_SYMBOL(pci_disable_device); 2846 EXPORT_SYMBOL(pci_find_capability); 2847 EXPORT_SYMBOL(pci_bus_find_capability); 2848 EXPORT_SYMBOL(pci_release_regions); 2849 EXPORT_SYMBOL(pci_request_regions); 2850 EXPORT_SYMBOL(pci_request_regions_exclusive); 2851 EXPORT_SYMBOL(pci_release_region); 2852 EXPORT_SYMBOL(pci_request_region); 2853 EXPORT_SYMBOL(pci_request_region_exclusive); 2854 EXPORT_SYMBOL(pci_release_selected_regions); 2855 EXPORT_SYMBOL(pci_request_selected_regions); 2856 EXPORT_SYMBOL(pci_request_selected_regions_exclusive); 2857 EXPORT_SYMBOL(pci_set_master); 2858 EXPORT_SYMBOL(pci_clear_master); 2859 EXPORT_SYMBOL(pci_set_mwi); 2860 EXPORT_SYMBOL(pci_try_set_mwi); 2861 EXPORT_SYMBOL(pci_clear_mwi); 2862 EXPORT_SYMBOL_GPL(pci_intx); 2863 EXPORT_SYMBOL(pci_set_dma_mask); 2864 EXPORT_SYMBOL(pci_set_consistent_dma_mask); 2865 EXPORT_SYMBOL(pci_assign_resource); 2866 EXPORT_SYMBOL(pci_find_parent_resource); 2867 EXPORT_SYMBOL(pci_select_bars); 2868 2869 EXPORT_SYMBOL(pci_set_power_state); 2870 EXPORT_SYMBOL(pci_save_state); 2871 EXPORT_SYMBOL(pci_restore_state); 2872 EXPORT_SYMBOL(pci_pme_capable); 2873 EXPORT_SYMBOL(pci_pme_active); 2874 EXPORT_SYMBOL(pci_enable_wake); 2875 EXPORT_SYMBOL(pci_wake_from_d3); 2876 EXPORT_SYMBOL(pci_target_state); 2877 EXPORT_SYMBOL(pci_prepare_to_sleep); 2878 EXPORT_SYMBOL(pci_back_from_sleep); 2879 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state); 2880 2881