1407d1a51SLizhi Hou // SPDX-License-Identifier: GPL-2.0+
2407d1a51SLizhi Hou /*
3407d1a51SLizhi Hou * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
4407d1a51SLizhi Hou */
5407d1a51SLizhi Hou
6407d1a51SLizhi Hou #include <linux/pci.h>
7407d1a51SLizhi Hou #include <linux/of.h>
8407d1a51SLizhi Hou #include <linux/of_irq.h>
9407d1a51SLizhi Hou #include <linux/bitfield.h>
10407d1a51SLizhi Hou #include <linux/bits.h>
11407d1a51SLizhi Hou #include "pci.h"
12407d1a51SLizhi Hou
13407d1a51SLizhi Hou #define OF_PCI_ADDRESS_CELLS 3
14407d1a51SLizhi Hou #define OF_PCI_SIZE_CELLS 2
15407d1a51SLizhi Hou #define OF_PCI_MAX_INT_PIN 4
16407d1a51SLizhi Hou
17407d1a51SLizhi Hou struct of_pci_addr_pair {
18407d1a51SLizhi Hou u32 phys_addr[OF_PCI_ADDRESS_CELLS];
19407d1a51SLizhi Hou u32 size[OF_PCI_SIZE_CELLS];
20407d1a51SLizhi Hou };
21407d1a51SLizhi Hou
22407d1a51SLizhi Hou /*
23407d1a51SLizhi Hou * Each entry in the ranges table is a tuple containing the child address,
24407d1a51SLizhi Hou * the parent address, and the size of the region in the child address space.
25407d1a51SLizhi Hou * Thus, for PCI, in each entry parent address is an address on the primary
26407d1a51SLizhi Hou * side and the child address is the corresponding address on the secondary
27407d1a51SLizhi Hou * side.
28407d1a51SLizhi Hou */
29407d1a51SLizhi Hou struct of_pci_range {
30407d1a51SLizhi Hou u32 child_addr[OF_PCI_ADDRESS_CELLS];
31407d1a51SLizhi Hou u32 parent_addr[OF_PCI_ADDRESS_CELLS];
32407d1a51SLizhi Hou u32 size[OF_PCI_SIZE_CELLS];
33407d1a51SLizhi Hou };
34407d1a51SLizhi Hou
35407d1a51SLizhi Hou #define OF_PCI_ADDR_SPACE_IO 0x1
36407d1a51SLizhi Hou #define OF_PCI_ADDR_SPACE_MEM32 0x2
37407d1a51SLizhi Hou #define OF_PCI_ADDR_SPACE_MEM64 0x3
38407d1a51SLizhi Hou
39407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_NONRELOC BIT(31)
40407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_SS GENMASK(25, 24)
41407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_PREFETCH BIT(30)
42407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_BUS GENMASK(23, 16)
43407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_DEV GENMASK(15, 11)
44407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_FUNC GENMASK(10, 8)
45407d1a51SLizhi Hou #define OF_PCI_ADDR_FIELD_REG GENMASK(7, 0)
46407d1a51SLizhi Hou
47407d1a51SLizhi Hou enum of_pci_prop_compatible {
48407d1a51SLizhi Hou PROP_COMPAT_PCI_VVVV_DDDD,
49407d1a51SLizhi Hou PROP_COMPAT_PCICLASS_CCSSPP,
50407d1a51SLizhi Hou PROP_COMPAT_PCICLASS_CCSS,
51407d1a51SLizhi Hou PROP_COMPAT_NUM,
52407d1a51SLizhi Hou };
53407d1a51SLizhi Hou
of_pci_set_address(struct pci_dev * pdev,u32 * prop,u64 addr,u32 reg_num,u32 flags,bool reloc)54407d1a51SLizhi Hou static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr,
55407d1a51SLizhi Hou u32 reg_num, u32 flags, bool reloc)
56407d1a51SLizhi Hou {
57407d1a51SLizhi Hou prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
58407d1a51SLizhi Hou FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
59407d1a51SLizhi Hou FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
60407d1a51SLizhi Hou prop[0] |= flags | reg_num;
61407d1a51SLizhi Hou if (!reloc) {
62407d1a51SLizhi Hou prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC;
63407d1a51SLizhi Hou prop[1] = upper_32_bits(addr);
64407d1a51SLizhi Hou prop[2] = lower_32_bits(addr);
65407d1a51SLizhi Hou }
66407d1a51SLizhi Hou }
67407d1a51SLizhi Hou
of_pci_get_addr_flags(struct resource * res,u32 * flags)68407d1a51SLizhi Hou static int of_pci_get_addr_flags(struct resource *res, u32 *flags)
69407d1a51SLizhi Hou {
70407d1a51SLizhi Hou u32 ss;
71407d1a51SLizhi Hou
72407d1a51SLizhi Hou if (res->flags & IORESOURCE_IO)
73407d1a51SLizhi Hou ss = OF_PCI_ADDR_SPACE_IO;
74407d1a51SLizhi Hou else if (res->flags & IORESOURCE_MEM_64)
75407d1a51SLizhi Hou ss = OF_PCI_ADDR_SPACE_MEM64;
76407d1a51SLizhi Hou else if (res->flags & IORESOURCE_MEM)
77407d1a51SLizhi Hou ss = OF_PCI_ADDR_SPACE_MEM32;
78407d1a51SLizhi Hou else
79407d1a51SLizhi Hou return -EINVAL;
80407d1a51SLizhi Hou
81407d1a51SLizhi Hou *flags = 0;
82407d1a51SLizhi Hou if (res->flags & IORESOURCE_PREFETCH)
83407d1a51SLizhi Hou *flags |= OF_PCI_ADDR_FIELD_PREFETCH;
84407d1a51SLizhi Hou
85407d1a51SLizhi Hou *flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss);
86407d1a51SLizhi Hou
87407d1a51SLizhi Hou return 0;
88407d1a51SLizhi Hou }
89407d1a51SLizhi Hou
of_pci_prop_bus_range(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)90407d1a51SLizhi Hou static int of_pci_prop_bus_range(struct pci_dev *pdev,
91407d1a51SLizhi Hou struct of_changeset *ocs,
92407d1a51SLizhi Hou struct device_node *np)
93407d1a51SLizhi Hou {
94407d1a51SLizhi Hou u32 bus_range[] = { pdev->subordinate->busn_res.start,
95407d1a51SLizhi Hou pdev->subordinate->busn_res.end };
96407d1a51SLizhi Hou
97407d1a51SLizhi Hou return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range,
98407d1a51SLizhi Hou ARRAY_SIZE(bus_range));
99407d1a51SLizhi Hou }
100407d1a51SLizhi Hou
of_pci_prop_ranges(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)101407d1a51SLizhi Hou static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
102407d1a51SLizhi Hou struct device_node *np)
103407d1a51SLizhi Hou {
104407d1a51SLizhi Hou struct of_pci_range *rp;
105407d1a51SLizhi Hou struct resource *res;
106407d1a51SLizhi Hou int i, j, ret;
107407d1a51SLizhi Hou u32 flags, num;
108407d1a51SLizhi Hou u64 val64;
109407d1a51SLizhi Hou
110407d1a51SLizhi Hou if (pci_is_bridge(pdev)) {
111407d1a51SLizhi Hou num = PCI_BRIDGE_RESOURCE_NUM;
112407d1a51SLizhi Hou res = &pdev->resource[PCI_BRIDGE_RESOURCES];
113407d1a51SLizhi Hou } else {
114407d1a51SLizhi Hou num = PCI_STD_NUM_BARS;
115407d1a51SLizhi Hou res = &pdev->resource[PCI_STD_RESOURCES];
116407d1a51SLizhi Hou }
117407d1a51SLizhi Hou
118407d1a51SLizhi Hou rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
119407d1a51SLizhi Hou if (!rp)
120407d1a51SLizhi Hou return -ENOMEM;
121407d1a51SLizhi Hou
122407d1a51SLizhi Hou for (i = 0, j = 0; j < num; j++) {
123407d1a51SLizhi Hou if (!resource_size(&res[j]))
124407d1a51SLizhi Hou continue;
125407d1a51SLizhi Hou
126407d1a51SLizhi Hou if (of_pci_get_addr_flags(&res[j], &flags))
127407d1a51SLizhi Hou continue;
128407d1a51SLizhi Hou
129*8b404b08SAndrea della Porta val64 = pci_bus_address(pdev, &res[j] - pdev->resource);
130407d1a51SLizhi Hou of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
131407d1a51SLizhi Hou false);
132407d1a51SLizhi Hou if (pci_is_bridge(pdev)) {
133407d1a51SLizhi Hou memcpy(rp[i].child_addr, rp[i].parent_addr,
134407d1a51SLizhi Hou sizeof(rp[i].child_addr));
135407d1a51SLizhi Hou } else {
136407d1a51SLizhi Hou /*
137407d1a51SLizhi Hou * For endpoint device, the lower 64-bits of child
138407d1a51SLizhi Hou * address is always zero.
139407d1a51SLizhi Hou */
140407d1a51SLizhi Hou rp[i].child_addr[0] = j;
141407d1a51SLizhi Hou }
142407d1a51SLizhi Hou
143407d1a51SLizhi Hou val64 = resource_size(&res[j]);
144407d1a51SLizhi Hou rp[i].size[0] = upper_32_bits(val64);
145407d1a51SLizhi Hou rp[i].size[1] = lower_32_bits(val64);
146407d1a51SLizhi Hou
147407d1a51SLizhi Hou i++;
148407d1a51SLizhi Hou }
149407d1a51SLizhi Hou
150407d1a51SLizhi Hou ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp,
151407d1a51SLizhi Hou i * sizeof(*rp) / sizeof(u32));
152407d1a51SLizhi Hou kfree(rp);
153407d1a51SLizhi Hou
154407d1a51SLizhi Hou return ret;
155407d1a51SLizhi Hou }
156407d1a51SLizhi Hou
of_pci_prop_reg(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)157407d1a51SLizhi Hou static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs,
158407d1a51SLizhi Hou struct device_node *np)
159407d1a51SLizhi Hou {
160407d1a51SLizhi Hou struct of_pci_addr_pair reg = { 0 };
161407d1a51SLizhi Hou
162407d1a51SLizhi Hou /* configuration space */
163407d1a51SLizhi Hou of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true);
164407d1a51SLizhi Hou
165407d1a51SLizhi Hou return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)®,
166407d1a51SLizhi Hou sizeof(reg) / sizeof(u32));
167407d1a51SLizhi Hou }
168407d1a51SLizhi Hou
of_pci_prop_interrupts(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)169407d1a51SLizhi Hou static int of_pci_prop_interrupts(struct pci_dev *pdev,
170407d1a51SLizhi Hou struct of_changeset *ocs,
171407d1a51SLizhi Hou struct device_node *np)
172407d1a51SLizhi Hou {
173407d1a51SLizhi Hou int ret;
174407d1a51SLizhi Hou u8 pin;
175407d1a51SLizhi Hou
176407d1a51SLizhi Hou ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
177407d1a51SLizhi Hou if (ret != 0)
178407d1a51SLizhi Hou return ret;
179407d1a51SLizhi Hou
180407d1a51SLizhi Hou if (!pin)
181407d1a51SLizhi Hou return 0;
182407d1a51SLizhi Hou
183407d1a51SLizhi Hou return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin);
184407d1a51SLizhi Hou }
185407d1a51SLizhi Hou
of_pci_prop_intr_map(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)186407d1a51SLizhi Hou static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
187407d1a51SLizhi Hou struct device_node *np)
188407d1a51SLizhi Hou {
18933efa29eSLizhi Hou u32 i, addr_sz[OF_PCI_MAX_INT_PIN] = { 0 }, map_sz = 0;
190407d1a51SLizhi Hou struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
191407d1a51SLizhi Hou __be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
192407d1a51SLizhi Hou u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
193407d1a51SLizhi Hou struct device_node *pnode;
194407d1a51SLizhi Hou struct pci_dev *child;
195407d1a51SLizhi Hou u32 *int_map, *mapp;
196407d1a51SLizhi Hou int ret;
197407d1a51SLizhi Hou u8 pin;
198407d1a51SLizhi Hou
199407d1a51SLizhi Hou pnode = pci_device_to_OF_node(pdev->bus->self);
200407d1a51SLizhi Hou if (!pnode)
201407d1a51SLizhi Hou pnode = pci_bus_to_OF_node(pdev->bus);
202407d1a51SLizhi Hou
203407d1a51SLizhi Hou if (!pnode) {
204407d1a51SLizhi Hou pci_err(pdev, "failed to get parent device node");
205407d1a51SLizhi Hou return -EINVAL;
206407d1a51SLizhi Hou }
207407d1a51SLizhi Hou
208407d1a51SLizhi Hou laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
209407d1a51SLizhi Hou for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
210407d1a51SLizhi Hou i = pin - 1;
211407d1a51SLizhi Hou out_irq[i].np = pnode;
212407d1a51SLizhi Hou out_irq[i].args_count = 1;
213407d1a51SLizhi Hou out_irq[i].args[0] = pin;
214407d1a51SLizhi Hou ret = of_irq_parse_raw(laddr, &out_irq[i]);
215407d1a51SLizhi Hou if (ret) {
21633efa29eSLizhi Hou out_irq[i].np = NULL;
21733efa29eSLizhi Hou pci_dbg(pdev, "parse irq %d failed, ret %d", pin, ret);
218407d1a51SLizhi Hou continue;
219407d1a51SLizhi Hou }
22033efa29eSLizhi Hou of_property_read_u32(out_irq[i].np, "#address-cells",
221407d1a51SLizhi Hou &addr_sz[i]);
222407d1a51SLizhi Hou }
223407d1a51SLizhi Hou
224407d1a51SLizhi Hou list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
225407d1a51SLizhi Hou for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
226407d1a51SLizhi Hou i = pci_swizzle_interrupt_pin(child, pin) - 1;
22733efa29eSLizhi Hou if (!out_irq[i].np)
22833efa29eSLizhi Hou continue;
229407d1a51SLizhi Hou map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
230407d1a51SLizhi Hou }
231407d1a51SLizhi Hou }
232407d1a51SLizhi Hou
23333efa29eSLizhi Hou /*
23433efa29eSLizhi Hou * Parsing interrupt failed for all pins. In this case, it does not
23533efa29eSLizhi Hou * need to generate interrupt-map property.
23633efa29eSLizhi Hou */
23733efa29eSLizhi Hou if (!map_sz)
23833efa29eSLizhi Hou return 0;
23933efa29eSLizhi Hou
240407d1a51SLizhi Hou int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
241b5f31d14SDuoming Zhou if (!int_map)
242b5f31d14SDuoming Zhou return -ENOMEM;
243407d1a51SLizhi Hou mapp = int_map;
244407d1a51SLizhi Hou
245407d1a51SLizhi Hou list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
246407d1a51SLizhi Hou for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
24733efa29eSLizhi Hou i = pci_swizzle_interrupt_pin(child, pin) - 1;
24833efa29eSLizhi Hou if (!out_irq[i].np)
24933efa29eSLizhi Hou continue;
25033efa29eSLizhi Hou
251407d1a51SLizhi Hou *mapp = (child->bus->number << 16) |
252407d1a51SLizhi Hou (child->devfn << 8);
253407d1a51SLizhi Hou mapp += OF_PCI_ADDRESS_CELLS;
254407d1a51SLizhi Hou *mapp = pin;
255407d1a51SLizhi Hou mapp++;
256407d1a51SLizhi Hou *mapp = out_irq[i].np->phandle;
257407d1a51SLizhi Hou mapp++;
258407d1a51SLizhi Hou if (addr_sz[i]) {
259407d1a51SLizhi Hou ret = of_property_read_u32_array(out_irq[i].np,
260407d1a51SLizhi Hou "reg", mapp,
261407d1a51SLizhi Hou addr_sz[i]);
262407d1a51SLizhi Hou if (ret)
263407d1a51SLizhi Hou goto failed;
264407d1a51SLizhi Hou }
265407d1a51SLizhi Hou mapp += addr_sz[i];
266407d1a51SLizhi Hou memcpy(mapp, out_irq[i].args,
267407d1a51SLizhi Hou out_irq[i].args_count * sizeof(u32));
268407d1a51SLizhi Hou mapp += out_irq[i].args_count;
269407d1a51SLizhi Hou }
270407d1a51SLizhi Hou }
271407d1a51SLizhi Hou
272407d1a51SLizhi Hou ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map,
273407d1a51SLizhi Hou map_sz);
274407d1a51SLizhi Hou if (ret)
275407d1a51SLizhi Hou goto failed;
276407d1a51SLizhi Hou
277407d1a51SLizhi Hou ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
278407d1a51SLizhi Hou if (ret)
279407d1a51SLizhi Hou goto failed;
280407d1a51SLizhi Hou
281407d1a51SLizhi Hou ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask",
282407d1a51SLizhi Hou int_map_mask,
283407d1a51SLizhi Hou ARRAY_SIZE(int_map_mask));
284407d1a51SLizhi Hou if (ret)
285407d1a51SLizhi Hou goto failed;
286407d1a51SLizhi Hou
287407d1a51SLizhi Hou kfree(int_map);
288407d1a51SLizhi Hou return 0;
289407d1a51SLizhi Hou
290407d1a51SLizhi Hou failed:
291407d1a51SLizhi Hou kfree(int_map);
292407d1a51SLizhi Hou return ret;
293407d1a51SLizhi Hou }
294407d1a51SLizhi Hou
of_pci_prop_compatible(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)295407d1a51SLizhi Hou static int of_pci_prop_compatible(struct pci_dev *pdev,
296407d1a51SLizhi Hou struct of_changeset *ocs,
297407d1a51SLizhi Hou struct device_node *np)
298407d1a51SLizhi Hou {
299407d1a51SLizhi Hou const char *compat_strs[PROP_COMPAT_NUM] = { 0 };
300407d1a51SLizhi Hou int i, ret;
301407d1a51SLizhi Hou
302407d1a51SLizhi Hou compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] =
303407d1a51SLizhi Hou kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device);
304407d1a51SLizhi Hou compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] =
305407d1a51SLizhi Hou kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class);
306407d1a51SLizhi Hou compat_strs[PROP_COMPAT_PCICLASS_CCSS] =
307407d1a51SLizhi Hou kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8);
308407d1a51SLizhi Hou
309407d1a51SLizhi Hou ret = of_changeset_add_prop_string_array(ocs, np, "compatible",
310407d1a51SLizhi Hou compat_strs, PROP_COMPAT_NUM);
311407d1a51SLizhi Hou for (i = 0; i < PROP_COMPAT_NUM; i++)
312407d1a51SLizhi Hou kfree(compat_strs[i]);
313407d1a51SLizhi Hou
314407d1a51SLizhi Hou return ret;
315407d1a51SLizhi Hou }
316407d1a51SLizhi Hou
of_pci_add_properties(struct pci_dev * pdev,struct of_changeset * ocs,struct device_node * np)317407d1a51SLizhi Hou int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
318407d1a51SLizhi Hou struct device_node *np)
319407d1a51SLizhi Hou {
320407d1a51SLizhi Hou int ret;
321407d1a51SLizhi Hou
322407d1a51SLizhi Hou /*
323407d1a51SLizhi Hou * The added properties will be released when the
324407d1a51SLizhi Hou * changeset is destroyed.
325407d1a51SLizhi Hou */
326407d1a51SLizhi Hou if (pci_is_bridge(pdev)) {
327407d1a51SLizhi Hou ret = of_changeset_add_prop_string(ocs, np, "device_type",
328407d1a51SLizhi Hou "pci");
329407d1a51SLizhi Hou if (ret)
330407d1a51SLizhi Hou return ret;
331407d1a51SLizhi Hou
332407d1a51SLizhi Hou ret = of_pci_prop_bus_range(pdev, ocs, np);
333407d1a51SLizhi Hou if (ret)
334407d1a51SLizhi Hou return ret;
335407d1a51SLizhi Hou
336407d1a51SLizhi Hou ret = of_pci_prop_intr_map(pdev, ocs, np);
337407d1a51SLizhi Hou if (ret)
338407d1a51SLizhi Hou return ret;
339407d1a51SLizhi Hou }
340407d1a51SLizhi Hou
341407d1a51SLizhi Hou ret = of_pci_prop_ranges(pdev, ocs, np);
342407d1a51SLizhi Hou if (ret)
343407d1a51SLizhi Hou return ret;
344407d1a51SLizhi Hou
345407d1a51SLizhi Hou ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
346407d1a51SLizhi Hou OF_PCI_ADDRESS_CELLS);
347407d1a51SLizhi Hou if (ret)
348407d1a51SLizhi Hou return ret;
349407d1a51SLizhi Hou
350407d1a51SLizhi Hou ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
351407d1a51SLizhi Hou OF_PCI_SIZE_CELLS);
352407d1a51SLizhi Hou if (ret)
353407d1a51SLizhi Hou return ret;
354407d1a51SLizhi Hou
355407d1a51SLizhi Hou ret = of_pci_prop_reg(pdev, ocs, np);
356407d1a51SLizhi Hou if (ret)
357407d1a51SLizhi Hou return ret;
358407d1a51SLizhi Hou
359407d1a51SLizhi Hou ret = of_pci_prop_compatible(pdev, ocs, np);
360407d1a51SLizhi Hou if (ret)
361407d1a51SLizhi Hou return ret;
362407d1a51SLizhi Hou
363407d1a51SLizhi Hou ret = of_pci_prop_interrupts(pdev, ocs, np);
364407d1a51SLizhi Hou if (ret)
365407d1a51SLizhi Hou return ret;
366407d1a51SLizhi Hou
367407d1a51SLizhi Hou return 0;
368407d1a51SLizhi Hou }
369