1*736759efSBjorn Helgaas /* SPDX-License-Identifier: GPL-2.0+ */ 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * cpcihp_zt5550.h 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * Copyright 2002 SOMA Networks, Inc. 81da177e4SLinus Torvalds * Copyright 2001 Intel San Luis Obispo 91da177e4SLinus Torvalds * Copyright 2000,2001 MontaVista Software Inc. 101da177e4SLinus Torvalds * 111da177e4SLinus Torvalds * Send feedback to <scottm@somanetworks.com> 121da177e4SLinus Torvalds */ 131da177e4SLinus Torvalds 141da177e4SLinus Torvalds #ifndef _CPCIHP_ZT5550_H 151da177e4SLinus Torvalds #define _CPCIHP_ZT5550_H 161da177e4SLinus Torvalds 171da177e4SLinus Torvalds /* Direct registers */ 181da177e4SLinus Torvalds #define CSR_HCINDEX 0x00 191da177e4SLinus Torvalds #define CSR_HCDATA 0x04 201da177e4SLinus Torvalds #define CSR_INTSTAT 0x08 211da177e4SLinus Torvalds #define CSR_INTMASK 0x09 221da177e4SLinus Torvalds #define CSR_CNT0CMD 0x0C 231da177e4SLinus Torvalds #define CSR_CNT1CMD 0x0E 241da177e4SLinus Torvalds #define CSR_CNT0 0x10 251da177e4SLinus Torvalds #define CSR_CNT1 0x14 261da177e4SLinus Torvalds 271da177e4SLinus Torvalds /* Masks for interrupt bits in CSR_INTMASK direct register */ 281da177e4SLinus Torvalds #define CNT0_INT_MASK 0x01 291da177e4SLinus Torvalds #define CNT1_INT_MASK 0x02 301da177e4SLinus Torvalds #define ENUM_INT_MASK 0x04 311da177e4SLinus Torvalds #define ALL_DIRECT_INTS_MASK 0x07 321da177e4SLinus Torvalds 331da177e4SLinus Torvalds /* Indexed registers (through CSR_INDEX, CSR_DATA) */ 341da177e4SLinus Torvalds #define HC_INT_MASK_REG 0x04 351da177e4SLinus Torvalds #define HC_STATUS_REG 0x08 361da177e4SLinus Torvalds #define HC_CMD_REG 0x0C 371da177e4SLinus Torvalds #define ARB_CONFIG_GNT_REG 0x10 381da177e4SLinus Torvalds #define ARB_CONFIG_CFG_REG 0x12 391da177e4SLinus Torvalds #define ARB_CONFIG_REG 0x10 401da177e4SLinus Torvalds #define ISOL_CONFIG_REG 0x18 411da177e4SLinus Torvalds #define FAULT_STATUS_REG 0x20 421da177e4SLinus Torvalds #define FAULT_CONFIG_REG 0x24 431da177e4SLinus Torvalds #define WD_CONFIG_REG 0x2C 441da177e4SLinus Torvalds #define HC_DIAG_REG 0x30 451da177e4SLinus Torvalds #define SERIAL_COMM_REG 0x34 461da177e4SLinus Torvalds #define SERIAL_OUT_REG 0x38 471da177e4SLinus Torvalds #define SERIAL_IN_REG 0x3C 481da177e4SLinus Torvalds 491da177e4SLinus Torvalds /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ 501da177e4SLinus Torvalds #define SERIAL_INT_MASK 0x01 511da177e4SLinus Torvalds #define FAULT_INT_MASK 0x02 521da177e4SLinus Torvalds #define HCF_INT_MASK 0x04 531da177e4SLinus Torvalds #define ALL_INDEXED_INTS_MASK 0x07 541da177e4SLinus Torvalds 551da177e4SLinus Torvalds /* Digital I/O port storing ENUM# */ 561da177e4SLinus Torvalds #define ENUM_PORT 0xE1 571da177e4SLinus Torvalds /* Mask to get to the ENUM# bit on the bus */ 581da177e4SLinus Torvalds #define ENUM_MASK 0x40 591da177e4SLinus Torvalds 601da177e4SLinus Torvalds #endif /* _CPCIHP_ZT5550_H */ 61