1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/module.h> 14 #include <linux/msi.h> 15 #include <linux/of_address.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_pci.h> 18 #include <linux/pci-ecam.h> 19 #include <linux/platform_device.h> 20 21 #include "../pci.h" 22 23 /* Number of MSI IRQs */ 24 #define MC_NUM_MSI_IRQS 32 25 #define MC_NUM_MSI_IRQS_CODED 5 26 27 /* PCIe Bridge Phy and Controller Phy offsets */ 28 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 29 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 30 31 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) 32 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) 33 34 /* PCIe Controller Phy Regs */ 35 #define SEC_ERROR_CNT 0x20 36 #define DED_ERROR_CNT 0x24 37 #define SEC_ERROR_INT 0x28 38 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 39 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 40 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 41 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 42 #define NUM_SEC_ERROR_INTS (4) 43 #define SEC_ERROR_INT_MASK 0x2c 44 #define DED_ERROR_INT 0x30 45 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 46 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 47 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 48 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 49 #define NUM_DED_ERROR_INTS (4) 50 #define DED_ERROR_INT_MASK 0x34 51 #define ECC_CONTROL 0x38 52 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 53 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 54 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 55 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 56 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 57 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 58 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 59 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 60 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 61 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 62 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 63 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 64 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 65 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 66 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 67 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 68 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 69 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 70 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 71 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 72 #define LTSSM_STATE 0x5c 73 #define LTSSM_L0_STATE 0x10 74 #define PCIE_EVENT_INT 0x14c 75 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 76 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 77 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 78 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 79 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 80 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 81 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 82 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 83 #define PCIE_EVENT_INT_ENB_SHIFT 16 84 #define NUM_PCIE_EVENTS (3) 85 86 /* PCIe Bridge Phy Regs */ 87 #define PCIE_PCI_IDS_DW1 0x9c 88 89 /* PCIe Config space MSI capability structure */ 90 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 91 #define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1) 92 #define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4) 93 94 #define IMASK_LOCAL 0x180 95 #define DMA_END_ENGINE_0_MASK 0x00000000u 96 #define DMA_END_ENGINE_0_SHIFT 0 97 #define DMA_END_ENGINE_1_MASK 0x00000000u 98 #define DMA_END_ENGINE_1_SHIFT 1 99 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u 100 #define DMA_ERROR_ENGINE_0_SHIFT 8 101 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u 102 #define DMA_ERROR_ENGINE_1_SHIFT 9 103 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u 104 #define A_ATR_EVT_POST_ERR_SHIFT 16 105 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u 106 #define A_ATR_EVT_FETCH_ERR_SHIFT 17 107 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u 108 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18 109 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u 110 #define A_ATR_EVT_DOORBELL_SHIFT 19 111 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u 112 #define P_ATR_EVT_POST_ERR_SHIFT 20 113 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u 114 #define P_ATR_EVT_FETCH_ERR_SHIFT 21 115 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u 116 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 117 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u 118 #define P_ATR_EVT_DOORBELL_SHIFT 23 119 #define PM_MSI_INT_INTA_MASK 0x01000000u 120 #define PM_MSI_INT_INTA_SHIFT 24 121 #define PM_MSI_INT_INTB_MASK 0x02000000u 122 #define PM_MSI_INT_INTB_SHIFT 25 123 #define PM_MSI_INT_INTC_MASK 0x04000000u 124 #define PM_MSI_INT_INTC_SHIFT 26 125 #define PM_MSI_INT_INTD_MASK 0x08000000u 126 #define PM_MSI_INT_INTD_SHIFT 27 127 #define PM_MSI_INT_INTX_MASK 0x0f000000u 128 #define PM_MSI_INT_INTX_SHIFT 24 129 #define PM_MSI_INT_MSI_MASK 0x10000000u 130 #define PM_MSI_INT_MSI_SHIFT 28 131 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u 132 #define PM_MSI_INT_AER_EVT_SHIFT 29 133 #define PM_MSI_INT_EVENTS_MASK 0x40000000u 134 #define PM_MSI_INT_EVENTS_SHIFT 30 135 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u 136 #define PM_MSI_INT_SYS_ERR_SHIFT 31 137 #define NUM_LOCAL_EVENTS 15 138 #define ISTATUS_LOCAL 0x184 139 #define IMASK_HOST 0x188 140 #define ISTATUS_HOST 0x18c 141 #define MSI_ADDR 0x190 142 #define ISTATUS_MSI 0x194 143 144 /* PCIe Master table init defines */ 145 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u 146 #define ATR0_PCIE_ATR_SIZE 0x25 147 #define ATR0_PCIE_ATR_SIZE_SHIFT 1 148 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u 149 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u 150 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu 151 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u 152 153 /* PCIe AXI slave table init defines */ 154 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u 155 #define ATR_SIZE_SHIFT 1 156 #define ATR_IMPL_ENABLE 1 157 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u 158 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u 159 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu 160 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u 161 #define PCIE_TX_RX_INTERFACE 0x00000000u 162 #define PCIE_CONFIG_INTERFACE 0x00000001u 163 164 #define ATR_ENTRY_SIZE 32 165 166 #define EVENT_PCIE_L2_EXIT 0 167 #define EVENT_PCIE_HOTRST_EXIT 1 168 #define EVENT_PCIE_DLUP_EXIT 2 169 #define EVENT_SEC_TX_RAM_SEC_ERR 3 170 #define EVENT_SEC_RX_RAM_SEC_ERR 4 171 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5 172 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6 173 #define EVENT_DED_TX_RAM_DED_ERR 7 174 #define EVENT_DED_RX_RAM_DED_ERR 8 175 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9 176 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10 177 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 178 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 179 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 180 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 181 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 182 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 183 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 184 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 185 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 186 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 187 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 188 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 189 #define EVENT_LOCAL_PM_MSI_INT_INTX 23 190 #define EVENT_LOCAL_PM_MSI_INT_MSI 24 191 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 192 #define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 193 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 194 #define NUM_EVENTS 28 195 196 #define PCIE_EVENT_CAUSE(x, s) \ 197 [EVENT_PCIE_ ## x] = { __stringify(x), s } 198 199 #define SEC_ERROR_CAUSE(x, s) \ 200 [EVENT_SEC_ ## x] = { __stringify(x), s } 201 202 #define DED_ERROR_CAUSE(x, s) \ 203 [EVENT_DED_ ## x] = { __stringify(x), s } 204 205 #define LOCAL_EVENT_CAUSE(x, s) \ 206 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 207 208 #define PCIE_EVENT(x) \ 209 .base = MC_PCIE_CTRL_ADDR, \ 210 .offset = PCIE_EVENT_INT, \ 211 .mask_offset = PCIE_EVENT_INT, \ 212 .mask_high = 1, \ 213 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 214 .enb_mask = PCIE_EVENT_INT_ENB_MASK 215 216 #define SEC_EVENT(x) \ 217 .base = MC_PCIE_CTRL_ADDR, \ 218 .offset = SEC_ERROR_INT, \ 219 .mask_offset = SEC_ERROR_INT_MASK, \ 220 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 221 .mask_high = 1, \ 222 .enb_mask = 0 223 224 #define DED_EVENT(x) \ 225 .base = MC_PCIE_CTRL_ADDR, \ 226 .offset = DED_ERROR_INT, \ 227 .mask_offset = DED_ERROR_INT_MASK, \ 228 .mask_high = 1, \ 229 .mask = DED_ERROR_INT_ ## x ## _INT, \ 230 .enb_mask = 0 231 232 #define LOCAL_EVENT(x) \ 233 .base = MC_PCIE_BRIDGE_ADDR, \ 234 .offset = ISTATUS_LOCAL, \ 235 .mask_offset = IMASK_LOCAL, \ 236 .mask_high = 0, \ 237 .mask = x ## _MASK, \ 238 .enb_mask = 0 239 240 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 241 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 242 243 #define SEC_ERROR_TO_EVENT_MAP(x) \ 244 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 245 246 #define DED_ERROR_TO_EVENT_MAP(x) \ 247 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 248 249 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 250 { x ## _MASK, EVENT_LOCAL_ ## x } 251 252 struct event_map { 253 u32 reg_mask; 254 u32 event_bit; 255 }; 256 257 struct mc_msi { 258 struct mutex lock; /* Protect used bitmap */ 259 struct irq_domain *msi_domain; 260 struct irq_domain *dev_domain; 261 u32 num_vectors; 262 u64 vector_phy; 263 DECLARE_BITMAP(used, MC_NUM_MSI_IRQS); 264 }; 265 266 struct mc_pcie { 267 void __iomem *axi_base_addr; 268 struct device *dev; 269 struct irq_domain *intx_domain; 270 struct irq_domain *event_domain; 271 raw_spinlock_t lock; 272 struct mc_msi msi; 273 }; 274 275 struct cause { 276 const char *sym; 277 const char *str; 278 }; 279 280 static const struct cause event_cause[NUM_EVENTS] = { 281 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 282 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 283 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 284 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 285 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 286 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 287 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 288 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 289 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 290 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 291 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 292 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 293 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 294 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 295 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 296 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 297 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 298 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 299 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 300 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 301 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 302 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 303 }; 304 305 static struct event_map pcie_event_to_event[] = { 306 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 307 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 308 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 309 }; 310 311 static struct event_map sec_error_to_event[] = { 312 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 313 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 314 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 315 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 316 }; 317 318 static struct event_map ded_error_to_event[] = { 319 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 320 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 321 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 322 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 323 }; 324 325 static struct event_map local_status_to_event[] = { 326 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 327 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 328 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 329 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 330 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 331 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 332 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 333 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 334 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 335 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 336 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 337 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 338 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 340 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 341 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 342 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 343 }; 344 345 static struct { 346 u32 base; 347 u32 offset; 348 u32 mask; 349 u32 shift; 350 u32 enb_mask; 351 u32 mask_high; 352 u32 mask_offset; 353 } event_descs[] = { 354 { PCIE_EVENT(L2_EXIT) }, 355 { PCIE_EVENT(HOTRST_EXIT) }, 356 { PCIE_EVENT(DLUP_EXIT) }, 357 { SEC_EVENT(TX_RAM_SEC_ERR) }, 358 { SEC_EVENT(RX_RAM_SEC_ERR) }, 359 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 360 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 361 { DED_EVENT(TX_RAM_DED_ERR) }, 362 { DED_EVENT(RX_RAM_DED_ERR) }, 363 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 364 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 365 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 366 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 367 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 368 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 369 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 370 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 371 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 372 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 373 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 374 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 375 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 376 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 377 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 378 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 379 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 380 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 381 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 382 }; 383 384 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 385 386 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base) 387 { 388 struct mc_msi *msi = &port->msi; 389 u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET; 390 u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS); 391 392 msg_ctrl |= PCI_MSI_FLAGS_ENABLE; 393 msg_ctrl &= ~PCI_MSI_FLAGS_QMASK; 394 msg_ctrl |= MC_MSI_MAX_Q_AVAIL; 395 msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE; 396 msg_ctrl |= MC_MSI_Q_SIZE; 397 msg_ctrl |= PCI_MSI_FLAGS_64BIT; 398 399 writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS); 400 401 writel_relaxed(lower_32_bits(msi->vector_phy), 402 base + cap_offset + PCI_MSI_ADDRESS_LO); 403 writel_relaxed(upper_32_bits(msi->vector_phy), 404 base + cap_offset + PCI_MSI_ADDRESS_HI); 405 } 406 407 static void mc_handle_msi(struct irq_desc *desc) 408 { 409 struct mc_pcie *port = irq_desc_get_handler_data(desc); 410 struct irq_chip *chip = irq_desc_get_chip(desc); 411 struct device *dev = port->dev; 412 struct mc_msi *msi = &port->msi; 413 void __iomem *bridge_base_addr = 414 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 415 unsigned long status; 416 u32 bit; 417 int ret; 418 419 chained_irq_enter(chip, desc); 420 421 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 422 if (status & PM_MSI_INT_MSI_MASK) { 423 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); 424 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); 425 for_each_set_bit(bit, &status, msi->num_vectors) { 426 ret = generic_handle_domain_irq(msi->dev_domain, bit); 427 if (ret) 428 dev_err_ratelimited(dev, "bad MSI IRQ %d\n", 429 bit); 430 } 431 } 432 433 chained_irq_exit(chip, desc); 434 } 435 436 static void mc_msi_bottom_irq_ack(struct irq_data *data) 437 { 438 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 439 void __iomem *bridge_base_addr = 440 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 441 u32 bitpos = data->hwirq; 442 443 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); 444 } 445 446 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 447 { 448 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 449 phys_addr_t addr = port->msi.vector_phy; 450 451 msg->address_lo = lower_32_bits(addr); 452 msg->address_hi = upper_32_bits(addr); 453 msg->data = data->hwirq; 454 455 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", 456 (int)data->hwirq, msg->address_hi, msg->address_lo); 457 } 458 459 static int mc_msi_set_affinity(struct irq_data *irq_data, 460 const struct cpumask *mask, bool force) 461 { 462 return -EINVAL; 463 } 464 465 static struct irq_chip mc_msi_bottom_irq_chip = { 466 .name = "Microchip MSI", 467 .irq_ack = mc_msi_bottom_irq_ack, 468 .irq_compose_msi_msg = mc_compose_msi_msg, 469 .irq_set_affinity = mc_msi_set_affinity, 470 }; 471 472 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 473 unsigned int nr_irqs, void *args) 474 { 475 struct mc_pcie *port = domain->host_data; 476 struct mc_msi *msi = &port->msi; 477 void __iomem *bridge_base_addr = 478 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 479 unsigned long bit; 480 u32 val; 481 482 mutex_lock(&msi->lock); 483 bit = find_first_zero_bit(msi->used, msi->num_vectors); 484 if (bit >= msi->num_vectors) { 485 mutex_unlock(&msi->lock); 486 return -ENOSPC; 487 } 488 489 set_bit(bit, msi->used); 490 491 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, 492 domain->host_data, handle_edge_irq, NULL, NULL); 493 494 /* Enable MSI interrupts */ 495 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 496 val |= PM_MSI_INT_MSI_MASK; 497 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 498 499 mutex_unlock(&msi->lock); 500 501 return 0; 502 } 503 504 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, 505 unsigned int nr_irqs) 506 { 507 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 508 struct mc_pcie *port = irq_data_get_irq_chip_data(d); 509 struct mc_msi *msi = &port->msi; 510 511 mutex_lock(&msi->lock); 512 513 if (test_bit(d->hwirq, msi->used)) 514 __clear_bit(d->hwirq, msi->used); 515 else 516 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); 517 518 mutex_unlock(&msi->lock); 519 } 520 521 static const struct irq_domain_ops msi_domain_ops = { 522 .alloc = mc_irq_msi_domain_alloc, 523 .free = mc_irq_msi_domain_free, 524 }; 525 526 static struct irq_chip mc_msi_irq_chip = { 527 .name = "Microchip PCIe MSI", 528 .irq_ack = irq_chip_ack_parent, 529 .irq_mask = pci_msi_mask_irq, 530 .irq_unmask = pci_msi_unmask_irq, 531 }; 532 533 static struct msi_domain_info mc_msi_domain_info = { 534 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 535 MSI_FLAG_PCI_MSIX), 536 .chip = &mc_msi_irq_chip, 537 }; 538 539 static int mc_allocate_msi_domains(struct mc_pcie *port) 540 { 541 struct device *dev = port->dev; 542 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 543 struct mc_msi *msi = &port->msi; 544 545 mutex_init(&port->msi.lock); 546 547 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, 548 &msi_domain_ops, port); 549 if (!msi->dev_domain) { 550 dev_err(dev, "failed to create IRQ domain\n"); 551 return -ENOMEM; 552 } 553 554 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, 555 msi->dev_domain); 556 if (!msi->msi_domain) { 557 dev_err(dev, "failed to create MSI domain\n"); 558 irq_domain_remove(msi->dev_domain); 559 return -ENOMEM; 560 } 561 562 return 0; 563 } 564 565 static void mc_handle_intx(struct irq_desc *desc) 566 { 567 struct mc_pcie *port = irq_desc_get_handler_data(desc); 568 struct irq_chip *chip = irq_desc_get_chip(desc); 569 struct device *dev = port->dev; 570 void __iomem *bridge_base_addr = 571 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 572 unsigned long status; 573 u32 bit; 574 int ret; 575 576 chained_irq_enter(chip, desc); 577 578 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 579 if (status & PM_MSI_INT_INTX_MASK) { 580 status &= PM_MSI_INT_INTX_MASK; 581 status >>= PM_MSI_INT_INTX_SHIFT; 582 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 583 ret = generic_handle_domain_irq(port->intx_domain, bit); 584 if (ret) 585 dev_err_ratelimited(dev, "bad INTx IRQ %d\n", 586 bit); 587 } 588 } 589 590 chained_irq_exit(chip, desc); 591 } 592 593 static void mc_ack_intx_irq(struct irq_data *data) 594 { 595 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 596 void __iomem *bridge_base_addr = 597 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 598 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 599 600 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); 601 } 602 603 static void mc_mask_intx_irq(struct irq_data *data) 604 { 605 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 606 void __iomem *bridge_base_addr = 607 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 608 unsigned long flags; 609 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 610 u32 val; 611 612 raw_spin_lock_irqsave(&port->lock, flags); 613 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 614 val &= ~mask; 615 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 616 raw_spin_unlock_irqrestore(&port->lock, flags); 617 } 618 619 static void mc_unmask_intx_irq(struct irq_data *data) 620 { 621 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 622 void __iomem *bridge_base_addr = 623 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 624 unsigned long flags; 625 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 626 u32 val; 627 628 raw_spin_lock_irqsave(&port->lock, flags); 629 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 630 val |= mask; 631 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 632 raw_spin_unlock_irqrestore(&port->lock, flags); 633 } 634 635 static struct irq_chip mc_intx_irq_chip = { 636 .name = "Microchip PCIe INTx", 637 .irq_ack = mc_ack_intx_irq, 638 .irq_mask = mc_mask_intx_irq, 639 .irq_unmask = mc_unmask_intx_irq, 640 }; 641 642 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 643 irq_hw_number_t hwirq) 644 { 645 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); 646 irq_set_chip_data(irq, domain->host_data); 647 648 return 0; 649 } 650 651 static const struct irq_domain_ops intx_domain_ops = { 652 .map = mc_pcie_intx_map, 653 }; 654 655 static inline u32 reg_to_event(u32 reg, struct event_map field) 656 { 657 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 658 } 659 660 static u32 pcie_events(void __iomem *addr) 661 { 662 u32 reg = readl_relaxed(addr); 663 u32 val = 0; 664 int i; 665 666 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 667 val |= reg_to_event(reg, pcie_event_to_event[i]); 668 669 return val; 670 } 671 672 static u32 sec_errors(void __iomem *addr) 673 { 674 u32 reg = readl_relaxed(addr); 675 u32 val = 0; 676 int i; 677 678 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 679 val |= reg_to_event(reg, sec_error_to_event[i]); 680 681 return val; 682 } 683 684 static u32 ded_errors(void __iomem *addr) 685 { 686 u32 reg = readl_relaxed(addr); 687 u32 val = 0; 688 int i; 689 690 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 691 val |= reg_to_event(reg, ded_error_to_event[i]); 692 693 return val; 694 } 695 696 static u32 local_events(void __iomem *addr) 697 { 698 u32 reg = readl_relaxed(addr); 699 u32 val = 0; 700 int i; 701 702 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 703 val |= reg_to_event(reg, local_status_to_event[i]); 704 705 return val; 706 } 707 708 static u32 get_events(struct mc_pcie *port) 709 { 710 void __iomem *bridge_base_addr = 711 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 712 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 713 u32 events = 0; 714 715 events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); 716 events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); 717 events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); 718 events |= local_events(bridge_base_addr + ISTATUS_LOCAL); 719 720 return events; 721 } 722 723 static irqreturn_t mc_event_handler(int irq, void *dev_id) 724 { 725 struct mc_pcie *port = dev_id; 726 struct device *dev = port->dev; 727 struct irq_data *data; 728 729 data = irq_domain_get_irq_data(port->event_domain, irq); 730 731 if (event_cause[data->hwirq].str) 732 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 733 else 734 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 735 736 return IRQ_HANDLED; 737 } 738 739 static void mc_handle_event(struct irq_desc *desc) 740 { 741 struct mc_pcie *port = irq_desc_get_handler_data(desc); 742 unsigned long events; 743 u32 bit; 744 struct irq_chip *chip = irq_desc_get_chip(desc); 745 746 chained_irq_enter(chip, desc); 747 748 events = get_events(port); 749 750 for_each_set_bit(bit, &events, NUM_EVENTS) 751 generic_handle_domain_irq(port->event_domain, bit); 752 753 chained_irq_exit(chip, desc); 754 } 755 756 static void mc_ack_event_irq(struct irq_data *data) 757 { 758 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 759 u32 event = data->hwirq; 760 void __iomem *addr; 761 u32 mask; 762 763 addr = port->axi_base_addr + event_descs[event].base + 764 event_descs[event].offset; 765 mask = event_descs[event].mask; 766 mask |= event_descs[event].enb_mask; 767 768 writel_relaxed(mask, addr); 769 } 770 771 static void mc_mask_event_irq(struct irq_data *data) 772 { 773 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 774 u32 event = data->hwirq; 775 void __iomem *addr; 776 u32 mask; 777 u32 val; 778 779 addr = port->axi_base_addr + event_descs[event].base + 780 event_descs[event].mask_offset; 781 mask = event_descs[event].mask; 782 if (event_descs[event].enb_mask) { 783 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 784 mask &= PCIE_EVENT_INT_ENB_MASK; 785 } 786 787 if (!event_descs[event].mask_high) 788 mask = ~mask; 789 790 raw_spin_lock(&port->lock); 791 val = readl_relaxed(addr); 792 if (event_descs[event].mask_high) 793 val |= mask; 794 else 795 val &= mask; 796 797 writel_relaxed(val, addr); 798 raw_spin_unlock(&port->lock); 799 } 800 801 static void mc_unmask_event_irq(struct irq_data *data) 802 { 803 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 804 u32 event = data->hwirq; 805 void __iomem *addr; 806 u32 mask; 807 u32 val; 808 809 addr = port->axi_base_addr + event_descs[event].base + 810 event_descs[event].mask_offset; 811 mask = event_descs[event].mask; 812 813 if (event_descs[event].enb_mask) 814 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 815 816 if (event_descs[event].mask_high) 817 mask = ~mask; 818 819 if (event_descs[event].enb_mask) 820 mask &= PCIE_EVENT_INT_ENB_MASK; 821 822 raw_spin_lock(&port->lock); 823 val = readl_relaxed(addr); 824 if (event_descs[event].mask_high) 825 val &= mask; 826 else 827 val |= mask; 828 writel_relaxed(val, addr); 829 raw_spin_unlock(&port->lock); 830 } 831 832 static struct irq_chip mc_event_irq_chip = { 833 .name = "Microchip PCIe EVENT", 834 .irq_ack = mc_ack_event_irq, 835 .irq_mask = mc_mask_event_irq, 836 .irq_unmask = mc_unmask_event_irq, 837 }; 838 839 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, 840 irq_hw_number_t hwirq) 841 { 842 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); 843 irq_set_chip_data(irq, domain->host_data); 844 845 return 0; 846 } 847 848 static const struct irq_domain_ops event_domain_ops = { 849 .map = mc_pcie_event_map, 850 }; 851 852 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 853 { 854 struct clk *clk; 855 int ret; 856 857 clk = devm_clk_get_optional(dev, id); 858 if (IS_ERR(clk)) 859 return clk; 860 if (!clk) 861 return clk; 862 863 ret = clk_prepare_enable(clk); 864 if (ret) 865 return ERR_PTR(ret); 866 867 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, 868 clk); 869 870 return clk; 871 } 872 873 static int mc_pcie_init_clks(struct device *dev) 874 { 875 int i; 876 struct clk *fic; 877 878 /* 879 * PCIe may be clocked via Fabric Interface using between 1 and 4 880 * clocks. Scan DT for clocks and enable them if present 881 */ 882 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 883 fic = mc_pcie_init_clk(dev, poss_clks[i]); 884 if (IS_ERR(fic)) 885 return PTR_ERR(fic); 886 } 887 888 return 0; 889 } 890 891 static int mc_pcie_init_irq_domains(struct mc_pcie *port) 892 { 893 struct device *dev = port->dev; 894 struct device_node *node = dev->of_node; 895 struct device_node *pcie_intc_node; 896 897 /* Setup INTx */ 898 pcie_intc_node = of_get_next_child(node, NULL); 899 if (!pcie_intc_node) { 900 dev_err(dev, "failed to find PCIe Intc node\n"); 901 return -EINVAL; 902 } 903 904 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, 905 &event_domain_ops, port); 906 if (!port->event_domain) { 907 dev_err(dev, "failed to get event domain\n"); 908 of_node_put(pcie_intc_node); 909 return -ENOMEM; 910 } 911 912 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); 913 914 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 915 &intx_domain_ops, port); 916 if (!port->intx_domain) { 917 dev_err(dev, "failed to get an INTx IRQ domain\n"); 918 of_node_put(pcie_intc_node); 919 return -ENOMEM; 920 } 921 922 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); 923 924 of_node_put(pcie_intc_node); 925 raw_spin_lock_init(&port->lock); 926 927 return mc_allocate_msi_domains(port); 928 } 929 930 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, 931 phys_addr_t axi_addr, phys_addr_t pci_addr, 932 size_t size) 933 { 934 u32 atr_sz = ilog2(size) - 1; 935 u32 val; 936 937 if (index == 0) 938 val = PCIE_CONFIG_INTERFACE; 939 else 940 val = PCIE_TX_RX_INTERFACE; 941 942 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 943 ATR0_AXI4_SLV0_TRSL_PARAM); 944 945 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | 946 ATR_IMPL_ENABLE; 947 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 948 ATR0_AXI4_SLV0_SRCADDR_PARAM); 949 950 val = upper_32_bits(axi_addr); 951 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 952 ATR0_AXI4_SLV0_SRC_ADDR); 953 954 val = lower_32_bits(pci_addr); 955 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 956 ATR0_AXI4_SLV0_TRSL_ADDR_LSB); 957 958 val = upper_32_bits(pci_addr); 959 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 960 ATR0_AXI4_SLV0_TRSL_ADDR_UDW); 961 962 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 963 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); 964 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 965 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); 966 } 967 968 static int mc_pcie_setup_windows(struct platform_device *pdev, 969 struct mc_pcie *port) 970 { 971 void __iomem *bridge_base_addr = 972 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 973 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 974 struct resource_entry *entry; 975 u64 pci_addr; 976 u32 index = 1; 977 978 resource_list_for_each_entry(entry, &bridge->windows) { 979 if (resource_type(entry->res) == IORESOURCE_MEM) { 980 pci_addr = entry->res->start - entry->offset; 981 mc_pcie_setup_window(bridge_base_addr, index, 982 entry->res->start, pci_addr, 983 resource_size(entry->res)); 984 index++; 985 } 986 } 987 988 return 0; 989 } 990 991 static int mc_platform_init(struct pci_config_window *cfg) 992 { 993 struct device *dev = cfg->parent; 994 struct platform_device *pdev = to_platform_device(dev); 995 struct mc_pcie *port; 996 void __iomem *bridge_base_addr; 997 void __iomem *ctrl_base_addr; 998 int ret; 999 int irq; 1000 int i, intx_irq, msi_irq, event_irq; 1001 u32 val; 1002 int err; 1003 1004 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1005 if (!port) 1006 return -ENOMEM; 1007 port->dev = dev; 1008 1009 ret = mc_pcie_init_clks(dev); 1010 if (ret) { 1011 dev_err(dev, "failed to get clock resources, error %d\n", ret); 1012 return -ENODEV; 1013 } 1014 1015 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); 1016 if (IS_ERR(port->axi_base_addr)) 1017 return PTR_ERR(port->axi_base_addr); 1018 1019 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1020 ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 1021 1022 port->msi.vector_phy = MSI_ADDR; 1023 port->msi.num_vectors = MC_NUM_MSI_IRQS; 1024 ret = mc_pcie_init_irq_domains(port); 1025 if (ret) { 1026 dev_err(dev, "failed creating IRQ domains\n"); 1027 return ret; 1028 } 1029 1030 irq = platform_get_irq(pdev, 0); 1031 if (irq < 0) 1032 return -ENODEV; 1033 1034 for (i = 0; i < NUM_EVENTS; i++) { 1035 event_irq = irq_create_mapping(port->event_domain, i); 1036 if (!event_irq) { 1037 dev_err(dev, "failed to map hwirq %d\n", i); 1038 return -ENXIO; 1039 } 1040 1041 err = devm_request_irq(dev, event_irq, mc_event_handler, 1042 0, event_cause[i].sym, port); 1043 if (err) { 1044 dev_err(dev, "failed to request IRQ %d\n", event_irq); 1045 return err; 1046 } 1047 } 1048 1049 intx_irq = irq_create_mapping(port->event_domain, 1050 EVENT_LOCAL_PM_MSI_INT_INTX); 1051 if (!intx_irq) { 1052 dev_err(dev, "failed to map INTx interrupt\n"); 1053 return -ENXIO; 1054 } 1055 1056 /* Plug the INTx chained handler */ 1057 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); 1058 1059 msi_irq = irq_create_mapping(port->event_domain, 1060 EVENT_LOCAL_PM_MSI_INT_MSI); 1061 if (!msi_irq) 1062 return -ENXIO; 1063 1064 /* Plug the MSI chained handler */ 1065 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); 1066 1067 /* Plug the main event chained handler */ 1068 irq_set_chained_handler_and_data(irq, mc_handle_event, port); 1069 1070 /* Hardware doesn't setup MSI by default */ 1071 mc_pcie_enable_msi(port, cfg->win); 1072 1073 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 1074 val |= PM_MSI_INT_INTX_MASK; 1075 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 1076 1077 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL); 1078 1079 val = PCIE_EVENT_INT_L2_EXIT_INT | 1080 PCIE_EVENT_INT_HOTRST_EXIT_INT | 1081 PCIE_EVENT_INT_DLUP_EXIT_INT; 1082 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT); 1083 1084 val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT | 1085 SEC_ERROR_INT_RX_RAM_SEC_ERR_INT | 1086 SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT | 1087 SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT; 1088 writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT); 1089 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK); 1090 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_CNT); 1091 1092 val = DED_ERROR_INT_TX_RAM_DED_ERR_INT | 1093 DED_ERROR_INT_RX_RAM_DED_ERR_INT | 1094 DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT | 1095 DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT; 1096 writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT); 1097 writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK); 1098 writel_relaxed(0, ctrl_base_addr + DED_ERROR_CNT); 1099 1100 writel_relaxed(0, bridge_base_addr + IMASK_HOST); 1101 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); 1102 1103 /* Configure Address Translation Table 0 for PCIe config space */ 1104 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, 1105 cfg->res.start, resource_size(&cfg->res)); 1106 1107 return mc_pcie_setup_windows(pdev, port); 1108 } 1109 1110 static const struct pci_ecam_ops mc_ecam_ops = { 1111 .init = mc_platform_init, 1112 .pci_ops = { 1113 .map_bus = pci_ecam_map_bus, 1114 .read = pci_generic_config_read, 1115 .write = pci_generic_config_write, 1116 } 1117 }; 1118 1119 static const struct of_device_id mc_pcie_of_match[] = { 1120 { 1121 .compatible = "microchip,pcie-host-1.0", 1122 .data = &mc_ecam_ops, 1123 }, 1124 {}, 1125 }; 1126 1127 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 1128 1129 static struct platform_driver mc_pcie_driver = { 1130 .probe = pci_host_common_probe, 1131 .driver = { 1132 .name = "microchip-pcie", 1133 .of_match_table = mc_pcie_of_match, 1134 .suppress_bind_attrs = true, 1135 }, 1136 }; 1137 1138 builtin_platform_driver(mc_pcie_driver); 1139 MODULE_LICENSE("GPL"); 1140 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 1141 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 1142