1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/module.h> 14 #include <linux/msi.h> 15 #include <linux/of_address.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci-ecam.h> 18 #include <linux/platform_device.h> 19 20 #include "../pci.h" 21 22 /* Number of MSI IRQs */ 23 #define MC_NUM_MSI_IRQS 32 24 #define MC_NUM_MSI_IRQS_CODED 5 25 26 /* PCIe Bridge Phy and Controller Phy offsets */ 27 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 28 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 29 30 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) 31 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) 32 33 /* PCIe Bridge Phy Regs */ 34 #define IMASK_LOCAL 0x180 35 #define DMA_END_ENGINE_0_MASK 0x00000000u 36 #define DMA_END_ENGINE_0_SHIFT 0 37 #define DMA_END_ENGINE_1_MASK 0x00000000u 38 #define DMA_END_ENGINE_1_SHIFT 1 39 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u 40 #define DMA_ERROR_ENGINE_0_SHIFT 8 41 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u 42 #define DMA_ERROR_ENGINE_1_SHIFT 9 43 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u 44 #define A_ATR_EVT_POST_ERR_SHIFT 16 45 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u 46 #define A_ATR_EVT_FETCH_ERR_SHIFT 17 47 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u 48 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18 49 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u 50 #define A_ATR_EVT_DOORBELL_SHIFT 19 51 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u 52 #define P_ATR_EVT_POST_ERR_SHIFT 20 53 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u 54 #define P_ATR_EVT_FETCH_ERR_SHIFT 21 55 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u 56 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 57 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u 58 #define P_ATR_EVT_DOORBELL_SHIFT 23 59 #define PM_MSI_INT_INTA_MASK 0x01000000u 60 #define PM_MSI_INT_INTA_SHIFT 24 61 #define PM_MSI_INT_INTB_MASK 0x02000000u 62 #define PM_MSI_INT_INTB_SHIFT 25 63 #define PM_MSI_INT_INTC_MASK 0x04000000u 64 #define PM_MSI_INT_INTC_SHIFT 26 65 #define PM_MSI_INT_INTD_MASK 0x08000000u 66 #define PM_MSI_INT_INTD_SHIFT 27 67 #define PM_MSI_INT_INTX_MASK 0x0f000000u 68 #define PM_MSI_INT_INTX_SHIFT 24 69 #define PM_MSI_INT_MSI_MASK 0x10000000u 70 #define PM_MSI_INT_MSI_SHIFT 28 71 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u 72 #define PM_MSI_INT_AER_EVT_SHIFT 29 73 #define PM_MSI_INT_EVENTS_MASK 0x40000000u 74 #define PM_MSI_INT_EVENTS_SHIFT 30 75 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u 76 #define PM_MSI_INT_SYS_ERR_SHIFT 31 77 #define NUM_LOCAL_EVENTS 15 78 #define ISTATUS_LOCAL 0x184 79 #define IMASK_HOST 0x188 80 #define ISTATUS_HOST 0x18c 81 #define IMSI_ADDR 0x190 82 #define MSI_ADDR 0x190 83 #define ISTATUS_MSI 0x194 84 85 /* PCIe Master table init defines */ 86 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u 87 #define ATR0_PCIE_ATR_SIZE 0x25 88 #define ATR0_PCIE_ATR_SIZE_SHIFT 1 89 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u 90 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u 91 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu 92 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u 93 94 /* PCIe AXI slave table init defines */ 95 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u 96 #define ATR_SIZE_SHIFT 1 97 #define ATR_IMPL_ENABLE 1 98 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u 99 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u 100 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu 101 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u 102 #define PCIE_TX_RX_INTERFACE 0x00000000u 103 #define PCIE_CONFIG_INTERFACE 0x00000001u 104 105 #define ATR_ENTRY_SIZE 32 106 107 /* PCIe Controller Phy Regs */ 108 #define SEC_ERROR_EVENT_CNT 0x20 109 #define DED_ERROR_EVENT_CNT 0x24 110 #define SEC_ERROR_INT 0x28 111 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 112 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 113 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 114 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 115 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0) 116 #define NUM_SEC_ERROR_INTS (4) 117 #define SEC_ERROR_INT_MASK 0x2c 118 #define DED_ERROR_INT 0x30 119 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 120 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 121 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 122 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 123 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0) 124 #define NUM_DED_ERROR_INTS (4) 125 #define DED_ERROR_INT_MASK 0x34 126 #define ECC_CONTROL 0x38 127 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 128 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 129 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 130 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 131 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 132 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 133 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 134 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 135 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 136 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 137 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 138 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 139 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 140 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 141 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 142 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 143 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 144 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 145 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 146 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 147 #define PCIE_EVENT_INT 0x14c 148 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 149 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 150 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 151 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 152 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 153 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 154 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 155 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 156 #define PCIE_EVENT_INT_ENB_SHIFT 16 157 #define NUM_PCIE_EVENTS (3) 158 159 /* PCIe Config space MSI capability structure */ 160 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 161 #define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1) 162 #define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4) 163 164 /* Events */ 165 #define EVENT_PCIE_L2_EXIT 0 166 #define EVENT_PCIE_HOTRST_EXIT 1 167 #define EVENT_PCIE_DLUP_EXIT 2 168 #define EVENT_SEC_TX_RAM_SEC_ERR 3 169 #define EVENT_SEC_RX_RAM_SEC_ERR 4 170 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 171 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 172 #define EVENT_DED_TX_RAM_DED_ERR 7 173 #define EVENT_DED_RX_RAM_DED_ERR 8 174 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 175 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 176 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 177 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 178 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 179 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 180 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 181 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 182 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 183 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 184 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 185 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 186 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 187 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 188 #define EVENT_LOCAL_PM_MSI_INT_INTX 23 189 #define EVENT_LOCAL_PM_MSI_INT_MSI 24 190 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 191 #define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 192 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 193 #define NUM_EVENTS 28 194 195 #define PCIE_EVENT_CAUSE(x, s) \ 196 [EVENT_PCIE_ ## x] = { __stringify(x), s } 197 198 #define SEC_ERROR_CAUSE(x, s) \ 199 [EVENT_SEC_ ## x] = { __stringify(x), s } 200 201 #define DED_ERROR_CAUSE(x, s) \ 202 [EVENT_DED_ ## x] = { __stringify(x), s } 203 204 #define LOCAL_EVENT_CAUSE(x, s) \ 205 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 206 207 #define PCIE_EVENT(x) \ 208 .base = MC_PCIE_CTRL_ADDR, \ 209 .offset = PCIE_EVENT_INT, \ 210 .mask_offset = PCIE_EVENT_INT, \ 211 .mask_high = 1, \ 212 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 213 .enb_mask = PCIE_EVENT_INT_ENB_MASK 214 215 #define SEC_EVENT(x) \ 216 .base = MC_PCIE_CTRL_ADDR, \ 217 .offset = SEC_ERROR_INT, \ 218 .mask_offset = SEC_ERROR_INT_MASK, \ 219 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 220 .mask_high = 1, \ 221 .enb_mask = 0 222 223 #define DED_EVENT(x) \ 224 .base = MC_PCIE_CTRL_ADDR, \ 225 .offset = DED_ERROR_INT, \ 226 .mask_offset = DED_ERROR_INT_MASK, \ 227 .mask_high = 1, \ 228 .mask = DED_ERROR_INT_ ## x ## _INT, \ 229 .enb_mask = 0 230 231 #define LOCAL_EVENT(x) \ 232 .base = MC_PCIE_BRIDGE_ADDR, \ 233 .offset = ISTATUS_LOCAL, \ 234 .mask_offset = IMASK_LOCAL, \ 235 .mask_high = 0, \ 236 .mask = x ## _MASK, \ 237 .enb_mask = 0 238 239 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 240 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 241 242 #define SEC_ERROR_TO_EVENT_MAP(x) \ 243 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 244 245 #define DED_ERROR_TO_EVENT_MAP(x) \ 246 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 247 248 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 249 { x ## _MASK, EVENT_LOCAL_ ## x } 250 251 struct event_map { 252 u32 reg_mask; 253 u32 event_bit; 254 }; 255 256 struct mc_msi { 257 struct mutex lock; /* Protect used bitmap */ 258 struct irq_domain *msi_domain; 259 struct irq_domain *dev_domain; 260 u32 num_vectors; 261 u64 vector_phy; 262 DECLARE_BITMAP(used, MC_NUM_MSI_IRQS); 263 }; 264 265 struct mc_pcie { 266 void __iomem *axi_base_addr; 267 struct device *dev; 268 struct irq_domain *intx_domain; 269 struct irq_domain *event_domain; 270 raw_spinlock_t lock; 271 struct mc_msi msi; 272 }; 273 274 struct cause { 275 const char *sym; 276 const char *str; 277 }; 278 279 static const struct cause event_cause[NUM_EVENTS] = { 280 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 281 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 282 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 283 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 284 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 285 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 286 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 287 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 288 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 289 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 290 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 291 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 292 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 293 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 294 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 295 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 296 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 297 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 298 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 299 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 300 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 301 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 302 }; 303 304 static struct event_map pcie_event_to_event[] = { 305 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 306 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 307 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 308 }; 309 310 static struct event_map sec_error_to_event[] = { 311 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 312 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 313 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 314 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 315 }; 316 317 static struct event_map ded_error_to_event[] = { 318 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 319 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 320 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 321 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 322 }; 323 324 static struct event_map local_status_to_event[] = { 325 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 326 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 327 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 328 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 329 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 330 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 331 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 332 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 333 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 334 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 335 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 336 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 337 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 338 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 340 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 341 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 342 }; 343 344 static struct { 345 u32 base; 346 u32 offset; 347 u32 mask; 348 u32 shift; 349 u32 enb_mask; 350 u32 mask_high; 351 u32 mask_offset; 352 } event_descs[] = { 353 { PCIE_EVENT(L2_EXIT) }, 354 { PCIE_EVENT(HOTRST_EXIT) }, 355 { PCIE_EVENT(DLUP_EXIT) }, 356 { SEC_EVENT(TX_RAM_SEC_ERR) }, 357 { SEC_EVENT(RX_RAM_SEC_ERR) }, 358 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 359 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 360 { DED_EVENT(TX_RAM_DED_ERR) }, 361 { DED_EVENT(RX_RAM_DED_ERR) }, 362 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 363 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 364 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 365 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 366 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 367 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 368 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 369 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 370 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 371 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 372 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 373 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 374 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 375 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 376 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 377 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 378 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 379 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 380 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 381 }; 382 383 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 384 385 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base) 386 { 387 struct mc_msi *msi = &port->msi; 388 u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET; 389 u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS); 390 391 msg_ctrl |= PCI_MSI_FLAGS_ENABLE; 392 msg_ctrl &= ~PCI_MSI_FLAGS_QMASK; 393 msg_ctrl |= MC_MSI_MAX_Q_AVAIL; 394 msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE; 395 msg_ctrl |= MC_MSI_Q_SIZE; 396 msg_ctrl |= PCI_MSI_FLAGS_64BIT; 397 398 writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS); 399 400 writel_relaxed(lower_32_bits(msi->vector_phy), 401 base + cap_offset + PCI_MSI_ADDRESS_LO); 402 writel_relaxed(upper_32_bits(msi->vector_phy), 403 base + cap_offset + PCI_MSI_ADDRESS_HI); 404 } 405 406 static void mc_handle_msi(struct irq_desc *desc) 407 { 408 struct mc_pcie *port = irq_desc_get_handler_data(desc); 409 struct irq_chip *chip = irq_desc_get_chip(desc); 410 struct device *dev = port->dev; 411 struct mc_msi *msi = &port->msi; 412 void __iomem *bridge_base_addr = 413 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 414 unsigned long status; 415 u32 bit; 416 int ret; 417 418 chained_irq_enter(chip, desc); 419 420 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 421 if (status & PM_MSI_INT_MSI_MASK) { 422 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); 423 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); 424 for_each_set_bit(bit, &status, msi->num_vectors) { 425 ret = generic_handle_domain_irq(msi->dev_domain, bit); 426 if (ret) 427 dev_err_ratelimited(dev, "bad MSI IRQ %d\n", 428 bit); 429 } 430 } 431 432 chained_irq_exit(chip, desc); 433 } 434 435 static void mc_msi_bottom_irq_ack(struct irq_data *data) 436 { 437 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 438 void __iomem *bridge_base_addr = 439 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 440 u32 bitpos = data->hwirq; 441 442 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); 443 } 444 445 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 446 { 447 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 448 phys_addr_t addr = port->msi.vector_phy; 449 450 msg->address_lo = lower_32_bits(addr); 451 msg->address_hi = upper_32_bits(addr); 452 msg->data = data->hwirq; 453 454 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", 455 (int)data->hwirq, msg->address_hi, msg->address_lo); 456 } 457 458 static int mc_msi_set_affinity(struct irq_data *irq_data, 459 const struct cpumask *mask, bool force) 460 { 461 return -EINVAL; 462 } 463 464 static struct irq_chip mc_msi_bottom_irq_chip = { 465 .name = "Microchip MSI", 466 .irq_ack = mc_msi_bottom_irq_ack, 467 .irq_compose_msi_msg = mc_compose_msi_msg, 468 .irq_set_affinity = mc_msi_set_affinity, 469 }; 470 471 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 472 unsigned int nr_irqs, void *args) 473 { 474 struct mc_pcie *port = domain->host_data; 475 struct mc_msi *msi = &port->msi; 476 void __iomem *bridge_base_addr = 477 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 478 unsigned long bit; 479 u32 val; 480 481 mutex_lock(&msi->lock); 482 bit = find_first_zero_bit(msi->used, msi->num_vectors); 483 if (bit >= msi->num_vectors) { 484 mutex_unlock(&msi->lock); 485 return -ENOSPC; 486 } 487 488 set_bit(bit, msi->used); 489 490 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, 491 domain->host_data, handle_edge_irq, NULL, NULL); 492 493 /* Enable MSI interrupts */ 494 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 495 val |= PM_MSI_INT_MSI_MASK; 496 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 497 498 mutex_unlock(&msi->lock); 499 500 return 0; 501 } 502 503 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, 504 unsigned int nr_irqs) 505 { 506 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 507 struct mc_pcie *port = irq_data_get_irq_chip_data(d); 508 struct mc_msi *msi = &port->msi; 509 510 mutex_lock(&msi->lock); 511 512 if (test_bit(d->hwirq, msi->used)) 513 __clear_bit(d->hwirq, msi->used); 514 else 515 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); 516 517 mutex_unlock(&msi->lock); 518 } 519 520 static const struct irq_domain_ops msi_domain_ops = { 521 .alloc = mc_irq_msi_domain_alloc, 522 .free = mc_irq_msi_domain_free, 523 }; 524 525 static struct irq_chip mc_msi_irq_chip = { 526 .name = "Microchip PCIe MSI", 527 .irq_ack = irq_chip_ack_parent, 528 .irq_mask = pci_msi_mask_irq, 529 .irq_unmask = pci_msi_unmask_irq, 530 }; 531 532 static struct msi_domain_info mc_msi_domain_info = { 533 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 534 MSI_FLAG_PCI_MSIX), 535 .chip = &mc_msi_irq_chip, 536 }; 537 538 static int mc_allocate_msi_domains(struct mc_pcie *port) 539 { 540 struct device *dev = port->dev; 541 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 542 struct mc_msi *msi = &port->msi; 543 544 mutex_init(&port->msi.lock); 545 546 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, 547 &msi_domain_ops, port); 548 if (!msi->dev_domain) { 549 dev_err(dev, "failed to create IRQ domain\n"); 550 return -ENOMEM; 551 } 552 553 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, 554 msi->dev_domain); 555 if (!msi->msi_domain) { 556 dev_err(dev, "failed to create MSI domain\n"); 557 irq_domain_remove(msi->dev_domain); 558 return -ENOMEM; 559 } 560 561 return 0; 562 } 563 564 static void mc_handle_intx(struct irq_desc *desc) 565 { 566 struct mc_pcie *port = irq_desc_get_handler_data(desc); 567 struct irq_chip *chip = irq_desc_get_chip(desc); 568 struct device *dev = port->dev; 569 void __iomem *bridge_base_addr = 570 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 571 unsigned long status; 572 u32 bit; 573 int ret; 574 575 chained_irq_enter(chip, desc); 576 577 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 578 if (status & PM_MSI_INT_INTX_MASK) { 579 status &= PM_MSI_INT_INTX_MASK; 580 status >>= PM_MSI_INT_INTX_SHIFT; 581 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 582 ret = generic_handle_domain_irq(port->intx_domain, bit); 583 if (ret) 584 dev_err_ratelimited(dev, "bad INTx IRQ %d\n", 585 bit); 586 } 587 } 588 589 chained_irq_exit(chip, desc); 590 } 591 592 static void mc_ack_intx_irq(struct irq_data *data) 593 { 594 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 595 void __iomem *bridge_base_addr = 596 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 597 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 598 599 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); 600 } 601 602 static void mc_mask_intx_irq(struct irq_data *data) 603 { 604 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 605 void __iomem *bridge_base_addr = 606 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 607 unsigned long flags; 608 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 609 u32 val; 610 611 raw_spin_lock_irqsave(&port->lock, flags); 612 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 613 val &= ~mask; 614 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 615 raw_spin_unlock_irqrestore(&port->lock, flags); 616 } 617 618 static void mc_unmask_intx_irq(struct irq_data *data) 619 { 620 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 621 void __iomem *bridge_base_addr = 622 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 623 unsigned long flags; 624 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 625 u32 val; 626 627 raw_spin_lock_irqsave(&port->lock, flags); 628 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 629 val |= mask; 630 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 631 raw_spin_unlock_irqrestore(&port->lock, flags); 632 } 633 634 static struct irq_chip mc_intx_irq_chip = { 635 .name = "Microchip PCIe INTx", 636 .irq_ack = mc_ack_intx_irq, 637 .irq_mask = mc_mask_intx_irq, 638 .irq_unmask = mc_unmask_intx_irq, 639 }; 640 641 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 642 irq_hw_number_t hwirq) 643 { 644 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); 645 irq_set_chip_data(irq, domain->host_data); 646 647 return 0; 648 } 649 650 static const struct irq_domain_ops intx_domain_ops = { 651 .map = mc_pcie_intx_map, 652 }; 653 654 static inline u32 reg_to_event(u32 reg, struct event_map field) 655 { 656 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 657 } 658 659 static u32 pcie_events(struct mc_pcie *port) 660 { 661 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 662 u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); 663 u32 val = 0; 664 int i; 665 666 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 667 val |= reg_to_event(reg, pcie_event_to_event[i]); 668 669 return val; 670 } 671 672 static u32 sec_errors(struct mc_pcie *port) 673 { 674 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 675 u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); 676 u32 val = 0; 677 int i; 678 679 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 680 val |= reg_to_event(reg, sec_error_to_event[i]); 681 682 return val; 683 } 684 685 static u32 ded_errors(struct mc_pcie *port) 686 { 687 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 688 u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); 689 u32 val = 0; 690 int i; 691 692 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 693 val |= reg_to_event(reg, ded_error_to_event[i]); 694 695 return val; 696 } 697 698 static u32 local_events(struct mc_pcie *port) 699 { 700 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 701 u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 702 u32 val = 0; 703 int i; 704 705 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 706 val |= reg_to_event(reg, local_status_to_event[i]); 707 708 return val; 709 } 710 711 static u32 get_events(struct mc_pcie *port) 712 { 713 u32 events = 0; 714 715 events |= pcie_events(port); 716 events |= sec_errors(port); 717 events |= ded_errors(port); 718 events |= local_events(port); 719 720 return events; 721 } 722 723 static irqreturn_t mc_event_handler(int irq, void *dev_id) 724 { 725 struct mc_pcie *port = dev_id; 726 struct device *dev = port->dev; 727 struct irq_data *data; 728 729 data = irq_domain_get_irq_data(port->event_domain, irq); 730 731 if (event_cause[data->hwirq].str) 732 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 733 else 734 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 735 736 return IRQ_HANDLED; 737 } 738 739 static void mc_handle_event(struct irq_desc *desc) 740 { 741 struct mc_pcie *port = irq_desc_get_handler_data(desc); 742 unsigned long events; 743 u32 bit; 744 struct irq_chip *chip = irq_desc_get_chip(desc); 745 746 chained_irq_enter(chip, desc); 747 748 events = get_events(port); 749 750 for_each_set_bit(bit, &events, NUM_EVENTS) 751 generic_handle_domain_irq(port->event_domain, bit); 752 753 chained_irq_exit(chip, desc); 754 } 755 756 static void mc_ack_event_irq(struct irq_data *data) 757 { 758 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 759 u32 event = data->hwirq; 760 void __iomem *addr; 761 u32 mask; 762 763 addr = port->axi_base_addr + event_descs[event].base + 764 event_descs[event].offset; 765 mask = event_descs[event].mask; 766 mask |= event_descs[event].enb_mask; 767 768 writel_relaxed(mask, addr); 769 } 770 771 static void mc_mask_event_irq(struct irq_data *data) 772 { 773 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 774 u32 event = data->hwirq; 775 void __iomem *addr; 776 u32 mask; 777 u32 val; 778 779 addr = port->axi_base_addr + event_descs[event].base + 780 event_descs[event].mask_offset; 781 mask = event_descs[event].mask; 782 if (event_descs[event].enb_mask) { 783 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 784 mask &= PCIE_EVENT_INT_ENB_MASK; 785 } 786 787 if (!event_descs[event].mask_high) 788 mask = ~mask; 789 790 raw_spin_lock(&port->lock); 791 val = readl_relaxed(addr); 792 if (event_descs[event].mask_high) 793 val |= mask; 794 else 795 val &= mask; 796 797 writel_relaxed(val, addr); 798 raw_spin_unlock(&port->lock); 799 } 800 801 static void mc_unmask_event_irq(struct irq_data *data) 802 { 803 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 804 u32 event = data->hwirq; 805 void __iomem *addr; 806 u32 mask; 807 u32 val; 808 809 addr = port->axi_base_addr + event_descs[event].base + 810 event_descs[event].mask_offset; 811 mask = event_descs[event].mask; 812 813 if (event_descs[event].enb_mask) 814 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 815 816 if (event_descs[event].mask_high) 817 mask = ~mask; 818 819 if (event_descs[event].enb_mask) 820 mask &= PCIE_EVENT_INT_ENB_MASK; 821 822 raw_spin_lock(&port->lock); 823 val = readl_relaxed(addr); 824 if (event_descs[event].mask_high) 825 val &= mask; 826 else 827 val |= mask; 828 writel_relaxed(val, addr); 829 raw_spin_unlock(&port->lock); 830 } 831 832 static struct irq_chip mc_event_irq_chip = { 833 .name = "Microchip PCIe EVENT", 834 .irq_ack = mc_ack_event_irq, 835 .irq_mask = mc_mask_event_irq, 836 .irq_unmask = mc_unmask_event_irq, 837 }; 838 839 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, 840 irq_hw_number_t hwirq) 841 { 842 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); 843 irq_set_chip_data(irq, domain->host_data); 844 845 return 0; 846 } 847 848 static const struct irq_domain_ops event_domain_ops = { 849 .map = mc_pcie_event_map, 850 }; 851 852 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 853 { 854 struct clk *clk; 855 int ret; 856 857 clk = devm_clk_get_optional(dev, id); 858 if (IS_ERR(clk)) 859 return clk; 860 if (!clk) 861 return clk; 862 863 ret = clk_prepare_enable(clk); 864 if (ret) 865 return ERR_PTR(ret); 866 867 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, 868 clk); 869 870 return clk; 871 } 872 873 static int mc_pcie_init_clks(struct device *dev) 874 { 875 int i; 876 struct clk *fic; 877 878 /* 879 * PCIe may be clocked via Fabric Interface using between 1 and 4 880 * clocks. Scan DT for clocks and enable them if present 881 */ 882 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 883 fic = mc_pcie_init_clk(dev, poss_clks[i]); 884 if (IS_ERR(fic)) 885 return PTR_ERR(fic); 886 } 887 888 return 0; 889 } 890 891 static int mc_pcie_init_irq_domains(struct mc_pcie *port) 892 { 893 struct device *dev = port->dev; 894 struct device_node *node = dev->of_node; 895 struct device_node *pcie_intc_node; 896 897 /* Setup INTx */ 898 pcie_intc_node = of_get_next_child(node, NULL); 899 if (!pcie_intc_node) { 900 dev_err(dev, "failed to find PCIe Intc node\n"); 901 return -EINVAL; 902 } 903 904 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, 905 &event_domain_ops, port); 906 if (!port->event_domain) { 907 dev_err(dev, "failed to get event domain\n"); 908 of_node_put(pcie_intc_node); 909 return -ENOMEM; 910 } 911 912 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); 913 914 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 915 &intx_domain_ops, port); 916 if (!port->intx_domain) { 917 dev_err(dev, "failed to get an INTx IRQ domain\n"); 918 of_node_put(pcie_intc_node); 919 return -ENOMEM; 920 } 921 922 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); 923 924 of_node_put(pcie_intc_node); 925 raw_spin_lock_init(&port->lock); 926 927 return mc_allocate_msi_domains(port); 928 } 929 930 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, 931 phys_addr_t axi_addr, phys_addr_t pci_addr, 932 size_t size) 933 { 934 u32 atr_sz = ilog2(size) - 1; 935 u32 val; 936 937 if (index == 0) 938 val = PCIE_CONFIG_INTERFACE; 939 else 940 val = PCIE_TX_RX_INTERFACE; 941 942 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 943 ATR0_AXI4_SLV0_TRSL_PARAM); 944 945 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | 946 ATR_IMPL_ENABLE; 947 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 948 ATR0_AXI4_SLV0_SRCADDR_PARAM); 949 950 val = upper_32_bits(axi_addr); 951 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 952 ATR0_AXI4_SLV0_SRC_ADDR); 953 954 val = lower_32_bits(pci_addr); 955 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 956 ATR0_AXI4_SLV0_TRSL_ADDR_LSB); 957 958 val = upper_32_bits(pci_addr); 959 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 960 ATR0_AXI4_SLV0_TRSL_ADDR_UDW); 961 962 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 963 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); 964 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 965 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); 966 } 967 968 static int mc_pcie_setup_windows(struct platform_device *pdev, 969 struct mc_pcie *port) 970 { 971 void __iomem *bridge_base_addr = 972 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 973 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 974 struct resource_entry *entry; 975 u64 pci_addr; 976 u32 index = 1; 977 978 resource_list_for_each_entry(entry, &bridge->windows) { 979 if (resource_type(entry->res) == IORESOURCE_MEM) { 980 pci_addr = entry->res->start - entry->offset; 981 mc_pcie_setup_window(bridge_base_addr, index, 982 entry->res->start, pci_addr, 983 resource_size(entry->res)); 984 index++; 985 } 986 } 987 988 return 0; 989 } 990 991 static inline void mc_clear_secs(struct mc_pcie *port) 992 { 993 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 994 995 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + 996 SEC_ERROR_INT); 997 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT); 998 } 999 1000 static inline void mc_clear_deds(struct mc_pcie *port) 1001 { 1002 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 1003 1004 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + 1005 DED_ERROR_INT); 1006 writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT); 1007 } 1008 1009 static void mc_disable_interrupts(struct mc_pcie *port) 1010 { 1011 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1012 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 1013 u32 val; 1014 1015 /* Ensure ECC bypass is enabled */ 1016 val = ECC_CONTROL_TX_RAM_ECC_BYPASS | 1017 ECC_CONTROL_RX_RAM_ECC_BYPASS | 1018 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS | 1019 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS; 1020 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL); 1021 1022 /* Disable SEC errors and clear any outstanding */ 1023 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + 1024 SEC_ERROR_INT_MASK); 1025 mc_clear_secs(port); 1026 1027 /* Disable DED errors and clear any outstanding */ 1028 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + 1029 DED_ERROR_INT_MASK); 1030 mc_clear_deds(port); 1031 1032 /* Disable local interrupts and clear any outstanding */ 1033 writel_relaxed(0, bridge_base_addr + IMASK_LOCAL); 1034 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL); 1035 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI); 1036 1037 /* Disable PCIe events and clear any outstanding */ 1038 val = PCIE_EVENT_INT_L2_EXIT_INT | 1039 PCIE_EVENT_INT_HOTRST_EXIT_INT | 1040 PCIE_EVENT_INT_DLUP_EXIT_INT | 1041 PCIE_EVENT_INT_L2_EXIT_INT_MASK | 1042 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK | 1043 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK; 1044 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT); 1045 1046 /* Disable host interrupts and clear any outstanding */ 1047 writel_relaxed(0, bridge_base_addr + IMASK_HOST); 1048 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); 1049 } 1050 1051 static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) 1052 { 1053 struct device *dev = &pdev->dev; 1054 int irq; 1055 int i, intx_irq, msi_irq, event_irq; 1056 int ret; 1057 1058 ret = mc_pcie_init_irq_domains(port); 1059 if (ret) { 1060 dev_err(dev, "failed creating IRQ domains\n"); 1061 return ret; 1062 } 1063 1064 irq = platform_get_irq(pdev, 0); 1065 if (irq < 0) 1066 return -ENODEV; 1067 1068 for (i = 0; i < NUM_EVENTS; i++) { 1069 event_irq = irq_create_mapping(port->event_domain, i); 1070 if (!event_irq) { 1071 dev_err(dev, "failed to map hwirq %d\n", i); 1072 return -ENXIO; 1073 } 1074 1075 ret = devm_request_irq(dev, event_irq, mc_event_handler, 1076 0, event_cause[i].sym, port); 1077 if (ret) { 1078 dev_err(dev, "failed to request IRQ %d\n", event_irq); 1079 return ret; 1080 } 1081 } 1082 1083 intx_irq = irq_create_mapping(port->event_domain, 1084 EVENT_LOCAL_PM_MSI_INT_INTX); 1085 if (!intx_irq) { 1086 dev_err(dev, "failed to map INTx interrupt\n"); 1087 return -ENXIO; 1088 } 1089 1090 /* Plug the INTx chained handler */ 1091 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); 1092 1093 msi_irq = irq_create_mapping(port->event_domain, 1094 EVENT_LOCAL_PM_MSI_INT_MSI); 1095 if (!msi_irq) 1096 return -ENXIO; 1097 1098 /* Plug the MSI chained handler */ 1099 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); 1100 1101 /* Plug the main event chained handler */ 1102 irq_set_chained_handler_and_data(irq, mc_handle_event, port); 1103 1104 return 0; 1105 } 1106 1107 static int mc_platform_init(struct pci_config_window *cfg) 1108 { 1109 struct device *dev = cfg->parent; 1110 struct platform_device *pdev = to_platform_device(dev); 1111 struct mc_pcie *port; 1112 void __iomem *bridge_base_addr; 1113 int ret; 1114 1115 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1116 if (!port) 1117 return -ENOMEM; 1118 port->dev = dev; 1119 1120 ret = mc_pcie_init_clks(dev); 1121 if (ret) { 1122 dev_err(dev, "failed to get clock resources, error %d\n", ret); 1123 return -ENODEV; 1124 } 1125 1126 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); 1127 if (IS_ERR(port->axi_base_addr)) 1128 return PTR_ERR(port->axi_base_addr); 1129 1130 mc_disable_interrupts(port); 1131 1132 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1133 1134 port->msi.vector_phy = MSI_ADDR; 1135 port->msi.num_vectors = MC_NUM_MSI_IRQS; 1136 1137 /* Hardware doesn't setup MSI by default */ 1138 mc_pcie_enable_msi(port, cfg->win); 1139 1140 /* Configure Address Translation Table 0 for PCIe config space */ 1141 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, 1142 cfg->res.start, resource_size(&cfg->res)); 1143 1144 ret = mc_pcie_setup_windows(pdev, port); 1145 if (ret) 1146 return ret; 1147 1148 /* Address translation is up; safe to enable interrupts */ 1149 return mc_init_interrupts(pdev, port); 1150 } 1151 1152 static const struct pci_ecam_ops mc_ecam_ops = { 1153 .init = mc_platform_init, 1154 .pci_ops = { 1155 .map_bus = pci_ecam_map_bus, 1156 .read = pci_generic_config_read, 1157 .write = pci_generic_config_write, 1158 } 1159 }; 1160 1161 static const struct of_device_id mc_pcie_of_match[] = { 1162 { 1163 .compatible = "microchip,pcie-host-1.0", 1164 .data = &mc_ecam_ops, 1165 }, 1166 {}, 1167 }; 1168 1169 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 1170 1171 static struct platform_driver mc_pcie_driver = { 1172 .probe = pci_host_common_probe, 1173 .driver = { 1174 .name = "microchip-pcie", 1175 .of_match_table = mc_pcie_of_match, 1176 .suppress_bind_attrs = true, 1177 }, 1178 }; 1179 1180 builtin_platform_driver(mc_pcie_driver); 1181 MODULE_LICENSE("GPL"); 1182 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 1183 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 1184