1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/irqchip/chained_irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/module.h> 14 #include <linux/msi.h> 15 #include <linux/of_address.h> 16 #include <linux/of_pci.h> 17 #include <linux/pci-ecam.h> 18 #include <linux/platform_device.h> 19 20 #include "../pci.h" 21 22 /* Number of MSI IRQs */ 23 #define MC_NUM_MSI_IRQS 32 24 #define MC_NUM_MSI_IRQS_CODED 5 25 26 /* PCIe Bridge Phy and Controller Phy offsets */ 27 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 28 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 29 30 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) 31 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) 32 33 /* PCIe Bridge Phy Regs */ 34 #define IMASK_LOCAL 0x180 35 #define DMA_END_ENGINE_0_MASK 0x00000000u 36 #define DMA_END_ENGINE_0_SHIFT 0 37 #define DMA_END_ENGINE_1_MASK 0x00000000u 38 #define DMA_END_ENGINE_1_SHIFT 1 39 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u 40 #define DMA_ERROR_ENGINE_0_SHIFT 8 41 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u 42 #define DMA_ERROR_ENGINE_1_SHIFT 9 43 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u 44 #define A_ATR_EVT_POST_ERR_SHIFT 16 45 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u 46 #define A_ATR_EVT_FETCH_ERR_SHIFT 17 47 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u 48 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18 49 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u 50 #define A_ATR_EVT_DOORBELL_SHIFT 19 51 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u 52 #define P_ATR_EVT_POST_ERR_SHIFT 20 53 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u 54 #define P_ATR_EVT_FETCH_ERR_SHIFT 21 55 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u 56 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 57 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u 58 #define P_ATR_EVT_DOORBELL_SHIFT 23 59 #define PM_MSI_INT_INTA_MASK 0x01000000u 60 #define PM_MSI_INT_INTA_SHIFT 24 61 #define PM_MSI_INT_INTB_MASK 0x02000000u 62 #define PM_MSI_INT_INTB_SHIFT 25 63 #define PM_MSI_INT_INTC_MASK 0x04000000u 64 #define PM_MSI_INT_INTC_SHIFT 26 65 #define PM_MSI_INT_INTD_MASK 0x08000000u 66 #define PM_MSI_INT_INTD_SHIFT 27 67 #define PM_MSI_INT_INTX_MASK 0x0f000000u 68 #define PM_MSI_INT_INTX_SHIFT 24 69 #define PM_MSI_INT_MSI_MASK 0x10000000u 70 #define PM_MSI_INT_MSI_SHIFT 28 71 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u 72 #define PM_MSI_INT_AER_EVT_SHIFT 29 73 #define PM_MSI_INT_EVENTS_MASK 0x40000000u 74 #define PM_MSI_INT_EVENTS_SHIFT 30 75 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u 76 #define PM_MSI_INT_SYS_ERR_SHIFT 31 77 #define NUM_LOCAL_EVENTS 15 78 #define ISTATUS_LOCAL 0x184 79 #define IMASK_HOST 0x188 80 #define ISTATUS_HOST 0x18c 81 #define IMSI_ADDR 0x190 82 #define MSI_ADDR 0x190 83 #define ISTATUS_MSI 0x194 84 85 /* PCIe Master table init defines */ 86 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u 87 #define ATR0_PCIE_ATR_SIZE 0x25 88 #define ATR0_PCIE_ATR_SIZE_SHIFT 1 89 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u 90 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u 91 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu 92 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u 93 94 /* PCIe AXI slave table init defines */ 95 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u 96 #define ATR_SIZE_SHIFT 1 97 #define ATR_IMPL_ENABLE 1 98 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u 99 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u 100 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu 101 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u 102 #define PCIE_TX_RX_INTERFACE 0x00000000u 103 #define PCIE_CONFIG_INTERFACE 0x00000001u 104 105 #define ATR_ENTRY_SIZE 32 106 107 /* PCIe Controller Phy Regs */ 108 #define SEC_ERROR_EVENT_CNT 0x20 109 #define DED_ERROR_EVENT_CNT 0x24 110 #define SEC_ERROR_INT 0x28 111 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 112 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 113 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 114 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 115 #define NUM_SEC_ERROR_INTS (4) 116 #define SEC_ERROR_INT_MASK 0x2c 117 #define DED_ERROR_INT 0x30 118 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 119 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 120 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 121 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 122 #define NUM_DED_ERROR_INTS (4) 123 #define DED_ERROR_INT_MASK 0x34 124 #define ECC_CONTROL 0x38 125 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 126 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 127 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 128 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 129 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 130 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 131 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 132 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 133 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 134 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 135 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 136 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 137 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 138 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 139 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 140 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 141 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 142 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 143 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 144 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 145 #define PCIE_EVENT_INT 0x14c 146 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 147 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 148 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 149 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 150 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 151 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 152 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 153 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 154 #define PCIE_EVENT_INT_ENB_SHIFT 16 155 #define NUM_PCIE_EVENTS (3) 156 157 /* PCIe Config space MSI capability structure */ 158 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 159 #define MC_MSI_MAX_Q_AVAIL (MC_NUM_MSI_IRQS_CODED << 1) 160 #define MC_MSI_Q_SIZE (MC_NUM_MSI_IRQS_CODED << 4) 161 162 /* Events */ 163 #define EVENT_PCIE_L2_EXIT 0 164 #define EVENT_PCIE_HOTRST_EXIT 1 165 #define EVENT_PCIE_DLUP_EXIT 2 166 #define EVENT_SEC_TX_RAM_SEC_ERR 3 167 #define EVENT_SEC_RX_RAM_SEC_ERR 4 168 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 169 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 170 #define EVENT_DED_TX_RAM_DED_ERR 7 171 #define EVENT_DED_RX_RAM_DED_ERR 8 172 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 173 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 174 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 175 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 176 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 177 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 178 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 179 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 180 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 181 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 182 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 183 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 184 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 185 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 186 #define EVENT_LOCAL_PM_MSI_INT_INTX 23 187 #define EVENT_LOCAL_PM_MSI_INT_MSI 24 188 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 189 #define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 190 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 191 #define NUM_EVENTS 28 192 193 #define PCIE_EVENT_CAUSE(x, s) \ 194 [EVENT_PCIE_ ## x] = { __stringify(x), s } 195 196 #define SEC_ERROR_CAUSE(x, s) \ 197 [EVENT_SEC_ ## x] = { __stringify(x), s } 198 199 #define DED_ERROR_CAUSE(x, s) \ 200 [EVENT_DED_ ## x] = { __stringify(x), s } 201 202 #define LOCAL_EVENT_CAUSE(x, s) \ 203 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 204 205 #define PCIE_EVENT(x) \ 206 .base = MC_PCIE_CTRL_ADDR, \ 207 .offset = PCIE_EVENT_INT, \ 208 .mask_offset = PCIE_EVENT_INT, \ 209 .mask_high = 1, \ 210 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 211 .enb_mask = PCIE_EVENT_INT_ENB_MASK 212 213 #define SEC_EVENT(x) \ 214 .base = MC_PCIE_CTRL_ADDR, \ 215 .offset = SEC_ERROR_INT, \ 216 .mask_offset = SEC_ERROR_INT_MASK, \ 217 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 218 .mask_high = 1, \ 219 .enb_mask = 0 220 221 #define DED_EVENT(x) \ 222 .base = MC_PCIE_CTRL_ADDR, \ 223 .offset = DED_ERROR_INT, \ 224 .mask_offset = DED_ERROR_INT_MASK, \ 225 .mask_high = 1, \ 226 .mask = DED_ERROR_INT_ ## x ## _INT, \ 227 .enb_mask = 0 228 229 #define LOCAL_EVENT(x) \ 230 .base = MC_PCIE_BRIDGE_ADDR, \ 231 .offset = ISTATUS_LOCAL, \ 232 .mask_offset = IMASK_LOCAL, \ 233 .mask_high = 0, \ 234 .mask = x ## _MASK, \ 235 .enb_mask = 0 236 237 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 238 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 239 240 #define SEC_ERROR_TO_EVENT_MAP(x) \ 241 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 242 243 #define DED_ERROR_TO_EVENT_MAP(x) \ 244 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 245 246 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 247 { x ## _MASK, EVENT_LOCAL_ ## x } 248 249 struct event_map { 250 u32 reg_mask; 251 u32 event_bit; 252 }; 253 254 struct mc_msi { 255 struct mutex lock; /* Protect used bitmap */ 256 struct irq_domain *msi_domain; 257 struct irq_domain *dev_domain; 258 u32 num_vectors; 259 u64 vector_phy; 260 DECLARE_BITMAP(used, MC_NUM_MSI_IRQS); 261 }; 262 263 struct mc_pcie { 264 void __iomem *axi_base_addr; 265 struct device *dev; 266 struct irq_domain *intx_domain; 267 struct irq_domain *event_domain; 268 raw_spinlock_t lock; 269 struct mc_msi msi; 270 }; 271 272 struct cause { 273 const char *sym; 274 const char *str; 275 }; 276 277 static const struct cause event_cause[NUM_EVENTS] = { 278 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 279 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 280 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 281 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 282 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 283 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 284 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 285 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 286 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 287 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 288 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 289 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 290 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 291 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 292 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 293 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 294 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 295 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 296 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 297 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 298 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 299 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 300 }; 301 302 static struct event_map pcie_event_to_event[] = { 303 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 304 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 305 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 306 }; 307 308 static struct event_map sec_error_to_event[] = { 309 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 310 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 311 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 312 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 313 }; 314 315 static struct event_map ded_error_to_event[] = { 316 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 317 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 318 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 319 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 320 }; 321 322 static struct event_map local_status_to_event[] = { 323 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 324 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 325 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 326 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 327 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 328 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 329 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 330 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 331 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 332 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 333 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 334 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 335 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 336 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 337 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 338 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 340 }; 341 342 static struct { 343 u32 base; 344 u32 offset; 345 u32 mask; 346 u32 shift; 347 u32 enb_mask; 348 u32 mask_high; 349 u32 mask_offset; 350 } event_descs[] = { 351 { PCIE_EVENT(L2_EXIT) }, 352 { PCIE_EVENT(HOTRST_EXIT) }, 353 { PCIE_EVENT(DLUP_EXIT) }, 354 { SEC_EVENT(TX_RAM_SEC_ERR) }, 355 { SEC_EVENT(RX_RAM_SEC_ERR) }, 356 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 357 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 358 { DED_EVENT(TX_RAM_DED_ERR) }, 359 { DED_EVENT(RX_RAM_DED_ERR) }, 360 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 361 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 362 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 363 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 364 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 365 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 366 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 367 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 368 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 369 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 370 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 371 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 372 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 373 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 374 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 375 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 376 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 377 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 378 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 379 }; 380 381 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 382 383 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *base) 384 { 385 struct mc_msi *msi = &port->msi; 386 u32 cap_offset = MC_MSI_CAP_CTRL_OFFSET; 387 u16 msg_ctrl = readw_relaxed(base + cap_offset + PCI_MSI_FLAGS); 388 389 msg_ctrl |= PCI_MSI_FLAGS_ENABLE; 390 msg_ctrl &= ~PCI_MSI_FLAGS_QMASK; 391 msg_ctrl |= MC_MSI_MAX_Q_AVAIL; 392 msg_ctrl &= ~PCI_MSI_FLAGS_QSIZE; 393 msg_ctrl |= MC_MSI_Q_SIZE; 394 msg_ctrl |= PCI_MSI_FLAGS_64BIT; 395 396 writew_relaxed(msg_ctrl, base + cap_offset + PCI_MSI_FLAGS); 397 398 writel_relaxed(lower_32_bits(msi->vector_phy), 399 base + cap_offset + PCI_MSI_ADDRESS_LO); 400 writel_relaxed(upper_32_bits(msi->vector_phy), 401 base + cap_offset + PCI_MSI_ADDRESS_HI); 402 } 403 404 static void mc_handle_msi(struct irq_desc *desc) 405 { 406 struct mc_pcie *port = irq_desc_get_handler_data(desc); 407 struct irq_chip *chip = irq_desc_get_chip(desc); 408 struct device *dev = port->dev; 409 struct mc_msi *msi = &port->msi; 410 void __iomem *bridge_base_addr = 411 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 412 unsigned long status; 413 u32 bit; 414 int ret; 415 416 chained_irq_enter(chip, desc); 417 418 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 419 if (status & PM_MSI_INT_MSI_MASK) { 420 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); 421 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); 422 for_each_set_bit(bit, &status, msi->num_vectors) { 423 ret = generic_handle_domain_irq(msi->dev_domain, bit); 424 if (ret) 425 dev_err_ratelimited(dev, "bad MSI IRQ %d\n", 426 bit); 427 } 428 } 429 430 chained_irq_exit(chip, desc); 431 } 432 433 static void mc_msi_bottom_irq_ack(struct irq_data *data) 434 { 435 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 436 void __iomem *bridge_base_addr = 437 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 438 u32 bitpos = data->hwirq; 439 440 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); 441 } 442 443 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 444 { 445 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 446 phys_addr_t addr = port->msi.vector_phy; 447 448 msg->address_lo = lower_32_bits(addr); 449 msg->address_hi = upper_32_bits(addr); 450 msg->data = data->hwirq; 451 452 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", 453 (int)data->hwirq, msg->address_hi, msg->address_lo); 454 } 455 456 static int mc_msi_set_affinity(struct irq_data *irq_data, 457 const struct cpumask *mask, bool force) 458 { 459 return -EINVAL; 460 } 461 462 static struct irq_chip mc_msi_bottom_irq_chip = { 463 .name = "Microchip MSI", 464 .irq_ack = mc_msi_bottom_irq_ack, 465 .irq_compose_msi_msg = mc_compose_msi_msg, 466 .irq_set_affinity = mc_msi_set_affinity, 467 }; 468 469 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 470 unsigned int nr_irqs, void *args) 471 { 472 struct mc_pcie *port = domain->host_data; 473 struct mc_msi *msi = &port->msi; 474 void __iomem *bridge_base_addr = 475 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 476 unsigned long bit; 477 u32 val; 478 479 mutex_lock(&msi->lock); 480 bit = find_first_zero_bit(msi->used, msi->num_vectors); 481 if (bit >= msi->num_vectors) { 482 mutex_unlock(&msi->lock); 483 return -ENOSPC; 484 } 485 486 set_bit(bit, msi->used); 487 488 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, 489 domain->host_data, handle_edge_irq, NULL, NULL); 490 491 /* Enable MSI interrupts */ 492 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 493 val |= PM_MSI_INT_MSI_MASK; 494 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 495 496 mutex_unlock(&msi->lock); 497 498 return 0; 499 } 500 501 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, 502 unsigned int nr_irqs) 503 { 504 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 505 struct mc_pcie *port = irq_data_get_irq_chip_data(d); 506 struct mc_msi *msi = &port->msi; 507 508 mutex_lock(&msi->lock); 509 510 if (test_bit(d->hwirq, msi->used)) 511 __clear_bit(d->hwirq, msi->used); 512 else 513 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); 514 515 mutex_unlock(&msi->lock); 516 } 517 518 static const struct irq_domain_ops msi_domain_ops = { 519 .alloc = mc_irq_msi_domain_alloc, 520 .free = mc_irq_msi_domain_free, 521 }; 522 523 static struct irq_chip mc_msi_irq_chip = { 524 .name = "Microchip PCIe MSI", 525 .irq_ack = irq_chip_ack_parent, 526 .irq_mask = pci_msi_mask_irq, 527 .irq_unmask = pci_msi_unmask_irq, 528 }; 529 530 static struct msi_domain_info mc_msi_domain_info = { 531 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 532 MSI_FLAG_PCI_MSIX), 533 .chip = &mc_msi_irq_chip, 534 }; 535 536 static int mc_allocate_msi_domains(struct mc_pcie *port) 537 { 538 struct device *dev = port->dev; 539 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 540 struct mc_msi *msi = &port->msi; 541 542 mutex_init(&port->msi.lock); 543 544 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, 545 &msi_domain_ops, port); 546 if (!msi->dev_domain) { 547 dev_err(dev, "failed to create IRQ domain\n"); 548 return -ENOMEM; 549 } 550 551 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, 552 msi->dev_domain); 553 if (!msi->msi_domain) { 554 dev_err(dev, "failed to create MSI domain\n"); 555 irq_domain_remove(msi->dev_domain); 556 return -ENOMEM; 557 } 558 559 return 0; 560 } 561 562 static void mc_handle_intx(struct irq_desc *desc) 563 { 564 struct mc_pcie *port = irq_desc_get_handler_data(desc); 565 struct irq_chip *chip = irq_desc_get_chip(desc); 566 struct device *dev = port->dev; 567 void __iomem *bridge_base_addr = 568 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 569 unsigned long status; 570 u32 bit; 571 int ret; 572 573 chained_irq_enter(chip, desc); 574 575 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 576 if (status & PM_MSI_INT_INTX_MASK) { 577 status &= PM_MSI_INT_INTX_MASK; 578 status >>= PM_MSI_INT_INTX_SHIFT; 579 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 580 ret = generic_handle_domain_irq(port->intx_domain, bit); 581 if (ret) 582 dev_err_ratelimited(dev, "bad INTx IRQ %d\n", 583 bit); 584 } 585 } 586 587 chained_irq_exit(chip, desc); 588 } 589 590 static void mc_ack_intx_irq(struct irq_data *data) 591 { 592 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 593 void __iomem *bridge_base_addr = 594 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 595 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 596 597 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); 598 } 599 600 static void mc_mask_intx_irq(struct irq_data *data) 601 { 602 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 603 void __iomem *bridge_base_addr = 604 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 605 unsigned long flags; 606 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 607 u32 val; 608 609 raw_spin_lock_irqsave(&port->lock, flags); 610 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 611 val &= ~mask; 612 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 613 raw_spin_unlock_irqrestore(&port->lock, flags); 614 } 615 616 static void mc_unmask_intx_irq(struct irq_data *data) 617 { 618 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 619 void __iomem *bridge_base_addr = 620 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 621 unsigned long flags; 622 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 623 u32 val; 624 625 raw_spin_lock_irqsave(&port->lock, flags); 626 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 627 val |= mask; 628 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 629 raw_spin_unlock_irqrestore(&port->lock, flags); 630 } 631 632 static struct irq_chip mc_intx_irq_chip = { 633 .name = "Microchip PCIe INTx", 634 .irq_ack = mc_ack_intx_irq, 635 .irq_mask = mc_mask_intx_irq, 636 .irq_unmask = mc_unmask_intx_irq, 637 }; 638 639 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 640 irq_hw_number_t hwirq) 641 { 642 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); 643 irq_set_chip_data(irq, domain->host_data); 644 645 return 0; 646 } 647 648 static const struct irq_domain_ops intx_domain_ops = { 649 .map = mc_pcie_intx_map, 650 }; 651 652 static inline u32 reg_to_event(u32 reg, struct event_map field) 653 { 654 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 655 } 656 657 static u32 pcie_events(void __iomem *addr) 658 { 659 u32 reg = readl_relaxed(addr); 660 u32 val = 0; 661 int i; 662 663 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 664 val |= reg_to_event(reg, pcie_event_to_event[i]); 665 666 return val; 667 } 668 669 static u32 sec_errors(void __iomem *addr) 670 { 671 u32 reg = readl_relaxed(addr); 672 u32 val = 0; 673 int i; 674 675 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 676 val |= reg_to_event(reg, sec_error_to_event[i]); 677 678 return val; 679 } 680 681 static u32 ded_errors(void __iomem *addr) 682 { 683 u32 reg = readl_relaxed(addr); 684 u32 val = 0; 685 int i; 686 687 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 688 val |= reg_to_event(reg, ded_error_to_event[i]); 689 690 return val; 691 } 692 693 static u32 local_events(void __iomem *addr) 694 { 695 u32 reg = readl_relaxed(addr); 696 u32 val = 0; 697 int i; 698 699 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 700 val |= reg_to_event(reg, local_status_to_event[i]); 701 702 return val; 703 } 704 705 static u32 get_events(struct mc_pcie *port) 706 { 707 void __iomem *bridge_base_addr = 708 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 709 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 710 u32 events = 0; 711 712 events |= pcie_events(ctrl_base_addr + PCIE_EVENT_INT); 713 events |= sec_errors(ctrl_base_addr + SEC_ERROR_INT); 714 events |= ded_errors(ctrl_base_addr + DED_ERROR_INT); 715 events |= local_events(bridge_base_addr + ISTATUS_LOCAL); 716 717 return events; 718 } 719 720 static irqreturn_t mc_event_handler(int irq, void *dev_id) 721 { 722 struct mc_pcie *port = dev_id; 723 struct device *dev = port->dev; 724 struct irq_data *data; 725 726 data = irq_domain_get_irq_data(port->event_domain, irq); 727 728 if (event_cause[data->hwirq].str) 729 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 730 else 731 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 732 733 return IRQ_HANDLED; 734 } 735 736 static void mc_handle_event(struct irq_desc *desc) 737 { 738 struct mc_pcie *port = irq_desc_get_handler_data(desc); 739 unsigned long events; 740 u32 bit; 741 struct irq_chip *chip = irq_desc_get_chip(desc); 742 743 chained_irq_enter(chip, desc); 744 745 events = get_events(port); 746 747 for_each_set_bit(bit, &events, NUM_EVENTS) 748 generic_handle_domain_irq(port->event_domain, bit); 749 750 chained_irq_exit(chip, desc); 751 } 752 753 static void mc_ack_event_irq(struct irq_data *data) 754 { 755 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 756 u32 event = data->hwirq; 757 void __iomem *addr; 758 u32 mask; 759 760 addr = port->axi_base_addr + event_descs[event].base + 761 event_descs[event].offset; 762 mask = event_descs[event].mask; 763 mask |= event_descs[event].enb_mask; 764 765 writel_relaxed(mask, addr); 766 } 767 768 static void mc_mask_event_irq(struct irq_data *data) 769 { 770 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 771 u32 event = data->hwirq; 772 void __iomem *addr; 773 u32 mask; 774 u32 val; 775 776 addr = port->axi_base_addr + event_descs[event].base + 777 event_descs[event].mask_offset; 778 mask = event_descs[event].mask; 779 if (event_descs[event].enb_mask) { 780 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 781 mask &= PCIE_EVENT_INT_ENB_MASK; 782 } 783 784 if (!event_descs[event].mask_high) 785 mask = ~mask; 786 787 raw_spin_lock(&port->lock); 788 val = readl_relaxed(addr); 789 if (event_descs[event].mask_high) 790 val |= mask; 791 else 792 val &= mask; 793 794 writel_relaxed(val, addr); 795 raw_spin_unlock(&port->lock); 796 } 797 798 static void mc_unmask_event_irq(struct irq_data *data) 799 { 800 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 801 u32 event = data->hwirq; 802 void __iomem *addr; 803 u32 mask; 804 u32 val; 805 806 addr = port->axi_base_addr + event_descs[event].base + 807 event_descs[event].mask_offset; 808 mask = event_descs[event].mask; 809 810 if (event_descs[event].enb_mask) 811 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 812 813 if (event_descs[event].mask_high) 814 mask = ~mask; 815 816 if (event_descs[event].enb_mask) 817 mask &= PCIE_EVENT_INT_ENB_MASK; 818 819 raw_spin_lock(&port->lock); 820 val = readl_relaxed(addr); 821 if (event_descs[event].mask_high) 822 val &= mask; 823 else 824 val |= mask; 825 writel_relaxed(val, addr); 826 raw_spin_unlock(&port->lock); 827 } 828 829 static struct irq_chip mc_event_irq_chip = { 830 .name = "Microchip PCIe EVENT", 831 .irq_ack = mc_ack_event_irq, 832 .irq_mask = mc_mask_event_irq, 833 .irq_unmask = mc_unmask_event_irq, 834 }; 835 836 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, 837 irq_hw_number_t hwirq) 838 { 839 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); 840 irq_set_chip_data(irq, domain->host_data); 841 842 return 0; 843 } 844 845 static const struct irq_domain_ops event_domain_ops = { 846 .map = mc_pcie_event_map, 847 }; 848 849 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 850 { 851 struct clk *clk; 852 int ret; 853 854 clk = devm_clk_get_optional(dev, id); 855 if (IS_ERR(clk)) 856 return clk; 857 if (!clk) 858 return clk; 859 860 ret = clk_prepare_enable(clk); 861 if (ret) 862 return ERR_PTR(ret); 863 864 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, 865 clk); 866 867 return clk; 868 } 869 870 static int mc_pcie_init_clks(struct device *dev) 871 { 872 int i; 873 struct clk *fic; 874 875 /* 876 * PCIe may be clocked via Fabric Interface using between 1 and 4 877 * clocks. Scan DT for clocks and enable them if present 878 */ 879 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 880 fic = mc_pcie_init_clk(dev, poss_clks[i]); 881 if (IS_ERR(fic)) 882 return PTR_ERR(fic); 883 } 884 885 return 0; 886 } 887 888 static int mc_pcie_init_irq_domains(struct mc_pcie *port) 889 { 890 struct device *dev = port->dev; 891 struct device_node *node = dev->of_node; 892 struct device_node *pcie_intc_node; 893 894 /* Setup INTx */ 895 pcie_intc_node = of_get_next_child(node, NULL); 896 if (!pcie_intc_node) { 897 dev_err(dev, "failed to find PCIe Intc node\n"); 898 return -EINVAL; 899 } 900 901 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, 902 &event_domain_ops, port); 903 if (!port->event_domain) { 904 dev_err(dev, "failed to get event domain\n"); 905 of_node_put(pcie_intc_node); 906 return -ENOMEM; 907 } 908 909 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); 910 911 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 912 &intx_domain_ops, port); 913 if (!port->intx_domain) { 914 dev_err(dev, "failed to get an INTx IRQ domain\n"); 915 of_node_put(pcie_intc_node); 916 return -ENOMEM; 917 } 918 919 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); 920 921 of_node_put(pcie_intc_node); 922 raw_spin_lock_init(&port->lock); 923 924 return mc_allocate_msi_domains(port); 925 } 926 927 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, 928 phys_addr_t axi_addr, phys_addr_t pci_addr, 929 size_t size) 930 { 931 u32 atr_sz = ilog2(size) - 1; 932 u32 val; 933 934 if (index == 0) 935 val = PCIE_CONFIG_INTERFACE; 936 else 937 val = PCIE_TX_RX_INTERFACE; 938 939 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 940 ATR0_AXI4_SLV0_TRSL_PARAM); 941 942 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | 943 ATR_IMPL_ENABLE; 944 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 945 ATR0_AXI4_SLV0_SRCADDR_PARAM); 946 947 val = upper_32_bits(axi_addr); 948 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 949 ATR0_AXI4_SLV0_SRC_ADDR); 950 951 val = lower_32_bits(pci_addr); 952 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 953 ATR0_AXI4_SLV0_TRSL_ADDR_LSB); 954 955 val = upper_32_bits(pci_addr); 956 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 957 ATR0_AXI4_SLV0_TRSL_ADDR_UDW); 958 959 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 960 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); 961 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 962 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); 963 } 964 965 static int mc_pcie_setup_windows(struct platform_device *pdev, 966 struct mc_pcie *port) 967 { 968 void __iomem *bridge_base_addr = 969 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 970 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 971 struct resource_entry *entry; 972 u64 pci_addr; 973 u32 index = 1; 974 975 resource_list_for_each_entry(entry, &bridge->windows) { 976 if (resource_type(entry->res) == IORESOURCE_MEM) { 977 pci_addr = entry->res->start - entry->offset; 978 mc_pcie_setup_window(bridge_base_addr, index, 979 entry->res->start, pci_addr, 980 resource_size(entry->res)); 981 index++; 982 } 983 } 984 985 return 0; 986 } 987 988 static int mc_platform_init(struct pci_config_window *cfg) 989 { 990 struct device *dev = cfg->parent; 991 struct platform_device *pdev = to_platform_device(dev); 992 struct mc_pcie *port; 993 void __iomem *bridge_base_addr; 994 void __iomem *ctrl_base_addr; 995 int ret; 996 int irq; 997 int i, intx_irq, msi_irq, event_irq; 998 u32 val; 999 int err; 1000 1001 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1002 if (!port) 1003 return -ENOMEM; 1004 port->dev = dev; 1005 1006 ret = mc_pcie_init_clks(dev); 1007 if (ret) { 1008 dev_err(dev, "failed to get clock resources, error %d\n", ret); 1009 return -ENODEV; 1010 } 1011 1012 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); 1013 if (IS_ERR(port->axi_base_addr)) 1014 return PTR_ERR(port->axi_base_addr); 1015 1016 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1017 ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 1018 1019 port->msi.vector_phy = MSI_ADDR; 1020 port->msi.num_vectors = MC_NUM_MSI_IRQS; 1021 ret = mc_pcie_init_irq_domains(port); 1022 if (ret) { 1023 dev_err(dev, "failed creating IRQ domains\n"); 1024 return ret; 1025 } 1026 1027 irq = platform_get_irq(pdev, 0); 1028 if (irq < 0) 1029 return -ENODEV; 1030 1031 for (i = 0; i < NUM_EVENTS; i++) { 1032 event_irq = irq_create_mapping(port->event_domain, i); 1033 if (!event_irq) { 1034 dev_err(dev, "failed to map hwirq %d\n", i); 1035 return -ENXIO; 1036 } 1037 1038 err = devm_request_irq(dev, event_irq, mc_event_handler, 1039 0, event_cause[i].sym, port); 1040 if (err) { 1041 dev_err(dev, "failed to request IRQ %d\n", event_irq); 1042 return err; 1043 } 1044 } 1045 1046 intx_irq = irq_create_mapping(port->event_domain, 1047 EVENT_LOCAL_PM_MSI_INT_INTX); 1048 if (!intx_irq) { 1049 dev_err(dev, "failed to map INTx interrupt\n"); 1050 return -ENXIO; 1051 } 1052 1053 /* Plug the INTx chained handler */ 1054 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); 1055 1056 msi_irq = irq_create_mapping(port->event_domain, 1057 EVENT_LOCAL_PM_MSI_INT_MSI); 1058 if (!msi_irq) 1059 return -ENXIO; 1060 1061 /* Plug the MSI chained handler */ 1062 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); 1063 1064 /* Plug the main event chained handler */ 1065 irq_set_chained_handler_and_data(irq, mc_handle_event, port); 1066 1067 /* Hardware doesn't setup MSI by default */ 1068 mc_pcie_enable_msi(port, cfg->win); 1069 1070 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 1071 val |= PM_MSI_INT_INTX_MASK; 1072 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 1073 1074 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL); 1075 1076 val = PCIE_EVENT_INT_L2_EXIT_INT | 1077 PCIE_EVENT_INT_HOTRST_EXIT_INT | 1078 PCIE_EVENT_INT_DLUP_EXIT_INT; 1079 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT); 1080 1081 val = SEC_ERROR_INT_TX_RAM_SEC_ERR_INT | 1082 SEC_ERROR_INT_RX_RAM_SEC_ERR_INT | 1083 SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT | 1084 SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT; 1085 writel_relaxed(val, ctrl_base_addr + SEC_ERROR_INT); 1086 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_INT_MASK); 1087 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT); 1088 1089 val = DED_ERROR_INT_TX_RAM_DED_ERR_INT | 1090 DED_ERROR_INT_RX_RAM_DED_ERR_INT | 1091 DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT | 1092 DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT; 1093 writel_relaxed(val, ctrl_base_addr + DED_ERROR_INT); 1094 writel_relaxed(0, ctrl_base_addr + DED_ERROR_INT_MASK); 1095 writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT); 1096 1097 writel_relaxed(0, bridge_base_addr + IMASK_HOST); 1098 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); 1099 1100 /* Configure Address Translation Table 0 for PCIe config space */ 1101 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, 1102 cfg->res.start, resource_size(&cfg->res)); 1103 1104 return mc_pcie_setup_windows(pdev, port); 1105 } 1106 1107 static const struct pci_ecam_ops mc_ecam_ops = { 1108 .init = mc_platform_init, 1109 .pci_ops = { 1110 .map_bus = pci_ecam_map_bus, 1111 .read = pci_generic_config_read, 1112 .write = pci_generic_config_write, 1113 } 1114 }; 1115 1116 static const struct of_device_id mc_pcie_of_match[] = { 1117 { 1118 .compatible = "microchip,pcie-host-1.0", 1119 .data = &mc_ecam_ops, 1120 }, 1121 {}, 1122 }; 1123 1124 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 1125 1126 static struct platform_driver mc_pcie_driver = { 1127 .probe = pci_host_common_probe, 1128 .driver = { 1129 .name = "microchip-pcie", 1130 .of_match_table = mc_pcie_of_match, 1131 .suppress_bind_attrs = true, 1132 }, 1133 }; 1134 1135 builtin_platform_driver(mc_pcie_driver); 1136 MODULE_LICENSE("GPL"); 1137 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 1138 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 1139