1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip AXI PCIe Bridge host controller driver 4 * 5 * Copyright (c) 2018 - 2020 Microchip Corporation. All rights reserved. 6 * 7 * Author: Daire McNamara <daire.mcnamara@microchip.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/msi.h> 16 #include <linux/of_address.h> 17 #include <linux/of_pci.h> 18 #include <linux/pci-ecam.h> 19 #include <linux/platform_device.h> 20 21 #include "../pci.h" 22 23 /* Number of MSI IRQs */ 24 #define MC_MAX_NUM_MSI_IRQS 32 25 26 /* PCIe Bridge Phy and Controller Phy offsets */ 27 #define MC_PCIE1_BRIDGE_ADDR 0x00008000u 28 #define MC_PCIE1_CTRL_ADDR 0x0000a000u 29 30 #define MC_PCIE_BRIDGE_ADDR (MC_PCIE1_BRIDGE_ADDR) 31 #define MC_PCIE_CTRL_ADDR (MC_PCIE1_CTRL_ADDR) 32 33 /* PCIe Bridge Phy Regs */ 34 #define PCIE_PCI_IRQ_DW0 0xa8 35 #define MSIX_CAP_MASK BIT(31) 36 #define NUM_MSI_MSGS_MASK GENMASK(6, 4) 37 #define NUM_MSI_MSGS_SHIFT 4 38 39 #define IMASK_LOCAL 0x180 40 #define DMA_END_ENGINE_0_MASK 0x00000000u 41 #define DMA_END_ENGINE_0_SHIFT 0 42 #define DMA_END_ENGINE_1_MASK 0x00000000u 43 #define DMA_END_ENGINE_1_SHIFT 1 44 #define DMA_ERROR_ENGINE_0_MASK 0x00000100u 45 #define DMA_ERROR_ENGINE_0_SHIFT 8 46 #define DMA_ERROR_ENGINE_1_MASK 0x00000200u 47 #define DMA_ERROR_ENGINE_1_SHIFT 9 48 #define A_ATR_EVT_POST_ERR_MASK 0x00010000u 49 #define A_ATR_EVT_POST_ERR_SHIFT 16 50 #define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u 51 #define A_ATR_EVT_FETCH_ERR_SHIFT 17 52 #define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u 53 #define A_ATR_EVT_DISCARD_ERR_SHIFT 18 54 #define A_ATR_EVT_DOORBELL_MASK 0x00000000u 55 #define A_ATR_EVT_DOORBELL_SHIFT 19 56 #define P_ATR_EVT_POST_ERR_MASK 0x00100000u 57 #define P_ATR_EVT_POST_ERR_SHIFT 20 58 #define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u 59 #define P_ATR_EVT_FETCH_ERR_SHIFT 21 60 #define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u 61 #define P_ATR_EVT_DISCARD_ERR_SHIFT 22 62 #define P_ATR_EVT_DOORBELL_MASK 0x00000000u 63 #define P_ATR_EVT_DOORBELL_SHIFT 23 64 #define PM_MSI_INT_INTA_MASK 0x01000000u 65 #define PM_MSI_INT_INTA_SHIFT 24 66 #define PM_MSI_INT_INTB_MASK 0x02000000u 67 #define PM_MSI_INT_INTB_SHIFT 25 68 #define PM_MSI_INT_INTC_MASK 0x04000000u 69 #define PM_MSI_INT_INTC_SHIFT 26 70 #define PM_MSI_INT_INTD_MASK 0x08000000u 71 #define PM_MSI_INT_INTD_SHIFT 27 72 #define PM_MSI_INT_INTX_MASK 0x0f000000u 73 #define PM_MSI_INT_INTX_SHIFT 24 74 #define PM_MSI_INT_MSI_MASK 0x10000000u 75 #define PM_MSI_INT_MSI_SHIFT 28 76 #define PM_MSI_INT_AER_EVT_MASK 0x20000000u 77 #define PM_MSI_INT_AER_EVT_SHIFT 29 78 #define PM_MSI_INT_EVENTS_MASK 0x40000000u 79 #define PM_MSI_INT_EVENTS_SHIFT 30 80 #define PM_MSI_INT_SYS_ERR_MASK 0x80000000u 81 #define PM_MSI_INT_SYS_ERR_SHIFT 31 82 #define NUM_LOCAL_EVENTS 15 83 #define ISTATUS_LOCAL 0x184 84 #define IMASK_HOST 0x188 85 #define ISTATUS_HOST 0x18c 86 #define IMSI_ADDR 0x190 87 #define ISTATUS_MSI 0x194 88 89 /* PCIe Master table init defines */ 90 #define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u 91 #define ATR0_PCIE_ATR_SIZE 0x25 92 #define ATR0_PCIE_ATR_SIZE_SHIFT 1 93 #define ATR0_PCIE_WIN0_SRC_ADDR 0x604u 94 #define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u 95 #define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu 96 #define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u 97 98 /* PCIe AXI slave table init defines */ 99 #define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u 100 #define ATR_SIZE_SHIFT 1 101 #define ATR_IMPL_ENABLE 1 102 #define ATR0_AXI4_SLV0_SRC_ADDR 0x804u 103 #define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u 104 #define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu 105 #define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u 106 #define PCIE_TX_RX_INTERFACE 0x00000000u 107 #define PCIE_CONFIG_INTERFACE 0x00000001u 108 109 #define ATR_ENTRY_SIZE 32 110 111 /* PCIe Controller Phy Regs */ 112 #define SEC_ERROR_EVENT_CNT 0x20 113 #define DED_ERROR_EVENT_CNT 0x24 114 #define SEC_ERROR_INT 0x28 115 #define SEC_ERROR_INT_TX_RAM_SEC_ERR_INT GENMASK(3, 0) 116 #define SEC_ERROR_INT_RX_RAM_SEC_ERR_INT GENMASK(7, 4) 117 #define SEC_ERROR_INT_PCIE2AXI_RAM_SEC_ERR_INT GENMASK(11, 8) 118 #define SEC_ERROR_INT_AXI2PCIE_RAM_SEC_ERR_INT GENMASK(15, 12) 119 #define SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT GENMASK(15, 0) 120 #define NUM_SEC_ERROR_INTS (4) 121 #define SEC_ERROR_INT_MASK 0x2c 122 #define DED_ERROR_INT 0x30 123 #define DED_ERROR_INT_TX_RAM_DED_ERR_INT GENMASK(3, 0) 124 #define DED_ERROR_INT_RX_RAM_DED_ERR_INT GENMASK(7, 4) 125 #define DED_ERROR_INT_PCIE2AXI_RAM_DED_ERR_INT GENMASK(11, 8) 126 #define DED_ERROR_INT_AXI2PCIE_RAM_DED_ERR_INT GENMASK(15, 12) 127 #define DED_ERROR_INT_ALL_RAM_DED_ERR_INT GENMASK(15, 0) 128 #define NUM_DED_ERROR_INTS (4) 129 #define DED_ERROR_INT_MASK 0x34 130 #define ECC_CONTROL 0x38 131 #define ECC_CONTROL_TX_RAM_INJ_ERROR_0 BIT(0) 132 #define ECC_CONTROL_TX_RAM_INJ_ERROR_1 BIT(1) 133 #define ECC_CONTROL_TX_RAM_INJ_ERROR_2 BIT(2) 134 #define ECC_CONTROL_TX_RAM_INJ_ERROR_3 BIT(3) 135 #define ECC_CONTROL_RX_RAM_INJ_ERROR_0 BIT(4) 136 #define ECC_CONTROL_RX_RAM_INJ_ERROR_1 BIT(5) 137 #define ECC_CONTROL_RX_RAM_INJ_ERROR_2 BIT(6) 138 #define ECC_CONTROL_RX_RAM_INJ_ERROR_3 BIT(7) 139 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_0 BIT(8) 140 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_1 BIT(9) 141 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_2 BIT(10) 142 #define ECC_CONTROL_PCIE2AXI_RAM_INJ_ERROR_3 BIT(11) 143 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_0 BIT(12) 144 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_1 BIT(13) 145 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_2 BIT(14) 146 #define ECC_CONTROL_AXI2PCIE_RAM_INJ_ERROR_3 BIT(15) 147 #define ECC_CONTROL_TX_RAM_ECC_BYPASS BIT(24) 148 #define ECC_CONTROL_RX_RAM_ECC_BYPASS BIT(25) 149 #define ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS BIT(26) 150 #define ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS BIT(27) 151 #define PCIE_EVENT_INT 0x14c 152 #define PCIE_EVENT_INT_L2_EXIT_INT BIT(0) 153 #define PCIE_EVENT_INT_HOTRST_EXIT_INT BIT(1) 154 #define PCIE_EVENT_INT_DLUP_EXIT_INT BIT(2) 155 #define PCIE_EVENT_INT_MASK GENMASK(2, 0) 156 #define PCIE_EVENT_INT_L2_EXIT_INT_MASK BIT(16) 157 #define PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK BIT(17) 158 #define PCIE_EVENT_INT_DLUP_EXIT_INT_MASK BIT(18) 159 #define PCIE_EVENT_INT_ENB_MASK GENMASK(18, 16) 160 #define PCIE_EVENT_INT_ENB_SHIFT 16 161 #define NUM_PCIE_EVENTS (3) 162 163 /* PCIe Config space MSI capability structure */ 164 #define MC_MSI_CAP_CTRL_OFFSET 0xe0u 165 166 /* Events */ 167 #define EVENT_PCIE_L2_EXIT 0 168 #define EVENT_PCIE_HOTRST_EXIT 1 169 #define EVENT_PCIE_DLUP_EXIT 2 170 #define EVENT_SEC_TX_RAM_SEC_ERR 3 171 #define EVENT_SEC_RX_RAM_SEC_ERR 4 172 #define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5 173 #define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6 174 #define EVENT_DED_TX_RAM_DED_ERR 7 175 #define EVENT_DED_RX_RAM_DED_ERR 8 176 #define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9 177 #define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10 178 #define EVENT_LOCAL_DMA_END_ENGINE_0 11 179 #define EVENT_LOCAL_DMA_END_ENGINE_1 12 180 #define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13 181 #define EVENT_LOCAL_DMA_ERROR_ENGINE_1 14 182 #define EVENT_LOCAL_A_ATR_EVT_POST_ERR 15 183 #define EVENT_LOCAL_A_ATR_EVT_FETCH_ERR 16 184 #define EVENT_LOCAL_A_ATR_EVT_DISCARD_ERR 17 185 #define EVENT_LOCAL_A_ATR_EVT_DOORBELL 18 186 #define EVENT_LOCAL_P_ATR_EVT_POST_ERR 19 187 #define EVENT_LOCAL_P_ATR_EVT_FETCH_ERR 20 188 #define EVENT_LOCAL_P_ATR_EVT_DISCARD_ERR 21 189 #define EVENT_LOCAL_P_ATR_EVT_DOORBELL 22 190 #define EVENT_LOCAL_PM_MSI_INT_INTX 23 191 #define EVENT_LOCAL_PM_MSI_INT_MSI 24 192 #define EVENT_LOCAL_PM_MSI_INT_AER_EVT 25 193 #define EVENT_LOCAL_PM_MSI_INT_EVENTS 26 194 #define EVENT_LOCAL_PM_MSI_INT_SYS_ERR 27 195 #define NUM_EVENTS 28 196 197 #define PCIE_EVENT_CAUSE(x, s) \ 198 [EVENT_PCIE_ ## x] = { __stringify(x), s } 199 200 #define SEC_ERROR_CAUSE(x, s) \ 201 [EVENT_SEC_ ## x] = { __stringify(x), s } 202 203 #define DED_ERROR_CAUSE(x, s) \ 204 [EVENT_DED_ ## x] = { __stringify(x), s } 205 206 #define LOCAL_EVENT_CAUSE(x, s) \ 207 [EVENT_LOCAL_ ## x] = { __stringify(x), s } 208 209 #define PCIE_EVENT(x) \ 210 .base = MC_PCIE_CTRL_ADDR, \ 211 .offset = PCIE_EVENT_INT, \ 212 .mask_offset = PCIE_EVENT_INT, \ 213 .mask_high = 1, \ 214 .mask = PCIE_EVENT_INT_ ## x ## _INT, \ 215 .enb_mask = PCIE_EVENT_INT_ENB_MASK 216 217 #define SEC_EVENT(x) \ 218 .base = MC_PCIE_CTRL_ADDR, \ 219 .offset = SEC_ERROR_INT, \ 220 .mask_offset = SEC_ERROR_INT_MASK, \ 221 .mask = SEC_ERROR_INT_ ## x ## _INT, \ 222 .mask_high = 1, \ 223 .enb_mask = 0 224 225 #define DED_EVENT(x) \ 226 .base = MC_PCIE_CTRL_ADDR, \ 227 .offset = DED_ERROR_INT, \ 228 .mask_offset = DED_ERROR_INT_MASK, \ 229 .mask_high = 1, \ 230 .mask = DED_ERROR_INT_ ## x ## _INT, \ 231 .enb_mask = 0 232 233 #define LOCAL_EVENT(x) \ 234 .base = MC_PCIE_BRIDGE_ADDR, \ 235 .offset = ISTATUS_LOCAL, \ 236 .mask_offset = IMASK_LOCAL, \ 237 .mask_high = 0, \ 238 .mask = x ## _MASK, \ 239 .enb_mask = 0 240 241 #define PCIE_EVENT_TO_EVENT_MAP(x) \ 242 { PCIE_EVENT_INT_ ## x ## _INT, EVENT_PCIE_ ## x } 243 244 #define SEC_ERROR_TO_EVENT_MAP(x) \ 245 { SEC_ERROR_INT_ ## x ## _INT, EVENT_SEC_ ## x } 246 247 #define DED_ERROR_TO_EVENT_MAP(x) \ 248 { DED_ERROR_INT_ ## x ## _INT, EVENT_DED_ ## x } 249 250 #define LOCAL_STATUS_TO_EVENT_MAP(x) \ 251 { x ## _MASK, EVENT_LOCAL_ ## x } 252 253 struct event_map { 254 u32 reg_mask; 255 u32 event_bit; 256 }; 257 258 struct mc_msi { 259 struct mutex lock; /* Protect used bitmap */ 260 struct irq_domain *msi_domain; 261 struct irq_domain *dev_domain; 262 u32 num_vectors; 263 u64 vector_phy; 264 DECLARE_BITMAP(used, MC_MAX_NUM_MSI_IRQS); 265 }; 266 267 struct mc_pcie { 268 void __iomem *axi_base_addr; 269 struct device *dev; 270 struct irq_domain *intx_domain; 271 struct irq_domain *event_domain; 272 raw_spinlock_t lock; 273 struct mc_msi msi; 274 }; 275 276 struct cause { 277 const char *sym; 278 const char *str; 279 }; 280 281 static const struct cause event_cause[NUM_EVENTS] = { 282 PCIE_EVENT_CAUSE(L2_EXIT, "L2 exit event"), 283 PCIE_EVENT_CAUSE(HOTRST_EXIT, "Hot reset exit event"), 284 PCIE_EVENT_CAUSE(DLUP_EXIT, "DLUP exit event"), 285 SEC_ERROR_CAUSE(TX_RAM_SEC_ERR, "sec error in tx buffer"), 286 SEC_ERROR_CAUSE(RX_RAM_SEC_ERR, "sec error in rx buffer"), 287 SEC_ERROR_CAUSE(PCIE2AXI_RAM_SEC_ERR, "sec error in pcie2axi buffer"), 288 SEC_ERROR_CAUSE(AXI2PCIE_RAM_SEC_ERR, "sec error in axi2pcie buffer"), 289 DED_ERROR_CAUSE(TX_RAM_DED_ERR, "ded error in tx buffer"), 290 DED_ERROR_CAUSE(RX_RAM_DED_ERR, "ded error in rx buffer"), 291 DED_ERROR_CAUSE(PCIE2AXI_RAM_DED_ERR, "ded error in pcie2axi buffer"), 292 DED_ERROR_CAUSE(AXI2PCIE_RAM_DED_ERR, "ded error in axi2pcie buffer"), 293 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_0, "dma engine 0 error"), 294 LOCAL_EVENT_CAUSE(DMA_ERROR_ENGINE_1, "dma engine 1 error"), 295 LOCAL_EVENT_CAUSE(A_ATR_EVT_POST_ERR, "axi write request error"), 296 LOCAL_EVENT_CAUSE(A_ATR_EVT_FETCH_ERR, "axi read request error"), 297 LOCAL_EVENT_CAUSE(A_ATR_EVT_DISCARD_ERR, "axi read timeout"), 298 LOCAL_EVENT_CAUSE(P_ATR_EVT_POST_ERR, "pcie write request error"), 299 LOCAL_EVENT_CAUSE(P_ATR_EVT_FETCH_ERR, "pcie read request error"), 300 LOCAL_EVENT_CAUSE(P_ATR_EVT_DISCARD_ERR, "pcie read timeout"), 301 LOCAL_EVENT_CAUSE(PM_MSI_INT_AER_EVT, "aer event"), 302 LOCAL_EVENT_CAUSE(PM_MSI_INT_EVENTS, "pm/ltr/hotplug event"), 303 LOCAL_EVENT_CAUSE(PM_MSI_INT_SYS_ERR, "system error"), 304 }; 305 306 static struct event_map pcie_event_to_event[] = { 307 PCIE_EVENT_TO_EVENT_MAP(L2_EXIT), 308 PCIE_EVENT_TO_EVENT_MAP(HOTRST_EXIT), 309 PCIE_EVENT_TO_EVENT_MAP(DLUP_EXIT), 310 }; 311 312 static struct event_map sec_error_to_event[] = { 313 SEC_ERROR_TO_EVENT_MAP(TX_RAM_SEC_ERR), 314 SEC_ERROR_TO_EVENT_MAP(RX_RAM_SEC_ERR), 315 SEC_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_SEC_ERR), 316 SEC_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_SEC_ERR), 317 }; 318 319 static struct event_map ded_error_to_event[] = { 320 DED_ERROR_TO_EVENT_MAP(TX_RAM_DED_ERR), 321 DED_ERROR_TO_EVENT_MAP(RX_RAM_DED_ERR), 322 DED_ERROR_TO_EVENT_MAP(PCIE2AXI_RAM_DED_ERR), 323 DED_ERROR_TO_EVENT_MAP(AXI2PCIE_RAM_DED_ERR), 324 }; 325 326 static struct event_map local_status_to_event[] = { 327 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_0), 328 LOCAL_STATUS_TO_EVENT_MAP(DMA_END_ENGINE_1), 329 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_0), 330 LOCAL_STATUS_TO_EVENT_MAP(DMA_ERROR_ENGINE_1), 331 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_POST_ERR), 332 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_FETCH_ERR), 333 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DISCARD_ERR), 334 LOCAL_STATUS_TO_EVENT_MAP(A_ATR_EVT_DOORBELL), 335 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_POST_ERR), 336 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_FETCH_ERR), 337 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DISCARD_ERR), 338 LOCAL_STATUS_TO_EVENT_MAP(P_ATR_EVT_DOORBELL), 339 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_INTX), 340 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_MSI), 341 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_AER_EVT), 342 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_EVENTS), 343 LOCAL_STATUS_TO_EVENT_MAP(PM_MSI_INT_SYS_ERR), 344 }; 345 346 static struct { 347 u32 base; 348 u32 offset; 349 u32 mask; 350 u32 shift; 351 u32 enb_mask; 352 u32 mask_high; 353 u32 mask_offset; 354 } event_descs[] = { 355 { PCIE_EVENT(L2_EXIT) }, 356 { PCIE_EVENT(HOTRST_EXIT) }, 357 { PCIE_EVENT(DLUP_EXIT) }, 358 { SEC_EVENT(TX_RAM_SEC_ERR) }, 359 { SEC_EVENT(RX_RAM_SEC_ERR) }, 360 { SEC_EVENT(PCIE2AXI_RAM_SEC_ERR) }, 361 { SEC_EVENT(AXI2PCIE_RAM_SEC_ERR) }, 362 { DED_EVENT(TX_RAM_DED_ERR) }, 363 { DED_EVENT(RX_RAM_DED_ERR) }, 364 { DED_EVENT(PCIE2AXI_RAM_DED_ERR) }, 365 { DED_EVENT(AXI2PCIE_RAM_DED_ERR) }, 366 { LOCAL_EVENT(DMA_END_ENGINE_0) }, 367 { LOCAL_EVENT(DMA_END_ENGINE_1) }, 368 { LOCAL_EVENT(DMA_ERROR_ENGINE_0) }, 369 { LOCAL_EVENT(DMA_ERROR_ENGINE_1) }, 370 { LOCAL_EVENT(A_ATR_EVT_POST_ERR) }, 371 { LOCAL_EVENT(A_ATR_EVT_FETCH_ERR) }, 372 { LOCAL_EVENT(A_ATR_EVT_DISCARD_ERR) }, 373 { LOCAL_EVENT(A_ATR_EVT_DOORBELL) }, 374 { LOCAL_EVENT(P_ATR_EVT_POST_ERR) }, 375 { LOCAL_EVENT(P_ATR_EVT_FETCH_ERR) }, 376 { LOCAL_EVENT(P_ATR_EVT_DISCARD_ERR) }, 377 { LOCAL_EVENT(P_ATR_EVT_DOORBELL) }, 378 { LOCAL_EVENT(PM_MSI_INT_INTX) }, 379 { LOCAL_EVENT(PM_MSI_INT_MSI) }, 380 { LOCAL_EVENT(PM_MSI_INT_AER_EVT) }, 381 { LOCAL_EVENT(PM_MSI_INT_EVENTS) }, 382 { LOCAL_EVENT(PM_MSI_INT_SYS_ERR) }, 383 }; 384 385 static char poss_clks[][5] = { "fic0", "fic1", "fic2", "fic3" }; 386 387 static void mc_pcie_enable_msi(struct mc_pcie *port, void __iomem *ecam) 388 { 389 struct mc_msi *msi = &port->msi; 390 u16 reg; 391 u8 queue_size; 392 393 /* Fixup MSI enable flag */ 394 reg = readw_relaxed(ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 395 reg |= PCI_MSI_FLAGS_ENABLE; 396 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 397 398 /* Fixup PCI MSI queue flags */ 399 queue_size = FIELD_GET(PCI_MSI_FLAGS_QMASK, reg); 400 reg |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, queue_size); 401 writew_relaxed(reg, ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_FLAGS); 402 403 /* Fixup MSI addr fields */ 404 writel_relaxed(lower_32_bits(msi->vector_phy), 405 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_LO); 406 writel_relaxed(upper_32_bits(msi->vector_phy), 407 ecam + MC_MSI_CAP_CTRL_OFFSET + PCI_MSI_ADDRESS_HI); 408 } 409 410 static void mc_handle_msi(struct irq_desc *desc) 411 { 412 struct mc_pcie *port = irq_desc_get_handler_data(desc); 413 struct irq_chip *chip = irq_desc_get_chip(desc); 414 struct device *dev = port->dev; 415 struct mc_msi *msi = &port->msi; 416 void __iomem *bridge_base_addr = 417 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 418 unsigned long status; 419 u32 bit; 420 int ret; 421 422 chained_irq_enter(chip, desc); 423 424 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 425 if (status & PM_MSI_INT_MSI_MASK) { 426 writel_relaxed(status & PM_MSI_INT_MSI_MASK, bridge_base_addr + ISTATUS_LOCAL); 427 status = readl_relaxed(bridge_base_addr + ISTATUS_MSI); 428 for_each_set_bit(bit, &status, msi->num_vectors) { 429 ret = generic_handle_domain_irq(msi->dev_domain, bit); 430 if (ret) 431 dev_err_ratelimited(dev, "bad MSI IRQ %d\n", 432 bit); 433 } 434 } 435 436 chained_irq_exit(chip, desc); 437 } 438 439 static void mc_msi_bottom_irq_ack(struct irq_data *data) 440 { 441 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 442 void __iomem *bridge_base_addr = 443 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 444 u32 bitpos = data->hwirq; 445 446 writel_relaxed(BIT(bitpos), bridge_base_addr + ISTATUS_MSI); 447 } 448 449 static void mc_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 450 { 451 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 452 phys_addr_t addr = port->msi.vector_phy; 453 454 msg->address_lo = lower_32_bits(addr); 455 msg->address_hi = upper_32_bits(addr); 456 msg->data = data->hwirq; 457 458 dev_dbg(port->dev, "msi#%x address_hi %#x address_lo %#x\n", 459 (int)data->hwirq, msg->address_hi, msg->address_lo); 460 } 461 462 static int mc_msi_set_affinity(struct irq_data *irq_data, 463 const struct cpumask *mask, bool force) 464 { 465 return -EINVAL; 466 } 467 468 static struct irq_chip mc_msi_bottom_irq_chip = { 469 .name = "Microchip MSI", 470 .irq_ack = mc_msi_bottom_irq_ack, 471 .irq_compose_msi_msg = mc_compose_msi_msg, 472 .irq_set_affinity = mc_msi_set_affinity, 473 }; 474 475 static int mc_irq_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 476 unsigned int nr_irqs, void *args) 477 { 478 struct mc_pcie *port = domain->host_data; 479 struct mc_msi *msi = &port->msi; 480 unsigned long bit; 481 482 mutex_lock(&msi->lock); 483 bit = find_first_zero_bit(msi->used, msi->num_vectors); 484 if (bit >= msi->num_vectors) { 485 mutex_unlock(&msi->lock); 486 return -ENOSPC; 487 } 488 489 set_bit(bit, msi->used); 490 491 irq_domain_set_info(domain, virq, bit, &mc_msi_bottom_irq_chip, 492 domain->host_data, handle_edge_irq, NULL, NULL); 493 494 mutex_unlock(&msi->lock); 495 496 return 0; 497 } 498 499 static void mc_irq_msi_domain_free(struct irq_domain *domain, unsigned int virq, 500 unsigned int nr_irqs) 501 { 502 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 503 struct mc_pcie *port = irq_data_get_irq_chip_data(d); 504 struct mc_msi *msi = &port->msi; 505 506 mutex_lock(&msi->lock); 507 508 if (test_bit(d->hwirq, msi->used)) 509 __clear_bit(d->hwirq, msi->used); 510 else 511 dev_err(port->dev, "trying to free unused MSI%lu\n", d->hwirq); 512 513 mutex_unlock(&msi->lock); 514 } 515 516 static const struct irq_domain_ops msi_domain_ops = { 517 .alloc = mc_irq_msi_domain_alloc, 518 .free = mc_irq_msi_domain_free, 519 }; 520 521 static struct irq_chip mc_msi_irq_chip = { 522 .name = "Microchip PCIe MSI", 523 .irq_ack = irq_chip_ack_parent, 524 .irq_mask = pci_msi_mask_irq, 525 .irq_unmask = pci_msi_unmask_irq, 526 }; 527 528 static struct msi_domain_info mc_msi_domain_info = { 529 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 530 MSI_FLAG_PCI_MSIX), 531 .chip = &mc_msi_irq_chip, 532 }; 533 534 static int mc_allocate_msi_domains(struct mc_pcie *port) 535 { 536 struct device *dev = port->dev; 537 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); 538 struct mc_msi *msi = &port->msi; 539 540 mutex_init(&port->msi.lock); 541 542 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_vectors, 543 &msi_domain_ops, port); 544 if (!msi->dev_domain) { 545 dev_err(dev, "failed to create IRQ domain\n"); 546 return -ENOMEM; 547 } 548 549 msi->msi_domain = pci_msi_create_irq_domain(fwnode, &mc_msi_domain_info, 550 msi->dev_domain); 551 if (!msi->msi_domain) { 552 dev_err(dev, "failed to create MSI domain\n"); 553 irq_domain_remove(msi->dev_domain); 554 return -ENOMEM; 555 } 556 557 return 0; 558 } 559 560 static void mc_handle_intx(struct irq_desc *desc) 561 { 562 struct mc_pcie *port = irq_desc_get_handler_data(desc); 563 struct irq_chip *chip = irq_desc_get_chip(desc); 564 struct device *dev = port->dev; 565 void __iomem *bridge_base_addr = 566 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 567 unsigned long status; 568 u32 bit; 569 int ret; 570 571 chained_irq_enter(chip, desc); 572 573 status = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 574 if (status & PM_MSI_INT_INTX_MASK) { 575 status &= PM_MSI_INT_INTX_MASK; 576 status >>= PM_MSI_INT_INTX_SHIFT; 577 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 578 ret = generic_handle_domain_irq(port->intx_domain, bit); 579 if (ret) 580 dev_err_ratelimited(dev, "bad INTx IRQ %d\n", 581 bit); 582 } 583 } 584 585 chained_irq_exit(chip, desc); 586 } 587 588 static void mc_ack_intx_irq(struct irq_data *data) 589 { 590 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 591 void __iomem *bridge_base_addr = 592 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 593 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 594 595 writel_relaxed(mask, bridge_base_addr + ISTATUS_LOCAL); 596 } 597 598 static void mc_mask_intx_irq(struct irq_data *data) 599 { 600 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 601 void __iomem *bridge_base_addr = 602 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 603 unsigned long flags; 604 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 605 u32 val; 606 607 raw_spin_lock_irqsave(&port->lock, flags); 608 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 609 val &= ~mask; 610 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 611 raw_spin_unlock_irqrestore(&port->lock, flags); 612 } 613 614 static void mc_unmask_intx_irq(struct irq_data *data) 615 { 616 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 617 void __iomem *bridge_base_addr = 618 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 619 unsigned long flags; 620 u32 mask = BIT(data->hwirq + PM_MSI_INT_INTX_SHIFT); 621 u32 val; 622 623 raw_spin_lock_irqsave(&port->lock, flags); 624 val = readl_relaxed(bridge_base_addr + IMASK_LOCAL); 625 val |= mask; 626 writel_relaxed(val, bridge_base_addr + IMASK_LOCAL); 627 raw_spin_unlock_irqrestore(&port->lock, flags); 628 } 629 630 static struct irq_chip mc_intx_irq_chip = { 631 .name = "Microchip PCIe INTx", 632 .irq_ack = mc_ack_intx_irq, 633 .irq_mask = mc_mask_intx_irq, 634 .irq_unmask = mc_unmask_intx_irq, 635 }; 636 637 static int mc_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 638 irq_hw_number_t hwirq) 639 { 640 irq_set_chip_and_handler(irq, &mc_intx_irq_chip, handle_level_irq); 641 irq_set_chip_data(irq, domain->host_data); 642 643 return 0; 644 } 645 646 static const struct irq_domain_ops intx_domain_ops = { 647 .map = mc_pcie_intx_map, 648 }; 649 650 static inline u32 reg_to_event(u32 reg, struct event_map field) 651 { 652 return (reg & field.reg_mask) ? BIT(field.event_bit) : 0; 653 } 654 655 static u32 pcie_events(struct mc_pcie *port) 656 { 657 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 658 u32 reg = readl_relaxed(ctrl_base_addr + PCIE_EVENT_INT); 659 u32 val = 0; 660 int i; 661 662 for (i = 0; i < ARRAY_SIZE(pcie_event_to_event); i++) 663 val |= reg_to_event(reg, pcie_event_to_event[i]); 664 665 return val; 666 } 667 668 static u32 sec_errors(struct mc_pcie *port) 669 { 670 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 671 u32 reg = readl_relaxed(ctrl_base_addr + SEC_ERROR_INT); 672 u32 val = 0; 673 int i; 674 675 for (i = 0; i < ARRAY_SIZE(sec_error_to_event); i++) 676 val |= reg_to_event(reg, sec_error_to_event[i]); 677 678 return val; 679 } 680 681 static u32 ded_errors(struct mc_pcie *port) 682 { 683 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 684 u32 reg = readl_relaxed(ctrl_base_addr + DED_ERROR_INT); 685 u32 val = 0; 686 int i; 687 688 for (i = 0; i < ARRAY_SIZE(ded_error_to_event); i++) 689 val |= reg_to_event(reg, ded_error_to_event[i]); 690 691 return val; 692 } 693 694 static u32 local_events(struct mc_pcie *port) 695 { 696 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 697 u32 reg = readl_relaxed(bridge_base_addr + ISTATUS_LOCAL); 698 u32 val = 0; 699 int i; 700 701 for (i = 0; i < ARRAY_SIZE(local_status_to_event); i++) 702 val |= reg_to_event(reg, local_status_to_event[i]); 703 704 return val; 705 } 706 707 static u32 get_events(struct mc_pcie *port) 708 { 709 u32 events = 0; 710 711 events |= pcie_events(port); 712 events |= sec_errors(port); 713 events |= ded_errors(port); 714 events |= local_events(port); 715 716 return events; 717 } 718 719 static irqreturn_t mc_event_handler(int irq, void *dev_id) 720 { 721 struct mc_pcie *port = dev_id; 722 struct device *dev = port->dev; 723 struct irq_data *data; 724 725 data = irq_domain_get_irq_data(port->event_domain, irq); 726 727 if (event_cause[data->hwirq].str) 728 dev_err_ratelimited(dev, "%s\n", event_cause[data->hwirq].str); 729 else 730 dev_err_ratelimited(dev, "bad event IRQ %ld\n", data->hwirq); 731 732 return IRQ_HANDLED; 733 } 734 735 static void mc_handle_event(struct irq_desc *desc) 736 { 737 struct mc_pcie *port = irq_desc_get_handler_data(desc); 738 unsigned long events; 739 u32 bit; 740 struct irq_chip *chip = irq_desc_get_chip(desc); 741 742 chained_irq_enter(chip, desc); 743 744 events = get_events(port); 745 746 for_each_set_bit(bit, &events, NUM_EVENTS) 747 generic_handle_domain_irq(port->event_domain, bit); 748 749 chained_irq_exit(chip, desc); 750 } 751 752 static void mc_ack_event_irq(struct irq_data *data) 753 { 754 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 755 u32 event = data->hwirq; 756 void __iomem *addr; 757 u32 mask; 758 759 addr = port->axi_base_addr + event_descs[event].base + 760 event_descs[event].offset; 761 mask = event_descs[event].mask; 762 mask |= event_descs[event].enb_mask; 763 764 writel_relaxed(mask, addr); 765 } 766 767 static void mc_mask_event_irq(struct irq_data *data) 768 { 769 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 770 u32 event = data->hwirq; 771 void __iomem *addr; 772 u32 mask; 773 u32 val; 774 775 addr = port->axi_base_addr + event_descs[event].base + 776 event_descs[event].mask_offset; 777 mask = event_descs[event].mask; 778 if (event_descs[event].enb_mask) { 779 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 780 mask &= PCIE_EVENT_INT_ENB_MASK; 781 } 782 783 if (!event_descs[event].mask_high) 784 mask = ~mask; 785 786 raw_spin_lock(&port->lock); 787 val = readl_relaxed(addr); 788 if (event_descs[event].mask_high) 789 val |= mask; 790 else 791 val &= mask; 792 793 writel_relaxed(val, addr); 794 raw_spin_unlock(&port->lock); 795 } 796 797 static void mc_unmask_event_irq(struct irq_data *data) 798 { 799 struct mc_pcie *port = irq_data_get_irq_chip_data(data); 800 u32 event = data->hwirq; 801 void __iomem *addr; 802 u32 mask; 803 u32 val; 804 805 addr = port->axi_base_addr + event_descs[event].base + 806 event_descs[event].mask_offset; 807 mask = event_descs[event].mask; 808 809 if (event_descs[event].enb_mask) 810 mask <<= PCIE_EVENT_INT_ENB_SHIFT; 811 812 if (event_descs[event].mask_high) 813 mask = ~mask; 814 815 if (event_descs[event].enb_mask) 816 mask &= PCIE_EVENT_INT_ENB_MASK; 817 818 raw_spin_lock(&port->lock); 819 val = readl_relaxed(addr); 820 if (event_descs[event].mask_high) 821 val &= mask; 822 else 823 val |= mask; 824 writel_relaxed(val, addr); 825 raw_spin_unlock(&port->lock); 826 } 827 828 static struct irq_chip mc_event_irq_chip = { 829 .name = "Microchip PCIe EVENT", 830 .irq_ack = mc_ack_event_irq, 831 .irq_mask = mc_mask_event_irq, 832 .irq_unmask = mc_unmask_event_irq, 833 }; 834 835 static int mc_pcie_event_map(struct irq_domain *domain, unsigned int irq, 836 irq_hw_number_t hwirq) 837 { 838 irq_set_chip_and_handler(irq, &mc_event_irq_chip, handle_level_irq); 839 irq_set_chip_data(irq, domain->host_data); 840 841 return 0; 842 } 843 844 static const struct irq_domain_ops event_domain_ops = { 845 .map = mc_pcie_event_map, 846 }; 847 848 static inline struct clk *mc_pcie_init_clk(struct device *dev, const char *id) 849 { 850 struct clk *clk; 851 int ret; 852 853 clk = devm_clk_get_optional(dev, id); 854 if (IS_ERR(clk)) 855 return clk; 856 if (!clk) 857 return clk; 858 859 ret = clk_prepare_enable(clk); 860 if (ret) 861 return ERR_PTR(ret); 862 863 devm_add_action_or_reset(dev, (void (*) (void *))clk_disable_unprepare, 864 clk); 865 866 return clk; 867 } 868 869 static int mc_pcie_init_clks(struct device *dev) 870 { 871 int i; 872 struct clk *fic; 873 874 /* 875 * PCIe may be clocked via Fabric Interface using between 1 and 4 876 * clocks. Scan DT for clocks and enable them if present 877 */ 878 for (i = 0; i < ARRAY_SIZE(poss_clks); i++) { 879 fic = mc_pcie_init_clk(dev, poss_clks[i]); 880 if (IS_ERR(fic)) 881 return PTR_ERR(fic); 882 } 883 884 return 0; 885 } 886 887 static int mc_pcie_init_irq_domains(struct mc_pcie *port) 888 { 889 struct device *dev = port->dev; 890 struct device_node *node = dev->of_node; 891 struct device_node *pcie_intc_node; 892 893 /* Setup INTx */ 894 pcie_intc_node = of_get_next_child(node, NULL); 895 if (!pcie_intc_node) { 896 dev_err(dev, "failed to find PCIe Intc node\n"); 897 return -EINVAL; 898 } 899 900 port->event_domain = irq_domain_add_linear(pcie_intc_node, NUM_EVENTS, 901 &event_domain_ops, port); 902 if (!port->event_domain) { 903 dev_err(dev, "failed to get event domain\n"); 904 of_node_put(pcie_intc_node); 905 return -ENOMEM; 906 } 907 908 irq_domain_update_bus_token(port->event_domain, DOMAIN_BUS_NEXUS); 909 910 port->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 911 &intx_domain_ops, port); 912 if (!port->intx_domain) { 913 dev_err(dev, "failed to get an INTx IRQ domain\n"); 914 of_node_put(pcie_intc_node); 915 return -ENOMEM; 916 } 917 918 irq_domain_update_bus_token(port->intx_domain, DOMAIN_BUS_WIRED); 919 920 of_node_put(pcie_intc_node); 921 raw_spin_lock_init(&port->lock); 922 923 return mc_allocate_msi_domains(port); 924 } 925 926 static void mc_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, 927 phys_addr_t axi_addr, phys_addr_t pci_addr, 928 size_t size) 929 { 930 u32 atr_sz = ilog2(size) - 1; 931 u32 val; 932 933 if (index == 0) 934 val = PCIE_CONFIG_INTERFACE; 935 else 936 val = PCIE_TX_RX_INTERFACE; 937 938 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 939 ATR0_AXI4_SLV0_TRSL_PARAM); 940 941 val = lower_32_bits(axi_addr) | (atr_sz << ATR_SIZE_SHIFT) | 942 ATR_IMPL_ENABLE; 943 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 944 ATR0_AXI4_SLV0_SRCADDR_PARAM); 945 946 val = upper_32_bits(axi_addr); 947 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 948 ATR0_AXI4_SLV0_SRC_ADDR); 949 950 val = lower_32_bits(pci_addr); 951 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 952 ATR0_AXI4_SLV0_TRSL_ADDR_LSB); 953 954 val = upper_32_bits(pci_addr); 955 writel(val, bridge_base_addr + (index * ATR_ENTRY_SIZE) + 956 ATR0_AXI4_SLV0_TRSL_ADDR_UDW); 957 958 val = readl(bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 959 val |= (ATR0_PCIE_ATR_SIZE << ATR0_PCIE_ATR_SIZE_SHIFT); 960 writel(val, bridge_base_addr + ATR0_PCIE_WIN0_SRCADDR_PARAM); 961 writel(0, bridge_base_addr + ATR0_PCIE_WIN0_SRC_ADDR); 962 } 963 964 static int mc_pcie_setup_windows(struct platform_device *pdev, 965 struct mc_pcie *port) 966 { 967 void __iomem *bridge_base_addr = 968 port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 969 struct pci_host_bridge *bridge = platform_get_drvdata(pdev); 970 struct resource_entry *entry; 971 u64 pci_addr; 972 u32 index = 1; 973 974 resource_list_for_each_entry(entry, &bridge->windows) { 975 if (resource_type(entry->res) == IORESOURCE_MEM) { 976 pci_addr = entry->res->start - entry->offset; 977 mc_pcie_setup_window(bridge_base_addr, index, 978 entry->res->start, pci_addr, 979 resource_size(entry->res)); 980 index++; 981 } 982 } 983 984 return 0; 985 } 986 987 static inline void mc_clear_secs(struct mc_pcie *port) 988 { 989 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 990 991 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + 992 SEC_ERROR_INT); 993 writel_relaxed(0, ctrl_base_addr + SEC_ERROR_EVENT_CNT); 994 } 995 996 static inline void mc_clear_deds(struct mc_pcie *port) 997 { 998 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 999 1000 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + 1001 DED_ERROR_INT); 1002 writel_relaxed(0, ctrl_base_addr + DED_ERROR_EVENT_CNT); 1003 } 1004 1005 static void mc_disable_interrupts(struct mc_pcie *port) 1006 { 1007 void __iomem *bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1008 void __iomem *ctrl_base_addr = port->axi_base_addr + MC_PCIE_CTRL_ADDR; 1009 u32 val; 1010 1011 /* Ensure ECC bypass is enabled */ 1012 val = ECC_CONTROL_TX_RAM_ECC_BYPASS | 1013 ECC_CONTROL_RX_RAM_ECC_BYPASS | 1014 ECC_CONTROL_PCIE2AXI_RAM_ECC_BYPASS | 1015 ECC_CONTROL_AXI2PCIE_RAM_ECC_BYPASS; 1016 writel_relaxed(val, ctrl_base_addr + ECC_CONTROL); 1017 1018 /* Disable SEC errors and clear any outstanding */ 1019 writel_relaxed(SEC_ERROR_INT_ALL_RAM_SEC_ERR_INT, ctrl_base_addr + 1020 SEC_ERROR_INT_MASK); 1021 mc_clear_secs(port); 1022 1023 /* Disable DED errors and clear any outstanding */ 1024 writel_relaxed(DED_ERROR_INT_ALL_RAM_DED_ERR_INT, ctrl_base_addr + 1025 DED_ERROR_INT_MASK); 1026 mc_clear_deds(port); 1027 1028 /* Disable local interrupts and clear any outstanding */ 1029 writel_relaxed(0, bridge_base_addr + IMASK_LOCAL); 1030 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_LOCAL); 1031 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_MSI); 1032 1033 /* Disable PCIe events and clear any outstanding */ 1034 val = PCIE_EVENT_INT_L2_EXIT_INT | 1035 PCIE_EVENT_INT_HOTRST_EXIT_INT | 1036 PCIE_EVENT_INT_DLUP_EXIT_INT | 1037 PCIE_EVENT_INT_L2_EXIT_INT_MASK | 1038 PCIE_EVENT_INT_HOTRST_EXIT_INT_MASK | 1039 PCIE_EVENT_INT_DLUP_EXIT_INT_MASK; 1040 writel_relaxed(val, ctrl_base_addr + PCIE_EVENT_INT); 1041 1042 /* Disable host interrupts and clear any outstanding */ 1043 writel_relaxed(0, bridge_base_addr + IMASK_HOST); 1044 writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); 1045 } 1046 1047 static int mc_init_interrupts(struct platform_device *pdev, struct mc_pcie *port) 1048 { 1049 struct device *dev = &pdev->dev; 1050 int irq; 1051 int i, intx_irq, msi_irq, event_irq; 1052 int ret; 1053 1054 ret = mc_pcie_init_irq_domains(port); 1055 if (ret) { 1056 dev_err(dev, "failed creating IRQ domains\n"); 1057 return ret; 1058 } 1059 1060 irq = platform_get_irq(pdev, 0); 1061 if (irq < 0) 1062 return -ENODEV; 1063 1064 for (i = 0; i < NUM_EVENTS; i++) { 1065 event_irq = irq_create_mapping(port->event_domain, i); 1066 if (!event_irq) { 1067 dev_err(dev, "failed to map hwirq %d\n", i); 1068 return -ENXIO; 1069 } 1070 1071 ret = devm_request_irq(dev, event_irq, mc_event_handler, 1072 0, event_cause[i].sym, port); 1073 if (ret) { 1074 dev_err(dev, "failed to request IRQ %d\n", event_irq); 1075 return ret; 1076 } 1077 } 1078 1079 intx_irq = irq_create_mapping(port->event_domain, 1080 EVENT_LOCAL_PM_MSI_INT_INTX); 1081 if (!intx_irq) { 1082 dev_err(dev, "failed to map INTx interrupt\n"); 1083 return -ENXIO; 1084 } 1085 1086 /* Plug the INTx chained handler */ 1087 irq_set_chained_handler_and_data(intx_irq, mc_handle_intx, port); 1088 1089 msi_irq = irq_create_mapping(port->event_domain, 1090 EVENT_LOCAL_PM_MSI_INT_MSI); 1091 if (!msi_irq) 1092 return -ENXIO; 1093 1094 /* Plug the MSI chained handler */ 1095 irq_set_chained_handler_and_data(msi_irq, mc_handle_msi, port); 1096 1097 /* Plug the main event chained handler */ 1098 irq_set_chained_handler_and_data(irq, mc_handle_event, port); 1099 1100 return 0; 1101 } 1102 1103 static int mc_platform_init(struct pci_config_window *cfg) 1104 { 1105 struct device *dev = cfg->parent; 1106 struct platform_device *pdev = to_platform_device(dev); 1107 struct mc_pcie *port; 1108 void __iomem *bridge_base_addr; 1109 int ret; 1110 u32 val; 1111 1112 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1113 if (!port) 1114 return -ENOMEM; 1115 port->dev = dev; 1116 1117 ret = mc_pcie_init_clks(dev); 1118 if (ret) { 1119 dev_err(dev, "failed to get clock resources, error %d\n", ret); 1120 return -ENODEV; 1121 } 1122 1123 port->axi_base_addr = devm_platform_ioremap_resource(pdev, 1); 1124 if (IS_ERR(port->axi_base_addr)) 1125 return PTR_ERR(port->axi_base_addr); 1126 1127 mc_disable_interrupts(port); 1128 1129 bridge_base_addr = port->axi_base_addr + MC_PCIE_BRIDGE_ADDR; 1130 1131 /* Allow enabling MSI by disabling MSI-X */ 1132 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); 1133 val &= ~MSIX_CAP_MASK; 1134 writel(val, bridge_base_addr + PCIE_PCI_IRQ_DW0); 1135 1136 /* Hardware doesn't setup MSI by default */ 1137 mc_pcie_enable_msi(port, cfg->win); 1138 1139 /* Pick num vectors from bitfile programmed onto FPGA fabric */ 1140 val = readl(bridge_base_addr + PCIE_PCI_IRQ_DW0); 1141 val &= NUM_MSI_MSGS_MASK; 1142 val >>= NUM_MSI_MSGS_SHIFT; 1143 1144 port->msi.num_vectors = 1 << val; 1145 1146 /* Pick vector address from design */ 1147 port->msi.vector_phy = readl_relaxed(bridge_base_addr + IMSI_ADDR); 1148 1149 /* Configure Address Translation Table 0 for PCIe config space */ 1150 mc_pcie_setup_window(bridge_base_addr, 0, cfg->res.start & 0xffffffff, 1151 cfg->res.start, resource_size(&cfg->res)); 1152 1153 ret = mc_pcie_setup_windows(pdev, port); 1154 if (ret) 1155 return ret; 1156 1157 /* Address translation is up; safe to enable interrupts */ 1158 return mc_init_interrupts(pdev, port); 1159 } 1160 1161 static const struct pci_ecam_ops mc_ecam_ops = { 1162 .init = mc_platform_init, 1163 .pci_ops = { 1164 .map_bus = pci_ecam_map_bus, 1165 .read = pci_generic_config_read, 1166 .write = pci_generic_config_write, 1167 } 1168 }; 1169 1170 static const struct of_device_id mc_pcie_of_match[] = { 1171 { 1172 .compatible = "microchip,pcie-host-1.0", 1173 .data = &mc_ecam_ops, 1174 }, 1175 {}, 1176 }; 1177 1178 MODULE_DEVICE_TABLE(of, mc_pcie_of_match); 1179 1180 static struct platform_driver mc_pcie_driver = { 1181 .probe = pci_host_common_probe, 1182 .driver = { 1183 .name = "microchip-pcie", 1184 .of_match_table = mc_pcie_of_match, 1185 .suppress_bind_attrs = true, 1186 }, 1187 }; 1188 1189 builtin_platform_driver(mc_pcie_driver); 1190 MODULE_LICENSE("GPL"); 1191 MODULE_DESCRIPTION("Microchip PCIe host controller driver"); 1192 MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>"); 1193