1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek PCIe host controller driver. 4 * 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Ryder Lee <ryder.lee@mediatek.com> 7 * Honghui Zhang <honghui.zhang@mediatek.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/iopoll.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/irqdomain.h> 16 #include <linux/kernel.h> 17 #include <linux/msi.h> 18 #include <linux/module.h> 19 #include <linux/of_address.h> 20 #include <linux/of_pci.h> 21 #include <linux/of_platform.h> 22 #include <linux/pci.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/reset.h> 27 28 #include "../pci.h" 29 30 /* PCIe shared registers */ 31 #define PCIE_SYS_CFG 0x00 32 #define PCIE_INT_ENABLE 0x0c 33 #define PCIE_CFG_ADDR 0x20 34 #define PCIE_CFG_DATA 0x24 35 36 /* PCIe per port registers */ 37 #define PCIE_BAR0_SETUP 0x10 38 #define PCIE_CLASS 0x34 39 #define PCIE_LINK_STATUS 0x50 40 41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x)) 42 #define PCIE_PORT_PERST(x) BIT(1 + (x)) 43 #define PCIE_PORT_LINKUP BIT(0) 44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16) 45 46 #define PCIE_BAR_ENABLE BIT(0) 47 #define PCIE_REVISION_ID BIT(0) 48 #define PCIE_CLASS_CODE (0x60400 << 8) 49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ 50 ((((regn) >> 8) & GENMASK(3, 0)) << 24)) 51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8)) 52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11)) 53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16)) 54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \ 55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \ 56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus)) 57 58 /* MediaTek specific configuration registers */ 59 #define PCIE_FTS_NUM 0x70c 60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8) 61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) 62 63 #define PCIE_FC_CREDIT 0x73c 64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) 65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16) 66 67 /* PCIe V2 share registers */ 68 #define PCIE_SYS_CFG_V2 0x0 69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8) 70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8) 71 72 /* PCIe V2 per-port registers */ 73 #define PCIE_MSI_VECTOR 0x0c0 74 75 #define PCIE_CONF_VEND_ID 0x100 76 #define PCIE_CONF_CLASS_ID 0x106 77 78 #define PCIE_INT_MASK 0x420 79 #define INTX_MASK GENMASK(19, 16) 80 #define INTX_SHIFT 16 81 #define PCIE_INT_STATUS 0x424 82 #define MSI_STATUS BIT(23) 83 #define PCIE_IMSI_STATUS 0x42c 84 #define PCIE_IMSI_ADDR 0x430 85 #define MSI_MASK BIT(23) 86 #define MTK_MSI_IRQS_NUM 32 87 88 #define PCIE_AHB_TRANS_BASE0_L 0x438 89 #define PCIE_AHB_TRANS_BASE0_H 0x43c 90 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0)) 91 #define PCIE_AXI_WINDOW0 0x448 92 #define WIN_ENABLE BIT(7) 93 94 /* PCIe V2 configuration transaction header */ 95 #define PCIE_CFG_HEADER0 0x460 96 #define PCIE_CFG_HEADER1 0x464 97 #define PCIE_CFG_HEADER2 0x468 98 #define PCIE_CFG_WDATA 0x470 99 #define PCIE_APP_TLP_REQ 0x488 100 #define PCIE_CFG_RDATA 0x48c 101 #define APP_CFG_REQ BIT(0) 102 #define APP_CPL_STATUS GENMASK(7, 5) 103 104 #define CFG_WRRD_TYPE_0 4 105 #define CFG_WR_FMT 2 106 #define CFG_RD_FMT 0 107 108 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0)) 109 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24)) 110 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29)) 111 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2)) 112 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16)) 113 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19)) 114 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24)) 115 #define CFG_HEADER_DW0(type, fmt) \ 116 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt)) 117 #define CFG_HEADER_DW1(where, size) \ 118 (GENMASK(((size) - 1), 0) << ((where) & 0x3)) 119 #define CFG_HEADER_DW2(regn, fun, dev, bus) \ 120 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \ 121 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus)) 122 123 #define PCIE_RST_CTRL 0x510 124 #define PCIE_PHY_RSTB BIT(0) 125 #define PCIE_PIPE_SRSTB BIT(1) 126 #define PCIE_MAC_SRSTB BIT(2) 127 #define PCIE_CRSTB BIT(3) 128 #define PCIE_PERSTB BIT(8) 129 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13) 130 #define PCIE_LINK_STATUS_V2 0x804 131 #define PCIE_PORT_LINKUP_V2 BIT(10) 132 133 struct mtk_pcie_port; 134 135 /** 136 * struct mtk_pcie_soc - differentiate between host generations 137 * @need_fix_class_id: whether this host's class ID needed to be fixed or not 138 * @ops: pointer to configuration access functions 139 * @startup: pointer to controller setting functions 140 * @setup_irq: pointer to initialize IRQ functions 141 */ 142 struct mtk_pcie_soc { 143 bool need_fix_class_id; 144 struct pci_ops *ops; 145 int (*startup)(struct mtk_pcie_port *port); 146 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); 147 }; 148 149 /** 150 * struct mtk_pcie_port - PCIe port information 151 * @base: IO mapped register base 152 * @list: port list 153 * @pcie: pointer to PCIe host info 154 * @reset: pointer to port reset control 155 * @sys_ck: pointer to transaction/data link layer clock 156 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access 157 * and RC initiated MMIO access 158 * @axi_ck: pointer to application layer MMIO channel operating clock 159 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock 160 * when pcie_mac_ck/pcie_pipe_ck is turned off 161 * @obff_ck: pointer to OBFF functional block operating clock 162 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock 163 * @phy: pointer to PHY control block 164 * @slot: port slot 165 * @irq: GIC irq 166 * @irq_domain: legacy INTx IRQ domain 167 * @inner_domain: inner IRQ domain 168 * @msi_domain: MSI IRQ domain 169 * @lock: protect the msi_irq_in_use bitmap 170 * @msi_irq_in_use: bit map for assigned MSI IRQ 171 */ 172 struct mtk_pcie_port { 173 void __iomem *base; 174 struct list_head list; 175 struct mtk_pcie *pcie; 176 struct reset_control *reset; 177 struct clk *sys_ck; 178 struct clk *ahb_ck; 179 struct clk *axi_ck; 180 struct clk *aux_ck; 181 struct clk *obff_ck; 182 struct clk *pipe_ck; 183 struct phy *phy; 184 u32 slot; 185 int irq; 186 struct irq_domain *irq_domain; 187 struct irq_domain *inner_domain; 188 struct irq_domain *msi_domain; 189 struct mutex lock; 190 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM); 191 }; 192 193 /** 194 * struct mtk_pcie - PCIe host information 195 * @dev: pointer to PCIe device 196 * @base: IO mapped register base 197 * @free_ck: free-run reference clock 198 * @mem: non-prefetchable memory resource 199 * @ports: pointer to PCIe port information 200 * @soc: pointer to SoC-dependent operations 201 * @busnr: root bus number 202 */ 203 struct mtk_pcie { 204 struct device *dev; 205 void __iomem *base; 206 struct clk *free_ck; 207 208 struct resource mem; 209 struct list_head ports; 210 const struct mtk_pcie_soc *soc; 211 unsigned int busnr; 212 }; 213 214 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie) 215 { 216 struct device *dev = pcie->dev; 217 218 clk_disable_unprepare(pcie->free_ck); 219 220 pm_runtime_put_sync(dev); 221 pm_runtime_disable(dev); 222 } 223 224 static void mtk_pcie_port_free(struct mtk_pcie_port *port) 225 { 226 struct mtk_pcie *pcie = port->pcie; 227 struct device *dev = pcie->dev; 228 229 devm_iounmap(dev, port->base); 230 list_del(&port->list); 231 devm_kfree(dev, port); 232 } 233 234 static void mtk_pcie_put_resources(struct mtk_pcie *pcie) 235 { 236 struct mtk_pcie_port *port, *tmp; 237 238 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 239 phy_power_off(port->phy); 240 phy_exit(port->phy); 241 clk_disable_unprepare(port->pipe_ck); 242 clk_disable_unprepare(port->obff_ck); 243 clk_disable_unprepare(port->axi_ck); 244 clk_disable_unprepare(port->aux_ck); 245 clk_disable_unprepare(port->ahb_ck); 246 clk_disable_unprepare(port->sys_ck); 247 mtk_pcie_port_free(port); 248 } 249 250 mtk_pcie_subsys_powerdown(pcie); 251 } 252 253 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) 254 { 255 u32 val; 256 int err; 257 258 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, 259 !(val & APP_CFG_REQ), 10, 260 100 * USEC_PER_MSEC); 261 if (err) 262 return PCIBIOS_SET_FAILED; 263 264 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) 265 return PCIBIOS_SET_FAILED; 266 267 return PCIBIOS_SUCCESSFUL; 268 } 269 270 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 271 int where, int size, u32 *val) 272 { 273 u32 tmp; 274 275 /* Write PCIe configuration transaction header for Cfgrd */ 276 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT), 277 port->base + PCIE_CFG_HEADER0); 278 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 279 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 280 port->base + PCIE_CFG_HEADER2); 281 282 /* Trigger h/w to transmit Cfgrd TLP */ 283 tmp = readl(port->base + PCIE_APP_TLP_REQ); 284 tmp |= APP_CFG_REQ; 285 writel(tmp, port->base + PCIE_APP_TLP_REQ); 286 287 /* Check completion status */ 288 if (mtk_pcie_check_cfg_cpld(port)) 289 return PCIBIOS_SET_FAILED; 290 291 /* Read cpld payload of Cfgrd */ 292 *val = readl(port->base + PCIE_CFG_RDATA); 293 294 if (size == 1) 295 *val = (*val >> (8 * (where & 3))) & 0xff; 296 else if (size == 2) 297 *val = (*val >> (8 * (where & 3))) & 0xffff; 298 299 return PCIBIOS_SUCCESSFUL; 300 } 301 302 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, 303 int where, int size, u32 val) 304 { 305 /* Write PCIe configuration transaction header for Cfgwr */ 306 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT), 307 port->base + PCIE_CFG_HEADER0); 308 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); 309 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus), 310 port->base + PCIE_CFG_HEADER2); 311 312 /* Write Cfgwr data */ 313 val = val << 8 * (where & 3); 314 writel(val, port->base + PCIE_CFG_WDATA); 315 316 /* Trigger h/w to transmit Cfgwr TLP */ 317 val = readl(port->base + PCIE_APP_TLP_REQ); 318 val |= APP_CFG_REQ; 319 writel(val, port->base + PCIE_APP_TLP_REQ); 320 321 /* Check completion status */ 322 return mtk_pcie_check_cfg_cpld(port); 323 } 324 325 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus, 326 unsigned int devfn) 327 { 328 struct mtk_pcie *pcie = bus->sysdata; 329 struct mtk_pcie_port *port; 330 struct pci_dev *dev = NULL; 331 332 /* 333 * Walk the bus hierarchy to get the devfn value 334 * of the port in the root bus. 335 */ 336 while (bus && bus->number) { 337 dev = bus->self; 338 bus = dev->bus; 339 devfn = dev->devfn; 340 } 341 342 list_for_each_entry(port, &pcie->ports, list) 343 if (port->slot == PCI_SLOT(devfn)) 344 return port; 345 346 return NULL; 347 } 348 349 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 350 int where, int size, u32 *val) 351 { 352 struct mtk_pcie_port *port; 353 u32 bn = bus->number; 354 int ret; 355 356 port = mtk_pcie_find_port(bus, devfn); 357 if (!port) { 358 *val = ~0; 359 return PCIBIOS_DEVICE_NOT_FOUND; 360 } 361 362 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); 363 if (ret) 364 *val = ~0; 365 366 return ret; 367 } 368 369 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 370 int where, int size, u32 val) 371 { 372 struct mtk_pcie_port *port; 373 u32 bn = bus->number; 374 375 port = mtk_pcie_find_port(bus, devfn); 376 if (!port) 377 return PCIBIOS_DEVICE_NOT_FOUND; 378 379 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); 380 } 381 382 static struct pci_ops mtk_pcie_ops_v2 = { 383 .read = mtk_pcie_config_read, 384 .write = mtk_pcie_config_write, 385 }; 386 387 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 388 { 389 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 390 phys_addr_t addr; 391 392 /* MT2712/MT7622 only support 32-bit MSI addresses */ 393 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 394 msg->address_hi = 0; 395 msg->address_lo = lower_32_bits(addr); 396 397 msg->data = data->hwirq; 398 399 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", 400 (int)data->hwirq, msg->address_hi, msg->address_lo); 401 } 402 403 static int mtk_msi_set_affinity(struct irq_data *irq_data, 404 const struct cpumask *mask, bool force) 405 { 406 return -EINVAL; 407 } 408 409 static void mtk_msi_ack_irq(struct irq_data *data) 410 { 411 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); 412 u32 hwirq = data->hwirq; 413 414 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); 415 } 416 417 static struct irq_chip mtk_msi_bottom_irq_chip = { 418 .name = "MTK MSI", 419 .irq_compose_msi_msg = mtk_compose_msi_msg, 420 .irq_set_affinity = mtk_msi_set_affinity, 421 .irq_ack = mtk_msi_ack_irq, 422 }; 423 424 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 425 unsigned int nr_irqs, void *args) 426 { 427 struct mtk_pcie_port *port = domain->host_data; 428 unsigned long bit; 429 430 WARN_ON(nr_irqs != 1); 431 mutex_lock(&port->lock); 432 433 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); 434 if (bit >= MTK_MSI_IRQS_NUM) { 435 mutex_unlock(&port->lock); 436 return -ENOSPC; 437 } 438 439 __set_bit(bit, port->msi_irq_in_use); 440 441 mutex_unlock(&port->lock); 442 443 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip, 444 domain->host_data, handle_edge_irq, 445 NULL, NULL); 446 447 return 0; 448 } 449 450 static void mtk_pcie_irq_domain_free(struct irq_domain *domain, 451 unsigned int virq, unsigned int nr_irqs) 452 { 453 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 454 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); 455 456 mutex_lock(&port->lock); 457 458 if (!test_bit(d->hwirq, port->msi_irq_in_use)) 459 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", 460 d->hwirq); 461 else 462 __clear_bit(d->hwirq, port->msi_irq_in_use); 463 464 mutex_unlock(&port->lock); 465 466 irq_domain_free_irqs_parent(domain, virq, nr_irqs); 467 } 468 469 static const struct irq_domain_ops msi_domain_ops = { 470 .alloc = mtk_pcie_irq_domain_alloc, 471 .free = mtk_pcie_irq_domain_free, 472 }; 473 474 static struct irq_chip mtk_msi_irq_chip = { 475 .name = "MTK PCIe MSI", 476 .irq_ack = irq_chip_ack_parent, 477 .irq_mask = pci_msi_mask_irq, 478 .irq_unmask = pci_msi_unmask_irq, 479 }; 480 481 static struct msi_domain_info mtk_msi_domain_info = { 482 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 483 MSI_FLAG_PCI_MSIX), 484 .chip = &mtk_msi_irq_chip, 485 }; 486 487 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) 488 { 489 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); 490 491 mutex_init(&port->lock); 492 493 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, 494 &msi_domain_ops, port); 495 if (!port->inner_domain) { 496 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); 497 return -ENOMEM; 498 } 499 500 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, 501 port->inner_domain); 502 if (!port->msi_domain) { 503 dev_err(port->pcie->dev, "failed to create MSI domain\n"); 504 irq_domain_remove(port->inner_domain); 505 return -ENOMEM; 506 } 507 508 return 0; 509 } 510 511 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) 512 { 513 u32 val; 514 phys_addr_t msg_addr; 515 516 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); 517 val = lower_32_bits(msg_addr); 518 writel(val, port->base + PCIE_IMSI_ADDR); 519 520 val = readl(port->base + PCIE_INT_MASK); 521 val &= ~MSI_MASK; 522 writel(val, port->base + PCIE_INT_MASK); 523 } 524 525 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie) 526 { 527 struct mtk_pcie_port *port, *tmp; 528 529 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 530 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 531 532 if (port->irq_domain) 533 irq_domain_remove(port->irq_domain); 534 535 if (IS_ENABLED(CONFIG_PCI_MSI)) { 536 if (port->msi_domain) 537 irq_domain_remove(port->msi_domain); 538 if (port->inner_domain) 539 irq_domain_remove(port->inner_domain); 540 } 541 542 irq_dispose_mapping(port->irq); 543 } 544 } 545 546 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 547 irq_hw_number_t hwirq) 548 { 549 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 550 irq_set_chip_data(irq, domain->host_data); 551 552 return 0; 553 } 554 555 static const struct irq_domain_ops intx_domain_ops = { 556 .map = mtk_pcie_intx_map, 557 }; 558 559 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, 560 struct device_node *node) 561 { 562 struct device *dev = port->pcie->dev; 563 struct device_node *pcie_intc_node; 564 int ret; 565 566 /* Setup INTx */ 567 pcie_intc_node = of_get_next_child(node, NULL); 568 if (!pcie_intc_node) { 569 dev_err(dev, "no PCIe Intc node found\n"); 570 return -ENODEV; 571 } 572 573 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, 574 &intx_domain_ops, port); 575 if (!port->irq_domain) { 576 dev_err(dev, "failed to get INTx IRQ domain\n"); 577 return -ENODEV; 578 } 579 580 if (IS_ENABLED(CONFIG_PCI_MSI)) { 581 ret = mtk_pcie_allocate_msi_domains(port); 582 if (ret) 583 return ret; 584 } 585 586 return 0; 587 } 588 589 static void mtk_pcie_intr_handler(struct irq_desc *desc) 590 { 591 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); 592 struct irq_chip *irqchip = irq_desc_get_chip(desc); 593 unsigned long status; 594 u32 virq; 595 u32 bit = INTX_SHIFT; 596 597 chained_irq_enter(irqchip, desc); 598 599 status = readl(port->base + PCIE_INT_STATUS); 600 if (status & INTX_MASK) { 601 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { 602 /* Clear the INTx */ 603 writel(1 << bit, port->base + PCIE_INT_STATUS); 604 virq = irq_find_mapping(port->irq_domain, 605 bit - INTX_SHIFT); 606 generic_handle_irq(virq); 607 } 608 } 609 610 if (IS_ENABLED(CONFIG_PCI_MSI)) { 611 if (status & MSI_STATUS){ 612 unsigned long imsi_status; 613 614 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { 615 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) { 616 virq = irq_find_mapping(port->inner_domain, bit); 617 generic_handle_irq(virq); 618 } 619 } 620 /* Clear MSI interrupt status */ 621 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); 622 } 623 } 624 625 chained_irq_exit(irqchip, desc); 626 627 return; 628 } 629 630 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, 631 struct device_node *node) 632 { 633 struct mtk_pcie *pcie = port->pcie; 634 struct device *dev = pcie->dev; 635 struct platform_device *pdev = to_platform_device(dev); 636 int err; 637 638 err = mtk_pcie_init_irq_domain(port, node); 639 if (err) { 640 dev_err(dev, "failed to init PCIe IRQ domain\n"); 641 return err; 642 } 643 644 port->irq = platform_get_irq(pdev, port->slot); 645 irq_set_chained_handler_and_data(port->irq, 646 mtk_pcie_intr_handler, port); 647 648 return 0; 649 } 650 651 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) 652 { 653 struct mtk_pcie *pcie = port->pcie; 654 struct resource *mem = &pcie->mem; 655 const struct mtk_pcie_soc *soc = port->pcie->soc; 656 u32 val; 657 size_t size; 658 int err; 659 660 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */ 661 if (pcie->base) { 662 val = readl(pcie->base + PCIE_SYS_CFG_V2); 663 val |= PCIE_CSR_LTSSM_EN(port->slot) | 664 PCIE_CSR_ASPM_L1_EN(port->slot); 665 writel(val, pcie->base + PCIE_SYS_CFG_V2); 666 } 667 668 /* Assert all reset signals */ 669 writel(0, port->base + PCIE_RST_CTRL); 670 671 /* 672 * Enable PCIe link down reset, if link status changed from link up to 673 * link down, this will reset MAC control registers and configuration 674 * space. 675 */ 676 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); 677 678 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ 679 val = readl(port->base + PCIE_RST_CTRL); 680 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | 681 PCIE_MAC_SRSTB | PCIE_CRSTB; 682 writel(val, port->base + PCIE_RST_CTRL); 683 684 /* Set up vendor ID and class code */ 685 if (soc->need_fix_class_id) { 686 val = PCI_VENDOR_ID_MEDIATEK; 687 writew(val, port->base + PCIE_CONF_VEND_ID); 688 689 val = PCI_CLASS_BRIDGE_PCI; 690 writew(val, port->base + PCIE_CONF_CLASS_ID); 691 } 692 693 /* 100ms timeout value should be enough for Gen1/2 training */ 694 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, 695 !!(val & PCIE_PORT_LINKUP_V2), 20, 696 100 * USEC_PER_MSEC); 697 if (err) 698 return -ETIMEDOUT; 699 700 /* Set INTx mask */ 701 val = readl(port->base + PCIE_INT_MASK); 702 val &= ~INTX_MASK; 703 writel(val, port->base + PCIE_INT_MASK); 704 705 if (IS_ENABLED(CONFIG_PCI_MSI)) 706 mtk_pcie_enable_msi(port); 707 708 /* Set AHB to PCIe translation windows */ 709 size = mem->end - mem->start; 710 val = lower_32_bits(mem->start) | AHB2PCIE_SIZE(fls(size)); 711 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); 712 713 val = upper_32_bits(mem->start); 714 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); 715 716 /* Set PCIe to AXI translation memory space.*/ 717 val = fls(0xffffffff) | WIN_ENABLE; 718 writel(val, port->base + PCIE_AXI_WINDOW0); 719 720 return 0; 721 } 722 723 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, 724 unsigned int devfn, int where) 725 { 726 struct mtk_pcie *pcie = bus->sysdata; 727 728 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn), 729 bus->number), pcie->base + PCIE_CFG_ADDR); 730 731 return pcie->base + PCIE_CFG_DATA + (where & 3); 732 } 733 734 static struct pci_ops mtk_pcie_ops = { 735 .map_bus = mtk_pcie_map_bus, 736 .read = pci_generic_config_read, 737 .write = pci_generic_config_write, 738 }; 739 740 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) 741 { 742 struct mtk_pcie *pcie = port->pcie; 743 u32 func = PCI_FUNC(port->slot << 3); 744 u32 slot = PCI_SLOT(port->slot << 3); 745 u32 val; 746 int err; 747 748 /* assert port PERST_N */ 749 val = readl(pcie->base + PCIE_SYS_CFG); 750 val |= PCIE_PORT_PERST(port->slot); 751 writel(val, pcie->base + PCIE_SYS_CFG); 752 753 /* de-assert port PERST_N */ 754 val = readl(pcie->base + PCIE_SYS_CFG); 755 val &= ~PCIE_PORT_PERST(port->slot); 756 writel(val, pcie->base + PCIE_SYS_CFG); 757 758 /* 100ms timeout value should be enough for Gen1/2 training */ 759 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, 760 !!(val & PCIE_PORT_LINKUP), 20, 761 100 * USEC_PER_MSEC); 762 if (err) 763 return -ETIMEDOUT; 764 765 /* enable interrupt */ 766 val = readl(pcie->base + PCIE_INT_ENABLE); 767 val |= PCIE_PORT_INT_EN(port->slot); 768 writel(val, pcie->base + PCIE_INT_ENABLE); 769 770 /* map to all DDR region. We need to set it before cfg operation. */ 771 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, 772 port->base + PCIE_BAR0_SETUP); 773 774 /* configure class code and revision ID */ 775 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); 776 777 /* configure FC credit */ 778 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 779 pcie->base + PCIE_CFG_ADDR); 780 val = readl(pcie->base + PCIE_CFG_DATA); 781 val &= ~PCIE_FC_CREDIT_MASK; 782 val |= PCIE_FC_CREDIT_VAL(0x806c); 783 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0), 784 pcie->base + PCIE_CFG_ADDR); 785 writel(val, pcie->base + PCIE_CFG_DATA); 786 787 /* configure RC FTS number to 250 when it leaves L0s */ 788 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 789 pcie->base + PCIE_CFG_ADDR); 790 val = readl(pcie->base + PCIE_CFG_DATA); 791 val &= ~PCIE_FTS_NUM_MASK; 792 val |= PCIE_FTS_NUM_L0(0x50); 793 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0), 794 pcie->base + PCIE_CFG_ADDR); 795 writel(val, pcie->base + PCIE_CFG_DATA); 796 797 return 0; 798 } 799 800 static void mtk_pcie_enable_port(struct mtk_pcie_port *port) 801 { 802 struct mtk_pcie *pcie = port->pcie; 803 struct device *dev = pcie->dev; 804 int err; 805 806 err = clk_prepare_enable(port->sys_ck); 807 if (err) { 808 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); 809 goto err_sys_clk; 810 } 811 812 err = clk_prepare_enable(port->ahb_ck); 813 if (err) { 814 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); 815 goto err_ahb_clk; 816 } 817 818 err = clk_prepare_enable(port->aux_ck); 819 if (err) { 820 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); 821 goto err_aux_clk; 822 } 823 824 err = clk_prepare_enable(port->axi_ck); 825 if (err) { 826 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); 827 goto err_axi_clk; 828 } 829 830 err = clk_prepare_enable(port->obff_ck); 831 if (err) { 832 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); 833 goto err_obff_clk; 834 } 835 836 err = clk_prepare_enable(port->pipe_ck); 837 if (err) { 838 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); 839 goto err_pipe_clk; 840 } 841 842 reset_control_assert(port->reset); 843 reset_control_deassert(port->reset); 844 845 err = phy_init(port->phy); 846 if (err) { 847 dev_err(dev, "failed to initialize port%d phy\n", port->slot); 848 goto err_phy_init; 849 } 850 851 err = phy_power_on(port->phy); 852 if (err) { 853 dev_err(dev, "failed to power on port%d phy\n", port->slot); 854 goto err_phy_on; 855 } 856 857 if (!pcie->soc->startup(port)) 858 return; 859 860 dev_info(dev, "Port%d link down\n", port->slot); 861 862 phy_power_off(port->phy); 863 err_phy_on: 864 phy_exit(port->phy); 865 err_phy_init: 866 clk_disable_unprepare(port->pipe_ck); 867 err_pipe_clk: 868 clk_disable_unprepare(port->obff_ck); 869 err_obff_clk: 870 clk_disable_unprepare(port->axi_ck); 871 err_axi_clk: 872 clk_disable_unprepare(port->aux_ck); 873 err_aux_clk: 874 clk_disable_unprepare(port->ahb_ck); 875 err_ahb_clk: 876 clk_disable_unprepare(port->sys_ck); 877 err_sys_clk: 878 mtk_pcie_port_free(port); 879 } 880 881 static int mtk_pcie_parse_port(struct mtk_pcie *pcie, 882 struct device_node *node, 883 int slot) 884 { 885 struct mtk_pcie_port *port; 886 struct resource *regs; 887 struct device *dev = pcie->dev; 888 struct platform_device *pdev = to_platform_device(dev); 889 char name[10]; 890 int err; 891 892 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 893 if (!port) 894 return -ENOMEM; 895 896 snprintf(name, sizeof(name), "port%d", slot); 897 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 898 port->base = devm_ioremap_resource(dev, regs); 899 if (IS_ERR(port->base)) { 900 dev_err(dev, "failed to map port%d base\n", slot); 901 return PTR_ERR(port->base); 902 } 903 904 snprintf(name, sizeof(name), "sys_ck%d", slot); 905 port->sys_ck = devm_clk_get(dev, name); 906 if (IS_ERR(port->sys_ck)) { 907 dev_err(dev, "failed to get sys_ck%d clock\n", slot); 908 return PTR_ERR(port->sys_ck); 909 } 910 911 /* sys_ck might be divided into the following parts in some chips */ 912 snprintf(name, sizeof(name), "ahb_ck%d", slot); 913 port->ahb_ck = devm_clk_get(dev, name); 914 if (IS_ERR(port->ahb_ck)) { 915 if (PTR_ERR(port->ahb_ck) == -EPROBE_DEFER) 916 return -EPROBE_DEFER; 917 918 port->ahb_ck = NULL; 919 } 920 921 snprintf(name, sizeof(name), "axi_ck%d", slot); 922 port->axi_ck = devm_clk_get(dev, name); 923 if (IS_ERR(port->axi_ck)) { 924 if (PTR_ERR(port->axi_ck) == -EPROBE_DEFER) 925 return -EPROBE_DEFER; 926 927 port->axi_ck = NULL; 928 } 929 930 snprintf(name, sizeof(name), "aux_ck%d", slot); 931 port->aux_ck = devm_clk_get(dev, name); 932 if (IS_ERR(port->aux_ck)) { 933 if (PTR_ERR(port->aux_ck) == -EPROBE_DEFER) 934 return -EPROBE_DEFER; 935 936 port->aux_ck = NULL; 937 } 938 939 snprintf(name, sizeof(name), "obff_ck%d", slot); 940 port->obff_ck = devm_clk_get(dev, name); 941 if (IS_ERR(port->obff_ck)) { 942 if (PTR_ERR(port->obff_ck) == -EPROBE_DEFER) 943 return -EPROBE_DEFER; 944 945 port->obff_ck = NULL; 946 } 947 948 snprintf(name, sizeof(name), "pipe_ck%d", slot); 949 port->pipe_ck = devm_clk_get(dev, name); 950 if (IS_ERR(port->pipe_ck)) { 951 if (PTR_ERR(port->pipe_ck) == -EPROBE_DEFER) 952 return -EPROBE_DEFER; 953 954 port->pipe_ck = NULL; 955 } 956 957 snprintf(name, sizeof(name), "pcie-rst%d", slot); 958 port->reset = devm_reset_control_get_optional_exclusive(dev, name); 959 if (PTR_ERR(port->reset) == -EPROBE_DEFER) 960 return PTR_ERR(port->reset); 961 962 /* some platforms may use default PHY setting */ 963 snprintf(name, sizeof(name), "pcie-phy%d", slot); 964 port->phy = devm_phy_optional_get(dev, name); 965 if (IS_ERR(port->phy)) 966 return PTR_ERR(port->phy); 967 968 port->slot = slot; 969 port->pcie = pcie; 970 971 if (pcie->soc->setup_irq) { 972 err = pcie->soc->setup_irq(port, node); 973 if (err) 974 return err; 975 } 976 977 INIT_LIST_HEAD(&port->list); 978 list_add_tail(&port->list, &pcie->ports); 979 980 return 0; 981 } 982 983 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie) 984 { 985 struct device *dev = pcie->dev; 986 struct platform_device *pdev = to_platform_device(dev); 987 struct resource *regs; 988 int err; 989 990 /* get shared registers, which are optional */ 991 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys"); 992 if (regs) { 993 pcie->base = devm_ioremap_resource(dev, regs); 994 if (IS_ERR(pcie->base)) { 995 dev_err(dev, "failed to map shared register\n"); 996 return PTR_ERR(pcie->base); 997 } 998 } 999 1000 pcie->free_ck = devm_clk_get(dev, "free_ck"); 1001 if (IS_ERR(pcie->free_ck)) { 1002 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) 1003 return -EPROBE_DEFER; 1004 1005 pcie->free_ck = NULL; 1006 } 1007 1008 pm_runtime_enable(dev); 1009 pm_runtime_get_sync(dev); 1010 1011 /* enable top level clock */ 1012 err = clk_prepare_enable(pcie->free_ck); 1013 if (err) { 1014 dev_err(dev, "failed to enable free_ck\n"); 1015 goto err_free_ck; 1016 } 1017 1018 return 0; 1019 1020 err_free_ck: 1021 pm_runtime_put_sync(dev); 1022 pm_runtime_disable(dev); 1023 1024 return err; 1025 } 1026 1027 static int mtk_pcie_setup(struct mtk_pcie *pcie) 1028 { 1029 struct device *dev = pcie->dev; 1030 struct device_node *node = dev->of_node, *child; 1031 struct mtk_pcie_port *port, *tmp; 1032 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1033 struct list_head *windows = &host->windows; 1034 struct resource_entry *win, *tmp_win; 1035 resource_size_t io_base; 1036 int err; 1037 1038 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, 1039 windows, &io_base); 1040 if (err) 1041 return err; 1042 1043 err = devm_request_pci_bus_resources(dev, windows); 1044 if (err < 0) 1045 return err; 1046 1047 /* Get the I/O and memory ranges from DT */ 1048 resource_list_for_each_entry_safe(win, tmp_win, windows) { 1049 switch (resource_type(win->res)) { 1050 case IORESOURCE_IO: 1051 err = devm_pci_remap_iospace(dev, win->res, io_base); 1052 if (err) { 1053 dev_warn(dev, "error %d: failed to map resource %pR\n", 1054 err, win->res); 1055 resource_list_destroy_entry(win); 1056 } 1057 break; 1058 case IORESOURCE_MEM: 1059 memcpy(&pcie->mem, win->res, sizeof(*win->res)); 1060 pcie->mem.name = "non-prefetchable"; 1061 break; 1062 case IORESOURCE_BUS: 1063 pcie->busnr = win->res->start; 1064 break; 1065 } 1066 } 1067 1068 for_each_available_child_of_node(node, child) { 1069 int slot; 1070 1071 err = of_pci_get_devfn(child); 1072 if (err < 0) { 1073 dev_err(dev, "failed to parse devfn: %d\n", err); 1074 return err; 1075 } 1076 1077 slot = PCI_SLOT(err); 1078 1079 err = mtk_pcie_parse_port(pcie, child, slot); 1080 if (err) 1081 return err; 1082 } 1083 1084 err = mtk_pcie_subsys_powerup(pcie); 1085 if (err) 1086 return err; 1087 1088 /* enable each port, and then check link status */ 1089 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1090 mtk_pcie_enable_port(port); 1091 1092 /* power down PCIe subsys if slots are all empty (link down) */ 1093 if (list_empty(&pcie->ports)) 1094 mtk_pcie_subsys_powerdown(pcie); 1095 1096 return 0; 1097 } 1098 1099 static int mtk_pcie_probe(struct platform_device *pdev) 1100 { 1101 struct device *dev = &pdev->dev; 1102 struct mtk_pcie *pcie; 1103 struct pci_host_bridge *host; 1104 int err; 1105 1106 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 1107 if (!host) 1108 return -ENOMEM; 1109 1110 pcie = pci_host_bridge_priv(host); 1111 1112 pcie->dev = dev; 1113 pcie->soc = of_device_get_match_data(dev); 1114 platform_set_drvdata(pdev, pcie); 1115 INIT_LIST_HEAD(&pcie->ports); 1116 1117 err = mtk_pcie_setup(pcie); 1118 if (err) 1119 return err; 1120 1121 host->busnr = pcie->busnr; 1122 host->dev.parent = pcie->dev; 1123 host->ops = pcie->soc->ops; 1124 host->map_irq = of_irq_parse_and_map_pci; 1125 host->swizzle_irq = pci_common_swizzle; 1126 host->sysdata = pcie; 1127 1128 err = pci_host_probe(host); 1129 if (err) 1130 goto put_resources; 1131 1132 return 0; 1133 1134 put_resources: 1135 if (!list_empty(&pcie->ports)) 1136 mtk_pcie_put_resources(pcie); 1137 1138 return err; 1139 } 1140 1141 1142 static void mtk_pcie_free_resources(struct mtk_pcie *pcie) 1143 { 1144 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1145 struct list_head *windows = &host->windows; 1146 1147 pci_free_resource_list(windows); 1148 } 1149 1150 static int mtk_pcie_remove(struct platform_device *pdev) 1151 { 1152 struct mtk_pcie *pcie = platform_get_drvdata(pdev); 1153 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); 1154 1155 pci_stop_root_bus(host->bus); 1156 pci_remove_root_bus(host->bus); 1157 mtk_pcie_free_resources(pcie); 1158 1159 mtk_pcie_irq_teardown(pcie); 1160 1161 mtk_pcie_put_resources(pcie); 1162 1163 return 0; 1164 } 1165 1166 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) 1167 { 1168 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1169 struct mtk_pcie_port *port; 1170 1171 if (list_empty(&pcie->ports)) 1172 return 0; 1173 1174 list_for_each_entry(port, &pcie->ports, list) { 1175 clk_disable_unprepare(port->pipe_ck); 1176 clk_disable_unprepare(port->obff_ck); 1177 clk_disable_unprepare(port->axi_ck); 1178 clk_disable_unprepare(port->aux_ck); 1179 clk_disable_unprepare(port->ahb_ck); 1180 clk_disable_unprepare(port->sys_ck); 1181 phy_power_off(port->phy); 1182 phy_exit(port->phy); 1183 } 1184 1185 clk_disable_unprepare(pcie->free_ck); 1186 1187 return 0; 1188 } 1189 1190 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) 1191 { 1192 struct mtk_pcie *pcie = dev_get_drvdata(dev); 1193 struct mtk_pcie_port *port, *tmp; 1194 1195 if (list_empty(&pcie->ports)) 1196 return 0; 1197 1198 clk_prepare_enable(pcie->free_ck); 1199 1200 list_for_each_entry_safe(port, tmp, &pcie->ports, list) 1201 mtk_pcie_enable_port(port); 1202 1203 /* In case of EP was removed while system suspend. */ 1204 if (list_empty(&pcie->ports)) 1205 clk_disable_unprepare(pcie->free_ck); 1206 1207 return 0; 1208 } 1209 1210 static const struct dev_pm_ops mtk_pcie_pm_ops = { 1211 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, 1212 mtk_pcie_resume_noirq) 1213 }; 1214 1215 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { 1216 .ops = &mtk_pcie_ops, 1217 .startup = mtk_pcie_startup_port, 1218 }; 1219 1220 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { 1221 .ops = &mtk_pcie_ops_v2, 1222 .startup = mtk_pcie_startup_port_v2, 1223 .setup_irq = mtk_pcie_setup_irq, 1224 }; 1225 1226 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = { 1227 .need_fix_class_id = true, 1228 .ops = &mtk_pcie_ops_v2, 1229 .startup = mtk_pcie_startup_port_v2, 1230 .setup_irq = mtk_pcie_setup_irq, 1231 }; 1232 1233 static const struct of_device_id mtk_pcie_ids[] = { 1234 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 }, 1235 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 }, 1236 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 }, 1237 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 }, 1238 {}, 1239 }; 1240 1241 static struct platform_driver mtk_pcie_driver = { 1242 .probe = mtk_pcie_probe, 1243 .remove = mtk_pcie_remove, 1244 .driver = { 1245 .name = "mtk-pcie", 1246 .of_match_table = mtk_pcie_ids, 1247 .suppress_bind_attrs = true, 1248 .pm = &mtk_pcie_pm_ops, 1249 }, 1250 }; 1251 module_platform_driver(mtk_pcie_driver); 1252 MODULE_LICENSE("GPL v2"); 1253