1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Loongson PCI Host Controller Driver 4 * 5 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com> 6 */ 7 8 #include <linux/of_device.h> 9 #include <linux/of_pci.h> 10 #include <linux/pci.h> 11 #include <linux/pci_ids.h> 12 #include <linux/pci-acpi.h> 13 #include <linux/pci-ecam.h> 14 15 #include "../pci.h" 16 17 /* Device IDs */ 18 #define DEV_PCIE_PORT_0 0x7a09 19 #define DEV_PCIE_PORT_1 0x7a19 20 #define DEV_PCIE_PORT_2 0x7a29 21 22 #define DEV_LS2K_APB 0x7a02 23 #define DEV_LS7A_GMAC 0x7a03 24 #define DEV_LS7A_DC1 0x7a06 25 #define DEV_LS7A_LPC 0x7a0c 26 #define DEV_LS7A_AHCI 0x7a08 27 #define DEV_LS7A_CONF 0x7a10 28 #define DEV_LS7A_GNET 0x7a13 29 #define DEV_LS7A_EHCI 0x7a14 30 #define DEV_LS7A_DC2 0x7a36 31 #define DEV_LS7A_HDMI 0x7a37 32 33 #define FLAG_CFG0 BIT(0) 34 #define FLAG_CFG1 BIT(1) 35 #define FLAG_DEV_FIX BIT(2) 36 #define FLAG_DEV_HIDDEN BIT(3) 37 38 struct loongson_pci_data { 39 u32 flags; 40 struct pci_ops *ops; 41 }; 42 43 struct loongson_pci { 44 void __iomem *cfg0_base; 45 void __iomem *cfg1_base; 46 struct platform_device *pdev; 47 const struct loongson_pci_data *data; 48 }; 49 50 /* Fixup wrong class code in PCIe bridges */ 51 static void bridge_class_quirk(struct pci_dev *dev) 52 { 53 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 54 } 55 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 56 DEV_PCIE_PORT_0, bridge_class_quirk); 57 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 58 DEV_PCIE_PORT_1, bridge_class_quirk); 59 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 60 DEV_PCIE_PORT_2, bridge_class_quirk); 61 62 static void system_bus_quirk(struct pci_dev *pdev) 63 { 64 /* 65 * The address space consumed by these devices is outside the 66 * resources of the host bridge. 67 */ 68 pdev->mmio_always_on = 1; 69 pdev->non_compliant_bars = 1; 70 } 71 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 72 DEV_LS2K_APB, system_bus_quirk); 73 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 74 DEV_LS7A_CONF, system_bus_quirk); 75 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 76 DEV_LS7A_LPC, system_bus_quirk); 77 78 static void loongson_mrrs_quirk(struct pci_dev *pdev) 79 { 80 /* 81 * Some Loongson PCIe ports have h/w limitations of maximum read 82 * request size. They can't handle anything larger than this. So 83 * force this limit on any devices attached under these ports. 84 */ 85 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 86 87 bridge->no_inc_mrrs = 1; 88 } 89 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 90 DEV_PCIE_PORT_0, loongson_mrrs_quirk); 91 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 92 DEV_PCIE_PORT_1, loongson_mrrs_quirk); 93 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 94 DEV_PCIE_PORT_2, loongson_mrrs_quirk); 95 96 static void loongson_pci_pin_quirk(struct pci_dev *pdev) 97 { 98 pdev->pin = 1 + (PCI_FUNC(pdev->devfn) & 3); 99 } 100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 101 DEV_LS7A_DC1, loongson_pci_pin_quirk); 102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 103 DEV_LS7A_DC2, loongson_pci_pin_quirk); 104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 105 DEV_LS7A_GMAC, loongson_pci_pin_quirk); 106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 107 DEV_LS7A_AHCI, loongson_pci_pin_quirk); 108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 109 DEV_LS7A_EHCI, loongson_pci_pin_quirk); 110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 111 DEV_LS7A_GNET, loongson_pci_pin_quirk); 112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LOONGSON, 113 DEV_LS7A_HDMI, loongson_pci_pin_quirk); 114 115 static struct loongson_pci *pci_bus_to_loongson_pci(struct pci_bus *bus) 116 { 117 struct pci_config_window *cfg; 118 119 if (acpi_disabled) 120 return (struct loongson_pci *)(bus->sysdata); 121 122 cfg = bus->sysdata; 123 return (struct loongson_pci *)(cfg->priv); 124 } 125 126 static void __iomem *cfg0_map(struct loongson_pci *priv, struct pci_bus *bus, 127 unsigned int devfn, int where) 128 { 129 unsigned long addroff = 0x0; 130 unsigned char busnum = bus->number; 131 132 if (!pci_is_root_bus(bus)) { 133 addroff |= BIT(24); /* Type 1 Access */ 134 addroff |= (busnum << 16); 135 } 136 addroff |= (devfn << 8) | where; 137 return priv->cfg0_base + addroff; 138 } 139 140 static void __iomem *cfg1_map(struct loongson_pci *priv, struct pci_bus *bus, 141 unsigned int devfn, int where) 142 { 143 unsigned long addroff = 0x0; 144 unsigned char busnum = bus->number; 145 146 if (!pci_is_root_bus(bus)) { 147 addroff |= BIT(28); /* Type 1 Access */ 148 addroff |= (busnum << 16); 149 } 150 addroff |= (devfn << 8) | (where & 0xff) | ((where & 0xf00) << 16); 151 return priv->cfg1_base + addroff; 152 } 153 154 static bool pdev_may_exist(struct pci_bus *bus, unsigned int device, 155 unsigned int function) 156 { 157 return !(pci_is_root_bus(bus) && 158 (device >= 9 && device <= 20) && (function > 0)); 159 } 160 161 static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, 162 unsigned int devfn, int where) 163 { 164 unsigned int device = PCI_SLOT(devfn); 165 unsigned int function = PCI_FUNC(devfn); 166 struct loongson_pci *priv = pci_bus_to_loongson_pci(bus); 167 168 /* 169 * Do not read more than one device on the bus other than 170 * the host bus. 171 */ 172 if ((priv->data->flags & FLAG_DEV_FIX) && bus->self) { 173 if (!pci_is_root_bus(bus) && (device > 0)) 174 return NULL; 175 } 176 177 /* Don't access non-existent devices */ 178 if (priv->data->flags & FLAG_DEV_HIDDEN) { 179 if (!pdev_may_exist(bus, device, function)) 180 return NULL; 181 } 182 183 /* CFG0 can only access standard space */ 184 if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base) 185 return cfg0_map(priv, bus, devfn, where); 186 187 /* CFG1 can access extended space */ 188 if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base) 189 return cfg1_map(priv, bus, devfn, where); 190 191 return NULL; 192 } 193 194 #ifdef CONFIG_OF 195 196 static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 197 { 198 int irq; 199 u8 val; 200 201 irq = of_irq_parse_and_map_pci(dev, slot, pin); 202 if (irq > 0) 203 return irq; 204 205 /* Care i8259 legacy systems */ 206 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val); 207 /* i8259 only have 15 IRQs */ 208 if (val > 15) 209 return 0; 210 211 return val; 212 } 213 214 /* LS2K/LS7A accept 8/16/32-bit PCI config operations */ 215 static struct pci_ops loongson_pci_ops = { 216 .map_bus = pci_loongson_map_bus, 217 .read = pci_generic_config_read, 218 .write = pci_generic_config_write, 219 }; 220 221 /* RS780/SR5690 only accept 32-bit PCI config operations */ 222 static struct pci_ops loongson_pci_ops32 = { 223 .map_bus = pci_loongson_map_bus, 224 .read = pci_generic_config_read32, 225 .write = pci_generic_config_write32, 226 }; 227 228 static const struct loongson_pci_data ls2k_pci_data = { 229 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN, 230 .ops = &loongson_pci_ops, 231 }; 232 233 static const struct loongson_pci_data ls7a_pci_data = { 234 .flags = FLAG_CFG1 | FLAG_DEV_FIX | FLAG_DEV_HIDDEN, 235 .ops = &loongson_pci_ops, 236 }; 237 238 static const struct loongson_pci_data rs780e_pci_data = { 239 .flags = FLAG_CFG0, 240 .ops = &loongson_pci_ops32, 241 }; 242 243 static const struct of_device_id loongson_pci_of_match[] = { 244 { .compatible = "loongson,ls2k-pci", 245 .data = &ls2k_pci_data, }, 246 { .compatible = "loongson,ls7a-pci", 247 .data = &ls7a_pci_data, }, 248 { .compatible = "loongson,rs780e-pci", 249 .data = &rs780e_pci_data, }, 250 {} 251 }; 252 253 static int loongson_pci_probe(struct platform_device *pdev) 254 { 255 struct loongson_pci *priv; 256 struct device *dev = &pdev->dev; 257 struct device_node *node = dev->of_node; 258 struct pci_host_bridge *bridge; 259 struct resource *regs; 260 261 if (!node) 262 return -ENODEV; 263 264 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv)); 265 if (!bridge) 266 return -ENODEV; 267 268 priv = pci_host_bridge_priv(bridge); 269 priv->pdev = pdev; 270 priv->data = of_device_get_match_data(dev); 271 272 if (priv->data->flags & FLAG_CFG0) { 273 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 274 if (!regs) 275 dev_err(dev, "missing mem resources for cfg0\n"); 276 else { 277 priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs); 278 if (IS_ERR(priv->cfg0_base)) 279 return PTR_ERR(priv->cfg0_base); 280 } 281 } 282 283 if (priv->data->flags & FLAG_CFG1) { 284 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); 285 if (!regs) 286 dev_info(dev, "missing mem resource for cfg1\n"); 287 else { 288 priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs); 289 if (IS_ERR(priv->cfg1_base)) 290 priv->cfg1_base = NULL; 291 } 292 } 293 294 bridge->sysdata = priv; 295 bridge->ops = priv->data->ops; 296 bridge->map_irq = loongson_map_irq; 297 298 return pci_host_probe(bridge); 299 } 300 301 static struct platform_driver loongson_pci_driver = { 302 .driver = { 303 .name = "loongson-pci", 304 .of_match_table = loongson_pci_of_match, 305 }, 306 .probe = loongson_pci_probe, 307 }; 308 builtin_platform_driver(loongson_pci_driver); 309 310 #endif 311 312 #ifdef CONFIG_ACPI 313 314 static int loongson_pci_ecam_init(struct pci_config_window *cfg) 315 { 316 struct device *dev = cfg->parent; 317 struct loongson_pci *priv; 318 struct loongson_pci_data *data; 319 320 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 321 if (!priv) 322 return -ENOMEM; 323 324 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 325 if (!data) 326 return -ENOMEM; 327 328 cfg->priv = priv; 329 data->flags = FLAG_CFG1 | FLAG_DEV_HIDDEN; 330 priv->data = data; 331 priv->cfg1_base = cfg->win - (cfg->busr.start << 16); 332 333 return 0; 334 } 335 336 const struct pci_ecam_ops loongson_pci_ecam_ops = { 337 .bus_shift = 16, 338 .init = loongson_pci_ecam_init, 339 .pci_ops = { 340 .map_bus = pci_loongson_map_bus, 341 .read = pci_generic_config_read, 342 .write = pci_generic_config_write, 343 } 344 }; 345 346 #endif 347