1 /* 2 ** System Bus Adapter (SBA) I/O MMU manager 3 ** 4 ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org> 5 ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com> 6 ** (c) Copyright 2000-2004 Hewlett-Packard Company 7 ** 8 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code) 9 ** 10 ** This program is free software; you can redistribute it and/or modify 11 ** it under the terms of the GNU General Public License as published by 12 ** the Free Software Foundation; either version 2 of the License, or 13 ** (at your option) any later version. 14 ** 15 ** 16 ** This module initializes the IOC (I/O Controller) found on B1000/C3000/ 17 ** J5000/J7000/N-class/L-class machines and their successors. 18 ** 19 ** FIXME: add DMA hint support programming in both sba and lba modules. 20 */ 21 22 #include <linux/types.h> 23 #include <linux/kernel.h> 24 #include <linux/spinlock.h> 25 #include <linux/slab.h> 26 #include <linux/init.h> 27 28 #include <linux/mm.h> 29 #include <linux/string.h> 30 #include <linux/pci.h> 31 32 #include <asm/byteorder.h> 33 #include <asm/io.h> 34 #include <asm/dma.h> /* for DMA_CHUNK_SIZE */ 35 36 #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 37 38 #include <linux/proc_fs.h> 39 #include <linux/seq_file.h> 40 41 #include <asm/ropes.h> 42 #include <asm/mckinley.h> /* for proc_mckinley_root */ 43 #include <asm/runway.h> /* for proc_runway_root */ 44 #include <asm/pdc.h> /* for PDC_MODEL_* */ 45 #include <asm/pdcpat.h> /* for is_pdc_pat() */ 46 #include <asm/parisc-device.h> 47 48 #define MODULE_NAME "SBA" 49 50 /* 51 ** The number of debug flags is a clue - this code is fragile. 52 ** Don't even think about messing with it unless you have 53 ** plenty of 710's to sacrifice to the computer gods. :^) 54 */ 55 #undef DEBUG_SBA_INIT 56 #undef DEBUG_SBA_RUN 57 #undef DEBUG_SBA_RUN_SG 58 #undef DEBUG_SBA_RESOURCE 59 #undef ASSERT_PDIR_SANITY 60 #undef DEBUG_LARGE_SG_ENTRIES 61 #undef DEBUG_DMB_TRAP 62 63 #ifdef DEBUG_SBA_INIT 64 #define DBG_INIT(x...) printk(x) 65 #else 66 #define DBG_INIT(x...) 67 #endif 68 69 #ifdef DEBUG_SBA_RUN 70 #define DBG_RUN(x...) printk(x) 71 #else 72 #define DBG_RUN(x...) 73 #endif 74 75 #ifdef DEBUG_SBA_RUN_SG 76 #define DBG_RUN_SG(x...) printk(x) 77 #else 78 #define DBG_RUN_SG(x...) 79 #endif 80 81 82 #ifdef DEBUG_SBA_RESOURCE 83 #define DBG_RES(x...) printk(x) 84 #else 85 #define DBG_RES(x...) 86 #endif 87 88 #define SBA_INLINE __inline__ 89 90 #define DEFAULT_DMA_HINT_REG 0 91 92 static struct sba_device *sba_list; 93 94 static unsigned long ioc_needs_fdc = 0; 95 96 /* global count of IOMMUs in the system */ 97 static unsigned int global_ioc_cnt = 0; 98 99 /* PA8700 (Piranha 2.2) bug workaround */ 100 static unsigned long piranha_bad_128k = 0; 101 102 /* Looks nice and keeps the compiler happy */ 103 #define SBA_DEV(d) ((struct sba_device *) (d)) 104 105 #ifdef SBA_AGP_SUPPORT 106 static int reserve_sba_gart = 1; 107 #endif 108 109 #define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1)) 110 111 112 /************************************ 113 ** SBA register read and write support 114 ** 115 ** BE WARNED: register writes are posted. 116 ** (ie follow writes which must reach HW with a read) 117 ** 118 ** Superdome (in particular, REO) allows only 64-bit CSR accesses. 119 */ 120 #define READ_REG32(addr) readl(addr) 121 #define READ_REG64(addr) readq(addr) 122 #define WRITE_REG32(val, addr) writel((val), (addr)) 123 #define WRITE_REG64(val, addr) writeq((val), (addr)) 124 125 #ifdef CONFIG_64BIT 126 #define READ_REG(addr) READ_REG64(addr) 127 #define WRITE_REG(value, addr) WRITE_REG64(value, addr) 128 #else 129 #define READ_REG(addr) READ_REG32(addr) 130 #define WRITE_REG(value, addr) WRITE_REG32(value, addr) 131 #endif 132 133 #ifdef DEBUG_SBA_INIT 134 135 /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */ 136 137 /** 138 * sba_dump_ranges - debugging only - print ranges assigned to this IOA 139 * @hpa: base address of the sba 140 * 141 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO 142 * IO Adapter (aka Bus Converter). 143 */ 144 static void 145 sba_dump_ranges(void __iomem *hpa) 146 { 147 DBG_INIT("SBA at 0x%p\n", hpa); 148 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE)); 149 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK)); 150 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE)); 151 DBG_INIT("\n"); 152 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE)); 153 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK)); 154 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE)); 155 } 156 157 /** 158 * sba_dump_tlb - debugging only - print IOMMU operating parameters 159 * @hpa: base address of the IOMMU 160 * 161 * Print the size/location of the IO MMU PDIR. 162 */ 163 static void sba_dump_tlb(void __iomem *hpa) 164 { 165 DBG_INIT("IO TLB at 0x%p\n", hpa); 166 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE)); 167 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK)); 168 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG)); 169 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE)); 170 DBG_INIT("\n"); 171 } 172 #else 173 #define sba_dump_ranges(x) 174 #define sba_dump_tlb(x) 175 #endif /* DEBUG_SBA_INIT */ 176 177 178 #ifdef ASSERT_PDIR_SANITY 179 180 /** 181 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry 182 * @ioc: IO MMU structure which owns the pdir we are interested in. 183 * @msg: text to print ont the output line. 184 * @pide: pdir index. 185 * 186 * Print one entry of the IO MMU PDIR in human readable form. 187 */ 188 static void 189 sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide) 190 { 191 /* start printing from lowest pde in rval */ 192 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]); 193 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]); 194 uint rcnt; 195 196 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n", 197 msg, 198 rptr, pide & (BITS_PER_LONG - 1), *rptr); 199 200 rcnt = 0; 201 while (rcnt < BITS_PER_LONG) { 202 printk(KERN_DEBUG "%s %2d %p %016Lx\n", 203 (rcnt == (pide & (BITS_PER_LONG - 1))) 204 ? " -->" : " ", 205 rcnt, ptr, *ptr ); 206 rcnt++; 207 ptr++; 208 } 209 printk(KERN_DEBUG "%s", msg); 210 } 211 212 213 /** 214 * sba_check_pdir - debugging only - consistency checker 215 * @ioc: IO MMU structure which owns the pdir we are interested in. 216 * @msg: text to print ont the output line. 217 * 218 * Verify the resource map and pdir state is consistent 219 */ 220 static int 221 sba_check_pdir(struct ioc *ioc, char *msg) 222 { 223 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]); 224 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */ 225 u64 *pptr = ioc->pdir_base; /* pdir ptr */ 226 uint pide = 0; 227 228 while (rptr < rptr_end) { 229 u32 rval = *rptr; 230 int rcnt = 32; /* number of bits we might check */ 231 232 while (rcnt) { 233 /* Get last byte and highest bit from that */ 234 u32 pde = ((u32) (((char *)pptr)[7])) << 24; 235 if ((rval ^ pde) & 0x80000000) 236 { 237 /* 238 ** BUMMER! -- res_map != pdir -- 239 ** Dump rval and matching pdir entries 240 */ 241 sba_dump_pdir_entry(ioc, msg, pide); 242 return(1); 243 } 244 rcnt--; 245 rval <<= 1; /* try the next bit */ 246 pptr++; 247 pide++; 248 } 249 rptr++; /* look at next word of res_map */ 250 } 251 /* It'd be nice if we always got here :^) */ 252 return 0; 253 } 254 255 256 /** 257 * sba_dump_sg - debugging only - print Scatter-Gather list 258 * @ioc: IO MMU structure which owns the pdir we are interested in. 259 * @startsg: head of the SG list 260 * @nents: number of entries in SG list 261 * 262 * print the SG list so we can verify it's correct by hand. 263 */ 264 static void 265 sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents) 266 { 267 while (nents-- > 0) { 268 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n", 269 nents, 270 (unsigned long) sg_dma_address(startsg), 271 sg_dma_len(startsg), 272 sg_virt_addr(startsg), startsg->length); 273 startsg++; 274 } 275 } 276 277 #endif /* ASSERT_PDIR_SANITY */ 278 279 280 281 282 /************************************************************** 283 * 284 * I/O Pdir Resource Management 285 * 286 * Bits set in the resource map are in use. 287 * Each bit can represent a number of pages. 288 * LSbs represent lower addresses (IOVA's). 289 * 290 ***************************************************************/ 291 #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */ 292 293 /* Convert from IOVP to IOVA and vice versa. */ 294 295 #ifdef ZX1_SUPPORT 296 /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */ 297 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset)) 298 #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask) 299 #else 300 /* only support Astro and ancestors. Saves a few cycles in key places */ 301 #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset)) 302 #define SBA_IOVP(ioc,iova) (iova) 303 #endif 304 305 #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT) 306 307 #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n))) 308 #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1) 309 310 311 /** 312 * sba_search_bitmap - find free space in IO PDIR resource bitmap 313 * @ioc: IO MMU structure which owns the pdir we are interested in. 314 * @bits_wanted: number of entries we need. 315 * 316 * Find consecutive free bits in resource bitmap. 317 * Each bit represents one entry in the IO Pdir. 318 * Cool perf optimization: search for log2(size) bits at a time. 319 */ 320 static SBA_INLINE unsigned long 321 sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted) 322 { 323 unsigned long *res_ptr = ioc->res_hint; 324 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]); 325 unsigned long pide = ~0UL; 326 327 if (bits_wanted > (BITS_PER_LONG/2)) { 328 /* Search word at a time - no mask needed */ 329 for(; res_ptr < res_end; ++res_ptr) { 330 if (*res_ptr == 0) { 331 *res_ptr = RESMAP_MASK(bits_wanted); 332 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 333 pide <<= 3; /* convert to bit address */ 334 break; 335 } 336 } 337 /* point to the next word on next pass */ 338 res_ptr++; 339 ioc->res_bitshift = 0; 340 } else { 341 /* 342 ** Search the resource bit map on well-aligned values. 343 ** "o" is the alignment. 344 ** We need the alignment to invalidate I/O TLB using 345 ** SBA HW features in the unmap path. 346 */ 347 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT); 348 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o); 349 unsigned long mask; 350 351 if (bitshiftcnt >= BITS_PER_LONG) { 352 bitshiftcnt = 0; 353 res_ptr++; 354 } 355 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt; 356 357 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr); 358 while(res_ptr < res_end) 359 { 360 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr); 361 WARN_ON(mask == 0); 362 if(((*res_ptr) & mask) == 0) { 363 *res_ptr |= mask; /* mark resources busy! */ 364 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map); 365 pide <<= 3; /* convert to bit address */ 366 pide += bitshiftcnt; 367 break; 368 } 369 mask >>= o; 370 bitshiftcnt += o; 371 if (mask == 0) { 372 mask = RESMAP_MASK(bits_wanted); 373 bitshiftcnt=0; 374 res_ptr++; 375 } 376 } 377 /* look in the same word on the next pass */ 378 ioc->res_bitshift = bitshiftcnt + bits_wanted; 379 } 380 381 /* wrapped ? */ 382 if (res_end <= res_ptr) { 383 ioc->res_hint = (unsigned long *) ioc->res_map; 384 ioc->res_bitshift = 0; 385 } else { 386 ioc->res_hint = res_ptr; 387 } 388 return (pide); 389 } 390 391 392 /** 393 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap 394 * @ioc: IO MMU structure which owns the pdir we are interested in. 395 * @size: number of bytes to create a mapping for 396 * 397 * Given a size, find consecutive unmarked and then mark those bits in the 398 * resource bit map. 399 */ 400 static int 401 sba_alloc_range(struct ioc *ioc, size_t size) 402 { 403 unsigned int pages_needed = size >> IOVP_SHIFT; 404 #ifdef SBA_COLLECT_STATS 405 unsigned long cr_start = mfctl(16); 406 #endif 407 unsigned long pide; 408 409 pide = sba_search_bitmap(ioc, pages_needed); 410 if (pide >= (ioc->res_size << 3)) { 411 pide = sba_search_bitmap(ioc, pages_needed); 412 if (pide >= (ioc->res_size << 3)) 413 panic("%s: I/O MMU @ %p is out of mapping resources\n", 414 __FILE__, ioc->ioc_hpa); 415 } 416 417 #ifdef ASSERT_PDIR_SANITY 418 /* verify the first enable bit is clear */ 419 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) { 420 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide); 421 } 422 #endif 423 424 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n", 425 __FUNCTION__, size, pages_needed, pide, 426 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map), 427 ioc->res_bitshift ); 428 429 #ifdef SBA_COLLECT_STATS 430 { 431 unsigned long cr_end = mfctl(16); 432 unsigned long tmp = cr_end - cr_start; 433 /* check for roll over */ 434 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp); 435 } 436 ioc->avg_search[ioc->avg_idx++] = cr_start; 437 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1; 438 439 ioc->used_pages += pages_needed; 440 #endif 441 442 return (pide); 443 } 444 445 446 /** 447 * sba_free_range - unmark bits in IO PDIR resource bitmap 448 * @ioc: IO MMU structure which owns the pdir we are interested in. 449 * @iova: IO virtual address which was previously allocated. 450 * @size: number of bytes to create a mapping for 451 * 452 * clear bits in the ioc's resource map 453 */ 454 static SBA_INLINE void 455 sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size) 456 { 457 unsigned long iovp = SBA_IOVP(ioc, iova); 458 unsigned int pide = PDIR_INDEX(iovp); 459 unsigned int ridx = pide >> 3; /* convert bit to byte address */ 460 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]); 461 462 int bits_not_wanted = size >> IOVP_SHIFT; 463 464 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */ 465 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1)); 466 467 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", 468 __FUNCTION__, (uint) iova, size, 469 bits_not_wanted, m, pide, res_ptr, *res_ptr); 470 471 #ifdef SBA_COLLECT_STATS 472 ioc->used_pages -= bits_not_wanted; 473 #endif 474 475 *res_ptr &= ~m; 476 } 477 478 479 /************************************************************** 480 * 481 * "Dynamic DMA Mapping" support (aka "Coherent I/O") 482 * 483 ***************************************************************/ 484 485 #ifdef SBA_HINT_SUPPORT 486 #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir) 487 #endif 488 489 typedef unsigned long space_t; 490 #define KERNEL_SPACE 0 491 492 /** 493 * sba_io_pdir_entry - fill in one IO PDIR entry 494 * @pdir_ptr: pointer to IO PDIR entry 495 * @sid: process Space ID - currently only support KERNEL_SPACE 496 * @vba: Virtual CPU address of buffer to map 497 * @hint: DMA hint set to use for this mapping 498 * 499 * SBA Mapping Routine 500 * 501 * Given a virtual address (vba, arg2) and space id, (sid, arg1) 502 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by 503 * pdir_ptr (arg0). 504 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry 505 * for Astro/Ike looks like: 506 * 507 * 508 * 0 19 51 55 63 509 * +-+---------------------+----------------------------------+----+--------+ 510 * |V| U | PPN[43:12] | U | VI | 511 * +-+---------------------+----------------------------------+----+--------+ 512 * 513 * Pluto is basically identical, supports fewer physical address bits: 514 * 515 * 0 23 51 55 63 516 * +-+------------------------+-------------------------------+----+--------+ 517 * |V| U | PPN[39:12] | U | VI | 518 * +-+------------------------+-------------------------------+----+--------+ 519 * 520 * V == Valid Bit (Most Significant Bit is bit 0) 521 * U == Unused 522 * PPN == Physical Page Number 523 * VI == Virtual Index (aka Coherent Index) 524 * 525 * LPA instruction output is put into PPN field. 526 * LCI (Load Coherence Index) instruction provides the "VI" bits. 527 * 528 * We pre-swap the bytes since PCX-W is Big Endian and the 529 * IOMMU uses little endian for the pdir. 530 */ 531 532 void SBA_INLINE 533 sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba, 534 unsigned long hint) 535 { 536 u64 pa; /* physical address */ 537 register unsigned ci; /* coherent index */ 538 539 pa = virt_to_phys(vba); 540 pa &= IOVP_MASK; 541 542 mtsp(sid,1); 543 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 544 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 545 546 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */ 547 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 548 549 /* 550 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 551 * (bit #61, big endian), we have to flush and sync every time 552 * IO-PDIR is changed in Ike/Astro. 553 */ 554 if (ioc_needs_fdc) 555 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 556 } 557 558 559 /** 560 * sba_mark_invalid - invalidate one or more IO PDIR entries 561 * @ioc: IO MMU structure which owns the pdir we are interested in. 562 * @iova: IO Virtual Address mapped earlier 563 * @byte_cnt: number of bytes this mapping covers. 564 * 565 * Marking the IO PDIR entry(ies) as Invalid and invalidate 566 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register) 567 * is to purge stale entries in the IO TLB when unmapping entries. 568 * 569 * The PCOM register supports purging of multiple pages, with a minium 570 * of 1 page and a maximum of 2GB. Hardware requires the address be 571 * aligned to the size of the range being purged. The size of the range 572 * must be a power of 2. The "Cool perf optimization" in the 573 * allocation routine helps keep that true. 574 */ 575 static SBA_INLINE void 576 sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt) 577 { 578 u32 iovp = (u32) SBA_IOVP(ioc,iova); 579 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)]; 580 581 #ifdef ASSERT_PDIR_SANITY 582 /* Assert first pdir entry is set. 583 ** 584 ** Even though this is a big-endian machine, the entries 585 ** in the iopdir are little endian. That's why we look at 586 ** the byte at +7 instead of at +0. 587 */ 588 if (0x80 != (((u8 *) pdir_ptr)[7])) { 589 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp)); 590 } 591 #endif 592 593 if (byte_cnt > IOVP_SIZE) 594 { 595 #if 0 596 unsigned long entries_per_cacheline = ioc_needs_fdc ? 597 L1_CACHE_ALIGN(((unsigned long) pdir_ptr)) 598 - (unsigned long) pdir_ptr; 599 : 262144; 600 #endif 601 602 /* set "size" field for PCOM */ 603 iovp |= get_order(byte_cnt) + PAGE_SHIFT; 604 605 do { 606 /* clear I/O Pdir entry "valid" bit first */ 607 ((u8 *) pdir_ptr)[7] = 0; 608 if (ioc_needs_fdc) { 609 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 610 #if 0 611 entries_per_cacheline = L1_CACHE_SHIFT - 3; 612 #endif 613 } 614 pdir_ptr++; 615 byte_cnt -= IOVP_SIZE; 616 } while (byte_cnt > IOVP_SIZE); 617 } else 618 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */ 619 620 /* 621 ** clear I/O PDIR entry "valid" bit. 622 ** We have to R/M/W the cacheline regardless how much of the 623 ** pdir entry that we clobber. 624 ** The rest of the entry would be useful for debugging if we 625 ** could dump core on HPMC. 626 */ 627 ((u8 *) pdir_ptr)[7] = 0; 628 if (ioc_needs_fdc) 629 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr)); 630 631 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM); 632 } 633 634 /** 635 * sba_dma_supported - PCI driver can query DMA support 636 * @dev: instance of PCI owned by the driver that's asking 637 * @mask: number of address bits this PCI device can handle 638 * 639 * See Documentation/DMA-mapping.txt 640 */ 641 static int sba_dma_supported( struct device *dev, u64 mask) 642 { 643 struct ioc *ioc; 644 645 if (dev == NULL) { 646 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n"); 647 BUG(); 648 return(0); 649 } 650 651 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first, 652 * then fall back to 32-bit if that fails. 653 * We are just "encouraging" 32-bit DMA masks here since we can 654 * never allow IOMMU bypass unless we add special support for ZX1. 655 */ 656 if (mask > ~0U) 657 return 0; 658 659 ioc = GET_IOC(dev); 660 661 /* 662 * check if mask is >= than the current max IO Virt Address 663 * The max IO Virt address will *always* < 30 bits. 664 */ 665 return((int)(mask >= (ioc->ibase - 1 + 666 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) ))); 667 } 668 669 670 /** 671 * sba_map_single - map one buffer and return IOVA for DMA 672 * @dev: instance of PCI owned by the driver that's asking. 673 * @addr: driver buffer to map. 674 * @size: number of bytes to map in driver buffer. 675 * @direction: R/W or both. 676 * 677 * See Documentation/DMA-mapping.txt 678 */ 679 static dma_addr_t 680 sba_map_single(struct device *dev, void *addr, size_t size, 681 enum dma_data_direction direction) 682 { 683 struct ioc *ioc; 684 unsigned long flags; 685 dma_addr_t iovp; 686 dma_addr_t offset; 687 u64 *pdir_start; 688 int pide; 689 690 ioc = GET_IOC(dev); 691 692 /* save offset bits */ 693 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK; 694 695 /* round up to nearest IOVP_SIZE */ 696 size = (size + offset + ~IOVP_MASK) & IOVP_MASK; 697 698 spin_lock_irqsave(&ioc->res_lock, flags); 699 #ifdef ASSERT_PDIR_SANITY 700 sba_check_pdir(ioc,"Check before sba_map_single()"); 701 #endif 702 703 #ifdef SBA_COLLECT_STATS 704 ioc->msingle_calls++; 705 ioc->msingle_pages += size >> IOVP_SHIFT; 706 #endif 707 pide = sba_alloc_range(ioc, size); 708 iovp = (dma_addr_t) pide << IOVP_SHIFT; 709 710 DBG_RUN("%s() 0x%p -> 0x%lx\n", 711 __FUNCTION__, addr, (long) iovp | offset); 712 713 pdir_start = &(ioc->pdir_base[pide]); 714 715 while (size > 0) { 716 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0); 717 718 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n", 719 pdir_start, 720 (u8) (((u8 *) pdir_start)[7]), 721 (u8) (((u8 *) pdir_start)[6]), 722 (u8) (((u8 *) pdir_start)[5]), 723 (u8) (((u8 *) pdir_start)[4]), 724 (u8) (((u8 *) pdir_start)[3]), 725 (u8) (((u8 *) pdir_start)[2]), 726 (u8) (((u8 *) pdir_start)[1]), 727 (u8) (((u8 *) pdir_start)[0]) 728 ); 729 730 addr += IOVP_SIZE; 731 size -= IOVP_SIZE; 732 pdir_start++; 733 } 734 735 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 736 if (ioc_needs_fdc) 737 asm volatile("sync" : : ); 738 739 #ifdef ASSERT_PDIR_SANITY 740 sba_check_pdir(ioc,"Check after sba_map_single()"); 741 #endif 742 spin_unlock_irqrestore(&ioc->res_lock, flags); 743 744 /* form complete address */ 745 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG); 746 } 747 748 749 /** 750 * sba_unmap_single - unmap one IOVA and free resources 751 * @dev: instance of PCI owned by the driver that's asking. 752 * @iova: IOVA of driver buffer previously mapped. 753 * @size: number of bytes mapped in driver buffer. 754 * @direction: R/W or both. 755 * 756 * See Documentation/DMA-mapping.txt 757 */ 758 static void 759 sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, 760 enum dma_data_direction direction) 761 { 762 struct ioc *ioc; 763 #if DELAYED_RESOURCE_CNT > 0 764 struct sba_dma_pair *d; 765 #endif 766 unsigned long flags; 767 dma_addr_t offset; 768 769 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size); 770 771 ioc = GET_IOC(dev); 772 offset = iova & ~IOVP_MASK; 773 iova ^= offset; /* clear offset bits */ 774 size += offset; 775 size = ROUNDUP(size, IOVP_SIZE); 776 777 spin_lock_irqsave(&ioc->res_lock, flags); 778 779 #ifdef SBA_COLLECT_STATS 780 ioc->usingle_calls++; 781 ioc->usingle_pages += size >> IOVP_SHIFT; 782 #endif 783 784 sba_mark_invalid(ioc, iova, size); 785 786 #if DELAYED_RESOURCE_CNT > 0 787 /* Delaying when we re-use a IO Pdir entry reduces the number 788 * of MMIO reads needed to flush writes to the PCOM register. 789 */ 790 d = &(ioc->saved[ioc->saved_cnt]); 791 d->iova = iova; 792 d->size = size; 793 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) { 794 int cnt = ioc->saved_cnt; 795 while (cnt--) { 796 sba_free_range(ioc, d->iova, d->size); 797 d--; 798 } 799 ioc->saved_cnt = 0; 800 801 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 802 } 803 #else /* DELAYED_RESOURCE_CNT == 0 */ 804 sba_free_range(ioc, iova, size); 805 806 /* If fdc's were issued, force fdc's to be visible now */ 807 if (ioc_needs_fdc) 808 asm volatile("sync" : : ); 809 810 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */ 811 #endif /* DELAYED_RESOURCE_CNT == 0 */ 812 813 spin_unlock_irqrestore(&ioc->res_lock, flags); 814 815 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support. 816 ** For Astro based systems this isn't a big deal WRT performance. 817 ** As long as 2.4 kernels copyin/copyout data from/to userspace, 818 ** we don't need the syncdma. The issue here is I/O MMU cachelines 819 ** are *not* coherent in all cases. May be hwrev dependent. 820 ** Need to investigate more. 821 asm volatile("syncdma"); 822 */ 823 } 824 825 826 /** 827 * sba_alloc_consistent - allocate/map shared mem for DMA 828 * @hwdev: instance of PCI owned by the driver that's asking. 829 * @size: number of bytes mapped in driver buffer. 830 * @dma_handle: IOVA of new buffer. 831 * 832 * See Documentation/DMA-mapping.txt 833 */ 834 static void *sba_alloc_consistent(struct device *hwdev, size_t size, 835 dma_addr_t *dma_handle, gfp_t gfp) 836 { 837 void *ret; 838 839 if (!hwdev) { 840 /* only support PCI */ 841 *dma_handle = 0; 842 return 0; 843 } 844 845 ret = (void *) __get_free_pages(gfp, get_order(size)); 846 847 if (ret) { 848 memset(ret, 0, size); 849 *dma_handle = sba_map_single(hwdev, ret, size, 0); 850 } 851 852 return ret; 853 } 854 855 856 /** 857 * sba_free_consistent - free/unmap shared mem for DMA 858 * @hwdev: instance of PCI owned by the driver that's asking. 859 * @size: number of bytes mapped in driver buffer. 860 * @vaddr: virtual address IOVA of "consistent" buffer. 861 * @dma_handler: IO virtual address of "consistent" buffer. 862 * 863 * See Documentation/DMA-mapping.txt 864 */ 865 static void 866 sba_free_consistent(struct device *hwdev, size_t size, void *vaddr, 867 dma_addr_t dma_handle) 868 { 869 sba_unmap_single(hwdev, dma_handle, size, 0); 870 free_pages((unsigned long) vaddr, get_order(size)); 871 } 872 873 874 /* 875 ** Since 0 is a valid pdir_base index value, can't use that 876 ** to determine if a value is valid or not. Use a flag to indicate 877 ** the SG list entry contains a valid pdir index. 878 */ 879 #define PIDE_FLAG 0x80000000UL 880 881 #ifdef SBA_COLLECT_STATS 882 #define IOMMU_MAP_STATS 883 #endif 884 #include "iommu-helpers.h" 885 886 #ifdef DEBUG_LARGE_SG_ENTRIES 887 int dump_run_sg = 0; 888 #endif 889 890 891 /** 892 * sba_map_sg - map Scatter/Gather list 893 * @dev: instance of PCI owned by the driver that's asking. 894 * @sglist: array of buffer/length pairs 895 * @nents: number of entries in list 896 * @direction: R/W or both. 897 * 898 * See Documentation/DMA-mapping.txt 899 */ 900 static int 901 sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, 902 enum dma_data_direction direction) 903 { 904 struct ioc *ioc; 905 int coalesced, filled = 0; 906 unsigned long flags; 907 908 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents); 909 910 ioc = GET_IOC(dev); 911 912 /* Fast path single entry scatterlists. */ 913 if (nents == 1) { 914 sg_dma_address(sglist) = sba_map_single(dev, 915 (void *)sg_virt_addr(sglist), 916 sglist->length, direction); 917 sg_dma_len(sglist) = sglist->length; 918 return 1; 919 } 920 921 spin_lock_irqsave(&ioc->res_lock, flags); 922 923 #ifdef ASSERT_PDIR_SANITY 924 if (sba_check_pdir(ioc,"Check before sba_map_sg()")) 925 { 926 sba_dump_sg(ioc, sglist, nents); 927 panic("Check before sba_map_sg()"); 928 } 929 #endif 930 931 #ifdef SBA_COLLECT_STATS 932 ioc->msg_calls++; 933 #endif 934 935 /* 936 ** First coalesce the chunks and allocate I/O pdir space 937 ** 938 ** If this is one DMA stream, we can properly map using the 939 ** correct virtual address associated with each DMA page. 940 ** w/o this association, we wouldn't have coherent DMA! 941 ** Access to the virtual address is what forces a two pass algorithm. 942 */ 943 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range); 944 945 /* 946 ** Program the I/O Pdir 947 ** 948 ** map the virtual addresses to the I/O Pdir 949 ** o dma_address will contain the pdir index 950 ** o dma_len will contain the number of bytes to map 951 ** o address contains the virtual address. 952 */ 953 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry); 954 955 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */ 956 if (ioc_needs_fdc) 957 asm volatile("sync" : : ); 958 959 #ifdef ASSERT_PDIR_SANITY 960 if (sba_check_pdir(ioc,"Check after sba_map_sg()")) 961 { 962 sba_dump_sg(ioc, sglist, nents); 963 panic("Check after sba_map_sg()\n"); 964 } 965 #endif 966 967 spin_unlock_irqrestore(&ioc->res_lock, flags); 968 969 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled); 970 971 return filled; 972 } 973 974 975 /** 976 * sba_unmap_sg - unmap Scatter/Gather list 977 * @dev: instance of PCI owned by the driver that's asking. 978 * @sglist: array of buffer/length pairs 979 * @nents: number of entries in list 980 * @direction: R/W or both. 981 * 982 * See Documentation/DMA-mapping.txt 983 */ 984 static void 985 sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents, 986 enum dma_data_direction direction) 987 { 988 struct ioc *ioc; 989 #ifdef ASSERT_PDIR_SANITY 990 unsigned long flags; 991 #endif 992 993 DBG_RUN_SG("%s() START %d entries, %p,%x\n", 994 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length); 995 996 ioc = GET_IOC(dev); 997 998 #ifdef SBA_COLLECT_STATS 999 ioc->usg_calls++; 1000 #endif 1001 1002 #ifdef ASSERT_PDIR_SANITY 1003 spin_lock_irqsave(&ioc->res_lock, flags); 1004 sba_check_pdir(ioc,"Check before sba_unmap_sg()"); 1005 spin_unlock_irqrestore(&ioc->res_lock, flags); 1006 #endif 1007 1008 while (sg_dma_len(sglist) && nents--) { 1009 1010 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction); 1011 #ifdef SBA_COLLECT_STATS 1012 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT; 1013 ioc->usingle_calls--; /* kluge since call is unmap_sg() */ 1014 #endif 1015 ++sglist; 1016 } 1017 1018 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents); 1019 1020 #ifdef ASSERT_PDIR_SANITY 1021 spin_lock_irqsave(&ioc->res_lock, flags); 1022 sba_check_pdir(ioc,"Check after sba_unmap_sg()"); 1023 spin_unlock_irqrestore(&ioc->res_lock, flags); 1024 #endif 1025 1026 } 1027 1028 static struct hppa_dma_ops sba_ops = { 1029 .dma_supported = sba_dma_supported, 1030 .alloc_consistent = sba_alloc_consistent, 1031 .alloc_noncoherent = sba_alloc_consistent, 1032 .free_consistent = sba_free_consistent, 1033 .map_single = sba_map_single, 1034 .unmap_single = sba_unmap_single, 1035 .map_sg = sba_map_sg, 1036 .unmap_sg = sba_unmap_sg, 1037 .dma_sync_single_for_cpu = NULL, 1038 .dma_sync_single_for_device = NULL, 1039 .dma_sync_sg_for_cpu = NULL, 1040 .dma_sync_sg_for_device = NULL, 1041 }; 1042 1043 1044 /************************************************************************** 1045 ** 1046 ** SBA PAT PDC support 1047 ** 1048 ** o call pdc_pat_cell_module() 1049 ** o store ranges in PCI "resource" structures 1050 ** 1051 **************************************************************************/ 1052 1053 static void 1054 sba_get_pat_resources(struct sba_device *sba_dev) 1055 { 1056 #if 0 1057 /* 1058 ** TODO/REVISIT/FIXME: support for directed ranges requires calls to 1059 ** PAT PDC to program the SBA/LBA directed range registers...this 1060 ** burden may fall on the LBA code since it directly supports the 1061 ** PCI subsystem. It's not clear yet. - ggg 1062 */ 1063 PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp); 1064 FIXME : ??? 1065 PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp); 1066 Tells where the dvi bits are located in the address. 1067 PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp); 1068 FIXME : ??? 1069 #endif 1070 } 1071 1072 1073 /************************************************************** 1074 * 1075 * Initialization and claim 1076 * 1077 ***************************************************************/ 1078 #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */ 1079 #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */ 1080 static void * 1081 sba_alloc_pdir(unsigned int pdir_size) 1082 { 1083 unsigned long pdir_base; 1084 unsigned long pdir_order = get_order(pdir_size); 1085 1086 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order); 1087 if (NULL == (void *) pdir_base) { 1088 panic("%s() could not allocate I/O Page Table\n", 1089 __FUNCTION__); 1090 } 1091 1092 /* If this is not PA8700 (PCX-W2) 1093 ** OR newer than ver 2.2 1094 ** OR in a system that doesn't need VINDEX bits from SBA, 1095 ** 1096 ** then we aren't exposed to the HW bug. 1097 */ 1098 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13 1099 || (boot_cpu_data.pdc.versions > 0x202) 1100 || (boot_cpu_data.pdc.capabilities & 0x08L) ) 1101 return (void *) pdir_base; 1102 1103 /* 1104 * PA8700 (PCX-W2, aka piranha) silent data corruption fix 1105 * 1106 * An interaction between PA8700 CPU (Ver 2.2 or older) and 1107 * Ike/Astro can cause silent data corruption. This is only 1108 * a problem if the I/O PDIR is located in memory such that 1109 * (little-endian) bits 17 and 18 are on and bit 20 is off. 1110 * 1111 * Since the max IO Pdir size is 2MB, by cleverly allocating the 1112 * right physical address, we can either avoid (IOPDIR <= 1MB) 1113 * or minimize (2MB IO Pdir) the problem if we restrict the 1114 * IO Pdir to a maximum size of 2MB-128K (1902K). 1115 * 1116 * Because we always allocate 2^N sized IO pdirs, either of the 1117 * "bad" regions will be the last 128K if at all. That's easy 1118 * to test for. 1119 * 1120 */ 1121 if (pdir_order <= (19-12)) { 1122 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) { 1123 /* allocate a new one on 512k alignment */ 1124 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12)); 1125 /* release original */ 1126 free_pages(pdir_base, pdir_order); 1127 1128 pdir_base = new_pdir; 1129 1130 /* release excess */ 1131 while (pdir_order < (19-12)) { 1132 new_pdir += pdir_size; 1133 free_pages(new_pdir, pdir_order); 1134 pdir_order +=1; 1135 pdir_size <<=1; 1136 } 1137 } 1138 } else { 1139 /* 1140 ** 1MB or 2MB Pdir 1141 ** Needs to be aligned on an "odd" 1MB boundary. 1142 */ 1143 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */ 1144 1145 /* release original */ 1146 free_pages( pdir_base, pdir_order); 1147 1148 /* release first 1MB */ 1149 free_pages(new_pdir, 20-12); 1150 1151 pdir_base = new_pdir + 1024*1024; 1152 1153 if (pdir_order > (20-12)) { 1154 /* 1155 ** 2MB Pdir. 1156 ** 1157 ** Flag tells init_bitmap() to mark bad 128k as used 1158 ** and to reduce the size by 128k. 1159 */ 1160 piranha_bad_128k = 1; 1161 1162 new_pdir += 3*1024*1024; 1163 /* release last 1MB */ 1164 free_pages(new_pdir, 20-12); 1165 1166 /* release unusable 128KB */ 1167 free_pages(new_pdir - 128*1024 , 17-12); 1168 1169 pdir_size -= 128*1024; 1170 } 1171 } 1172 1173 memset((void *) pdir_base, 0, pdir_size); 1174 return (void *) pdir_base; 1175 } 1176 1177 static struct device *next_device(struct klist_iter *i) 1178 { 1179 struct klist_node * n = klist_next(i); 1180 return n ? container_of(n, struct device, knode_parent) : NULL; 1181 } 1182 1183 /* setup Mercury or Elroy IBASE/IMASK registers. */ 1184 static void 1185 setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1186 { 1187 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ 1188 extern void lba_set_iregs(struct parisc_device *, u32, u32); 1189 struct device *dev; 1190 struct klist_iter i; 1191 1192 klist_iter_init(&sba->dev.klist_children, &i); 1193 while ((dev = next_device(&i))) { 1194 struct parisc_device *lba = to_parisc_device(dev); 1195 int rope_num = (lba->hpa.start >> 13) & 0xf; 1196 if (rope_num >> 3 == ioc_num) 1197 lba_set_iregs(lba, ioc->ibase, ioc->imask); 1198 } 1199 klist_iter_exit(&i); 1200 } 1201 1202 static void 1203 sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1204 { 1205 u32 iova_space_mask; 1206 u32 iova_space_size; 1207 int iov_order, tcnfg; 1208 #ifdef SBA_AGP_SUPPORT 1209 int agp_found = 0; 1210 #endif 1211 /* 1212 ** Firmware programs the base and size of a "safe IOVA space" 1213 ** (one that doesn't overlap memory or LMMIO space) in the 1214 ** IBASE and IMASK registers. 1215 */ 1216 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE); 1217 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1; 1218 1219 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) { 1220 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n"); 1221 iova_space_size /= 2; 1222 } 1223 1224 /* 1225 ** iov_order is always based on a 1GB IOVA space since we want to 1226 ** turn on the other half for AGP GART. 1227 */ 1228 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT)); 1229 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64); 1230 1231 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n", 1232 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20, 1233 iov_order + PAGE_SHIFT); 1234 1235 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL, 1236 get_order(ioc->pdir_size)); 1237 if (!ioc->pdir_base) 1238 panic("Couldn't allocate I/O Page Table\n"); 1239 1240 memset(ioc->pdir_base, 0, ioc->pdir_size); 1241 1242 DBG_INIT("%s() pdir %p size %x\n", 1243 __FUNCTION__, ioc->pdir_base, ioc->pdir_size); 1244 1245 #ifdef SBA_HINT_SUPPORT 1246 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1247 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1248 1249 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1250 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1251 #endif 1252 1253 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base); 1254 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1255 1256 /* build IMASK for IOC and Elroy */ 1257 iova_space_mask = 0xffffffff; 1258 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1259 ioc->imask = iova_space_mask; 1260 #ifdef ZX1_SUPPORT 1261 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1262 #endif 1263 sba_dump_tlb(ioc->ioc_hpa); 1264 1265 setup_ibase_imask(sba, ioc, ioc_num); 1266 1267 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK); 1268 1269 #ifdef CONFIG_64BIT 1270 /* 1271 ** Setting the upper bits makes checking for bypass addresses 1272 ** a little faster later on. 1273 */ 1274 ioc->imask |= 0xFFFFFFFF00000000UL; 1275 #endif 1276 1277 /* Set I/O PDIR Page size to system page size */ 1278 switch (PAGE_SHIFT) { 1279 case 12: tcnfg = 0; break; /* 4K */ 1280 case 13: tcnfg = 1; break; /* 8K */ 1281 case 14: tcnfg = 2; break; /* 16K */ 1282 case 16: tcnfg = 3; break; /* 64K */ 1283 default: 1284 panic(__FILE__ "Unsupported system page size %d", 1285 1 << PAGE_SHIFT); 1286 break; 1287 } 1288 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG); 1289 1290 /* 1291 ** Program the IOC's ibase and enable IOVA translation 1292 ** Bit zero == enable bit. 1293 */ 1294 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE); 1295 1296 /* 1297 ** Clear I/O TLB of any possible entries. 1298 ** (Yes. This is a bit paranoid...but so what) 1299 */ 1300 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); 1301 1302 #ifdef SBA_AGP_SUPPORT 1303 /* 1304 ** If an AGP device is present, only use half of the IOV space 1305 ** for PCI DMA. Unfortunately we can't know ahead of time 1306 ** whether GART support will actually be used, for now we 1307 ** can just key on any AGP device found in the system. 1308 ** We program the next pdir index after we stop w/ a key for 1309 ** the GART code to handshake on. 1310 */ 1311 device=NULL; 1312 for (lba = sba->child; lba; lba = lba->sibling) { 1313 if (IS_QUICKSILVER(lba)) 1314 break; 1315 } 1316 1317 if (lba) { 1318 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__); 1319 ioc->pdir_size /= 2; 1320 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE; 1321 } else { 1322 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__); 1323 } 1324 #endif /* 0 */ 1325 1326 } 1327 1328 static void 1329 sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num) 1330 { 1331 u32 iova_space_size, iova_space_mask; 1332 unsigned int pdir_size, iov_order; 1333 1334 /* 1335 ** Determine IOVA Space size from memory size. 1336 ** 1337 ** Ideally, PCI drivers would register the maximum number 1338 ** of DMA they can have outstanding for each device they 1339 ** own. Next best thing would be to guess how much DMA 1340 ** can be outstanding based on PCI Class/sub-class. Both 1341 ** methods still require some "extra" to support PCI 1342 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD). 1343 ** 1344 ** While we have 32-bits "IOVA" space, top two 2 bits are used 1345 ** for DMA hints - ergo only 30 bits max. 1346 */ 1347 1348 iova_space_size = (u32) (num_physpages/global_ioc_cnt); 1349 1350 /* limit IOVA space size to 1MB-1GB */ 1351 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) { 1352 iova_space_size = 1 << (20 - PAGE_SHIFT); 1353 } 1354 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) { 1355 iova_space_size = 1 << (30 - PAGE_SHIFT); 1356 } 1357 1358 /* 1359 ** iova space must be log2() in size. 1360 ** thus, pdir/res_map will also be log2(). 1361 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced) 1362 */ 1363 iov_order = get_order(iova_space_size << PAGE_SHIFT); 1364 1365 /* iova_space_size is now bytes, not pages */ 1366 iova_space_size = 1 << (iov_order + PAGE_SHIFT); 1367 1368 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64); 1369 1370 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n", 1371 __FUNCTION__, 1372 ioc->ioc_hpa, 1373 (unsigned long) num_physpages >> (20 - PAGE_SHIFT), 1374 iova_space_size>>20, 1375 iov_order + PAGE_SHIFT); 1376 1377 ioc->pdir_base = sba_alloc_pdir(pdir_size); 1378 1379 DBG_INIT("%s() pdir %p size %x\n", 1380 __FUNCTION__, ioc->pdir_base, pdir_size); 1381 1382 #ifdef SBA_HINT_SUPPORT 1383 /* FIXME : DMA HINTs not used */ 1384 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT; 1385 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT)); 1386 1387 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n", 1388 ioc->hint_shift_pdir, ioc->hint_mask_pdir); 1389 #endif 1390 1391 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE); 1392 1393 /* build IMASK for IOC and Elroy */ 1394 iova_space_mask = 0xffffffff; 1395 iova_space_mask <<= (iov_order + PAGE_SHIFT); 1396 1397 /* 1398 ** On C3000 w/512MB mem, HP-UX 10.20 reports: 1399 ** ibase=0, imask=0xFE000000, size=0x2000000. 1400 */ 1401 ioc->ibase = 0; 1402 ioc->imask = iova_space_mask; /* save it */ 1403 #ifdef ZX1_SUPPORT 1404 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1); 1405 #endif 1406 1407 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n", 1408 __FUNCTION__, ioc->ibase, ioc->imask); 1409 1410 /* 1411 ** FIXME: Hint registers are programmed with default hint 1412 ** values during boot, so hints should be sane even if we 1413 ** can't reprogram them the way drivers want. 1414 */ 1415 1416 setup_ibase_imask(sba, ioc, ioc_num); 1417 1418 /* 1419 ** Program the IOC's ibase and enable IOVA translation 1420 */ 1421 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE); 1422 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK); 1423 1424 /* Set I/O PDIR Page size to 4K */ 1425 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG); 1426 1427 /* 1428 ** Clear I/O TLB of any possible entries. 1429 ** (Yes. This is a bit paranoid...but so what) 1430 */ 1431 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM); 1432 1433 ioc->ibase = 0; /* used by SBA_IOVA and related macros */ 1434 1435 DBG_INIT("%s() DONE\n", __FUNCTION__); 1436 } 1437 1438 1439 1440 /************************************************************************** 1441 ** 1442 ** SBA initialization code (HW and SW) 1443 ** 1444 ** o identify SBA chip itself 1445 ** o initialize SBA chip modes (HardFail) 1446 ** o initialize SBA chip modes (HardFail) 1447 ** o FIXME: initialize DMA hints for reasonable defaults 1448 ** 1449 **************************************************************************/ 1450 1451 static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset) 1452 { 1453 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE); 1454 } 1455 1456 static void sba_hw_init(struct sba_device *sba_dev) 1457 { 1458 int i; 1459 int num_ioc; 1460 u64 ioc_ctl; 1461 1462 if (!is_pdc_pat()) { 1463 /* Shutdown the USB controller on Astro-based workstations. 1464 ** Once we reprogram the IOMMU, the next DMA performed by 1465 ** USB will HPMC the box. USB is only enabled if a 1466 ** keyboard is present and found. 1467 ** 1468 ** With serial console, j6k v5.0 firmware says: 1469 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7 1470 ** 1471 ** FIXME: Using GFX+USB console at power up but direct 1472 ** linux to serial console is still broken. 1473 ** USB could generate DMA so we must reset USB. 1474 ** The proper sequence would be: 1475 ** o block console output 1476 ** o reset USB device 1477 ** o reprogram serial port 1478 ** o unblock console output 1479 */ 1480 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) { 1481 pdc_io_reset_devices(); 1482 } 1483 1484 } 1485 1486 1487 #if 0 1488 printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa, 1489 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class); 1490 1491 /* 1492 ** Need to deal with DMA from LAN. 1493 ** Maybe use page zero boot device as a handle to talk 1494 ** to PDC about which device to shutdown. 1495 ** 1496 ** Netbooting, j6k v5.0 firmware says: 1497 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002 1498 ** ARGH! invalid class. 1499 */ 1500 if ((PAGE0->mem_boot.cl_class != CL_RANDOM) 1501 && (PAGE0->mem_boot.cl_class != CL_SEQU)) { 1502 pdc_io_reset(); 1503 } 1504 #endif 1505 1506 if (!IS_PLUTO(sba_dev->dev)) { 1507 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL); 1508 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->", 1509 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl); 1510 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE); 1511 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC; 1512 /* j6700 v1.6 firmware sets 0x294f */ 1513 /* A500 firmware sets 0x4d */ 1514 1515 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL); 1516 1517 #ifdef DEBUG_SBA_INIT 1518 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL); 1519 DBG_INIT(" 0x%Lx\n", ioc_ctl); 1520 #endif 1521 } /* if !PLUTO */ 1522 1523 if (IS_ASTRO(sba_dev->dev)) { 1524 int err; 1525 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET); 1526 num_ioc = 1; 1527 1528 sba_dev->chip_resv.name = "Astro Intr Ack"; 1529 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL; 1530 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ; 1531 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1532 BUG_ON(err < 0); 1533 1534 } else if (IS_PLUTO(sba_dev->dev)) { 1535 int err; 1536 1537 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET); 1538 num_ioc = 1; 1539 1540 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA"; 1541 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL; 1542 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1); 1543 err = request_resource(&iomem_resource, &(sba_dev->chip_resv)); 1544 WARN_ON(err < 0); 1545 1546 sba_dev->iommu_resv.name = "IOVA Space"; 1547 sba_dev->iommu_resv.start = 0x40000000UL; 1548 sba_dev->iommu_resv.end = 0x50000000UL - 1; 1549 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv)); 1550 WARN_ON(err < 0); 1551 } else { 1552 /* IKE, REO */ 1553 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0)); 1554 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1)); 1555 num_ioc = 2; 1556 1557 /* TODO - LOOKUP Ike/Stretch chipset mem map */ 1558 } 1559 /* XXX: What about Reo Grande? */ 1560 1561 sba_dev->num_ioc = num_ioc; 1562 for (i = 0; i < num_ioc; i++) { 1563 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa; 1564 unsigned int j; 1565 1566 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) { 1567 1568 /* 1569 * Clear ROPE(N)_CONFIG AO bit. 1570 * Disables "NT Ordering" (~= !"Relaxed Ordering") 1571 * Overrides bit 1 in DMA Hint Sets. 1572 * Improves netperf UDP_STREAM by ~10% for bcm5701. 1573 */ 1574 if (IS_PLUTO(sba_dev->dev)) { 1575 void __iomem *rope_cfg; 1576 unsigned long cfg_val; 1577 1578 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j; 1579 cfg_val = READ_REG(rope_cfg); 1580 cfg_val &= ~IOC_ROPE_AO; 1581 WRITE_REG(cfg_val, rope_cfg); 1582 } 1583 1584 /* 1585 ** Make sure the box crashes on rope errors. 1586 */ 1587 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j); 1588 } 1589 1590 /* flush out the last writes */ 1591 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL); 1592 1593 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n", 1594 i, 1595 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40), 1596 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50) 1597 ); 1598 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n", 1599 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108), 1600 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400) 1601 ); 1602 1603 if (IS_PLUTO(sba_dev->dev)) { 1604 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i); 1605 } else { 1606 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i); 1607 } 1608 } 1609 } 1610 1611 static void 1612 sba_common_init(struct sba_device *sba_dev) 1613 { 1614 int i; 1615 1616 /* add this one to the head of the list (order doesn't matter) 1617 ** This will be useful for debugging - especially if we get coredumps 1618 */ 1619 sba_dev->next = sba_list; 1620 sba_list = sba_dev; 1621 1622 for(i=0; i< sba_dev->num_ioc; i++) { 1623 int res_size; 1624 #ifdef DEBUG_DMB_TRAP 1625 extern void iterate_pages(unsigned long , unsigned long , 1626 void (*)(pte_t * , unsigned long), 1627 unsigned long ); 1628 void set_data_memory_break(pte_t * , unsigned long); 1629 #endif 1630 /* resource map size dictated by pdir_size */ 1631 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */ 1632 1633 /* Second part of PIRANHA BUG */ 1634 if (piranha_bad_128k) { 1635 res_size -= (128*1024)/sizeof(u64); 1636 } 1637 1638 res_size >>= 3; /* convert bit count to byte count */ 1639 DBG_INIT("%s() res_size 0x%x\n", 1640 __FUNCTION__, res_size); 1641 1642 sba_dev->ioc[i].res_size = res_size; 1643 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size)); 1644 1645 #ifdef DEBUG_DMB_TRAP 1646 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1647 set_data_memory_break, 0); 1648 #endif 1649 1650 if (NULL == sba_dev->ioc[i].res_map) 1651 { 1652 panic("%s:%s() could not allocate resource map\n", 1653 __FILE__, __FUNCTION__ ); 1654 } 1655 1656 memset(sba_dev->ioc[i].res_map, 0, res_size); 1657 /* next available IOVP - circular search */ 1658 sba_dev->ioc[i].res_hint = (unsigned long *) 1659 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]); 1660 1661 #ifdef ASSERT_PDIR_SANITY 1662 /* Mark first bit busy - ie no IOVA 0 */ 1663 sba_dev->ioc[i].res_map[0] = 0x80; 1664 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL; 1665 #endif 1666 1667 /* Third (and last) part of PIRANHA BUG */ 1668 if (piranha_bad_128k) { 1669 /* region from +1408K to +1536 is un-usable. */ 1670 1671 int idx_start = (1408*1024/sizeof(u64)) >> 3; 1672 int idx_end = (1536*1024/sizeof(u64)) >> 3; 1673 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]); 1674 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]); 1675 1676 /* mark that part of the io pdir busy */ 1677 while (p_start < p_end) 1678 *p_start++ = -1; 1679 1680 } 1681 1682 #ifdef DEBUG_DMB_TRAP 1683 iterate_pages( sba_dev->ioc[i].res_map, res_size, 1684 set_data_memory_break, 0); 1685 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size, 1686 set_data_memory_break, 0); 1687 #endif 1688 1689 DBG_INIT("%s() %d res_map %x %p\n", 1690 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map); 1691 } 1692 1693 spin_lock_init(&sba_dev->sba_lock); 1694 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC; 1695 1696 #ifdef DEBUG_SBA_INIT 1697 /* 1698 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set 1699 * (bit #61, big endian), we have to flush and sync every time 1700 * IO-PDIR is changed in Ike/Astro. 1701 */ 1702 if (ioc_needs_fdc) { 1703 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n"); 1704 } else { 1705 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); 1706 } 1707 #endif 1708 } 1709 1710 #ifdef CONFIG_PROC_FS 1711 static int sba_proc_info(struct seq_file *m, void *p) 1712 { 1713 struct sba_device *sba_dev = sba_list; 1714 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1715 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */ 1716 #ifdef SBA_COLLECT_STATS 1717 unsigned long avg = 0, min, max; 1718 #endif 1719 int i, len = 0; 1720 1721 len += seq_printf(m, "%s rev %d.%d\n", 1722 sba_dev->name, 1723 (sba_dev->hw_rev & 0x7) + 1, 1724 (sba_dev->hw_rev & 0x18) >> 3 1725 ); 1726 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n", 1727 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */ 1728 total_pages); 1729 1730 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n", 1731 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */ 1732 1733 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n", 1734 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE), 1735 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK), 1736 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE) 1737 ); 1738 1739 for (i=0; i<4; i++) 1740 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i, 1741 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18), 1742 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18), 1743 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18) 1744 ); 1745 1746 #ifdef SBA_COLLECT_STATS 1747 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n", 1748 total_pages - ioc->used_pages, ioc->used_pages, 1749 (int) (ioc->used_pages * 100 / total_pages)); 1750 1751 min = max = ioc->avg_search[0]; 1752 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) { 1753 avg += ioc->avg_search[i]; 1754 if (ioc->avg_search[i] > max) max = ioc->avg_search[i]; 1755 if (ioc->avg_search[i] < min) min = ioc->avg_search[i]; 1756 } 1757 avg /= SBA_SEARCH_SAMPLE; 1758 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n", 1759 min, avg, max); 1760 1761 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n", 1762 ioc->msingle_calls, ioc->msingle_pages, 1763 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls)); 1764 1765 /* KLUGE - unmap_sg calls unmap_single for each mapped page */ 1766 min = ioc->usingle_calls; 1767 max = ioc->usingle_pages - ioc->usg_pages; 1768 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n", 1769 min, max, (int) ((max * 1000)/min)); 1770 1771 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1772 ioc->msg_calls, ioc->msg_pages, 1773 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls)); 1774 1775 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n", 1776 ioc->usg_calls, ioc->usg_pages, 1777 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls)); 1778 #endif 1779 1780 return 0; 1781 } 1782 1783 static int 1784 sba_proc_open(struct inode *i, struct file *f) 1785 { 1786 return single_open(f, &sba_proc_info, NULL); 1787 } 1788 1789 static struct file_operations sba_proc_fops = { 1790 .owner = THIS_MODULE, 1791 .open = sba_proc_open, 1792 .read = seq_read, 1793 .llseek = seq_lseek, 1794 .release = single_release, 1795 }; 1796 1797 static int 1798 sba_proc_bitmap_info(struct seq_file *m, void *p) 1799 { 1800 struct sba_device *sba_dev = sba_list; 1801 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */ 1802 unsigned int *res_ptr = (unsigned int *)ioc->res_map; 1803 int i, len = 0; 1804 1805 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) { 1806 if ((i & 7) == 0) 1807 len += seq_printf(m, "\n "); 1808 len += seq_printf(m, " %08x", *res_ptr); 1809 } 1810 len += seq_printf(m, "\n"); 1811 1812 return 0; 1813 } 1814 1815 static int 1816 sba_proc_bitmap_open(struct inode *i, struct file *f) 1817 { 1818 return single_open(f, &sba_proc_bitmap_info, NULL); 1819 } 1820 1821 static struct file_operations sba_proc_bitmap_fops = { 1822 .owner = THIS_MODULE, 1823 .open = sba_proc_bitmap_open, 1824 .read = seq_read, 1825 .llseek = seq_lseek, 1826 .release = single_release, 1827 }; 1828 #endif /* CONFIG_PROC_FS */ 1829 1830 static struct parisc_device_id sba_tbl[] = { 1831 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb }, 1832 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc }, 1833 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc }, 1834 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc }, 1835 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc }, 1836 { 0, } 1837 }; 1838 1839 int sba_driver_callback(struct parisc_device *); 1840 1841 static struct parisc_driver sba_driver = { 1842 .name = MODULE_NAME, 1843 .id_table = sba_tbl, 1844 .probe = sba_driver_callback, 1845 }; 1846 1847 /* 1848 ** Determine if sba should claim this chip (return 0) or not (return 1). 1849 ** If so, initialize the chip and tell other partners in crime they 1850 ** have work to do. 1851 */ 1852 int 1853 sba_driver_callback(struct parisc_device *dev) 1854 { 1855 struct sba_device *sba_dev; 1856 u32 func_class; 1857 int i; 1858 char *version; 1859 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE); 1860 struct proc_dir_entry *info_entry, *bitmap_entry, *root; 1861 1862 sba_dump_ranges(sba_addr); 1863 1864 /* Read HW Rev First */ 1865 func_class = READ_REG(sba_addr + SBA_FCLASS); 1866 1867 if (IS_ASTRO(dev)) { 1868 unsigned long fclass; 1869 static char astro_rev[]="Astro ?.?"; 1870 1871 /* Astro is broken...Read HW Rev First */ 1872 fclass = READ_REG(sba_addr); 1873 1874 astro_rev[6] = '1' + (char) (fclass & 0x7); 1875 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3); 1876 version = astro_rev; 1877 1878 } else if (IS_IKE(dev)) { 1879 static char ike_rev[] = "Ike rev ?"; 1880 ike_rev[8] = '0' + (char) (func_class & 0xff); 1881 version = ike_rev; 1882 } else if (IS_PLUTO(dev)) { 1883 static char pluto_rev[]="Pluto ?.?"; 1884 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4); 1885 pluto_rev[8] = '0' + (char) (func_class & 0x0f); 1886 version = pluto_rev; 1887 } else { 1888 static char reo_rev[] = "REO rev ?"; 1889 reo_rev[8] = '0' + (char) (func_class & 0xff); 1890 version = reo_rev; 1891 } 1892 1893 if (!global_ioc_cnt) { 1894 global_ioc_cnt = count_parisc_driver(&sba_driver); 1895 1896 /* Astro and Pluto have one IOC per SBA */ 1897 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev))) 1898 global_ioc_cnt *= 2; 1899 } 1900 1901 printk(KERN_INFO "%s found %s at 0x%lx\n", 1902 MODULE_NAME, version, dev->hpa.start); 1903 1904 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL); 1905 if (!sba_dev) { 1906 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n"); 1907 return -ENOMEM; 1908 } 1909 1910 parisc_set_drvdata(dev, sba_dev); 1911 1912 for(i=0; i<MAX_IOC; i++) 1913 spin_lock_init(&(sba_dev->ioc[i].res_lock)); 1914 1915 sba_dev->dev = dev; 1916 sba_dev->hw_rev = func_class; 1917 sba_dev->name = dev->name; 1918 sba_dev->sba_hpa = sba_addr; 1919 1920 sba_get_pat_resources(sba_dev); 1921 sba_hw_init(sba_dev); 1922 sba_common_init(sba_dev); 1923 1924 hppa_dma_ops = &sba_ops; 1925 1926 #ifdef CONFIG_PROC_FS 1927 switch (dev->id.hversion) { 1928 case PLUTO_MCKINLEY_PORT: 1929 root = proc_mckinley_root; 1930 break; 1931 case ASTRO_RUNWAY_PORT: 1932 case IKE_MERCED_PORT: 1933 default: 1934 root = proc_runway_root; 1935 break; 1936 } 1937 1938 info_entry = create_proc_entry("sba_iommu", 0, root); 1939 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root); 1940 1941 if (info_entry) 1942 info_entry->proc_fops = &sba_proc_fops; 1943 1944 if (bitmap_entry) 1945 bitmap_entry->proc_fops = &sba_proc_bitmap_fops; 1946 #endif 1947 1948 parisc_vmerge_boundary = IOVP_SIZE; 1949 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG; 1950 parisc_has_iommu(); 1951 return 0; 1952 } 1953 1954 /* 1955 ** One time initialization to let the world know the SBA was found. 1956 ** This is the only routine which is NOT static. 1957 ** Must be called exactly once before pci_init(). 1958 */ 1959 void __init sba_init(void) 1960 { 1961 register_parisc_driver(&sba_driver); 1962 } 1963 1964 1965 /** 1966 * sba_get_iommu - Assign the iommu pointer for the pci bus controller. 1967 * @dev: The parisc device. 1968 * 1969 * Returns the appropriate IOMMU data for the given parisc PCI controller. 1970 * This is cached and used later for PCI DMA Mapping. 1971 */ 1972 void * sba_get_iommu(struct parisc_device *pci_hba) 1973 { 1974 struct parisc_device *sba_dev = parisc_parent(pci_hba); 1975 struct sba_device *sba = sba_dev->dev.driver_data; 1976 char t = sba_dev->id.hw_type; 1977 int iocnum = (pci_hba->hw_path >> 3); /* rope # */ 1978 1979 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT)); 1980 1981 return &(sba->ioc[iocnum]); 1982 } 1983 1984 1985 /** 1986 * sba_directed_lmmio - return first directed LMMIO range routed to rope 1987 * @pa_dev: The parisc device. 1988 * @r: resource PCI host controller wants start/end fields assigned. 1989 * 1990 * For the given parisc PCI controller, determine if any direct ranges 1991 * are routed down the corresponding rope. 1992 */ 1993 void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r) 1994 { 1995 struct parisc_device *sba_dev = parisc_parent(pci_hba); 1996 struct sba_device *sba = sba_dev->dev.driver_data; 1997 char t = sba_dev->id.hw_type; 1998 int i; 1999 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2000 2001 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2002 2003 r->start = r->end = 0; 2004 2005 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */ 2006 for (i=0; i<4; i++) { 2007 int base, size; 2008 void __iomem *reg = sba->sba_hpa + i*0x18; 2009 2010 base = READ_REG32(reg + LMMIO_DIRECT0_BASE); 2011 if ((base & 1) == 0) 2012 continue; /* not enabled */ 2013 2014 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE); 2015 2016 if ((size & (ROPES_PER_IOC-1)) != rope) 2017 continue; /* directed down different rope */ 2018 2019 r->start = (base & ~1UL) | PCI_F_EXTEND; 2020 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK); 2021 r->end = r->start + size; 2022 } 2023 } 2024 2025 2026 /** 2027 * sba_distributed_lmmio - return portion of distributed LMMIO range 2028 * @pa_dev: The parisc device. 2029 * @r: resource PCI host controller wants start/end fields assigned. 2030 * 2031 * For the given parisc PCI controller, return portion of distributed LMMIO 2032 * range. The distributed LMMIO is always present and it's just a question 2033 * of the base address and size of the range. 2034 */ 2035 void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r ) 2036 { 2037 struct parisc_device *sba_dev = parisc_parent(pci_hba); 2038 struct sba_device *sba = sba_dev->dev.driver_data; 2039 char t = sba_dev->id.hw_type; 2040 int base, size; 2041 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */ 2042 2043 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT)); 2044 2045 r->start = r->end = 0; 2046 2047 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE); 2048 if ((base & 1) == 0) { 2049 BUG(); /* Gah! Distr Range wasn't enabled! */ 2050 return; 2051 } 2052 2053 r->start = (base & ~1UL) | PCI_F_EXTEND; 2054 2055 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC; 2056 r->start += rope * (size + 1); /* adjust base for this rope */ 2057 r->end = r->start + size; 2058 } 2059