11da177e4SLinus Torvalds /* 21da177e4SLinus Torvalds ** 31da177e4SLinus Torvalds ** PCI Lower Bus Adapter (LBA) manager 41da177e4SLinus Torvalds ** 51da177e4SLinus Torvalds ** (c) Copyright 1999,2000 Grant Grundler 61da177e4SLinus Torvalds ** (c) Copyright 1999,2000 Hewlett-Packard Company 71da177e4SLinus Torvalds ** 81da177e4SLinus Torvalds ** This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds ** it under the terms of the GNU General Public License as published by 101da177e4SLinus Torvalds ** the Free Software Foundation; either version 2 of the License, or 111da177e4SLinus Torvalds ** (at your option) any later version. 121da177e4SLinus Torvalds ** 131da177e4SLinus Torvalds ** 141da177e4SLinus Torvalds ** This module primarily provides access to PCI bus (config/IOport 151da177e4SLinus Torvalds ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class 161da177e4SLinus Torvalds ** with 4 digit model numbers - eg C3000 (and A400...sigh). 171da177e4SLinus Torvalds ** 181da177e4SLinus Torvalds ** LBA driver isn't as simple as the Dino driver because: 191da177e4SLinus Torvalds ** (a) this chip has substantial bug fixes between revisions 201da177e4SLinus Torvalds ** (Only one Dino bug has a software workaround :^( ) 211da177e4SLinus Torvalds ** (b) has more options which we don't (yet) support (DMA hints, OLARD) 221da177e4SLinus Torvalds ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver) 231da177e4SLinus Torvalds ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC). 241da177e4SLinus Torvalds ** (dino only deals with "Legacy" PDC) 251da177e4SLinus Torvalds ** 261da177e4SLinus Torvalds ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver. 271da177e4SLinus Torvalds ** (I/O SAPIC is integratd in the LBA chip). 281da177e4SLinus Torvalds ** 291da177e4SLinus Torvalds ** FIXME: Add support to SBA and LBA drivers for DMA hint sets 301da177e4SLinus Torvalds ** FIXME: Add support for PCI card hot-plug (OLARD). 311da177e4SLinus Torvalds */ 321da177e4SLinus Torvalds 331da177e4SLinus Torvalds #include <linux/delay.h> 341da177e4SLinus Torvalds #include <linux/types.h> 351da177e4SLinus Torvalds #include <linux/kernel.h> 361da177e4SLinus Torvalds #include <linux/spinlock.h> 371da177e4SLinus Torvalds #include <linux/init.h> /* for __init and __devinit */ 381da177e4SLinus Torvalds #include <linux/pci.h> 391da177e4SLinus Torvalds #include <linux/ioport.h> 401da177e4SLinus Torvalds #include <linux/slab.h> 411da177e4SLinus Torvalds #include <linux/smp_lock.h> 421da177e4SLinus Torvalds 431da177e4SLinus Torvalds #include <asm/byteorder.h> 441da177e4SLinus Torvalds #include <asm/pdc.h> 451da177e4SLinus Torvalds #include <asm/pdcpat.h> 461da177e4SLinus Torvalds #include <asm/page.h> 471da177e4SLinus Torvalds #include <asm/system.h> 481da177e4SLinus Torvalds 491790cf91SKyle McMartin #include <asm/ropes.h> 501da177e4SLinus Torvalds #include <asm/hardware.h> /* for register_parisc_driver() stuff */ 511da177e4SLinus Torvalds #include <asm/parisc-device.h> 521da177e4SLinus Torvalds #include <asm/io.h> /* read/write stuff */ 531da177e4SLinus Torvalds 541da177e4SLinus Torvalds #undef DEBUG_LBA /* general stuff */ 551da177e4SLinus Torvalds #undef DEBUG_LBA_PORT /* debug I/O Port access */ 561da177e4SLinus Torvalds #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */ 571da177e4SLinus Torvalds #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */ 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */ 601da177e4SLinus Torvalds 611da177e4SLinus Torvalds 621da177e4SLinus Torvalds #ifdef DEBUG_LBA 631da177e4SLinus Torvalds #define DBG(x...) printk(x) 641da177e4SLinus Torvalds #else 651da177e4SLinus Torvalds #define DBG(x...) 661da177e4SLinus Torvalds #endif 671da177e4SLinus Torvalds 681da177e4SLinus Torvalds #ifdef DEBUG_LBA_PORT 691da177e4SLinus Torvalds #define DBG_PORT(x...) printk(x) 701da177e4SLinus Torvalds #else 711da177e4SLinus Torvalds #define DBG_PORT(x...) 721da177e4SLinus Torvalds #endif 731da177e4SLinus Torvalds 741da177e4SLinus Torvalds #ifdef DEBUG_LBA_CFG 751da177e4SLinus Torvalds #define DBG_CFG(x...) printk(x) 761da177e4SLinus Torvalds #else 771da177e4SLinus Torvalds #define DBG_CFG(x...) 781da177e4SLinus Torvalds #endif 791da177e4SLinus Torvalds 801da177e4SLinus Torvalds #ifdef DEBUG_LBA_PAT 811da177e4SLinus Torvalds #define DBG_PAT(x...) printk(x) 821da177e4SLinus Torvalds #else 831da177e4SLinus Torvalds #define DBG_PAT(x...) 841da177e4SLinus Torvalds #endif 851da177e4SLinus Torvalds 861da177e4SLinus Torvalds 871da177e4SLinus Torvalds /* 881da177e4SLinus Torvalds ** Config accessor functions only pass in the 8-bit bus number and not 891da177e4SLinus Torvalds ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus 901da177e4SLinus Torvalds ** number based on what firmware wrote into the scratch register. 911da177e4SLinus Torvalds ** 921da177e4SLinus Torvalds ** The "secondary" bus number is set to this before calling 931da177e4SLinus Torvalds ** pci_register_ops(). If any PPB's are present, the scan will 941da177e4SLinus Torvalds ** discover them and update the "secondary" and "subordinate" 951da177e4SLinus Torvalds ** fields in the pci_bus structure. 961da177e4SLinus Torvalds ** 971da177e4SLinus Torvalds ** Changes in the configuration *may* result in a different 981da177e4SLinus Torvalds ** bus number for each LBA depending on what firmware does. 991da177e4SLinus Torvalds */ 1001da177e4SLinus Torvalds 1011da177e4SLinus Torvalds #define MODULE_NAME "LBA" 1021da177e4SLinus Torvalds 1031da177e4SLinus Torvalds /* non-postable I/O port space, densely packed */ 1041da177e4SLinus Torvalds #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 1058039de10SHelge Deller static void __iomem *astro_iop_base __read_mostly; 1061da177e4SLinus Torvalds 1071da177e4SLinus Torvalds static u32 lba_t32; 1081da177e4SLinus Torvalds 1091da177e4SLinus Torvalds /* lba flags */ 1101da177e4SLinus Torvalds #define LBA_FLAG_SKIP_PROBE 0x10 1111da177e4SLinus Torvalds 1121da177e4SLinus Torvalds #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE) 1131da177e4SLinus Torvalds 1141da177e4SLinus Torvalds 1151da177e4SLinus Torvalds /* Looks nice and keeps the compiler happy */ 1161da177e4SLinus Torvalds #define LBA_DEV(d) ((struct lba_device *) (d)) 1171da177e4SLinus Torvalds 1181da177e4SLinus Torvalds 1191da177e4SLinus Torvalds /* 1201da177e4SLinus Torvalds ** Only allow 8 subsidiary busses per LBA 1211da177e4SLinus Torvalds ** Problem is the PCI bus numbering is globally shared. 1221da177e4SLinus Torvalds */ 1231da177e4SLinus Torvalds #define LBA_MAX_NUM_BUSES 8 1241da177e4SLinus Torvalds 1251da177e4SLinus Torvalds /************************************ 1261da177e4SLinus Torvalds * LBA register read and write support 1271da177e4SLinus Torvalds * 1281da177e4SLinus Torvalds * BE WARNED: register writes are posted. 1291da177e4SLinus Torvalds * (ie follow writes which must reach HW with a read) 1301da177e4SLinus Torvalds */ 1311da177e4SLinus Torvalds #define READ_U8(addr) __raw_readb(addr) 1321da177e4SLinus Torvalds #define READ_U16(addr) __raw_readw(addr) 1331da177e4SLinus Torvalds #define READ_U32(addr) __raw_readl(addr) 1341da177e4SLinus Torvalds #define WRITE_U8(value, addr) __raw_writeb(value, addr) 1351da177e4SLinus Torvalds #define WRITE_U16(value, addr) __raw_writew(value, addr) 1361da177e4SLinus Torvalds #define WRITE_U32(value, addr) __raw_writel(value, addr) 1371da177e4SLinus Torvalds 1381da177e4SLinus Torvalds #define READ_REG8(addr) readb(addr) 1391da177e4SLinus Torvalds #define READ_REG16(addr) readw(addr) 1401da177e4SLinus Torvalds #define READ_REG32(addr) readl(addr) 1411da177e4SLinus Torvalds #define READ_REG64(addr) readq(addr) 1421da177e4SLinus Torvalds #define WRITE_REG8(value, addr) writeb(value, addr) 1431da177e4SLinus Torvalds #define WRITE_REG16(value, addr) writew(value, addr) 1441da177e4SLinus Torvalds #define WRITE_REG32(value, addr) writel(value, addr) 1451da177e4SLinus Torvalds 1461da177e4SLinus Torvalds 1471da177e4SLinus Torvalds #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8)) 1481da177e4SLinus Torvalds #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16)) 1491da177e4SLinus Torvalds #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f) 1501da177e4SLinus Torvalds #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7) 1511da177e4SLinus Torvalds 1521da177e4SLinus Torvalds 1531da177e4SLinus Torvalds /* 1541da177e4SLinus Torvalds ** Extract LBA (Rope) number from HPA 1551da177e4SLinus Torvalds ** REVISIT: 16 ropes for Stretch/Ike? 1561da177e4SLinus Torvalds */ 1571da177e4SLinus Torvalds #define ROPES_PER_IOC 8 1581da177e4SLinus Torvalds #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1)) 1591da177e4SLinus Torvalds 1601da177e4SLinus Torvalds 1611da177e4SLinus Torvalds static void 1621da177e4SLinus Torvalds lba_dump_res(struct resource *r, int d) 1631da177e4SLinus Torvalds { 1641da177e4SLinus Torvalds int i; 1651da177e4SLinus Torvalds 1661da177e4SLinus Torvalds if (NULL == r) 1671da177e4SLinus Torvalds return; 1681da177e4SLinus Torvalds 1691da177e4SLinus Torvalds printk(KERN_DEBUG "(%p)", r->parent); 1701da177e4SLinus Torvalds for (i = d; i ; --i) printk(" "); 171*645d11d4SMatthew Wilcox printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r, 172*645d11d4SMatthew Wilcox (long)r->start, (long)r->end, r->flags); 1731da177e4SLinus Torvalds lba_dump_res(r->child, d+2); 1741da177e4SLinus Torvalds lba_dump_res(r->sibling, d); 1751da177e4SLinus Torvalds } 1761da177e4SLinus Torvalds 1771da177e4SLinus Torvalds 1781da177e4SLinus Torvalds /* 1791da177e4SLinus Torvalds ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex 1801da177e4SLinus Torvalds ** workaround for cfg cycles: 1811da177e4SLinus Torvalds ** -- preserve LBA state 1821da177e4SLinus Torvalds ** -- prevent any DMA from occurring 1831da177e4SLinus Torvalds ** -- turn on smart mode 1841da177e4SLinus Torvalds ** -- probe with config writes before doing config reads 1851da177e4SLinus Torvalds ** -- check ERROR_STATUS 1861da177e4SLinus Torvalds ** -- clear ERROR_STATUS 1871da177e4SLinus Torvalds ** -- restore LBA state 1881da177e4SLinus Torvalds ** 1891da177e4SLinus Torvalds ** The workaround is only used for device discovery. 1901da177e4SLinus Torvalds */ 1911da177e4SLinus Torvalds 1921da177e4SLinus Torvalds static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d) 1931da177e4SLinus Torvalds { 1941da177e4SLinus Torvalds u8 first_bus = d->hba.hba_bus->secondary; 1951da177e4SLinus Torvalds u8 last_sub_bus = d->hba.hba_bus->subordinate; 1961da177e4SLinus Torvalds 1971da177e4SLinus Torvalds if ((bus < first_bus) || 1981da177e4SLinus Torvalds (bus > last_sub_bus) || 1991da177e4SLinus Torvalds ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) { 2001da177e4SLinus Torvalds return 0; 2011da177e4SLinus Torvalds } 2021da177e4SLinus Torvalds 2031da177e4SLinus Torvalds return 1; 2041da177e4SLinus Torvalds } 2051da177e4SLinus Torvalds 2061da177e4SLinus Torvalds 2071da177e4SLinus Torvalds 2081da177e4SLinus Torvalds #define LBA_CFG_SETUP(d, tok) { \ 2091da177e4SLinus Torvalds /* Save contents of error config register. */ \ 2101da177e4SLinus Torvalds error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \ 2111da177e4SLinus Torvalds \ 2121da177e4SLinus Torvalds /* Save contents of status control register. */ \ 2131da177e4SLinus Torvalds status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \ 2141da177e4SLinus Torvalds \ 2151da177e4SLinus Torvalds /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \ 2161da177e4SLinus Torvalds ** arbitration for full bus walks. \ 2171da177e4SLinus Torvalds */ \ 2181da177e4SLinus Torvalds /* Save contents of arb mask register. */ \ 2191da177e4SLinus Torvalds arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \ 2201da177e4SLinus Torvalds \ 2211da177e4SLinus Torvalds /* \ 2221da177e4SLinus Torvalds * Turn off all device arbitration bits (i.e. everything \ 2231da177e4SLinus Torvalds * except arbitration enable bit). \ 2241da177e4SLinus Torvalds */ \ 2251da177e4SLinus Torvalds WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \ 2261da177e4SLinus Torvalds \ 2271da177e4SLinus Torvalds /* \ 2281da177e4SLinus Torvalds * Set the smart mode bit so that master aborts don't cause \ 2291da177e4SLinus Torvalds * LBA to go into PCI fatal mode (required). \ 2301da177e4SLinus Torvalds */ \ 2311da177e4SLinus Torvalds WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \ 2321da177e4SLinus Torvalds } 2331da177e4SLinus Torvalds 2341da177e4SLinus Torvalds 2351da177e4SLinus Torvalds #define LBA_CFG_PROBE(d, tok) { \ 2361da177e4SLinus Torvalds /* \ 2371da177e4SLinus Torvalds * Setup Vendor ID write and read back the address register \ 2381da177e4SLinus Torvalds * to make sure that LBA is the bus master. \ 2391da177e4SLinus Torvalds */ \ 2401da177e4SLinus Torvalds WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\ 2411da177e4SLinus Torvalds /* \ 2421da177e4SLinus Torvalds * Read address register to ensure that LBA is the bus master, \ 2431da177e4SLinus Torvalds * which implies that DMA traffic has stopped when DMA arb is off. \ 2441da177e4SLinus Torvalds */ \ 2451da177e4SLinus Torvalds lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 2461da177e4SLinus Torvalds /* \ 2471da177e4SLinus Torvalds * Generate a cfg write cycle (will have no affect on \ 2481da177e4SLinus Torvalds * Vendor ID register since read-only). \ 2491da177e4SLinus Torvalds */ \ 2501da177e4SLinus Torvalds WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \ 2511da177e4SLinus Torvalds /* \ 2521da177e4SLinus Torvalds * Make sure write has completed before proceeding further, \ 2531da177e4SLinus Torvalds * i.e. before setting clear enable. \ 2541da177e4SLinus Torvalds */ \ 2551da177e4SLinus Torvalds lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 2561da177e4SLinus Torvalds } 2571da177e4SLinus Torvalds 2581da177e4SLinus Torvalds 2591da177e4SLinus Torvalds /* 2601da177e4SLinus Torvalds * HPREVISIT: 2611da177e4SLinus Torvalds * -- Can't tell if config cycle got the error. 2621da177e4SLinus Torvalds * 2631da177e4SLinus Torvalds * OV bit is broken until rev 4.0, so can't use OV bit and 2641da177e4SLinus Torvalds * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle. 2651da177e4SLinus Torvalds * 2661da177e4SLinus Torvalds * As of rev 4.0, no longer need the error check. 2671da177e4SLinus Torvalds * 2681da177e4SLinus Torvalds * -- Even if we could tell, we still want to return -1 2691da177e4SLinus Torvalds * for **ANY** error (not just master abort). 2701da177e4SLinus Torvalds * 2711da177e4SLinus Torvalds * -- Only clear non-fatal errors (we don't want to bring 2721da177e4SLinus Torvalds * LBA out of pci-fatal mode). 2731da177e4SLinus Torvalds * 2741da177e4SLinus Torvalds * Actually, there is still a race in which 2751da177e4SLinus Torvalds * we could be clearing a fatal error. We will 2761da177e4SLinus Torvalds * live with this during our initial bus walk 2771da177e4SLinus Torvalds * until rev 4.0 (no driver activity during 2781da177e4SLinus Torvalds * initial bus walk). The initial bus walk 2791da177e4SLinus Torvalds * has race conditions concerning the use of 2801da177e4SLinus Torvalds * smart mode as well. 2811da177e4SLinus Torvalds */ 2821da177e4SLinus Torvalds 2831da177e4SLinus Torvalds #define LBA_MASTER_ABORT_ERROR 0xc 2841da177e4SLinus Torvalds #define LBA_FATAL_ERROR 0x10 2851da177e4SLinus Torvalds 2861da177e4SLinus Torvalds #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \ 2871da177e4SLinus Torvalds u32 error_status = 0; \ 2881da177e4SLinus Torvalds /* \ 2891da177e4SLinus Torvalds * Set clear enable (CE) bit. Unset by HW when new \ 2901da177e4SLinus Torvalds * errors are logged -- LBA HW ERS section 14.3.3). \ 2911da177e4SLinus Torvalds */ \ 2921da177e4SLinus Torvalds WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \ 2931da177e4SLinus Torvalds error_status = READ_REG32(base + LBA_ERROR_STATUS); \ 2941da177e4SLinus Torvalds if ((error_status & 0x1f) != 0) { \ 2951da177e4SLinus Torvalds /* \ 2961da177e4SLinus Torvalds * Fail the config read request. \ 2971da177e4SLinus Torvalds */ \ 2981da177e4SLinus Torvalds error = 1; \ 2991da177e4SLinus Torvalds if ((error_status & LBA_FATAL_ERROR) == 0) { \ 3001da177e4SLinus Torvalds /* \ 3011da177e4SLinus Torvalds * Clear error status (if fatal bit not set) by setting \ 3021da177e4SLinus Torvalds * clear error log bit (CL). \ 3031da177e4SLinus Torvalds */ \ 3041da177e4SLinus Torvalds WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \ 3051da177e4SLinus Torvalds } \ 3061da177e4SLinus Torvalds } \ 3071da177e4SLinus Torvalds } 3081da177e4SLinus Torvalds 3091da177e4SLinus Torvalds #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \ 3101da177e4SLinus Torvalds WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); 3111da177e4SLinus Torvalds 3121da177e4SLinus Torvalds #define LBA_CFG_ADDR_SETUP(d, addr) { \ 3131da177e4SLinus Torvalds WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 3141da177e4SLinus Torvalds /* \ 3151da177e4SLinus Torvalds * Read address register to ensure that LBA is the bus master, \ 3161da177e4SLinus Torvalds * which implies that DMA traffic has stopped when DMA arb is off. \ 3171da177e4SLinus Torvalds */ \ 3181da177e4SLinus Torvalds lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \ 3191da177e4SLinus Torvalds } 3201da177e4SLinus Torvalds 3211da177e4SLinus Torvalds 3221da177e4SLinus Torvalds #define LBA_CFG_RESTORE(d, base) { \ 3231da177e4SLinus Torvalds /* \ 3241da177e4SLinus Torvalds * Restore status control register (turn off clear enable). \ 3251da177e4SLinus Torvalds */ \ 3261da177e4SLinus Torvalds WRITE_REG32(status_control, base + LBA_STAT_CTL); \ 3271da177e4SLinus Torvalds /* \ 3281da177e4SLinus Torvalds * Restore error config register (turn off smart mode). \ 3291da177e4SLinus Torvalds */ \ 3301da177e4SLinus Torvalds WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \ 3311da177e4SLinus Torvalds /* \ 3321da177e4SLinus Torvalds * Restore arb mask register (reenables DMA arbitration). \ 3331da177e4SLinus Torvalds */ \ 3341da177e4SLinus Torvalds WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \ 3351da177e4SLinus Torvalds } 3361da177e4SLinus Torvalds 3371da177e4SLinus Torvalds 3381da177e4SLinus Torvalds 3391da177e4SLinus Torvalds static unsigned int 3401da177e4SLinus Torvalds lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size) 3411da177e4SLinus Torvalds { 3421da177e4SLinus Torvalds u32 data = ~0U; 3431da177e4SLinus Torvalds int error = 0; 3441da177e4SLinus Torvalds u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */ 3451da177e4SLinus Torvalds u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */ 3461da177e4SLinus Torvalds u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */ 3471da177e4SLinus Torvalds 3481da177e4SLinus Torvalds LBA_CFG_SETUP(d, tok); 3491da177e4SLinus Torvalds LBA_CFG_PROBE(d, tok); 3501da177e4SLinus Torvalds LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 3511da177e4SLinus Torvalds if (!error) { 3521da177e4SLinus Torvalds void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 3531da177e4SLinus Torvalds 3541da177e4SLinus Torvalds LBA_CFG_ADDR_SETUP(d, tok | reg); 3551da177e4SLinus Torvalds switch (size) { 3561da177e4SLinus Torvalds case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break; 3571da177e4SLinus Torvalds case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break; 3581da177e4SLinus Torvalds case 4: data = READ_REG32(data_reg); break; 3591da177e4SLinus Torvalds } 3601da177e4SLinus Torvalds } 3611da177e4SLinus Torvalds LBA_CFG_RESTORE(d, d->hba.base_addr); 3621da177e4SLinus Torvalds return(data); 3631da177e4SLinus Torvalds } 3641da177e4SLinus Torvalds 3651da177e4SLinus Torvalds 3661da177e4SLinus Torvalds static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 3671da177e4SLinus Torvalds { 3681da177e4SLinus Torvalds struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 3691da177e4SLinus Torvalds u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 3701da177e4SLinus Torvalds u32 tok = LBA_CFG_TOK(local_bus, devfn); 3711da177e4SLinus Torvalds void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 3721da177e4SLinus Torvalds 3731da177e4SLinus Torvalds if ((pos > 255) || (devfn > 255)) 3741da177e4SLinus Torvalds return -EINVAL; 3751da177e4SLinus Torvalds 3761da177e4SLinus Torvalds /* FIXME: B2K/C3600 workaround is always use old method... */ 3771da177e4SLinus Torvalds /* if (!LBA_SKIP_PROBE(d)) */ { 3781da177e4SLinus Torvalds /* original - Generate config cycle on broken elroy 3791da177e4SLinus Torvalds with risk we will miss PCI bus errors. */ 3801da177e4SLinus Torvalds *data = lba_rd_cfg(d, tok, pos, size); 3811da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __FUNCTION__, tok, pos, *data); 3821da177e4SLinus Torvalds return 0; 3831da177e4SLinus Torvalds } 3841da177e4SLinus Torvalds 3851da177e4SLinus Torvalds if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->secondary, devfn, d)) { 3861da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __FUNCTION__, tok, pos); 3871da177e4SLinus Torvalds /* either don't want to look or know device isn't present. */ 3881da177e4SLinus Torvalds *data = ~0U; 3891da177e4SLinus Torvalds return(0); 3901da177e4SLinus Torvalds } 3911da177e4SLinus Torvalds 3921da177e4SLinus Torvalds /* Basic Algorithm 3931da177e4SLinus Torvalds ** Should only get here on fully working LBA rev. 3941da177e4SLinus Torvalds ** This is how simple the code should have been. 3951da177e4SLinus Torvalds */ 3961da177e4SLinus Torvalds LBA_CFG_ADDR_SETUP(d, tok | pos); 3971da177e4SLinus Torvalds switch(size) { 3981da177e4SLinus Torvalds case 1: *data = READ_REG8 (data_reg + (pos & 3)); break; 3991da177e4SLinus Torvalds case 2: *data = READ_REG16(data_reg + (pos & 2)); break; 4001da177e4SLinus Torvalds case 4: *data = READ_REG32(data_reg); break; 4011da177e4SLinus Torvalds } 4021da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __FUNCTION__, tok, pos, *data); 4031da177e4SLinus Torvalds return 0; 4041da177e4SLinus Torvalds } 4051da177e4SLinus Torvalds 4061da177e4SLinus Torvalds 4071da177e4SLinus Torvalds static void 4081da177e4SLinus Torvalds lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size) 4091da177e4SLinus Torvalds { 4101da177e4SLinus Torvalds int error = 0; 4111da177e4SLinus Torvalds u32 arb_mask = 0; 4121da177e4SLinus Torvalds u32 error_config = 0; 4131da177e4SLinus Torvalds u32 status_control = 0; 4141da177e4SLinus Torvalds void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 4151da177e4SLinus Torvalds 4161da177e4SLinus Torvalds LBA_CFG_SETUP(d, tok); 4171da177e4SLinus Torvalds LBA_CFG_ADDR_SETUP(d, tok | reg); 4181da177e4SLinus Torvalds switch (size) { 4191da177e4SLinus Torvalds case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break; 4201da177e4SLinus Torvalds case 2: WRITE_REG16(data, data_reg + (reg & 2)); break; 4211da177e4SLinus Torvalds case 4: WRITE_REG32(data, data_reg); break; 4221da177e4SLinus Torvalds } 4231da177e4SLinus Torvalds LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error); 4241da177e4SLinus Torvalds LBA_CFG_RESTORE(d, d->hba.base_addr); 4251da177e4SLinus Torvalds } 4261da177e4SLinus Torvalds 4271da177e4SLinus Torvalds 4281da177e4SLinus Torvalds /* 4291da177e4SLinus Torvalds * LBA 4.0 config write code implements non-postable semantics 4301da177e4SLinus Torvalds * by doing a read of CONFIG ADDR after the write. 4311da177e4SLinus Torvalds */ 4321da177e4SLinus Torvalds 4331da177e4SLinus Torvalds static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 4341da177e4SLinus Torvalds { 4351da177e4SLinus Torvalds struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 4361da177e4SLinus Torvalds u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 4371da177e4SLinus Torvalds u32 tok = LBA_CFG_TOK(local_bus,devfn); 4381da177e4SLinus Torvalds 4391da177e4SLinus Torvalds if ((pos > 255) || (devfn > 255)) 4401da177e4SLinus Torvalds return -EINVAL; 4411da177e4SLinus Torvalds 4421da177e4SLinus Torvalds if (!LBA_SKIP_PROBE(d)) { 4431da177e4SLinus Torvalds /* Original Workaround */ 4441da177e4SLinus Torvalds lba_wr_cfg(d, tok, pos, (u32) data, size); 4451da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __FUNCTION__, tok, pos,data); 4461da177e4SLinus Torvalds return 0; 4471da177e4SLinus Torvalds } 4481da177e4SLinus Torvalds 4491da177e4SLinus Torvalds if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->secondary, devfn, d))) { 4501da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __FUNCTION__, tok, pos,data); 4511da177e4SLinus Torvalds return 1; /* New Workaround */ 4521da177e4SLinus Torvalds } 4531da177e4SLinus Torvalds 4541da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __FUNCTION__, tok, pos, data); 4551da177e4SLinus Torvalds 4561da177e4SLinus Torvalds /* Basic Algorithm */ 4571da177e4SLinus Torvalds LBA_CFG_ADDR_SETUP(d, tok | pos); 4581da177e4SLinus Torvalds switch(size) { 4591da177e4SLinus Torvalds case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3)); 4601da177e4SLinus Torvalds break; 4611da177e4SLinus Torvalds case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2)); 4621da177e4SLinus Torvalds break; 4631da177e4SLinus Torvalds case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA); 4641da177e4SLinus Torvalds break; 4651da177e4SLinus Torvalds } 4661da177e4SLinus Torvalds /* flush posted write */ 4671da177e4SLinus Torvalds lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 4681da177e4SLinus Torvalds return 0; 4691da177e4SLinus Torvalds } 4701da177e4SLinus Torvalds 4711da177e4SLinus Torvalds 4721da177e4SLinus Torvalds static struct pci_ops elroy_cfg_ops = { 4731da177e4SLinus Torvalds .read = elroy_cfg_read, 4741da177e4SLinus Torvalds .write = elroy_cfg_write, 4751da177e4SLinus Torvalds }; 4761da177e4SLinus Torvalds 4771da177e4SLinus Torvalds /* 4781da177e4SLinus Torvalds * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy 4791da177e4SLinus Torvalds * TR4.0 as no additional bugs were found in this areea between Elroy and 4801da177e4SLinus Torvalds * Mercury 4811da177e4SLinus Torvalds */ 4821da177e4SLinus Torvalds 4831da177e4SLinus Torvalds static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data) 4841da177e4SLinus Torvalds { 4851da177e4SLinus Torvalds struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 4861da177e4SLinus Torvalds u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 4871da177e4SLinus Torvalds u32 tok = LBA_CFG_TOK(local_bus, devfn); 4881da177e4SLinus Torvalds void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 4891da177e4SLinus Torvalds 4901da177e4SLinus Torvalds if ((pos > 255) || (devfn > 255)) 4911da177e4SLinus Torvalds return -EINVAL; 4921da177e4SLinus Torvalds 4931da177e4SLinus Torvalds LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 4941da177e4SLinus Torvalds switch(size) { 4951da177e4SLinus Torvalds case 1: 4961da177e4SLinus Torvalds *data = READ_REG8(data_reg + (pos & 3)); 4971da177e4SLinus Torvalds break; 4981da177e4SLinus Torvalds case 2: 4991da177e4SLinus Torvalds *data = READ_REG16(data_reg + (pos & 2)); 5001da177e4SLinus Torvalds break; 5011da177e4SLinus Torvalds case 4: 5021da177e4SLinus Torvalds *data = READ_REG32(data_reg); break; 5031da177e4SLinus Torvalds break; 5041da177e4SLinus Torvalds } 5051da177e4SLinus Torvalds 5061da177e4SLinus Torvalds DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data); 5071da177e4SLinus Torvalds return 0; 5081da177e4SLinus Torvalds } 5091da177e4SLinus Torvalds 5101da177e4SLinus Torvalds /* 5111da177e4SLinus Torvalds * LBA 4.0 config write code implements non-postable semantics 5121da177e4SLinus Torvalds * by doing a read of CONFIG ADDR after the write. 5131da177e4SLinus Torvalds */ 5141da177e4SLinus Torvalds 5151da177e4SLinus Torvalds static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data) 5161da177e4SLinus Torvalds { 5171da177e4SLinus Torvalds struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge)); 5181da177e4SLinus Torvalds void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA; 5191da177e4SLinus Torvalds u32 local_bus = (bus->parent == NULL) ? 0 : bus->secondary; 5201da177e4SLinus Torvalds u32 tok = LBA_CFG_TOK(local_bus,devfn); 5211da177e4SLinus Torvalds 5221da177e4SLinus Torvalds if ((pos > 255) || (devfn > 255)) 5231da177e4SLinus Torvalds return -EINVAL; 5241da177e4SLinus Torvalds 5251da177e4SLinus Torvalds DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __FUNCTION__, tok, pos, data); 5261da177e4SLinus Torvalds 5271da177e4SLinus Torvalds LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); 5281da177e4SLinus Torvalds switch(size) { 5291da177e4SLinus Torvalds case 1: 5301da177e4SLinus Torvalds WRITE_REG8 (data, data_reg + (pos & 3)); 5311da177e4SLinus Torvalds break; 5321da177e4SLinus Torvalds case 2: 5331da177e4SLinus Torvalds WRITE_REG16(data, data_reg + (pos & 2)); 5341da177e4SLinus Torvalds break; 5351da177e4SLinus Torvalds case 4: 5361da177e4SLinus Torvalds WRITE_REG32(data, data_reg); 5371da177e4SLinus Torvalds break; 5381da177e4SLinus Torvalds } 5391da177e4SLinus Torvalds 5401da177e4SLinus Torvalds /* flush posted write */ 5411da177e4SLinus Torvalds lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR); 5421da177e4SLinus Torvalds return 0; 5431da177e4SLinus Torvalds } 5441da177e4SLinus Torvalds 5451da177e4SLinus Torvalds static struct pci_ops mercury_cfg_ops = { 5461da177e4SLinus Torvalds .read = mercury_cfg_read, 5471da177e4SLinus Torvalds .write = mercury_cfg_write, 5481da177e4SLinus Torvalds }; 5491da177e4SLinus Torvalds 5501da177e4SLinus Torvalds 5511da177e4SLinus Torvalds static void 5521da177e4SLinus Torvalds lba_bios_init(void) 5531da177e4SLinus Torvalds { 5541da177e4SLinus Torvalds DBG(MODULE_NAME ": lba_bios_init\n"); 5551da177e4SLinus Torvalds } 5561da177e4SLinus Torvalds 5571da177e4SLinus Torvalds 5581da177e4SLinus Torvalds #ifdef CONFIG_64BIT 5591da177e4SLinus Torvalds 5601da177e4SLinus Torvalds /* 5611da177e4SLinus Torvalds ** Determine if a device is already configured. 5621da177e4SLinus Torvalds ** If so, reserve it resources. 5631da177e4SLinus Torvalds ** 5641da177e4SLinus Torvalds ** Read PCI cfg command register and see if I/O or MMIO is enabled. 5651da177e4SLinus Torvalds ** PAT has to enable the devices it's using. 5661da177e4SLinus Torvalds ** 5671da177e4SLinus Torvalds ** Note: resources are fixed up before we try to claim them. 5681da177e4SLinus Torvalds */ 5691da177e4SLinus Torvalds static void 5701da177e4SLinus Torvalds lba_claim_dev_resources(struct pci_dev *dev) 5711da177e4SLinus Torvalds { 5721da177e4SLinus Torvalds u16 cmd; 5731da177e4SLinus Torvalds int i, srch_flags; 5741da177e4SLinus Torvalds 5751da177e4SLinus Torvalds (void) pci_read_config_word(dev, PCI_COMMAND, &cmd); 5761da177e4SLinus Torvalds 5771da177e4SLinus Torvalds srch_flags = (cmd & PCI_COMMAND_IO) ? IORESOURCE_IO : 0; 5781da177e4SLinus Torvalds if (cmd & PCI_COMMAND_MEMORY) 5791da177e4SLinus Torvalds srch_flags |= IORESOURCE_MEM; 5801da177e4SLinus Torvalds 5811da177e4SLinus Torvalds if (!srch_flags) 5821da177e4SLinus Torvalds return; 5831da177e4SLinus Torvalds 5841da177e4SLinus Torvalds for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 5851da177e4SLinus Torvalds if (dev->resource[i].flags & srch_flags) { 5861da177e4SLinus Torvalds pci_claim_resource(dev, i); 5871da177e4SLinus Torvalds DBG(" claimed %s %d [%lx,%lx]/%lx\n", 5881da177e4SLinus Torvalds pci_name(dev), i, 5891da177e4SLinus Torvalds dev->resource[i].start, 5901da177e4SLinus Torvalds dev->resource[i].end, 5911da177e4SLinus Torvalds dev->resource[i].flags 5921da177e4SLinus Torvalds ); 5931da177e4SLinus Torvalds } 5941da177e4SLinus Torvalds } 5951da177e4SLinus Torvalds } 5961da177e4SLinus Torvalds 5971da177e4SLinus Torvalds 5981da177e4SLinus Torvalds /* 5996ca45a24SGrant Grundler * truncate_pat_collision: Deal with overlaps or outright collisions 6006ca45a24SGrant Grundler * between PAT PDC reported ranges. 6016ca45a24SGrant Grundler * 6026ca45a24SGrant Grundler * Broken PA8800 firmware will report lmmio range that 6036ca45a24SGrant Grundler * overlaps with CPU HPA. Just truncate the lmmio range. 6046ca45a24SGrant Grundler * 6056ca45a24SGrant Grundler * BEWARE: conflicts with this lmmio range may be an 6066ca45a24SGrant Grundler * elmmio range which is pointing down another rope. 6076ca45a24SGrant Grundler * 6086ca45a24SGrant Grundler * FIXME: only deals with one collision per range...theoretically we 6096ca45a24SGrant Grundler * could have several. Supporting more than one collision will get messy. 6106ca45a24SGrant Grundler */ 6116ca45a24SGrant Grundler static unsigned long 6126ca45a24SGrant Grundler truncate_pat_collision(struct resource *root, struct resource *new) 6136ca45a24SGrant Grundler { 6146ca45a24SGrant Grundler unsigned long start = new->start; 6156ca45a24SGrant Grundler unsigned long end = new->end; 6166ca45a24SGrant Grundler struct resource *tmp = root->child; 6176ca45a24SGrant Grundler 6186ca45a24SGrant Grundler if (end <= start || start < root->start || !tmp) 6196ca45a24SGrant Grundler return 0; 6206ca45a24SGrant Grundler 6216ca45a24SGrant Grundler /* find first overlap */ 6226ca45a24SGrant Grundler while (tmp && tmp->end < start) 6236ca45a24SGrant Grundler tmp = tmp->sibling; 6246ca45a24SGrant Grundler 6256ca45a24SGrant Grundler /* no entries overlap */ 6266ca45a24SGrant Grundler if (!tmp) return 0; 6276ca45a24SGrant Grundler 6286ca45a24SGrant Grundler /* found one that starts behind the new one 6296ca45a24SGrant Grundler ** Don't need to do anything. 6306ca45a24SGrant Grundler */ 6316ca45a24SGrant Grundler if (tmp->start >= end) return 0; 6326ca45a24SGrant Grundler 6336ca45a24SGrant Grundler if (tmp->start <= start) { 6346ca45a24SGrant Grundler /* "front" of new one overlaps */ 6356ca45a24SGrant Grundler new->start = tmp->end + 1; 6366ca45a24SGrant Grundler 6376ca45a24SGrant Grundler if (tmp->end >= end) { 6386ca45a24SGrant Grundler /* AACCKK! totally overlaps! drop this range. */ 6396ca45a24SGrant Grundler return 1; 6406ca45a24SGrant Grundler } 6416ca45a24SGrant Grundler } 6426ca45a24SGrant Grundler 6436ca45a24SGrant Grundler if (tmp->end < end ) { 6446ca45a24SGrant Grundler /* "end" of new one overlaps */ 6456ca45a24SGrant Grundler new->end = tmp->start - 1; 6466ca45a24SGrant Grundler } 6476ca45a24SGrant Grundler 6486ca45a24SGrant Grundler printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] " 6496ca45a24SGrant Grundler "to [%lx,%lx]\n", 6506ca45a24SGrant Grundler start, end, 651*645d11d4SMatthew Wilcox (long)new->start, (long)new->end ); 6526ca45a24SGrant Grundler 6536ca45a24SGrant Grundler return 0; /* truncation successful */ 6546ca45a24SGrant Grundler } 6556ca45a24SGrant Grundler 6566ca45a24SGrant Grundler #else 6576ca45a24SGrant Grundler #define lba_claim_dev_resources(dev) do { } while (0) 6586ca45a24SGrant Grundler #define truncate_pat_collision(r,n) (0) 6596ca45a24SGrant Grundler #endif 6606ca45a24SGrant Grundler 6616ca45a24SGrant Grundler /* 6621da177e4SLinus Torvalds ** The algorithm is generic code. 6631da177e4SLinus Torvalds ** But it needs to access local data structures to get the IRQ base. 6641da177e4SLinus Torvalds ** Could make this a "pci_fixup_irq(bus, region)" but not sure 6651da177e4SLinus Torvalds ** it's worth it. 6661da177e4SLinus Torvalds ** 6671da177e4SLinus Torvalds ** Called by do_pci_scan_bus() immediately after each PCI bus is walked. 6681da177e4SLinus Torvalds ** Resources aren't allocated until recursive buswalk below HBA is completed. 6691da177e4SLinus Torvalds */ 6701da177e4SLinus Torvalds static void 6711da177e4SLinus Torvalds lba_fixup_bus(struct pci_bus *bus) 6721da177e4SLinus Torvalds { 6731da177e4SLinus Torvalds struct list_head *ln; 6741da177e4SLinus Torvalds #ifdef FBB_SUPPORT 6751da177e4SLinus Torvalds u16 status; 6761da177e4SLinus Torvalds #endif 6771da177e4SLinus Torvalds struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge)); 6781da177e4SLinus Torvalds int lba_portbase = HBA_PORT_BASE(ldev->hba.hba_num); 6791da177e4SLinus Torvalds 6801da177e4SLinus Torvalds DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n", 6811da177e4SLinus Torvalds bus, bus->secondary, bus->bridge->platform_data); 6821da177e4SLinus Torvalds 6831da177e4SLinus Torvalds /* 6841da177e4SLinus Torvalds ** Properly Setup MMIO resources for this bus. 6851da177e4SLinus Torvalds ** pci_alloc_primary_bus() mangles this. 6861da177e4SLinus Torvalds */ 6871da177e4SLinus Torvalds if (bus->self) { 6881da177e4SLinus Torvalds /* PCI-PCI Bridge */ 6891da177e4SLinus Torvalds pci_read_bridge_bases(bus); 6901da177e4SLinus Torvalds } else { 6911da177e4SLinus Torvalds /* Host-PCI Bridge */ 6921da177e4SLinus Torvalds int err, i; 6931da177e4SLinus Torvalds 6941da177e4SLinus Torvalds DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 6951da177e4SLinus Torvalds ldev->hba.io_space.name, 6961da177e4SLinus Torvalds ldev->hba.io_space.start, ldev->hba.io_space.end, 6971da177e4SLinus Torvalds ldev->hba.io_space.flags); 6981da177e4SLinus Torvalds DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n", 6991da177e4SLinus Torvalds ldev->hba.lmmio_space.name, 7001da177e4SLinus Torvalds ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end, 7011da177e4SLinus Torvalds ldev->hba.lmmio_space.flags); 7021da177e4SLinus Torvalds 7031da177e4SLinus Torvalds err = request_resource(&ioport_resource, &(ldev->hba.io_space)); 7041da177e4SLinus Torvalds if (err < 0) { 7051da177e4SLinus Torvalds lba_dump_res(&ioport_resource, 2); 7061da177e4SLinus Torvalds BUG(); 7071da177e4SLinus Torvalds } 7086ca45a24SGrant Grundler /* advertize Host bridge resources to PCI bus */ 7096ca45a24SGrant Grundler bus->resource[0] = &(ldev->hba.io_space); 7106ca45a24SGrant Grundler i = 1; 7111da177e4SLinus Torvalds 7121da177e4SLinus Torvalds if (ldev->hba.elmmio_space.start) { 7131da177e4SLinus Torvalds err = request_resource(&iomem_resource, 7141da177e4SLinus Torvalds &(ldev->hba.elmmio_space)); 7151da177e4SLinus Torvalds if (err < 0) { 7161da177e4SLinus Torvalds 7171da177e4SLinus Torvalds printk("FAILED: lba_fixup_bus() request for " 7181da177e4SLinus Torvalds "elmmio_space [%lx/%lx]\n", 719*645d11d4SMatthew Wilcox (long)ldev->hba.elmmio_space.start, 720*645d11d4SMatthew Wilcox (long)ldev->hba.elmmio_space.end); 7211da177e4SLinus Torvalds 7221da177e4SLinus Torvalds /* lba_dump_res(&iomem_resource, 2); */ 7231da177e4SLinus Torvalds /* BUG(); */ 7246ca45a24SGrant Grundler } else 7256ca45a24SGrant Grundler bus->resource[i++] = &(ldev->hba.elmmio_space); 7261da177e4SLinus Torvalds } 7271da177e4SLinus Torvalds 7286ca45a24SGrant Grundler 7296ca45a24SGrant Grundler /* Overlaps with elmmio can (and should) fail here. 7306ca45a24SGrant Grundler * We will prune (or ignore) the distributed range. 7316ca45a24SGrant Grundler * 7326ca45a24SGrant Grundler * FIXME: SBA code should register all elmmio ranges first. 7336ca45a24SGrant Grundler * that would take care of elmmio ranges routed 7346ca45a24SGrant Grundler * to a different rope (already discovered) from 7356ca45a24SGrant Grundler * getting registered *after* LBA code has already 7366ca45a24SGrant Grundler * registered it's distributed lmmio range. 7376ca45a24SGrant Grundler */ 7386ca45a24SGrant Grundler if (truncate_pat_collision(&iomem_resource, 7396ca45a24SGrant Grundler &(ldev->hba.lmmio_space))) { 7406ca45a24SGrant Grundler 7416ca45a24SGrant Grundler printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n", 742*645d11d4SMatthew Wilcox (long)ldev->hba.lmmio_space.start, 743*645d11d4SMatthew Wilcox (long)ldev->hba.lmmio_space.end); 7446ca45a24SGrant Grundler } else { 7451da177e4SLinus Torvalds err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space)); 7461da177e4SLinus Torvalds if (err < 0) { 7476ca45a24SGrant Grundler printk(KERN_ERR "FAILED: lba_fixup_bus() request for " 7481da177e4SLinus Torvalds "lmmio_space [%lx/%lx]\n", 749*645d11d4SMatthew Wilcox (long)ldev->hba.lmmio_space.start, 750*645d11d4SMatthew Wilcox (long)ldev->hba.lmmio_space.end); 7516ca45a24SGrant Grundler } else 7526ca45a24SGrant Grundler bus->resource[i++] = &(ldev->hba.lmmio_space); 7531da177e4SLinus Torvalds } 7541da177e4SLinus Torvalds 7551da177e4SLinus Torvalds #ifdef CONFIG_64BIT 7561da177e4SLinus Torvalds /* GMMIO is distributed range. Every LBA/Rope gets part it. */ 7571da177e4SLinus Torvalds if (ldev->hba.gmmio_space.flags) { 7581da177e4SLinus Torvalds err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space)); 7591da177e4SLinus Torvalds if (err < 0) { 7601da177e4SLinus Torvalds printk("FAILED: lba_fixup_bus() request for " 7611da177e4SLinus Torvalds "gmmio_space [%lx/%lx]\n", 762*645d11d4SMatthew Wilcox (long)ldev->hba.gmmio_space.start, 763*645d11d4SMatthew Wilcox (long)ldev->hba.gmmio_space.end); 7641da177e4SLinus Torvalds lba_dump_res(&iomem_resource, 2); 7651da177e4SLinus Torvalds BUG(); 7661da177e4SLinus Torvalds } 7676ca45a24SGrant Grundler bus->resource[i++] = &(ldev->hba.gmmio_space); 7681da177e4SLinus Torvalds } 7691da177e4SLinus Torvalds #endif 7701da177e4SLinus Torvalds 7711da177e4SLinus Torvalds } 7721da177e4SLinus Torvalds 7731da177e4SLinus Torvalds list_for_each(ln, &bus->devices) { 7741da177e4SLinus Torvalds int i; 7751da177e4SLinus Torvalds struct pci_dev *dev = pci_dev_b(ln); 7761da177e4SLinus Torvalds 7771da177e4SLinus Torvalds DBG("lba_fixup_bus() %s\n", pci_name(dev)); 7781da177e4SLinus Torvalds 7791da177e4SLinus Torvalds /* Virtualize Device/Bridge Resources. */ 7801da177e4SLinus Torvalds for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) { 7811da177e4SLinus Torvalds struct resource *res = &dev->resource[i]; 7821da177e4SLinus Torvalds 7831da177e4SLinus Torvalds /* If resource not allocated - skip it */ 7841da177e4SLinus Torvalds if (!res->start) 7851da177e4SLinus Torvalds continue; 7861da177e4SLinus Torvalds 7871da177e4SLinus Torvalds if (res->flags & IORESOURCE_IO) { 7881da177e4SLinus Torvalds DBG("lba_fixup_bus() I/O Ports [%lx/%lx] -> ", 7891da177e4SLinus Torvalds res->start, res->end); 7901da177e4SLinus Torvalds res->start |= lba_portbase; 7911da177e4SLinus Torvalds res->end |= lba_portbase; 7921da177e4SLinus Torvalds DBG("[%lx/%lx]\n", res->start, res->end); 7931da177e4SLinus Torvalds } else if (res->flags & IORESOURCE_MEM) { 7941da177e4SLinus Torvalds /* 7951da177e4SLinus Torvalds ** Convert PCI (IO_VIEW) addresses to 7961da177e4SLinus Torvalds ** processor (PA_VIEW) addresses 7971da177e4SLinus Torvalds */ 7981da177e4SLinus Torvalds DBG("lba_fixup_bus() MMIO [%lx/%lx] -> ", 7991da177e4SLinus Torvalds res->start, res->end); 8001da177e4SLinus Torvalds res->start = PCI_HOST_ADDR(HBA_DATA(ldev), res->start); 8011da177e4SLinus Torvalds res->end = PCI_HOST_ADDR(HBA_DATA(ldev), res->end); 8021da177e4SLinus Torvalds DBG("[%lx/%lx]\n", res->start, res->end); 8031da177e4SLinus Torvalds } else { 8041da177e4SLinus Torvalds DBG("lba_fixup_bus() WTF? 0x%lx [%lx/%lx] XXX", 8051da177e4SLinus Torvalds res->flags, res->start, res->end); 8061da177e4SLinus Torvalds } 8071da177e4SLinus Torvalds } 8081da177e4SLinus Torvalds 8091da177e4SLinus Torvalds #ifdef FBB_SUPPORT 8101da177e4SLinus Torvalds /* 8111da177e4SLinus Torvalds ** If one device does not support FBB transfers, 8121da177e4SLinus Torvalds ** No one on the bus can be allowed to use them. 8131da177e4SLinus Torvalds */ 8141da177e4SLinus Torvalds (void) pci_read_config_word(dev, PCI_STATUS, &status); 8151da177e4SLinus Torvalds bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK); 8161da177e4SLinus Torvalds #endif 8171da177e4SLinus Torvalds 8181da177e4SLinus Torvalds if (is_pdc_pat()) { 8191da177e4SLinus Torvalds /* Claim resources for PDC's devices */ 8201da177e4SLinus Torvalds lba_claim_dev_resources(dev); 8211da177e4SLinus Torvalds } 8221da177e4SLinus Torvalds 8231da177e4SLinus Torvalds /* 8241da177e4SLinus Torvalds ** P2PB's have no IRQs. ignore them. 8251da177e4SLinus Torvalds */ 8261da177e4SLinus Torvalds if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) 8271da177e4SLinus Torvalds continue; 8281da177e4SLinus Torvalds 8291da177e4SLinus Torvalds /* Adjust INTERRUPT_LINE for this dev */ 8301da177e4SLinus Torvalds iosapic_fixup_irq(ldev->iosapic_obj, dev); 8311da177e4SLinus Torvalds } 8321da177e4SLinus Torvalds 8331da177e4SLinus Torvalds #ifdef FBB_SUPPORT 8341da177e4SLinus Torvalds /* FIXME/REVISIT - finish figuring out to set FBB on both 8351da177e4SLinus Torvalds ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL. 8361da177e4SLinus Torvalds ** Can't fixup here anyway....garr... 8371da177e4SLinus Torvalds */ 8381da177e4SLinus Torvalds if (fbb_enable) { 8391da177e4SLinus Torvalds if (bus->self) { 8401da177e4SLinus Torvalds u8 control; 8411da177e4SLinus Torvalds /* enable on PPB */ 8421da177e4SLinus Torvalds (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); 8431da177e4SLinus Torvalds (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK); 8441da177e4SLinus Torvalds 8451da177e4SLinus Torvalds } else { 8461da177e4SLinus Torvalds /* enable on LBA */ 8471da177e4SLinus Torvalds } 8481da177e4SLinus Torvalds fbb_enable = PCI_COMMAND_FAST_BACK; 8491da177e4SLinus Torvalds } 8501da177e4SLinus Torvalds 8511da177e4SLinus Torvalds /* Lastly enable FBB/PERR/SERR on all devices too */ 8521da177e4SLinus Torvalds list_for_each(ln, &bus->devices) { 8531da177e4SLinus Torvalds (void) pci_read_config_word(dev, PCI_COMMAND, &status); 8541da177e4SLinus Torvalds status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable; 8551da177e4SLinus Torvalds (void) pci_write_config_word(dev, PCI_COMMAND, status); 8561da177e4SLinus Torvalds } 8571da177e4SLinus Torvalds #endif 8581da177e4SLinus Torvalds } 8591da177e4SLinus Torvalds 8601da177e4SLinus Torvalds 8611da177e4SLinus Torvalds struct pci_bios_ops lba_bios_ops = { 8621da177e4SLinus Torvalds .init = lba_bios_init, 8631da177e4SLinus Torvalds .fixup_bus = lba_fixup_bus, 8641da177e4SLinus Torvalds }; 8651da177e4SLinus Torvalds 8661da177e4SLinus Torvalds 8671da177e4SLinus Torvalds 8681da177e4SLinus Torvalds 8691da177e4SLinus Torvalds /******************************************************* 8701da177e4SLinus Torvalds ** 8711da177e4SLinus Torvalds ** LBA Sprockets "I/O Port" Space Accessor Functions 8721da177e4SLinus Torvalds ** 8731da177e4SLinus Torvalds ** This set of accessor functions is intended for use with 8741da177e4SLinus Torvalds ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes). 8751da177e4SLinus Torvalds ** 8761da177e4SLinus Torvalds ** Many PCI devices don't require use of I/O port space (eg Tulip, 8771da177e4SLinus Torvalds ** NCR720) since they export the same registers to both MMIO and 8781da177e4SLinus Torvalds ** I/O port space. In general I/O port space is slower than 8791da177e4SLinus Torvalds ** MMIO since drivers are designed so PIO writes can be posted. 8801da177e4SLinus Torvalds ** 8811da177e4SLinus Torvalds ********************************************************/ 8821da177e4SLinus Torvalds 8831da177e4SLinus Torvalds #define LBA_PORT_IN(size, mask) \ 8841da177e4SLinus Torvalds static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \ 8851da177e4SLinus Torvalds { \ 8861da177e4SLinus Torvalds u##size t; \ 8871da177e4SLinus Torvalds t = READ_REG##size(astro_iop_base + addr); \ 8881da177e4SLinus Torvalds DBG_PORT(" 0x%x\n", t); \ 8891da177e4SLinus Torvalds return (t); \ 8901da177e4SLinus Torvalds } 8911da177e4SLinus Torvalds 8921da177e4SLinus Torvalds LBA_PORT_IN( 8, 3) 8931da177e4SLinus Torvalds LBA_PORT_IN(16, 2) 8941da177e4SLinus Torvalds LBA_PORT_IN(32, 0) 8951da177e4SLinus Torvalds 8961da177e4SLinus Torvalds 8971da177e4SLinus Torvalds 8981da177e4SLinus Torvalds /* 8991da177e4SLinus Torvalds ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR 9001da177e4SLinus Torvalds ** 9011da177e4SLinus Torvalds ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is 9021da177e4SLinus Torvalds ** guarantee non-postable completion semantics - not avoid X4107. 9031da177e4SLinus Torvalds ** The READ_U32 only guarantees the write data gets to elroy but 9041da177e4SLinus Torvalds ** out to the PCI bus. We can't read stuff from I/O port space 9051da177e4SLinus Torvalds ** since we don't know what has side-effects. Attempting to read 9061da177e4SLinus Torvalds ** from configuration space would be suicidal given the number of 9071da177e4SLinus Torvalds ** bugs in that elroy functionality. 9081da177e4SLinus Torvalds ** 9091da177e4SLinus Torvalds ** Description: 9101da177e4SLinus Torvalds ** DMA read results can improperly pass PIO writes (X4107). The 9111da177e4SLinus Torvalds ** result of this bug is that if a processor modifies a location in 9121da177e4SLinus Torvalds ** memory after having issued PIO writes, the PIO writes are not 9131da177e4SLinus Torvalds ** guaranteed to be completed before a PCI device is allowed to see 9141da177e4SLinus Torvalds ** the modified data in a DMA read. 9151da177e4SLinus Torvalds ** 9161da177e4SLinus Torvalds ** Note that IKE bug X3719 in TR1 IKEs will result in the same 9171da177e4SLinus Torvalds ** symptom. 9181da177e4SLinus Torvalds ** 9191da177e4SLinus Torvalds ** Workaround: 9201da177e4SLinus Torvalds ** The workaround for this bug is to always follow a PIO write with 9211da177e4SLinus Torvalds ** a PIO read to the same bus before starting DMA on that PCI bus. 9221da177e4SLinus Torvalds ** 9231da177e4SLinus Torvalds */ 9241da177e4SLinus Torvalds #define LBA_PORT_OUT(size, mask) \ 9251da177e4SLinus Torvalds static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \ 9261da177e4SLinus Torvalds { \ 9271da177e4SLinus Torvalds DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \ 9281da177e4SLinus Torvalds WRITE_REG##size(val, astro_iop_base + addr); \ 9291da177e4SLinus Torvalds if (LBA_DEV(d)->hw_rev < 3) \ 9301da177e4SLinus Torvalds lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \ 9311da177e4SLinus Torvalds } 9321da177e4SLinus Torvalds 9331da177e4SLinus Torvalds LBA_PORT_OUT( 8, 3) 9341da177e4SLinus Torvalds LBA_PORT_OUT(16, 2) 9351da177e4SLinus Torvalds LBA_PORT_OUT(32, 0) 9361da177e4SLinus Torvalds 9371da177e4SLinus Torvalds 9381da177e4SLinus Torvalds static struct pci_port_ops lba_astro_port_ops = { 9391da177e4SLinus Torvalds .inb = lba_astro_in8, 9401da177e4SLinus Torvalds .inw = lba_astro_in16, 9411da177e4SLinus Torvalds .inl = lba_astro_in32, 9421da177e4SLinus Torvalds .outb = lba_astro_out8, 9431da177e4SLinus Torvalds .outw = lba_astro_out16, 9441da177e4SLinus Torvalds .outl = lba_astro_out32 9451da177e4SLinus Torvalds }; 9461da177e4SLinus Torvalds 9471da177e4SLinus Torvalds 9481da177e4SLinus Torvalds #ifdef CONFIG_64BIT 9491da177e4SLinus Torvalds #define PIOP_TO_GMMIO(lba, addr) \ 9501da177e4SLinus Torvalds ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3)) 9511da177e4SLinus Torvalds 9521da177e4SLinus Torvalds /******************************************************* 9531da177e4SLinus Torvalds ** 9541da177e4SLinus Torvalds ** LBA PAT "I/O Port" Space Accessor Functions 9551da177e4SLinus Torvalds ** 9561da177e4SLinus Torvalds ** This set of accessor functions is intended for use with 9571da177e4SLinus Torvalds ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes). 9581da177e4SLinus Torvalds ** 9591da177e4SLinus Torvalds ** This uses the PIOP space located in the first 64MB of GMMIO. 9601da177e4SLinus Torvalds ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way. 9611da177e4SLinus Torvalds ** bits 1:0 stay the same. bits 15:2 become 25:12. 9621da177e4SLinus Torvalds ** Then add the base and we can generate an I/O Port cycle. 9631da177e4SLinus Torvalds ********************************************************/ 9641da177e4SLinus Torvalds #undef LBA_PORT_IN 9651da177e4SLinus Torvalds #define LBA_PORT_IN(size, mask) \ 9661da177e4SLinus Torvalds static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \ 9671da177e4SLinus Torvalds { \ 9681da177e4SLinus Torvalds u##size t; \ 9691da177e4SLinus Torvalds DBG_PORT("%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \ 9701da177e4SLinus Torvalds t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \ 9711da177e4SLinus Torvalds DBG_PORT(" 0x%x\n", t); \ 9721da177e4SLinus Torvalds return (t); \ 9731da177e4SLinus Torvalds } 9741da177e4SLinus Torvalds 9751da177e4SLinus Torvalds LBA_PORT_IN( 8, 3) 9761da177e4SLinus Torvalds LBA_PORT_IN(16, 2) 9771da177e4SLinus Torvalds LBA_PORT_IN(32, 0) 9781da177e4SLinus Torvalds 9791da177e4SLinus Torvalds 9801da177e4SLinus Torvalds #undef LBA_PORT_OUT 9811da177e4SLinus Torvalds #define LBA_PORT_OUT(size, mask) \ 9821da177e4SLinus Torvalds static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \ 9831da177e4SLinus Torvalds { \ 984c2c4798eSMatthew Wilcox void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \ 9851da177e4SLinus Torvalds DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \ 9861da177e4SLinus Torvalds WRITE_REG##size(val, where); \ 9871da177e4SLinus Torvalds /* flush the I/O down to the elroy at least */ \ 9881da177e4SLinus Torvalds lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \ 9891da177e4SLinus Torvalds } 9901da177e4SLinus Torvalds 9911da177e4SLinus Torvalds LBA_PORT_OUT( 8, 3) 9921da177e4SLinus Torvalds LBA_PORT_OUT(16, 2) 9931da177e4SLinus Torvalds LBA_PORT_OUT(32, 0) 9941da177e4SLinus Torvalds 9951da177e4SLinus Torvalds 9961da177e4SLinus Torvalds static struct pci_port_ops lba_pat_port_ops = { 9971da177e4SLinus Torvalds .inb = lba_pat_in8, 9981da177e4SLinus Torvalds .inw = lba_pat_in16, 9991da177e4SLinus Torvalds .inl = lba_pat_in32, 10001da177e4SLinus Torvalds .outb = lba_pat_out8, 10011da177e4SLinus Torvalds .outw = lba_pat_out16, 10021da177e4SLinus Torvalds .outl = lba_pat_out32 10031da177e4SLinus Torvalds }; 10041da177e4SLinus Torvalds 10051da177e4SLinus Torvalds 10061da177e4SLinus Torvalds 10071da177e4SLinus Torvalds /* 10081da177e4SLinus Torvalds ** make range information from PDC available to PCI subsystem. 10091da177e4SLinus Torvalds ** We make the PDC call here in order to get the PCI bus range 10101da177e4SLinus Torvalds ** numbers. The rest will get forwarded in pcibios_fixup_bus(). 10111da177e4SLinus Torvalds ** We don't have a struct pci_bus assigned to us yet. 10121da177e4SLinus Torvalds */ 10131da177e4SLinus Torvalds static void 10141da177e4SLinus Torvalds lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 10151da177e4SLinus Torvalds { 10161da177e4SLinus Torvalds unsigned long bytecnt; 10171da177e4SLinus Torvalds pdc_pat_cell_mod_maddr_block_t pa_pdc_cell; /* PA_VIEW */ 10181da177e4SLinus Torvalds pdc_pat_cell_mod_maddr_block_t io_pdc_cell; /* IO_VIEW */ 10191da177e4SLinus Torvalds long io_count; 10201da177e4SLinus Torvalds long status; /* PDC return status */ 10211da177e4SLinus Torvalds long pa_count; 10221da177e4SLinus Torvalds int i; 10231da177e4SLinus Torvalds 10241da177e4SLinus Torvalds /* return cell module (IO view) */ 10251da177e4SLinus Torvalds status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 10261da177e4SLinus Torvalds PA_VIEW, & pa_pdc_cell); 10271da177e4SLinus Torvalds pa_count = pa_pdc_cell.mod[1]; 10281da177e4SLinus Torvalds 10291da177e4SLinus Torvalds status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index, 10301da177e4SLinus Torvalds IO_VIEW, &io_pdc_cell); 10311da177e4SLinus Torvalds io_count = io_pdc_cell.mod[1]; 10321da177e4SLinus Torvalds 10331da177e4SLinus Torvalds /* We've already done this once for device discovery...*/ 10341da177e4SLinus Torvalds if (status != PDC_OK) { 10351da177e4SLinus Torvalds panic("pdc_pat_cell_module() call failed for LBA!\n"); 10361da177e4SLinus Torvalds } 10371da177e4SLinus Torvalds 10381da177e4SLinus Torvalds if (PAT_GET_ENTITY(pa_pdc_cell.mod_info) != PAT_ENTITY_LBA) { 10391da177e4SLinus Torvalds panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n"); 10401da177e4SLinus Torvalds } 10411da177e4SLinus Torvalds 10421da177e4SLinus Torvalds /* 10431da177e4SLinus Torvalds ** Inspect the resources PAT tells us about 10441da177e4SLinus Torvalds */ 10451da177e4SLinus Torvalds for (i = 0; i < pa_count; i++) { 10461da177e4SLinus Torvalds struct { 10471da177e4SLinus Torvalds unsigned long type; 10481da177e4SLinus Torvalds unsigned long start; 10491da177e4SLinus Torvalds unsigned long end; /* aka finish */ 10501da177e4SLinus Torvalds } *p, *io; 10511da177e4SLinus Torvalds struct resource *r; 10521da177e4SLinus Torvalds 10531da177e4SLinus Torvalds p = (void *) &(pa_pdc_cell.mod[2+i*3]); 10541da177e4SLinus Torvalds io = (void *) &(io_pdc_cell.mod[2+i*3]); 10551da177e4SLinus Torvalds 10561da177e4SLinus Torvalds /* Convert the PAT range data to PCI "struct resource" */ 10571da177e4SLinus Torvalds switch(p->type & 0xff) { 10581da177e4SLinus Torvalds case PAT_PBNUM: 10591da177e4SLinus Torvalds lba_dev->hba.bus_num.start = p->start; 10601da177e4SLinus Torvalds lba_dev->hba.bus_num.end = p->end; 10611da177e4SLinus Torvalds break; 10621da177e4SLinus Torvalds 10631da177e4SLinus Torvalds case PAT_LMMIO: 10641da177e4SLinus Torvalds /* used to fix up pre-initialized MEM BARs */ 10651da177e4SLinus Torvalds if (!lba_dev->hba.lmmio_space.start) { 10661da177e4SLinus Torvalds sprintf(lba_dev->hba.lmmio_name, 1067*645d11d4SMatthew Wilcox "PCI%02x LMMIO", 1068*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 10691da177e4SLinus Torvalds lba_dev->hba.lmmio_space_offset = p->start - 10701da177e4SLinus Torvalds io->start; 10711da177e4SLinus Torvalds r = &lba_dev->hba.lmmio_space; 10721da177e4SLinus Torvalds r->name = lba_dev->hba.lmmio_name; 10731da177e4SLinus Torvalds } else if (!lba_dev->hba.elmmio_space.start) { 10741da177e4SLinus Torvalds sprintf(lba_dev->hba.elmmio_name, 1075*645d11d4SMatthew Wilcox "PCI%02x ELMMIO", 1076*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 10771da177e4SLinus Torvalds r = &lba_dev->hba.elmmio_space; 10781da177e4SLinus Torvalds r->name = lba_dev->hba.elmmio_name; 10791da177e4SLinus Torvalds } else { 10801da177e4SLinus Torvalds printk(KERN_WARNING MODULE_NAME 10811da177e4SLinus Torvalds " only supports 2 LMMIO resources!\n"); 10821da177e4SLinus Torvalds break; 10831da177e4SLinus Torvalds } 10841da177e4SLinus Torvalds 10851da177e4SLinus Torvalds r->start = p->start; 10861da177e4SLinus Torvalds r->end = p->end; 10871da177e4SLinus Torvalds r->flags = IORESOURCE_MEM; 10881da177e4SLinus Torvalds r->parent = r->sibling = r->child = NULL; 10891da177e4SLinus Torvalds break; 10901da177e4SLinus Torvalds 10911da177e4SLinus Torvalds case PAT_GMMIO: 10921da177e4SLinus Torvalds /* MMIO space > 4GB phys addr; for 64-bit BAR */ 1093*645d11d4SMatthew Wilcox sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO", 1094*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 10951da177e4SLinus Torvalds r = &lba_dev->hba.gmmio_space; 10961da177e4SLinus Torvalds r->name = lba_dev->hba.gmmio_name; 10971da177e4SLinus Torvalds r->start = p->start; 10981da177e4SLinus Torvalds r->end = p->end; 10991da177e4SLinus Torvalds r->flags = IORESOURCE_MEM; 11001da177e4SLinus Torvalds r->parent = r->sibling = r->child = NULL; 11011da177e4SLinus Torvalds break; 11021da177e4SLinus Torvalds 11031da177e4SLinus Torvalds case PAT_NPIOP: 11041da177e4SLinus Torvalds printk(KERN_WARNING MODULE_NAME 11051da177e4SLinus Torvalds " range[%d] : ignoring NPIOP (0x%lx)\n", 11061da177e4SLinus Torvalds i, p->start); 11071da177e4SLinus Torvalds break; 11081da177e4SLinus Torvalds 11091da177e4SLinus Torvalds case PAT_PIOP: 11101da177e4SLinus Torvalds /* 11111da177e4SLinus Torvalds ** Postable I/O port space is per PCI host adapter. 11121da177e4SLinus Torvalds ** base of 64MB PIOP region 11131da177e4SLinus Torvalds */ 11145076c158SHelge Deller lba_dev->iop_base = ioremap_nocache(p->start, 64 * 1024 * 1024); 11151da177e4SLinus Torvalds 1116*645d11d4SMatthew Wilcox sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1117*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 11181da177e4SLinus Torvalds r = &lba_dev->hba.io_space; 11191da177e4SLinus Torvalds r->name = lba_dev->hba.io_name; 11201da177e4SLinus Torvalds r->start = HBA_PORT_BASE(lba_dev->hba.hba_num); 11211da177e4SLinus Torvalds r->end = r->start + HBA_PORT_SPACE_SIZE - 1; 11221da177e4SLinus Torvalds r->flags = IORESOURCE_IO; 11231da177e4SLinus Torvalds r->parent = r->sibling = r->child = NULL; 11241da177e4SLinus Torvalds break; 11251da177e4SLinus Torvalds 11261da177e4SLinus Torvalds default: 11271da177e4SLinus Torvalds printk(KERN_WARNING MODULE_NAME 11281da177e4SLinus Torvalds " range[%d] : unknown pat range type (0x%lx)\n", 11291da177e4SLinus Torvalds i, p->type & 0xff); 11301da177e4SLinus Torvalds break; 11311da177e4SLinus Torvalds } 11321da177e4SLinus Torvalds } 11331da177e4SLinus Torvalds } 11341da177e4SLinus Torvalds #else 11351da177e4SLinus Torvalds /* keep compiler from complaining about missing declarations */ 11361da177e4SLinus Torvalds #define lba_pat_port_ops lba_astro_port_ops 11371da177e4SLinus Torvalds #define lba_pat_resources(pa_dev, lba_dev) 11381da177e4SLinus Torvalds #endif /* CONFIG_64BIT */ 11391da177e4SLinus Torvalds 11401da177e4SLinus Torvalds 11411da177e4SLinus Torvalds extern void sba_distributed_lmmio(struct parisc_device *, struct resource *); 11421da177e4SLinus Torvalds extern void sba_directed_lmmio(struct parisc_device *, struct resource *); 11431da177e4SLinus Torvalds 11441da177e4SLinus Torvalds 11451da177e4SLinus Torvalds static void 11461da177e4SLinus Torvalds lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev) 11471da177e4SLinus Torvalds { 11481da177e4SLinus Torvalds struct resource *r; 11491da177e4SLinus Torvalds int lba_num; 11501da177e4SLinus Torvalds 11511da177e4SLinus Torvalds lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND; 11521da177e4SLinus Torvalds 11531da177e4SLinus Torvalds /* 11541da177e4SLinus Torvalds ** With "legacy" firmware, the lowest byte of FW_SCRATCH 11551da177e4SLinus Torvalds ** represents bus->secondary and the second byte represents 11561da177e4SLinus Torvalds ** bus->subsidiary (i.e. highest PPB programmed by firmware). 11571da177e4SLinus Torvalds ** PCI bus walk *should* end up with the same result. 11581da177e4SLinus Torvalds ** FIXME: But we don't have sanity checks in PCI or LBA. 11591da177e4SLinus Torvalds */ 11601da177e4SLinus Torvalds lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH); 11611da177e4SLinus Torvalds r = &(lba_dev->hba.bus_num); 11621da177e4SLinus Torvalds r->name = "LBA PCI Busses"; 11631da177e4SLinus Torvalds r->start = lba_num & 0xff; 11641da177e4SLinus Torvalds r->end = (lba_num>>8) & 0xff; 11651da177e4SLinus Torvalds 11661da177e4SLinus Torvalds /* Set up local PCI Bus resources - we don't need them for 11671da177e4SLinus Torvalds ** Legacy boxes but it's nice to see in /proc/iomem. 11681da177e4SLinus Torvalds */ 11691da177e4SLinus Torvalds r = &(lba_dev->hba.lmmio_space); 1170*645d11d4SMatthew Wilcox sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO", 1171*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 11721da177e4SLinus Torvalds r->name = lba_dev->hba.lmmio_name; 11731da177e4SLinus Torvalds 11741da177e4SLinus Torvalds #if 1 11751da177e4SLinus Torvalds /* We want the CPU -> IO routing of addresses. 11761da177e4SLinus Torvalds * The SBA BASE/MASK registers control CPU -> IO routing. 11771da177e4SLinus Torvalds * Ask SBA what is routed to this rope/LBA. 11781da177e4SLinus Torvalds */ 11791da177e4SLinus Torvalds sba_distributed_lmmio(pa_dev, r); 11801da177e4SLinus Torvalds #else 11811da177e4SLinus Torvalds /* 11821da177e4SLinus Torvalds * The LBA BASE/MASK registers control IO -> System routing. 11831da177e4SLinus Torvalds * 11841da177e4SLinus Torvalds * The following code works but doesn't get us what we want. 11851da177e4SLinus Torvalds * Well, only because firmware (v5.0) on C3000 doesn't program 11861da177e4SLinus Torvalds * the LBA BASE/MASE registers to be the exact inverse of 11871da177e4SLinus Torvalds * the corresponding SBA registers. Other Astro/Pluto 11881da177e4SLinus Torvalds * based platform firmware may do it right. 11891da177e4SLinus Torvalds * 11901da177e4SLinus Torvalds * Should someone want to mess with MSI, they may need to 11911da177e4SLinus Torvalds * reprogram LBA BASE/MASK registers. Thus preserve the code 11921da177e4SLinus Torvalds * below until MSI is known to work on C3000/A500/N4000/RP3440. 11931da177e4SLinus Torvalds * 11941da177e4SLinus Torvalds * Using the code below, /proc/iomem shows: 11951da177e4SLinus Torvalds * ... 11961da177e4SLinus Torvalds * f0000000-f0ffffff : PCI00 LMMIO 11971da177e4SLinus Torvalds * f05d0000-f05d0000 : lcd_data 11981da177e4SLinus Torvalds * f05d0008-f05d0008 : lcd_cmd 11991da177e4SLinus Torvalds * f1000000-f1ffffff : PCI01 LMMIO 12001da177e4SLinus Torvalds * f4000000-f4ffffff : PCI02 LMMIO 12011da177e4SLinus Torvalds * f4000000-f4001fff : sym53c8xx 12021da177e4SLinus Torvalds * f4002000-f4003fff : sym53c8xx 12031da177e4SLinus Torvalds * f4004000-f40043ff : sym53c8xx 12041da177e4SLinus Torvalds * f4005000-f40053ff : sym53c8xx 12051da177e4SLinus Torvalds * f4007000-f4007fff : ohci_hcd 12061da177e4SLinus Torvalds * f4008000-f40083ff : tulip 12071da177e4SLinus Torvalds * f6000000-f6ffffff : PCI03 LMMIO 12081da177e4SLinus Torvalds * f8000000-fbffffff : PCI00 ELMMIO 12091da177e4SLinus Torvalds * fa100000-fa4fffff : stifb mmio 12101da177e4SLinus Torvalds * fb000000-fb1fffff : stifb fb 12111da177e4SLinus Torvalds * 12121da177e4SLinus Torvalds * But everything listed under PCI02 actually lives under PCI00. 12131da177e4SLinus Torvalds * This is clearly wrong. 12141da177e4SLinus Torvalds * 12151da177e4SLinus Torvalds * Asking SBA how things are routed tells the correct story: 12161da177e4SLinus Torvalds * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000 12171da177e4SLinus Torvalds * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006 12181da177e4SLinus Torvalds * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004 12191da177e4SLinus Torvalds * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000 12201da177e4SLinus Torvalds * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000 12211da177e4SLinus Torvalds * 12221da177e4SLinus Torvalds * Which looks like this in /proc/iomem: 12231da177e4SLinus Torvalds * f4000000-f47fffff : PCI00 LMMIO 12241da177e4SLinus Torvalds * f4000000-f4001fff : sym53c8xx 12251da177e4SLinus Torvalds * ...[deteled core devices - same as above]... 12261da177e4SLinus Torvalds * f4008000-f40083ff : tulip 12271da177e4SLinus Torvalds * f4800000-f4ffffff : PCI01 LMMIO 12281da177e4SLinus Torvalds * f6000000-f67fffff : PCI02 LMMIO 12291da177e4SLinus Torvalds * f7000000-f77fffff : PCI03 LMMIO 12301da177e4SLinus Torvalds * f9000000-f9ffffff : PCI02 ELMMIO 12311da177e4SLinus Torvalds * fa000000-fbffffff : PCI03 ELMMIO 12321da177e4SLinus Torvalds * fa100000-fa4fffff : stifb mmio 12331da177e4SLinus Torvalds * fb000000-fb1fffff : stifb fb 12341da177e4SLinus Torvalds * 12351da177e4SLinus Torvalds * ie all Built-in core are under now correctly under PCI00. 12361da177e4SLinus Torvalds * The "PCI02 ELMMIO" directed range is for: 12371da177e4SLinus Torvalds * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2 12381da177e4SLinus Torvalds * 12391da177e4SLinus Torvalds * All is well now. 12401da177e4SLinus Torvalds */ 12411da177e4SLinus Torvalds r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE); 12421da177e4SLinus Torvalds if (r->start & 1) { 12431da177e4SLinus Torvalds unsigned long rsize; 12441da177e4SLinus Torvalds 12451da177e4SLinus Torvalds r->flags = IORESOURCE_MEM; 12461da177e4SLinus Torvalds /* mmio_mask also clears Enable bit */ 12471da177e4SLinus Torvalds r->start &= mmio_mask; 12481da177e4SLinus Torvalds r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 12491da177e4SLinus Torvalds rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK); 12501da177e4SLinus Torvalds 12511da177e4SLinus Torvalds /* 12521da177e4SLinus Torvalds ** Each rope only gets part of the distributed range. 12531da177e4SLinus Torvalds ** Adjust "window" for this rope. 12541da177e4SLinus Torvalds */ 12551da177e4SLinus Torvalds rsize /= ROPES_PER_IOC; 125653f01bbaSMatthew Wilcox r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start); 12571da177e4SLinus Torvalds r->end = r->start + rsize; 12581da177e4SLinus Torvalds } else { 12591da177e4SLinus Torvalds r->end = r->start = 0; /* Not enabled. */ 12601da177e4SLinus Torvalds } 12611da177e4SLinus Torvalds #endif 12621da177e4SLinus Torvalds 12631da177e4SLinus Torvalds /* 12641da177e4SLinus Torvalds ** "Directed" ranges are used when the "distributed range" isn't 12651da177e4SLinus Torvalds ** sufficient for all devices below a given LBA. Typically devices 12661da177e4SLinus Torvalds ** like graphics cards or X25 may need a directed range when the 12671da177e4SLinus Torvalds ** bus has multiple slots (ie multiple devices) or the device 12681da177e4SLinus Torvalds ** needs more than the typical 4 or 8MB a distributed range offers. 12691da177e4SLinus Torvalds ** 12701da177e4SLinus Torvalds ** The main reason for ignoring it now frigging complications. 12711da177e4SLinus Torvalds ** Directed ranges may overlap (and have precedence) over 12721da177e4SLinus Torvalds ** distributed ranges. Or a distributed range assigned to a unused 12731da177e4SLinus Torvalds ** rope may be used by a directed range on a different rope. 12741da177e4SLinus Torvalds ** Support for graphics devices may require fixing this 12751da177e4SLinus Torvalds ** since they may be assigned a directed range which overlaps 12761da177e4SLinus Torvalds ** an existing (but unused portion of) distributed range. 12771da177e4SLinus Torvalds */ 12781da177e4SLinus Torvalds r = &(lba_dev->hba.elmmio_space); 1279*645d11d4SMatthew Wilcox sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO", 1280*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 12811da177e4SLinus Torvalds r->name = lba_dev->hba.elmmio_name; 12821da177e4SLinus Torvalds 12831da177e4SLinus Torvalds #if 1 12841da177e4SLinus Torvalds /* See comment which precedes call to sba_directed_lmmio() */ 12851da177e4SLinus Torvalds sba_directed_lmmio(pa_dev, r); 12861da177e4SLinus Torvalds #else 12871da177e4SLinus Torvalds r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE); 12881da177e4SLinus Torvalds 12891da177e4SLinus Torvalds if (r->start & 1) { 12901da177e4SLinus Torvalds unsigned long rsize; 12911da177e4SLinus Torvalds r->flags = IORESOURCE_MEM; 12921da177e4SLinus Torvalds /* mmio_mask also clears Enable bit */ 12931da177e4SLinus Torvalds r->start &= mmio_mask; 12941da177e4SLinus Torvalds r->start = PCI_HOST_ADDR(HBA_DATA(lba_dev), r->start); 12951da177e4SLinus Torvalds rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK); 12961da177e4SLinus Torvalds r->end = r->start + ~rsize; 12971da177e4SLinus Torvalds } 12981da177e4SLinus Torvalds #endif 12991da177e4SLinus Torvalds 13001da177e4SLinus Torvalds r = &(lba_dev->hba.io_space); 1301*645d11d4SMatthew Wilcox sprintf(lba_dev->hba.io_name, "PCI%02x Ports", 1302*645d11d4SMatthew Wilcox (int)lba_dev->hba.bus_num.start); 13031da177e4SLinus Torvalds r->name = lba_dev->hba.io_name; 13041da177e4SLinus Torvalds r->flags = IORESOURCE_IO; 13051da177e4SLinus Torvalds r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L; 13061da177e4SLinus Torvalds r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1)); 13071da177e4SLinus Torvalds 13081da177e4SLinus Torvalds /* Virtualize the I/O Port space ranges */ 13091da177e4SLinus Torvalds lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num); 13101da177e4SLinus Torvalds r->start |= lba_num; 13111da177e4SLinus Torvalds r->end |= lba_num; 13121da177e4SLinus Torvalds } 13131da177e4SLinus Torvalds 13141da177e4SLinus Torvalds 13151da177e4SLinus Torvalds /************************************************************************** 13161da177e4SLinus Torvalds ** 13171da177e4SLinus Torvalds ** LBA initialization code (HW and SW) 13181da177e4SLinus Torvalds ** 13191da177e4SLinus Torvalds ** o identify LBA chip itself 13201da177e4SLinus Torvalds ** o initialize LBA chip modes (HardFail) 13211da177e4SLinus Torvalds ** o FIXME: initialize DMA hints for reasonable defaults 13221da177e4SLinus Torvalds ** o enable configuration functions 13231da177e4SLinus Torvalds ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked) 13241da177e4SLinus Torvalds ** 13251da177e4SLinus Torvalds **************************************************************************/ 13261da177e4SLinus Torvalds 13271da177e4SLinus Torvalds static int __init 13281da177e4SLinus Torvalds lba_hw_init(struct lba_device *d) 13291da177e4SLinus Torvalds { 13301da177e4SLinus Torvalds u32 stat; 13311da177e4SLinus Torvalds u32 bus_reset; /* PDC_PAT_BUG */ 13321da177e4SLinus Torvalds 13331da177e4SLinus Torvalds #if 0 13341da177e4SLinus Torvalds printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n", 13351da177e4SLinus Torvalds d->hba.base_addr, 13361da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_STAT_CTL), 13371da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG), 13381da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS), 13391da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_DMA_CTL) ); 13401da177e4SLinus Torvalds printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n", 13411da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ARB_MASK), 13421da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ARB_PRI), 13431da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ARB_MODE), 13441da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) ); 13451da177e4SLinus Torvalds printk(KERN_DEBUG " HINT cfg 0x%Lx\n", 13461da177e4SLinus Torvalds READ_REG64(d->hba.base_addr + LBA_HINT_CFG)); 13471da177e4SLinus Torvalds printk(KERN_DEBUG " HINT reg "); 13481da177e4SLinus Torvalds { int i; 13491da177e4SLinus Torvalds for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8) 13501da177e4SLinus Torvalds printk(" %Lx", READ_REG64(d->hba.base_addr + i)); 13511da177e4SLinus Torvalds } 13521da177e4SLinus Torvalds printk("\n"); 13531da177e4SLinus Torvalds #endif /* DEBUG_LBA_PAT */ 13541da177e4SLinus Torvalds 13551da177e4SLinus Torvalds #ifdef CONFIG_64BIT 13561da177e4SLinus Torvalds /* 13571da177e4SLinus Torvalds * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support 13581da177e4SLinus Torvalds * Only N-Class and up can really make use of Get slot status. 13591da177e4SLinus Torvalds * maybe L-class too but I've never played with it there. 13601da177e4SLinus Torvalds */ 13611da177e4SLinus Torvalds #endif 13621da177e4SLinus Torvalds 13631da177e4SLinus Torvalds /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */ 13641da177e4SLinus Torvalds bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1; 13651da177e4SLinus Torvalds if (bus_reset) { 13661da177e4SLinus Torvalds printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n"); 13671da177e4SLinus Torvalds } 13681da177e4SLinus Torvalds 13691da177e4SLinus Torvalds stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); 13701da177e4SLinus Torvalds if (stat & LBA_SMART_MODE) { 13711da177e4SLinus Torvalds printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n"); 13721da177e4SLinus Torvalds stat &= ~LBA_SMART_MODE; 13731da177e4SLinus Torvalds WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG); 13741da177e4SLinus Torvalds } 13751da177e4SLinus Torvalds 13761da177e4SLinus Torvalds /* Set HF mode as the default (vs. -1 mode). */ 13771da177e4SLinus Torvalds stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); 13781da177e4SLinus Torvalds WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL); 13791da177e4SLinus Torvalds 13801da177e4SLinus Torvalds /* 13811da177e4SLinus Torvalds ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal 13821da177e4SLinus Torvalds ** if it's not already set. If we just cleared the PCI Bus Reset 13831da177e4SLinus Torvalds ** signal, wait a bit for the PCI devices to recover and setup. 13841da177e4SLinus Torvalds */ 13851da177e4SLinus Torvalds if (bus_reset) 13861da177e4SLinus Torvalds mdelay(pci_post_reset_delay); 13871da177e4SLinus Torvalds 13881da177e4SLinus Torvalds if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) { 13891da177e4SLinus Torvalds /* 13901da177e4SLinus Torvalds ** PDC_PAT_BUG: PDC rev 40.48 on L2000. 13911da177e4SLinus Torvalds ** B2000/C3600/J6000 also have this problem? 13921da177e4SLinus Torvalds ** 13931da177e4SLinus Torvalds ** Elroys with hot pluggable slots don't get configured 13941da177e4SLinus Torvalds ** correctly if the slot is empty. ARB_MASK is set to 0 13951da177e4SLinus Torvalds ** and we can't master transactions on the bus if it's 13961da177e4SLinus Torvalds ** not at least one. 0x3 enables elroy and first slot. 13971da177e4SLinus Torvalds */ 13981da177e4SLinus Torvalds printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n"); 13991da177e4SLinus Torvalds WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK); 14001da177e4SLinus Torvalds } 14011da177e4SLinus Torvalds 14021da177e4SLinus Torvalds /* 14031da177e4SLinus Torvalds ** FIXME: Hint registers are programmed with default hint 14041da177e4SLinus Torvalds ** values by firmware. Hints should be sane even if we 14051da177e4SLinus Torvalds ** can't reprogram them the way drivers want. 14061da177e4SLinus Torvalds */ 14071da177e4SLinus Torvalds return 0; 14081da177e4SLinus Torvalds } 14091da177e4SLinus Torvalds 1410353dfe12SMatthew Wilcox /* 1411353dfe12SMatthew Wilcox * Unfortunately, when firmware numbers busses, it doesn't take into account 1412353dfe12SMatthew Wilcox * Cardbus bridges. So we have to renumber the busses to suit ourselves. 1413353dfe12SMatthew Wilcox * Elroy/Mercury don't actually know what bus number they're attached to; 1414353dfe12SMatthew Wilcox * we use bus 0 to indicate the directly attached bus and any other bus 1415353dfe12SMatthew Wilcox * number will be taken care of by the PCI-PCI bridge. 1416353dfe12SMatthew Wilcox */ 1417353dfe12SMatthew Wilcox static unsigned int lba_next_bus = 0; 14181da177e4SLinus Torvalds 14191da177e4SLinus Torvalds /* 1420353dfe12SMatthew Wilcox * Determine if lba should claim this chip (return 0) or not (return 1). 1421353dfe12SMatthew Wilcox * If so, initialize the chip and tell other partners in crime they 1422353dfe12SMatthew Wilcox * have work to do. 14231da177e4SLinus Torvalds */ 14241da177e4SLinus Torvalds static int __init 14251da177e4SLinus Torvalds lba_driver_probe(struct parisc_device *dev) 14261da177e4SLinus Torvalds { 14271da177e4SLinus Torvalds struct lba_device *lba_dev; 14281da177e4SLinus Torvalds struct pci_bus *lba_bus; 14291da177e4SLinus Torvalds struct pci_ops *cfg_ops; 14301da177e4SLinus Torvalds u32 func_class; 14311da177e4SLinus Torvalds void *tmp_obj; 14321da177e4SLinus Torvalds char *version; 14335076c158SHelge Deller void __iomem *addr = ioremap_nocache(dev->hpa.start, 4096); 14341da177e4SLinus Torvalds 14351da177e4SLinus Torvalds /* Read HW Rev First */ 14361da177e4SLinus Torvalds func_class = READ_REG32(addr + LBA_FCLASS); 14371da177e4SLinus Torvalds 14381da177e4SLinus Torvalds if (IS_ELROY(dev)) { 14391da177e4SLinus Torvalds func_class &= 0xf; 14401da177e4SLinus Torvalds switch (func_class) { 14411da177e4SLinus Torvalds case 0: version = "TR1.0"; break; 14421da177e4SLinus Torvalds case 1: version = "TR2.0"; break; 14431da177e4SLinus Torvalds case 2: version = "TR2.1"; break; 14441da177e4SLinus Torvalds case 3: version = "TR2.2"; break; 14451da177e4SLinus Torvalds case 4: version = "TR3.0"; break; 14461da177e4SLinus Torvalds case 5: version = "TR4.0"; break; 14471da177e4SLinus Torvalds default: version = "TR4+"; 14481da177e4SLinus Torvalds } 14491da177e4SLinus Torvalds 1450ba9877b6SKyle McMartin printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n", 1451*645d11d4SMatthew Wilcox version, func_class & 0xf, (long)dev->hpa.start); 14521da177e4SLinus Torvalds 14531da177e4SLinus Torvalds if (func_class < 2) { 14541da177e4SLinus Torvalds printk(KERN_WARNING "Can't support LBA older than " 14551da177e4SLinus Torvalds "TR2.1 - continuing under adversity.\n"); 14561da177e4SLinus Torvalds } 14571da177e4SLinus Torvalds 14581da177e4SLinus Torvalds #if 0 14591da177e4SLinus Torvalds /* Elroy TR4.0 should work with simple algorithm. 14601da177e4SLinus Torvalds But it doesn't. Still missing something. *sigh* 14611da177e4SLinus Torvalds */ 14621da177e4SLinus Torvalds if (func_class > 4) { 14631da177e4SLinus Torvalds cfg_ops = &mercury_cfg_ops; 14641da177e4SLinus Torvalds } else 14651da177e4SLinus Torvalds #endif 14661da177e4SLinus Torvalds { 14671da177e4SLinus Torvalds cfg_ops = &elroy_cfg_ops; 14681da177e4SLinus Torvalds } 14691da177e4SLinus Torvalds 14701da177e4SLinus Torvalds } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) { 1471ba9877b6SKyle McMartin int major, minor; 1472ba9877b6SKyle McMartin 14731da177e4SLinus Torvalds func_class &= 0xff; 1474ba9877b6SKyle McMartin major = func_class >> 4, minor = func_class & 0xf; 1475ba9877b6SKyle McMartin 14761da177e4SLinus Torvalds /* We could use one printk for both Elroy and Mercury, 14771da177e4SLinus Torvalds * but for the mask for func_class. 14781da177e4SLinus Torvalds */ 1479ba9877b6SKyle McMartin printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n", 1480ba9877b6SKyle McMartin IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major, 1481*645d11d4SMatthew Wilcox minor, func_class, (long)dev->hpa.start); 1482ba9877b6SKyle McMartin 14831da177e4SLinus Torvalds cfg_ops = &mercury_cfg_ops; 14841da177e4SLinus Torvalds } else { 1485*645d11d4SMatthew Wilcox printk(KERN_ERR "Unknown LBA found at 0x%lx\n", 1486*645d11d4SMatthew Wilcox (long)dev->hpa.start); 14871da177e4SLinus Torvalds return -ENODEV; 14881da177e4SLinus Torvalds } 14891da177e4SLinus Torvalds 1490353dfe12SMatthew Wilcox /* Tell I/O SAPIC driver we have a IRQ handler/region. */ 149153f01bbaSMatthew Wilcox tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE); 14921da177e4SLinus Torvalds 14931da177e4SLinus Torvalds /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't 14941da177e4SLinus Torvalds ** have an IRT entry will get NULL back from iosapic code. 14951da177e4SLinus Torvalds */ 14961da177e4SLinus Torvalds 1497cb6fc18eSHelge Deller lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL); 14981da177e4SLinus Torvalds if (!lba_dev) { 14991da177e4SLinus Torvalds printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n"); 15001da177e4SLinus Torvalds return(1); 15011da177e4SLinus Torvalds } 15021da177e4SLinus Torvalds 15031da177e4SLinus Torvalds 15041da177e4SLinus Torvalds /* ---------- First : initialize data we already have --------- */ 15051da177e4SLinus Torvalds 15061da177e4SLinus Torvalds lba_dev->hw_rev = func_class; 15071da177e4SLinus Torvalds lba_dev->hba.base_addr = addr; 15081da177e4SLinus Torvalds lba_dev->hba.dev = dev; 15091da177e4SLinus Torvalds lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */ 15101da177e4SLinus Torvalds lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */ 1511b0eecc4dSKyle McMartin parisc_set_drvdata(dev, lba_dev); 15121da177e4SLinus Torvalds 15131da177e4SLinus Torvalds /* ------------ Second : initialize common stuff ---------- */ 15141da177e4SLinus Torvalds pci_bios = &lba_bios_ops; 15151da177e4SLinus Torvalds pcibios_register_hba(HBA_DATA(lba_dev)); 15161da177e4SLinus Torvalds spin_lock_init(&lba_dev->lba_lock); 15171da177e4SLinus Torvalds 15181da177e4SLinus Torvalds if (lba_hw_init(lba_dev)) 15191da177e4SLinus Torvalds return(1); 15201da177e4SLinus Torvalds 15211da177e4SLinus Torvalds /* ---------- Third : setup I/O Port and MMIO resources --------- */ 15221da177e4SLinus Torvalds 15231da177e4SLinus Torvalds if (is_pdc_pat()) { 15241da177e4SLinus Torvalds /* PDC PAT firmware uses PIOP region of GMMIO space. */ 15251da177e4SLinus Torvalds pci_port = &lba_pat_port_ops; 15261da177e4SLinus Torvalds /* Go ask PDC PAT what resources this LBA has */ 15271da177e4SLinus Torvalds lba_pat_resources(dev, lba_dev); 15281da177e4SLinus Torvalds } else { 15291da177e4SLinus Torvalds if (!astro_iop_base) { 15301da177e4SLinus Torvalds /* Sprockets PDC uses NPIOP region */ 15315076c158SHelge Deller astro_iop_base = ioremap_nocache(LBA_PORT_BASE, 64 * 1024); 15321da177e4SLinus Torvalds pci_port = &lba_astro_port_ops; 15331da177e4SLinus Torvalds } 15341da177e4SLinus Torvalds 15351da177e4SLinus Torvalds /* Poke the chip a bit for /proc output */ 15361da177e4SLinus Torvalds lba_legacy_resources(dev, lba_dev); 15371da177e4SLinus Torvalds } 15381da177e4SLinus Torvalds 1539353dfe12SMatthew Wilcox if (lba_dev->hba.bus_num.start < lba_next_bus) 1540353dfe12SMatthew Wilcox lba_dev->hba.bus_num.start = lba_next_bus; 1541353dfe12SMatthew Wilcox 15421da177e4SLinus Torvalds dev->dev.platform_data = lba_dev; 15431da177e4SLinus Torvalds lba_bus = lba_dev->hba.hba_bus = 15441da177e4SLinus Torvalds pci_scan_bus_parented(&dev->dev, lba_dev->hba.bus_num.start, 15451da177e4SLinus Torvalds cfg_ops, NULL); 1546353dfe12SMatthew Wilcox if (lba_bus) { 1547353dfe12SMatthew Wilcox lba_next_bus = lba_bus->subordinate + 1; 1548c431ada4SRajesh Shah pci_bus_add_devices(lba_bus); 1549353dfe12SMatthew Wilcox } 15501da177e4SLinus Torvalds 15511da177e4SLinus Torvalds /* This is in lieu of calling pci_assign_unassigned_resources() */ 15521da177e4SLinus Torvalds if (is_pdc_pat()) { 15531da177e4SLinus Torvalds /* assign resources to un-initialized devices */ 15541da177e4SLinus Torvalds 15551da177e4SLinus Torvalds DBG_PAT("LBA pci_bus_size_bridges()\n"); 15561da177e4SLinus Torvalds pci_bus_size_bridges(lba_bus); 15571da177e4SLinus Torvalds 15581da177e4SLinus Torvalds DBG_PAT("LBA pci_bus_assign_resources()\n"); 15591da177e4SLinus Torvalds pci_bus_assign_resources(lba_bus); 15601da177e4SLinus Torvalds 15611da177e4SLinus Torvalds #ifdef DEBUG_LBA_PAT 15621da177e4SLinus Torvalds DBG_PAT("\nLBA PIOP resource tree\n"); 15631da177e4SLinus Torvalds lba_dump_res(&lba_dev->hba.io_space, 2); 15641da177e4SLinus Torvalds DBG_PAT("\nLBA LMMIO resource tree\n"); 15651da177e4SLinus Torvalds lba_dump_res(&lba_dev->hba.lmmio_space, 2); 15661da177e4SLinus Torvalds #endif 15671da177e4SLinus Torvalds } 15681da177e4SLinus Torvalds pci_enable_bridges(lba_bus); 15691da177e4SLinus Torvalds 15701da177e4SLinus Torvalds 15711da177e4SLinus Torvalds /* 15721da177e4SLinus Torvalds ** Once PCI register ops has walked the bus, access to config 15731da177e4SLinus Torvalds ** space is restricted. Avoids master aborts on config cycles. 15741da177e4SLinus Torvalds ** Early LBA revs go fatal on *any* master abort. 15751da177e4SLinus Torvalds */ 15761da177e4SLinus Torvalds if (cfg_ops == &elroy_cfg_ops) { 15771da177e4SLinus Torvalds lba_dev->flags |= LBA_FLAG_SKIP_PROBE; 15781da177e4SLinus Torvalds } 15791da177e4SLinus Torvalds 15801da177e4SLinus Torvalds /* Whew! Finally done! Tell services we got this one covered. */ 15811da177e4SLinus Torvalds return 0; 15821da177e4SLinus Torvalds } 15831da177e4SLinus Torvalds 15841da177e4SLinus Torvalds static struct parisc_device_id lba_tbl[] = { 15851da177e4SLinus Torvalds { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa }, 15861da177e4SLinus Torvalds { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa }, 15871da177e4SLinus Torvalds { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa }, 15881da177e4SLinus Torvalds { 0, } 15891da177e4SLinus Torvalds }; 15901da177e4SLinus Torvalds 15911da177e4SLinus Torvalds static struct parisc_driver lba_driver = { 15921da177e4SLinus Torvalds .name = MODULE_NAME, 15931da177e4SLinus Torvalds .id_table = lba_tbl, 15941da177e4SLinus Torvalds .probe = lba_driver_probe, 15951da177e4SLinus Torvalds }; 15961da177e4SLinus Torvalds 15971da177e4SLinus Torvalds /* 15981da177e4SLinus Torvalds ** One time initialization to let the world know the LBA was found. 15991da177e4SLinus Torvalds ** Must be called exactly once before pci_init(). 16001da177e4SLinus Torvalds */ 16011da177e4SLinus Torvalds void __init lba_init(void) 16021da177e4SLinus Torvalds { 16031da177e4SLinus Torvalds register_parisc_driver(&lba_driver); 16041da177e4SLinus Torvalds } 16051da177e4SLinus Torvalds 16061da177e4SLinus Torvalds /* 16071da177e4SLinus Torvalds ** Initialize the IBASE/IMASK registers for LBA (Elroy). 16081da177e4SLinus Torvalds ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA). 16091da177e4SLinus Torvalds ** sba_iommu is responsible for locking (none needed at init time). 16101da177e4SLinus Torvalds */ 16111da177e4SLinus Torvalds void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask) 16121da177e4SLinus Torvalds { 16135076c158SHelge Deller void __iomem * base_addr = ioremap_nocache(lba->hpa.start, 4096); 16141da177e4SLinus Torvalds 16151da177e4SLinus Torvalds imask <<= 2; /* adjust for hints - 2 more bits */ 16161da177e4SLinus Torvalds 16171da177e4SLinus Torvalds /* Make sure we aren't trying to set bits that aren't writeable. */ 16181da177e4SLinus Torvalds WARN_ON((ibase & 0x001fffff) != 0); 16191da177e4SLinus Torvalds WARN_ON((imask & 0x001fffff) != 0); 16201da177e4SLinus Torvalds 16211da177e4SLinus Torvalds DBG("%s() ibase 0x%x imask 0x%x\n", __FUNCTION__, ibase, imask); 16221da177e4SLinus Torvalds WRITE_REG32( imask, base_addr + LBA_IMASK); 16231da177e4SLinus Torvalds WRITE_REG32( ibase, base_addr + LBA_IBASE); 16241da177e4SLinus Torvalds iounmap(base_addr); 16251da177e4SLinus Torvalds } 16261da177e4SLinus Torvalds 1627